Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	27644	1			T4	22		T7	4		T9	81
auto[SpiFlashAddrCfg]	6028	1			T3	2		T9	22		T11	4
auto[SpiFlashAddr3b]	7292	1			T2	4		T7	2		T9	22
auto[SpiFlashAddr4b]	6134	1			T7	6		T9	25		T12	17

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26594

1

T2

4

T3

2

T4

22

auto[1]

20504

1

T9

62

T12

73

T17

9

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24712

1

T4

22

T7

2

T9

94

auto[1]

22386

1

T2

4

T3

2

T7

10

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	31396	1			T4	22		T7	4		T9	96
values[1]	806	1			T9	2		T12	2		T17	2
values[2]	1159	1			T9	3		T12	1		T17	1
values[3]	1189	1			T9	7		T12	12		T17	2
values[4]	1142	1			T9	1		T12	6		T17	1
values[5]	1089	1			T9	6		T12	4		T23	3
values[6]	1208	1			T9	2		T12	7		T17	3
values[7]	1179	1			T9	1		T12	3		T17	1
values[8]	7930	1			T2	4		T3	2		T7	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23838

1

T3

2

T4

22

T7

12

auto[1]

23260

1

T2

4

T9

150

T40

282

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

45394

1

T2

4

T3

2

T4

22

write

1704

1

T9

15

T12

7

T17

3

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15747

1

T2

4

T3

2

T4

22

valids[0x1]

31351

1

T7

2

T9

93

T11

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1203	1			T9	10		T12	3		T23	6
internal_process_ops[0x5a]	1315	1			T9	5		T12	8		T19	2
internal_process_ops[0x05]	16513	1			T9	25		T12	27		T13	4
internal_process_ops[0x35]	1338	1			T9	1		T12	1		T13	6
internal_process_ops[0x15]	1215	1			T9	7		T11	2		T12	3
internal_process_ops[0x03]	877	1			T7	2		T9	3		T12	5
internal_process_ops[0x0b]	804	1			T9	2		T12	3		T17	1
internal_process_ops[0x3b]	838	1			T7	4		T9	2		T12	5
internal_process_ops[0x6b]	810	1			T2	3		T9	1		T12	6
internal_process_ops[0xbb]	891	1			T2	1		T3	2		T12	4
internal_process_ops[0xeb]	807	1			T9	3		T12	3		T17	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46289

1

T2

4

T3

2

T4

22

auto[1]

809

1

T9

4

T12

4

T17

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45430

1

T2

4

T3

2

T4

22

auto[1]

1668

1

T9

5

T12

5

T17

3

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8222

1

T4

22

T7

4

T11

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4697

1

T12

36

T23

21

T26

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1621

1

T3

2

T11

4

T12

20

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1408

1

T12

10

T17

3

T23

7

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2111

1

T7

2

T12

18

T19

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1757

1

T12

14

T17

4

T23

13

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1770

1

T7

6

T12

4

T17

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1461

1

T12

10

T23

15

T24

9

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

53

1

T156

2

T35

2

T28

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

58

1

T25

1

T31

4

T32

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

39

1

T12

1

T23

1

T24

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

40

1

T28

1

T29

2

T157

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

73

1

T17

1

T30

1

T158

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

47

1

T12

1

T27

1

T35

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

30

1

T24

2

T25

1

T28

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

63

1

T17

1

T24

3

T27

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

43

1

T12

1

T23

2

T155

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

35

1

T35

2

T29

1

T32

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

64

1

T12

1

T35

1

T29

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

56

1

T17

1

T27

2

T35

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

65

1

T24

1

T25

1

T29

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

44

1

T12

2

T25

4

T35

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

44

1

T25

1

T35

1

T159

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

37

1

T12

1

T23

1

T28

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8002

1

T9

58

T40

114

T41

27

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6320

1

T9

20

T40

66

T41

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1284

1

T9

7

T40

11

T37

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1271

1

T9

13

T40

15

T41

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1504

1

T2

4

T9

12

T40

16

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1499

1

T9

6

T40

17

T41

7

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1207

1

T9

6

T40

10

T36

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1260

1

T9

13

T40

21

T41

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

65

1

T40

1

T160

1

T161

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

39

1

T161

3

T162

1

T78

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

54

1

T9

2

T163

1

T164

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

55

1

T9

1

T165

1

T162

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

56

1

T166

1

T167

1

T168

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

38

1

T41

1

T160

1

T165

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

75

1

T9

2

T40

1

T166

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

62

1

T40

1

T166

2

T161

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

62

1

T40

2

T77

2

T78

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

60

1

T167

1

T78

4

T169

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

54

1

T9

4

T161

2

T165

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

47

1

T161

2

T170

2

T171

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

53

1

T9

3

T166

1

T163

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

82

1

T9

2

T40

1

T41

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

65

1

T40

2

T41

2

T165

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

46

1

T9

1

T40

4

T166

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3371	1			T4	22		T7	4		T12	23
auto[0]	values[0]	valids[0x1]	11709	1			T11	2		T12	45		T13	10
auto[0]	values[1]	valids[0x1]	392	1			T12	2		T17	2		T23	1
auto[0]	values[2]	valids[0x0]	465	1			T12	1		T17	1		T23	6
auto[0]	values[2]	valids[0x1]	226	1			T23	2		T24	3		T156	2
auto[0]	values[3]	valids[0x0]	397	1			T12	7		T17	2		T42	2
auto[0]	values[3]	valids[0x1]	253	1			T12	5		T23	1		T26	2
auto[0]	values[4]	valids[0x0]	409	1			T12	2		T23	3		T172	2
auto[0]	values[4]	valids[0x1]	246	1			T12	4		T17	1		T24	1
auto[0]	values[5]	valids[0x0]	342	1			T12	4		T23	3		T24	3
auto[0]	values[5]	valids[0x1]	243	1			T24	1		T25	2		T35	3
auto[0]	values[6]	valids[0x0]	420	1			T12	2		T23	3		T24	6
auto[0]	values[6]	valids[0x1]	239	1			T12	5		T17	3		T24	3
auto[0]	values[7]	valids[0x0]	442	1			T12	1		T17	1		T24	2
auto[0]	values[7]	valids[0x1]	261	1			T12	2		T23	3		T98	2
auto[0]	values[8]	valids[0x0]	2776	1			T3	2		T7	6		T11	4
auto[0]	values[8]	valids[0x1]	1647	1			T7	2		T12	15		T19	2
auto[1]	values[0]	valids[0x0]	3351	1			T9	34		T40	43		T41	8
auto[1]	values[0]	valids[0x1]	12965	1			T9	62		T40	165		T36	1
auto[1]	values[1]	valids[0x1]	414	1			T9	2		T40	3		T166	1
auto[1]	values[2]	valids[0x0]	302	1			T9	3		T40	6		T41	4
auto[1]	values[2]	valids[0x1]	166	1			T163	1		T161	4		T167	4
auto[1]	values[3]	valids[0x0]	329	1			T9	2		T38	1		T173	1
auto[1]	values[3]	valids[0x1]	210	1			T9	5		T40	1		T160	1
auto[1]	values[4]	valids[0x0]	270	1			T40	3		T41	1		T166	2
auto[1]	values[4]	valids[0x1]	217	1			T9	1		T40	3		T166	2
auto[1]	values[5]	valids[0x0]	273	1			T9	4		T40	3		T41	8
auto[1]	values[5]	valids[0x1]	231	1			T9	2		T40	2		T163	5
auto[1]	values[6]	valids[0x0]	334	1			T9	1		T40	3		T41	1
auto[1]	values[6]	valids[0x1]	215	1			T9	1		T41	4		T141	2
auto[1]	values[7]	valids[0x0]	277	1			T40	2		T166	1		T160	2
auto[1]	values[7]	valids[0x1]	199	1			T9	1		T40	5		T166	3
auto[1]	values[8]	valids[0x0]	1989	1			T2	4		T9	13		T40	29
auto[1]	values[8]	valids[0x1]	1518	1			T9	19		T40	14		T41	4