Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2831234

1

T2

135

T3

242

T4

28

auto[1]

15181

1

T9

10

T12

23

T17

12

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

848917

1

T2

135

T3

242

T4

28

auto[1]

1997498

1

T9

6969

T11

512

T12

12225

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	587909	1			T2	22		T3	40		T7	1
auto[524288:1048575]	246789	1			T3	43		T9	517		T12	3
auto[1048576:1572863]	333892	1			T12	3120		T13	342		T23	10
auto[1572864:2097151]	335541	1			T2	111		T9	13		T12	2722
auto[2097152:2621439]	285616	1			T3	2		T4	4		T9	3524
auto[2621440:3145727]	335895	1			T2	1		T3	2		T4	24
auto[3145728:3670015]	333791	1			T2	1		T3	76		T9	1034
auto[3670016:4194303]	386982	1			T3	79		T9	411		T12	13

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2015658

1

T2

12

T3

35

T4

28

auto[1]

830757

1

T2

123

T3

207

T13

2442

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2503230

1

T2

135

T3

242

T4

12

auto[1]

343185

1

T4

16

T9

679

T12

2722

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	214960	1			T2	22		T3	40		T7	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	315444	1			T9	726		T11	512		T12	3502
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	65549	1			T3	43		T13	187		T19	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	143873	1			T9	514		T13	27		T23	1800
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	98331	1			T12	2		T13	335		T23	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	198993	1			T12	3118		T13	7		T23	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	90961	1			T2	111		T9	4		T12	7
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	189586	1			T9	2		T12	1		T13	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	58665	1			T3	2		T4	1		T9	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	190023	1			T9	3518		T12	256		T13	3162
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	90037	1			T2	1		T3	2		T4	11
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	205241	1			T9	257		T13	195		T23	256
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	89301	1			T2	1		T3	76		T9	6
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	198239	1			T9	1028		T12	2617		T13	412
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	132924	1			T3	79		T9	2		T12	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	209245	1			T9	256		T12	1		T23	256
auto[0]	auto[1]	auto[0:524287]	auto[0]	1421	1			T9	4		T12	3		T27	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	53227	1			T9	514		T27	132		T35	512
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	240	1			T9	3		T12	1		T17	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	35317	1			T12	2		T23	2		T40	129
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	450	1			T40	11		T24	2		T28	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	34448	1			T40	5		T24	986		T163	2647
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1406	1			T12	1		T17	2		T40	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	51868	1			T12	2710		T17	2519		T24	257
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	813	1			T4	3		T9	1		T17	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	34100	1			T9	2		T17	2		T24	513
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1023	1			T4	13		T17	4		T25	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	37739	1			T17	3		T40	2487		T25	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	468	1			T12	5		T28	8		T29	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	44205	1			T28	5		T29	1		T163	2652
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	698	1			T9	6		T25	2		T28	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	42439	1			T9	147		T28	2602		T29	3213
auto[1]	auto[0]	auto[0:524287]	auto[0]	259	1			T12	1		T24	1		T43	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2251	1			T12	1		T24	1		T43	14
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	150	1			T23	1		T40	4		T27	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1279	1			T23	2		T40	21		T25	92
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	143	1			T23	1		T24	1		T25	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1064	1			T23	5		T24	34		T25	17
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	137	1			T9	2		T12	1		T23	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1053	1			T9	5		T12	2		T23	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	165	1			T23	1		T41	2		T28	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1470	1			T41	2		T28	1		T166	109
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	161	1			T9	1		T35	1		T166	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1177	1			T166	9		T30	5		T32	13
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	183	1			T12	2		T23	2		T40	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1060	1			T12	5		T40	22		T24	32
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	148	1			T12	1		T24	2		T28	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1158	1			T12	10		T24	10		T28	13
auto[1]	auto[1]	auto[0:524287]	auto[0]	42	1			T9	2		T165	1		T290	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	305	1			T165	26		T290	12		T168	3
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	38	1			T40	1		T29	1		T166	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	343	1			T40	1		T29	1		T166	9
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	43	1			T40	5		T165	1		T290	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	420	1			T40	65		T165	1		T290	18
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	40	1			T17	1		T24	1		T161	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	490	1			T17	2		T24	20		T161	33
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	43	1			T17	2		T24	1		T160	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	337	1			T17	7		T160	2		T163	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	45	1			T163	1		T32	2		T299	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	472	1			T32	34		T299	8		T290	9
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	36	1			T28	1		T29	1		T163	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	299	1			T28	17		T29	1		T163	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	37	1			T29	2		T167	1		T192	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	333	1			T167	1		T192	1		T205	4

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1665085	1			T2	12		T3	35		T4	12
auto[0]	auto[0]	auto[1]	826287	1			T2	123		T3	207		T13	2442
auto[0]	auto[1]	auto[0]	335673	1			T4	16		T9	677		T12	2722
auto[0]	auto[1]	auto[1]	4189	1			T40	2		T28	1		T163	1
auto[1]	auto[0]	auto[0]	11635	1			T9	8		T12	23		T23	16
auto[1]	auto[0]	auto[1]	223	1			T40	3		T24	1		T43	1
auto[1]	auto[1]	auto[0]	3265	1			T9	2		T17	12		T40	67
auto[1]	auto[1]	auto[1]	58	1			T40	5		T28	1		T29	1