Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14142

1

T3

2

T4

22

T7

12

auto[1]

9696

1

T12

73

T17

9

T23

58

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3275	1			T3	2		T4	22		T12	37
values[1]	3304	1			T7	12		T17	28		T23	21
values[2]	3386	1			T12	20		T19	6		T42	6
values[3]	2602	1			T98	22		T24	57		T27	40
values[4]	2631	1			T12	23		T17	24		T23	51
values[5]	3003	1			T12	21		T23	24		T24	54
values[6]	2629	1			T11	6		T12	42		T13	10
values[7]	3008	1			T24	20		T27	21		T43	26

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2939	1			T7	12		T12	37		T92	12
values[1]	3253	1			T23	20		T25	84		T35	60
values[2]	2761	1			T12	23		T17	28		T90	10
values[3]	3559	1			T4	22		T23	21		T24	32
values[4]	2825	1			T3	2		T42	6		T23	27
values[5]	3001	1			T12	22		T23	24		T99	4
values[6]	2134	1			T11	6		T12	41		T19	6
values[7]	3366	1			T12	20		T13	10		T17	24

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	187	1			T12	11		T183	66		T204	8
auto[0]	values[0]	values[1]	237	1			T25	14		T35	9		T28	22
auto[0]	values[0]	values[2]	134	1			T159	24		T191	12		T210	34
auto[0]	values[0]	values[3]	453	1			T4	22		T32	24		T155	16
auto[0]	values[0]	values[4]	275	1			T3	2		T28	12		T29	7
auto[0]	values[0]	values[5]	441	1			T29	27		T194	8		T191	5
auto[0]	values[0]	values[6]	155	1			T29	6		T32	12		T158	14
auto[0]	values[0]	values[7]	192	1			T24	11		T190	2		T221	2
auto[0]	values[1]	values[0]	172	1			T7	12		T189	6		T260	20
auto[0]	values[1]	values[1]	358	1			T35	8		T227	124		T310	10
auto[0]	values[1]	values[2]	342	1			T17	23		T205	11		T311	192
auto[0]	values[1]	values[3]	465	1			T23	16		T29	15		T30	7
auto[0]	values[1]	values[4]	130	1			T24	15		T35	12		T28	11
auto[0]	values[1]	values[5]	287	1			T24	38		T177	12		T191	70
auto[0]	values[1]	values[6]	93	1			T191	12		T152	13		T230	14
auto[0]	values[1]	values[7]	342	1			T30	8		T217	8		T218	20
auto[0]	values[2]	values[0]	238	1			T27	14		T25	18		T158	7
auto[0]	values[2]	values[1]	214	1			T29	33		T158	10		T180	14
auto[0]	values[2]	values[2]	233	1			T159	14		T261	12		T229	109
auto[0]	values[2]	values[3]	302	1			T35	13		T179	4		T32	64
auto[0]	values[2]	values[4]	287	1			T42	6		T25	13		T35	10
auto[0]	values[2]	values[5]	178	1			T156	8		T25	7		T28	18
auto[0]	values[2]	values[6]	145	1			T12	10		T19	6		T91	6
auto[0]	values[2]	values[7]	244	1			T35	16		T29	12		T200	16
auto[0]	values[3]	values[0]	299	1			T24	8		T25	19		T199	10
auto[0]	values[3]	values[1]	112	1			T35	15		T32	10		T155	13
auto[0]	values[3]	values[2]	132	1			T312	4		T263	13		T241	7
auto[0]	values[3]	values[3]	101	1			T176	11		T189	8		T313	6
auto[0]	values[3]	values[4]	266	1			T209	6		T185	19		T176	14
auto[0]	values[3]	values[5]	113	1			T201	11		T241	18		T257	11
auto[0]	values[3]	values[6]	224	1			T27	10		T201	13		T195	14
auto[0]	values[3]	values[7]	309	1			T98	22		T27	10		T28	12
auto[0]	values[4]	values[0]	173	1			T30	17		T176	17		T191	13
auto[0]	values[4]	values[1]	163	1			T176	9		T202	15		T211	11
auto[0]	values[4]	values[2]	131	1			T12	17		T30	7		T196	8
auto[0]	values[4]	values[3]	236	1			T24	11		T214	8		T29	13
auto[0]	values[4]	values[4]	214	1			T23	11		T175	115		T181	2
auto[0]	values[4]	values[5]	196	1			T23	15		T172	8		T180	11
auto[0]	values[4]	values[6]	105	1			T205	6		T180	13		T229	13
auto[0]	values[4]	values[7]	159	1			T17	20		T28	10		T32	14
auto[0]	values[5]	values[0]	125	1			T202	9		T237	14		T314	10
auto[0]	values[5]	values[1]	286	1			T25	9		T28	34		T29	29
auto[0]	values[5]	values[2]	193	1			T35	10		T158	11		T155	10
auto[0]	values[5]	values[3]	260	1			T30	24		T31	12		T32	14
auto[0]	values[5]	values[4]	147	1			T184	20		T152	8		T264	11
auto[0]	values[5]	values[5]	216	1			T31	21		T159	10		T202	12
auto[0]	values[5]	values[6]	212	1			T12	13		T24	49		T180	11
auto[0]	values[5]	values[7]	266	1			T23	9		T31	14		T176	9
auto[0]	values[6]	values[0]	229	1			T92	12		T31	10		T159	17
auto[0]	values[6]	values[1]	161	1			T23	7		T206	8		T176	15
auto[0]	values[6]	values[2]	250	1			T90	10		T25	8		T198	6
auto[0]	values[6]	values[3]	126	1			T109	4		T35	7		T201	12
auto[0]	values[6]	values[4]	312	1			T25	15		T315	2		T205	74
auto[0]	values[6]	values[5]	74	1			T12	10		T99	4		T210	13
auto[0]	values[6]	values[6]	238	1			T11	6		T30	15		T264	6
auto[0]	values[6]	values[7]	193	1			T12	9		T13	10		T35	11
auto[0]	values[7]	values[0]	214	1			T35	8		T155	31		T159	14
auto[0]	values[7]	values[1]	156	1			T155	23		T316	6		T191	14
auto[0]	values[7]	values[2]	367	1			T43	26		T35	11		T185	9
auto[0]	values[7]	values[3]	266	1			T25	9		T193	16		T187	12
auto[0]	values[7]	values[4]	190	1			T24	13		T27	10		T152	20
auto[0]	values[7]	values[5]	240	1			T176	15		T294	24		T211	43
auto[0]	values[7]	values[6]	147	1			T28	23		T159	40		T317	6
auto[0]	values[7]	values[7]	237	1			T178	14		T174	8		T318	6
auto[1]	values[0]	values[0]	106	1			T12	26		T319	18		T320	6
auto[1]	values[0]	values[1]	217	1			T25	50		T35	11		T28	23
auto[1]	values[0]	values[2]	173	1			T159	31		T191	27		T210	11
auto[1]	values[0]	values[3]	225	1			T32	5		T155	8		T261	25
auto[1]	values[0]	values[4]	169	1			T28	26		T29	27		T31	8
auto[1]	values[0]	values[5]	117	1			T29	15		T191	15		T201	13
auto[1]	values[0]	values[6]	75	1			T29	20		T32	8		T158	6
auto[1]	values[0]	values[7]	119	1			T24	9		T185	13		T159	6
auto[1]	values[1]	values[0]	140	1			T265	20		T189	20		T260	3
auto[1]	values[1]	values[1]	152	1			T35	12		T157	12		T201	12
auto[1]	values[1]	values[2]	94	1			T17	5		T205	16		T180	8
auto[1]	values[1]	values[3]	194	1			T23	5		T29	6		T30	13
auto[1]	values[1]	values[4]	94	1			T26	8		T24	6		T35	8
auto[1]	values[1]	values[5]	116	1			T24	3		T191	8		T201	9
auto[1]	values[1]	values[6]	56	1			T191	8		T152	7		T230	12
auto[1]	values[1]	values[7]	269	1			T30	12		T191	9		T201	69
auto[1]	values[2]	values[0]	270	1			T27	6		T25	2		T158	13
auto[1]	values[2]	values[1]	357	1			T29	32		T158	17		T180	6
auto[1]	values[2]	values[2]	99	1			T159	8		T261	8		T229	20
auto[1]	values[2]	values[3]	238	1			T35	10		T32	8		T155	17
auto[1]	values[2]	values[4]	158	1			T25	25		T35	10		T32	4
auto[1]	values[2]	values[5]	117	1			T25	13		T28	2		T205	9
auto[1]	values[2]	values[6]	153	1			T12	10		T35	8		T28	7
auto[1]	values[2]	values[7]	153	1			T35	4		T29	10		T152	17
auto[1]	values[3]	values[0]	205	1			T24	49		T25	21		T250	32
auto[1]	values[3]	values[1]	104	1			T35	5		T32	10		T33	12
auto[1]	values[3]	values[2]	91	1			T263	7		T241	13		T321	13
auto[1]	values[3]	values[3]	176	1			T176	17		T189	16		T261	12
auto[1]	values[3]	values[4]	158	1			T185	7		T176	7		T191	9
auto[1]	values[3]	values[5]	70	1			T213	10		T201	9		T241	3
auto[1]	values[3]	values[6]	125	1			T27	10		T201	7		T264	4
auto[1]	values[3]	values[7]	117	1			T27	10		T28	8		T29	9
auto[1]	values[4]	values[0]	202	1			T30	8		T176	3		T191	32
auto[1]	values[4]	values[1]	143	1			T176	11		T202	7		T211	9
auto[1]	values[4]	values[2]	97	1			T12	6		T30	13		T322	14
auto[1]	values[4]	values[3]	167	1			T24	21		T29	7		T159	24
auto[1]	values[4]	values[4]	127	1			T23	16		T256	16		T323	5
auto[1]	values[4]	values[5]	120	1			T23	9		T180	9		T263	10
auto[1]	values[4]	values[6]	119	1			T205	28		T288	10		T180	7
auto[1]	values[4]	values[7]	279	1			T17	4		T28	44		T32	91
auto[1]	values[5]	values[0]	170	1			T202	11		T237	6		T240	36
auto[1]	values[5]	values[1]	240	1			T25	11		T28	2		T29	14
auto[1]	values[5]	values[2]	130	1			T35	10		T158	11		T155	10
auto[1]	values[5]	values[3]	140	1			T30	6		T31	8		T32	6
auto[1]	values[5]	values[4]	90	1			T152	12		T264	13		T237	9
auto[1]	values[5]	values[5]	249	1			T31	8		T159	11		T202	8
auto[1]	values[5]	values[6]	118	1			T12	8		T24	5		T180	11
auto[1]	values[5]	values[7]	161	1			T23	15		T31	11		T176	11
auto[1]	values[6]	values[0]	100	1			T31	10		T159	8		T229	13
auto[1]	values[6]	values[1]	232	1			T23	13		T176	6		T250	7
auto[1]	values[6]	values[2]	128	1			T25	62		T31	8		T155	25
auto[1]	values[6]	values[3]	72	1			T35	17		T201	8		T245	4
auto[1]	values[6]	values[4]	126	1			T25	5		T205	5		T211	10
auto[1]	values[6]	values[5]	147	1			T12	12		T225	10		T210	92
auto[1]	values[6]	values[6]	87	1			T30	9		T264	14		T210	13
auto[1]	values[6]	values[7]	154	1			T12	11		T35	10		T30	11
auto[1]	values[7]	values[0]	109	1			T35	12		T155	9		T159	6
auto[1]	values[7]	values[1]	121	1			T155	23		T191	6		T264	20
auto[1]	values[7]	values[2]	167	1			T35	10		T185	11		T176	7
auto[1]	values[7]	values[3]	138	1			T25	11		T220	20		T187	12
auto[1]	values[7]	values[4]	82	1			T24	7		T27	11		T152	3
auto[1]	values[7]	values[5]	320	1			T176	8		T211	39		T261	9
auto[1]	values[7]	values[6]	82	1			T28	17		T159	19		T207	14
auto[1]	values[7]	values[7]	172	1			T201	10		T152	8		T202	10