Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2532744	1			T1	3465		T2	1		T3	1
all_pins[1]	2532744	1			T1	3465		T2	1		T3	1
all_pins[2]	2532744	1			T1	3465		T2	1		T3	1
all_pins[3]	2532744	1			T1	3465		T2	1		T3	1
all_pins[4]	2532744	1			T1	3465		T2	1		T3	1
all_pins[5]	2532744	1			T1	3465		T2	1		T3	1
all_pins[6]	2532744	1			T1	3465		T2	1		T3	1
all_pins[7]	2532744	1			T1	3465		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20234799	1			T1	27720		T2	8		T3	8
values[0x1]	27153	1			T17	6645		T41	14		T60	56
transitions[0x0=>0x1]	25394	1			T17	6264		T41	12		T60	43
transitions[0x1=>0x0]	25411	1			T17	6264		T41	12		T60	43

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2532235	1			T1	3465		T2	1		T3	1
all_pins[0]	values[0x1]	509	1			T17	42		T41	3		T60	5
all_pins[0]	transitions[0x0=>0x1]	253	1			T17	40		T41	3		T60	3
all_pins[0]	transitions[0x1=>0x0]	134	1			T17	5		T41	2		T60	5
all_pins[1]	values[0x0]	2532354	1			T1	3465		T2	1		T3	1
all_pins[1]	values[0x1]	390	1			T17	7		T41	2		T60	7
all_pins[1]	transitions[0x0=>0x1]	247	1			T17	4		T41	2		T60	4
all_pins[1]	transitions[0x1=>0x0]	172	1			T17	6		T60	5		T77	1
all_pins[2]	values[0x0]	2532429	1			T1	3465		T2	1		T3	1
all_pins[2]	values[0x1]	315	1			T17	9		T60	8		T77	1
all_pins[2]	transitions[0x0=>0x1]	268	1			T17	7		T60	6		T77	1
all_pins[2]	transitions[0x1=>0x0]	134	1			T17	2		T60	7		T77	2
all_pins[3]	values[0x0]	2532563	1			T1	3465		T2	1		T3	1
all_pins[3]	values[0x1]	181	1			T17	4		T60	9		T77	2
all_pins[3]	transitions[0x0=>0x1]	123	1			T17	4		T60	9		T155	2
all_pins[3]	transitions[0x1=>0x0]	135	1			T17	4		T41	2		T60	3
all_pins[4]	values[0x0]	2532551	1			T1	3465		T2	1		T3	1
all_pins[4]	values[0x1]	193	1			T17	4		T41	2		T60	3
all_pins[4]	transitions[0x0=>0x1]	156	1			T17	4		T41	2		T60	1
all_pins[4]	transitions[0x1=>0x0]	1494	1			T17	371		T41	3		T60	3
all_pins[5]	values[0x0]	2531213	1			T1	3465		T2	1		T3	1
all_pins[5]	values[0x1]	1531	1			T17	371		T41	3		T60	5
all_pins[5]	transitions[0x0=>0x1]	423	1			T17	2		T41	3		T60	2
all_pins[5]	transitions[0x1=>0x0]	22725	1			T17	5830		T60	11		T155	1
all_pins[6]	values[0x0]	2508911	1			T1	3465		T2	1		T3	1
all_pins[6]	values[0x1]	23833	1			T17	6199		T60	14		T155	2
all_pins[6]	transitions[0x0=>0x1]	23786	1			T17	6197		T60	13		T155	2
all_pins[6]	transitions[0x1=>0x0]	154	1			T17	7		T41	4		T60	4
all_pins[7]	values[0x0]	2532543	1			T1	3465		T2	1		T3	1
all_pins[7]	values[0x1]	201	1			T17	9		T41	4		T60	5
all_pins[7]	transitions[0x0=>0x1]	138	1			T17	6		T41	2		T60	5
all_pins[7]	transitions[0x1=>0x0]	463	1			T17	39		T41	1		T60	5