Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 0 18 100.00
Crosses 128 1 127 99.22


Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_data 8 0 8 100.00 100 1 1 0
cp_mask 8 0 8 100.00 100 1 1 0
cp_payload_swap_en 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 128 1 127 99.22 100 1 1 0


Summary for Variable cp_data

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_data

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 2913 1 T4 22 T12 58 T23 24
values[1] 2913 1 T23 51 T98 22 T99 4
values[2] 2919 1 T19 6 T92 12 T90 10
values[3] 3592 1 T12 43 T17 28 T24 73
values[4] 2436 1 T3 2 T12 20 T42 6
values[5] 3093 1 T11 6 T13 10 T24 54
values[6] 3593 1 T17 24 T24 20 T156 8
values[7] 2379 1 T7 12 T12 22 T172 8



Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 2861 1 T99 4 T91 6 T27 20
values[1] 3283 1 T4 22 T23 45 T156 8
values[2] 3654 1 T12 23 T23 24 T24 77
values[3] 2989 1 T3 2 T98 22 T24 127
values[4] 2500 1 T7 12 T12 20 T19 6
values[5] 2928 1 T12 80 T42 6 T172 8
values[6] 3354 1 T11 6 T13 10 T23 27
values[7] 2269 1 T12 20 T17 28 T24 20



Summary for Variable cp_payload_swap_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_payload_swap_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23458 1 T3 2 T4 22 T7 12
auto[1] 380 1 T12 4 T17 2 T23 1



Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 1 127 99.22 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_payload_swap_encp_datacp_maskCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [values[5]] [values[7]] 0 1 1


Covered bins
cp_payload_swap_encp_datacp_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] values[0] 334 1 T91 6 T25 19 T174 8
auto[0] values[0] values[1] 494 1 T4 22 T23 24 T32 36
auto[0] values[0] values[2] 419 1 T35 20 T30 21 T158 20
auto[0] values[0] values[3] 395 1 T175 115 T155 19 T176 22
auto[0] values[0] values[4] 277 1 T25 20 T29 22 T177 12
auto[0] values[0] values[5] 246 1 T12 56 T29 20 T31 49
auto[0] values[0] values[6] 503 1 T178 14 T29 21 T30 17
auto[0] values[0] values[7] 187 1 T35 21 T179 4 T180 20
auto[0] values[1] values[0] 188 1 T99 4 T35 41 T28 21
auto[0] values[1] values[1] 401 1 T30 30 T181 2 T182 10
auto[0] values[1] values[2] 528 1 T23 24 T24 57 T158 20
auto[0] values[1] values[3] 320 1 T98 22 T31 28 T183 66
auto[0] values[1] values[4] 200 1 T184 20 T185 22 T186 14
auto[0] values[1] values[5] 423 1 T25 20 T32 69 T187 25
auto[0] values[1] values[6] 360 1 T23 27 T29 17 T159 36
auto[0] values[1] values[7] 432 1 T25 20 T28 20 T29 23
auto[0] values[2] values[0] 581 1 T35 20 T32 105 T188 2
auto[0] values[2] values[1] 495 1 T29 21 T159 20 T189 24
auto[0] values[2] values[2] 315 1 T190 2 T155 20 T191 19
auto[0] values[2] values[3] 375 1 T24 41 T28 36 T176 20
auto[0] values[2] values[4] 294 1 T19 6 T192 26 T187 20
auto[0] values[2] values[5] 200 1 T31 49 T32 31 T180 20
auto[0] values[2] values[6] 388 1 T92 12 T90 10 T26 8
auto[0] values[2] values[7] 241 1 T193 16 T194 8 T155 20
auto[0] values[3] values[0] 244 1 T195 14 T196 8 T197 2
auto[0] values[3] values[1] 434 1 T25 63 T35 20 T198 6
auto[0] values[3] values[2] 606 1 T12 22 T24 20 T25 17
auto[0] values[3] values[3] 420 1 T24 30 T199 10 T176 20
auto[0] values[3] values[4] 384 1 T12 20 T32 20 T176 20
auto[0] values[3] values[5] 473 1 T109 4 T28 53 T200 16
auto[0] values[3] values[6] 607 1 T24 20 T27 16 T35 19
auto[0] values[3] values[7] 368 1 T17 27 T25 38 T31 20
auto[0] values[4] values[0] 328 1 T176 51 T201 21 T202 20
auto[0] values[4] values[1] 285 1 T23 20 T203 8 T192 26
auto[0] values[4] values[2] 296 1 T204 8 T205 27 T180 20
auto[0] values[4] values[3] 210 1 T3 2 T35 23 T32 27
auto[0] values[4] values[4] 340 1 T23 20 T28 38 T159 31
auto[0] values[4] values[5] 376 1 T42 6 T29 47 T155 20
auto[0] values[4] values[6] 308 1 T29 20 T30 23 T206 8
auto[0] values[4] values[7] 263 1 T12 20 T155 44 T185 26
auto[0] values[5] values[0] 389 1 T207 14 T208 8 T44 20
auto[0] values[5] values[1] 288 1 T28 20 T155 40 T209 6
auto[0] values[5] values[2] 557 1 T210 156 T211 21 T212 6
auto[0] values[5] values[3] 442 1 T24 54 T213 10 T158 26
auto[0] values[5] values[4] 359 1 T25 20 T35 20 T28 20
auto[0] values[5] values[5] 546 1 T35 20 T28 19 T158 20
auto[0] values[5] values[6] 371 1 T11 6 T13 10 T214 8
auto[0] values[5] values[7] 104 1 T155 20 T215 2 T210 26
auto[0] values[6] values[0] 524 1 T155 44 T185 20 T216 26
auto[0] values[6] values[1] 582 1 T156 8 T217 8 T218 20
auto[0] values[6] values[2] 519 1 T205 20 T201 25 T219 2
auto[0] values[6] values[3] 430 1 T25 70 T176 20 T187 25
auto[0] values[6] values[4] 338 1 T17 23 T35 20 T28 24
auto[0] values[6] values[5] 316 1 T158 18 T155 20 T191 20
auto[0] values[6] values[6] 492 1 T27 20 T28 19 T220 20
auto[0] values[6] values[7] 324 1 T24 20 T221 2 T222 18
auto[0] values[7] values[0] 217 1 T27 20 T35 20 T33 8
auto[0] values[7] values[1] 261 1 T211 28 T223 22 T224 54
auto[0] values[7] values[2] 366 1 T43 26 T225 10 T159 22
auto[0] values[7] values[3] 358 1 T25 20 T226 10 T227 124
auto[0] values[7] values[4] 267 1 T7 12 T176 21 T88 16
auto[0] values[7] values[5] 291 1 T12 21 T172 8 T30 24
auto[0] values[7] values[6] 261 1 T29 21 T155 19 T228 6
auto[0] values[7] values[7] 318 1 T35 20 T30 20 T187 46
auto[1] values[0] values[0] 14 1 T25 1 T29 4 T155 1
auto[1] values[0] values[1] 9 1 T32 4 T229 2 T230 1
auto[1] values[0] values[2] 2 1 T187 2 - - - -
auto[1] values[0] values[3] 4 1 T155 1 T176 1 T231 2
auto[1] values[0] values[4] 8 1 T185 1 T159 2 T211 2
auto[1] values[0] values[5] 7 1 T12 2 T29 1 T232 3
auto[1] values[0] values[6] 9 1 T30 3 T233 1 T234 2
auto[1] values[0] values[7] 5 1 T35 2 T235 2 T236 1
auto[1] values[1] values[0] 7 1 T28 4 T210 1 T237 1
auto[1] values[1] values[1] 5 1 T152 3 T44 2 - -
auto[1] values[1] values[2] 8 1 T176 1 T191 1 T238 1
auto[1] values[1] values[3] 4 1 T31 1 T201 2 T229 1
auto[1] values[1] values[4] 6 1 T185 1 T44 2 T239 1
auto[1] values[1] values[5] 8 1 T32 3 T230 2 T240 3
auto[1] values[1] values[6] 12 1 T29 3 T159 1 T157 4
auto[1] values[1] values[7] 11 1 T241 1 T236 2 T239 4
auto[1] values[2] values[0] 6 1 T229 2 T240 1 T242 1
auto[1] values[2] values[1] 6 1 T180 1 T44 2 T240 3
auto[1] values[2] values[2] 2 1 T191 1 T243 1 - -
auto[1] values[2] values[3] 2 1 T244 2 - - - -
auto[1] values[2] values[4] 5 1 T202 2 T154 1 T245 2
auto[1] values[2] values[5] 3 1 T31 3 - - - -
auto[1] values[2] values[6] 4 1 T27 1 T159 1 T191 2
auto[1] values[2] values[7] 2 1 T245 2 - - - -
auto[1] values[3] values[0] 2 1 T246 1 T247 1 - -
auto[1] values[3] values[1] 5 1 T25 1 T244 2 T248 2
auto[1] values[3] values[2] 10 1 T12 1 T25 3 T249 2
auto[1] values[3] values[3] 11 1 T24 2 T176 1 T250 2
auto[1] values[3] values[4] 5 1 T242 1 T251 4 - -
auto[1] values[3] values[5] 8 1 T28 1 T158 1 T211 3
auto[1] values[3] values[6] 12 1 T24 1 T27 4 T35 1
auto[1] values[3] values[7] 3 1 T17 1 T252 2 - -
auto[1] values[4] values[0] 4 1 T253 1 T254 2 T246 1
auto[1] values[4] values[1] 5 1 T23 1 T211 1 T229 1
auto[1] values[4] values[2] 3 1 T237 2 T255 1 - -
auto[1] values[4] values[3] 5 1 T35 1 T32 2 T224 2
auto[1] values[4] values[4] 1 1 T243 1 - - - -
auto[1] values[4] values[5] 6 1 T29 1 T44 2 T246 2
auto[1] values[4] values[6] 3 1 T30 1 T44 1 T244 1
auto[1] values[4] values[7] 3 1 T155 3 - - - -
auto[1] values[5] values[0] 5 1 T224 3 T256 1 T257 1
auto[1] values[5] values[1] 4 1 T44 2 T258 2 - -
auto[1] values[5] values[2] 7 1 T210 1 T234 1 T259 1
auto[1] values[5] values[3] 2 1 T158 1 T154 1 - -
auto[1] values[5] values[4] 6 1 T187 3 T229 1 T244 2
auto[1] values[5] values[5] 7 1 T35 1 T28 1 T180 2
auto[1] values[5] values[6] 6 1 T260 1 T229 1 T44 2
auto[1] values[6] values[0] 13 1 T191 2 T152 3 T245 2
auto[1] values[6] values[1] 7 1 T159 1 T211 1 T261 2
auto[1] values[6] values[2] 9 1 T201 1 T152 1 T210 1
auto[1] values[6] values[3] 6 1 T187 1 T262 2 T242 1
auto[1] values[6] values[4] 7 1 T17 1 T28 1 T263 2
auto[1] values[6] values[5] 7 1 T158 2 T264 2 T210 1
auto[1] values[6] values[6] 14 1 T27 1 T28 1 T238 2
auto[1] values[6] values[7] 5 1 T265 2 T205 3 - -
auto[1] values[7] values[0] 5 1 T33 4 T264 1 - -
auto[1] values[7] values[1] 2 1 T224 1 T266 1 - -
auto[1] values[7] values[2] 7 1 T154 1 T254 1 T267 1
auto[1] values[7] values[3] 5 1 T249 2 T246 3 - -
auto[1] values[7] values[4] 3 1 T240 1 T132 2 - -
auto[1] values[7] values[5] 11 1 T12 1 T30 1 T211 1
auto[1] values[7] values[6] 4 1 T29 2 T155 1 T211 1
auto[1] values[7] values[7] 3 1 T152 1 T210 1 T244 1

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