Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1770

1

T1

6

T8

4

T9

9

auto[1]

1702

1

T1

6

T8

4

T9

17

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2023

1

T1

12

T9

19

T12

10

auto[1]

1449

1

T8

8

T9

7

T12

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2716

1

T1

10

T8

8

T9

14

auto[1]

756

1

T1

2

T9

12

T12

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	702	1			T1	2		T8	3		T9	5
valid[1]	693	1			T1	3		T9	7		T12	1
valid[2]	668	1			T1	2		T8	1		T9	9
valid[3]	722	1			T1	4		T8	3		T9	3
valid[4]	687	1			T1	1		T8	1		T9	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	126	1			T1	1		T9	1		T17	2
auto[0]	auto[0]	valid[0]	auto[1]	141	1			T8	1		T83	1		T84	1
auto[0]	auto[0]	valid[1]	auto[0]	116	1			T1	2		T17	1		T41	2
auto[0]	auto[0]	valid[1]	auto[1]	159	1			T9	2		T34	1		T85	1
auto[0]	auto[0]	valid[2]	auto[0]	122	1			T9	1		T17	2		T22	1
auto[0]	auto[0]	valid[2]	auto[1]	148	1			T8	1		T9	1		T83	1
auto[0]	auto[0]	valid[3]	auto[0]	127	1			T1	2		T17	2		T22	1
auto[0]	auto[0]	valid[3]	auto[1]	149	1			T8	2		T83	1		T41	1
auto[0]	auto[0]	valid[4]	auto[0]	139	1			T9	1		T12	3		T23	1
auto[0]	auto[0]	valid[4]	auto[1]	153	1			T12	2		T82	1		T83	1
auto[0]	auto[1]	valid[0]	auto[0]	144	1			T1	1		T9	1		T12	1
auto[0]	auto[1]	valid[0]	auto[1]	145	1			T8	2		T9	2		T83	1
auto[0]	auto[1]	valid[1]	auto[0]	122	1			T1	1		T9	3		T12	1
auto[0]	auto[1]	valid[1]	auto[1]	138	1			T9	1		T34	1		T83	1
auto[0]	auto[1]	valid[2]	auto[0]	111	1			T1	2		T17	1		T27	1
auto[0]	auto[1]	valid[2]	auto[1]	131	1			T9	1		T83	2		T86	1
auto[0]	auto[1]	valid[3]	auto[0]	136	1			T12	1		T17	1		T22	1
auto[0]	auto[1]	valid[3]	auto[1]	143	1			T8	1		T83	1		T84	1
auto[0]	auto[1]	valid[4]	auto[0]	124	1			T1	1		T17	2		T22	1
auto[0]	auto[1]	valid[4]	auto[1]	142	1			T8	1		T41	1		T86	3
auto[1]	auto[0]	valid[0]	auto[0]	79	1			T9	1		T12	1		T335	1
auto[1]	auto[0]	valid[1]	auto[0]	81	1			T22	1		T27	1		T41	1
auto[1]	auto[0]	valid[2]	auto[0]	77	1			T9	2		T40	1		T24	1
auto[1]	auto[0]	valid[3]	auto[0]	89	1			T1	1		T12	1		T17	1
auto[1]	auto[0]	valid[4]	auto[0]	64	1			T17	1		T339	1		T341	2
auto[1]	auto[1]	valid[0]	auto[0]	67	1			T339	1		T27	1		T41	1
auto[1]	auto[1]	valid[1]	auto[0]	77	1			T9	1		T17	2		T23	1
auto[1]	auto[1]	valid[2]	auto[0]	79	1			T9	4		T12	2		T17	1
auto[1]	auto[1]	valid[3]	auto[0]	78	1			T1	1		T9	3		T40	1
auto[1]	auto[1]	valid[4]	auto[0]	65	1			T9	1		T27	1		T41	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal