Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49778

1

T1

273

T9

374

T12

335

auto[1]

15047

1

T8

8

T9

121

T12

29

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46711

1

T1

168

T8

8

T9

342

auto[1]

18114

1

T1

105

T9

153

T12

112

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33410	1			T1	134		T8	8		T9	247
others[1]	5513	1			T1	23		T9	35		T12	37
others[2]	5361	1			T1	22		T9	38		T12	30
others[3]	6174	1			T1	27		T9	58		T12	24
interest[1]	3572	1			T1	25		T9	26		T12	18
interest[4]	21863	1			T1	79		T8	8		T9	163
interest[64]	10795	1			T1	42		T9	91		T12	59

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16264	1			T1	79		T9	115		T12	112
auto[0]	auto[0]	others[1]	2754	1			T1	14		T9	12		T12	30
auto[0]	auto[0]	others[2]	2659	1			T1	15		T9	21		T12	21
auto[0]	auto[0]	others[3]	3049	1			T1	15		T9	21		T12	17
auto[0]	auto[0]	interest[1]	1772	1			T1	16		T9	12		T12	11
auto[0]	auto[0]	interest[4]	10602	1			T1	50		T9	77		T12	61
auto[0]	auto[0]	interest[64]	5166	1			T1	29		T9	40		T12	32
auto[0]	auto[1]	others[0]	7819	1			T8	8		T9	63		T12	16
auto[0]	auto[1]	others[1]	1216	1			T9	10		T12	1		T82	2
auto[0]	auto[1]	others[2]	1216	1			T9	3		T12	2		T82	3
auto[0]	auto[1]	others[3]	1440	1			T9	16		T12	2		T82	5
auto[0]	auto[1]	interest[1]	819	1			T9	5		T12	1		T82	1
auto[0]	auto[1]	interest[4]	5201	1			T8	8		T9	44		T12	8
auto[0]	auto[1]	interest[64]	2537	1			T9	24		T12	7		T82	5
auto[1]	auto[0]	others[0]	9327	1			T1	55		T9	69		T12	68
auto[1]	auto[0]	others[1]	1543	1			T1	9		T9	13		T12	6
auto[1]	auto[0]	others[2]	1486	1			T1	7		T9	14		T12	7
auto[1]	auto[0]	others[3]	1685	1			T1	12		T9	21		T12	5
auto[1]	auto[0]	interest[1]	981	1			T1	9		T9	9		T12	6
auto[1]	auto[0]	interest[4]	6060	1			T1	29		T9	42		T12	43
auto[1]	auto[0]	interest[64]	3092	1			T1	13		T9	27		T12	20

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal