Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	749	1			T17	21		T41	10		T60	27
all_values[1]	749	1			T17	21		T41	10		T60	27
all_values[2]	749	1			T17	21		T41	10		T60	27
all_values[3]	749	1			T17	21		T41	10		T60	27
all_values[4]	749	1			T17	21		T41	10		T60	27
all_values[5]	749	1			T17	21		T41	10		T60	27
all_values[6]	749	1			T17	21		T41	10		T60	27
all_values[7]	749	1			T17	21		T41	10		T60	27

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3161

1

T17

92

T41

53

T60

112

auto[1]

2831

1

T17

76

T41

27

T60

104

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2380

1

T17

62

T41

37

T60

88

auto[1]

3612

1

T17

106

T41

43

T60

128

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3457

1

T17

102

T41

46

T60

122

auto[1]

2535

1

T17

66

T41

34

T60

94

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	125	1			T17	5		T41	3		T60	1
all_values[0]	auto[0]	auto[0]	auto[1]	83	1			T17	2		T41	1		T60	3
all_values[0]	auto[0]	auto[1]	auto[0]	133	1			T17	6		T41	2		T60	8
all_values[0]	auto[0]	auto[1]	auto[1]	89	1			T17	3		T41	1		T60	2
all_values[0]	auto[1]	auto[0]	auto[1]	174	1			T17	4		T41	1		T60	9
all_values[0]	auto[1]	auto[1]	auto[1]	145	1			T17	1		T41	2		T60	4
all_values[1]	auto[0]	auto[0]	auto[0]	158	1			T17	2		T41	5		T60	11
all_values[1]	auto[0]	auto[0]	auto[1]	65	1			T17	3		T60	1		T149	1
all_values[1]	auto[0]	auto[1]	auto[0]	131	1			T17	2		T60	1		T77	1
all_values[1]	auto[0]	auto[1]	auto[1]	82	1			T17	3		T60	3		T155	3
all_values[1]	auto[1]	auto[0]	auto[1]	170	1			T17	5		T41	3		T60	3
all_values[1]	auto[1]	auto[1]	auto[1]	143	1			T17	6		T41	2		T60	8
all_values[2]	auto[0]	auto[0]	auto[0]	169	1			T17	2		T41	3		T60	3
all_values[2]	auto[0]	auto[0]	auto[1]	86	1			T17	5		T41	1		T60	4
all_values[2]	auto[0]	auto[1]	auto[0]	120	1			T17	2		T60	7		T77	2
all_values[2]	auto[0]	auto[1]	auto[1]	69	1			T17	4		T60	2		T155	1
all_values[2]	auto[1]	auto[0]	auto[1]	154	1			T17	5		T41	5		T60	6
all_values[2]	auto[1]	auto[1]	auto[1]	151	1			T17	3		T41	1		T60	5
all_values[3]	auto[0]	auto[0]	auto[0]	170	1			T17	8		T41	3		T60	5
all_values[3]	auto[0]	auto[0]	auto[1]	72	1			T17	3		T41	2		T60	3
all_values[3]	auto[0]	auto[1]	auto[0]	126	1			T17	3		T41	1		T60	4
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T17	2		T60	2		T77	1
all_values[3]	auto[1]	auto[0]	auto[1]	161	1			T17	3		T41	3		T60	3
all_values[3]	auto[1]	auto[1]	auto[1]	148	1			T17	2		T41	1		T60	10
all_values[4]	auto[0]	auto[0]	auto[0]	156	1			T17	3		T41	3		T60	7
all_values[4]	auto[0]	auto[0]	auto[1]	75	1			T17	2		T41	2		T60	2
all_values[4]	auto[0]	auto[1]	auto[0]	107	1			T17	4		T60	6		T149	2
all_values[4]	auto[0]	auto[1]	auto[1]	83	1			T17	3		T77	2		T155	1
all_values[4]	auto[1]	auto[0]	auto[1]	174	1			T17	6		T41	4		T60	9
all_values[4]	auto[1]	auto[1]	auto[1]	154	1			T17	3		T41	1		T60	3
all_values[5]	auto[0]	auto[0]	auto[0]	210	1			T17	8		T41	1		T60	10
all_values[5]	auto[0]	auto[1]	auto[0]	226	1			T17	3		T41	5		T60	10
all_values[5]	auto[1]	auto[0]	auto[1]	165	1			T17	8		T41	2		T60	3
all_values[5]	auto[1]	auto[1]	auto[1]	148	1			T17	2		T41	2		T60	4
all_values[6]	auto[0]	auto[0]	auto[0]	147	1			T17	3		T41	3		T60	1
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T17	1		T41	1		T60	5
all_values[6]	auto[0]	auto[1]	auto[0]	124	1			T17	5		T41	4		T60	3
all_values[6]	auto[0]	auto[1]	auto[1]	73	1			T17	2		T60	3		T149	3
all_values[6]	auto[1]	auto[0]	auto[1]	178	1			T17	5		T41	1		T60	5
all_values[6]	auto[1]	auto[1]	auto[1]	153	1			T17	5		T41	1		T60	10
all_values[7]	auto[0]	auto[0]	auto[0]	154	1			T17	3		T41	3		T60	6
all_values[7]	auto[0]	auto[0]	auto[1]	75	1			T17	3		T60	3		T155	4
all_values[7]	auto[0]	auto[1]	auto[0]	124	1			T17	3		T41	1		T60	5
all_values[7]	auto[0]	auto[1]	auto[1]	79	1			T17	4		T41	1		T60	1
all_values[7]	auto[1]	auto[0]	auto[1]	166	1			T17	3		T41	3		T60	9
all_values[7]	auto[1]	auto[1]	auto[1]	151	1			T17	5		T41	2		T60	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal