Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3364928	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3700758

1

T1

954

T2

2

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3949570	1			T1	131		T2	3		T3	27
values[0x0]	1556558	1			T1	446		T3	8		T5	415
values[0x1]	1559558	1			T1	443		T3	11		T5	463

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2383457	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4682229

1

T1

966

T2

3

T3

23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26885	1			T1	13		T5	1		T6	139
valid_sources[0x01]	25503	1			T5	3		T6	134		T7	3
valid_sources[0x02]	27827	1			T1	2		T5	4		T6	138
valid_sources[0x03]	31881	1			T1	6		T3	1		T5	6
valid_sources[0x04]	30294	1			T3	1		T5	7		T6	122
valid_sources[0x05]	25206	1			T4	10		T5	3		T6	132
valid_sources[0x06]	27795	1			T5	1		T6	127		T7	1
valid_sources[0x07]	29433	1			T1	10		T5	3		T6	114
valid_sources[0x08]	26584	1			T3	1		T5	6		T6	98
valid_sources[0x09]	28149	1			T1	8		T5	4		T6	134
valid_sources[0x0a]	27715	1			T5	2		T6	150		T7	2
valid_sources[0x0b]	25146	1			T1	10		T5	3		T6	127
valid_sources[0x0c]	25020	1			T5	7		T6	121		T7	1
valid_sources[0x0d]	30494	1			T5	2		T6	154		T7	3
valid_sources[0x0e]	25722	1			T6	113		T8	5		T9	7
valid_sources[0x0f]	24301	1			T1	5		T5	10		T6	130
valid_sources[0x10]	27352	1			T5	7		T6	137		T8	4
valid_sources[0x11]	32555	1			T1	8		T5	6		T6	132
valid_sources[0x12]	30542	1			T5	3		T6	128		T7	3
valid_sources[0x13]	24654	1			T5	4		T6	139		T8	2
valid_sources[0x14]	27187	1			T1	17		T5	5		T6	129
valid_sources[0x15]	42440	1			T1	22		T5	2		T6	111
valid_sources[0x16]	29829	1			T5	4		T6	118		T7	1
valid_sources[0x17]	25818	1			T5	6		T6	113		T8	10
valid_sources[0x18]	30971	1			T5	7		T6	108		T7	2
valid_sources[0x19]	27749	1			T1	5		T3	1		T5	4
valid_sources[0x1a]	27746	1			T1	11		T3	1		T5	6
valid_sources[0x1b]	25353	1			T1	8		T5	1		T6	105
valid_sources[0x1c]	29818	1			T5	1		T6	141		T8	3
valid_sources[0x1d]	31374	1			T1	1		T5	2		T6	147
valid_sources[0x1e]	26192	1			T1	11		T5	5		T6	128
valid_sources[0x1f]	25689	1			T1	23		T5	6		T6	116
valid_sources[0x20]	26186	1			T5	2		T6	131		T7	4
valid_sources[0x21]	25552	1			T5	7		T6	139		T7	1
valid_sources[0x22]	27129	1			T1	30		T5	2		T6	140
valid_sources[0x23]	25302	1			T1	1		T5	3		T6	141
valid_sources[0x24]	28280	1			T5	4		T6	121		T8	1
valid_sources[0x25]	25295	1			T1	2		T5	1		T6	120
valid_sources[0x26]	27749	1			T5	3		T6	135		T8	2
valid_sources[0x27]	23915	1			T4	1		T5	3		T6	123
valid_sources[0x28]	25839	1			T1	1		T5	3		T6	129
valid_sources[0x29]	27534	1			T1	7		T5	6		T6	148
valid_sources[0x2a]	26337	1			T3	1		T5	3		T6	151
valid_sources[0x2b]	27763	1			T1	4		T5	6		T6	135
valid_sources[0x2c]	26337	1			T3	2		T5	5		T6	137
valid_sources[0x2d]	30367	1			T5	2		T6	135		T8	5
valid_sources[0x2e]	27658	1			T5	2		T6	142		T8	8
valid_sources[0x2f]	28476	1			T1	35		T5	4		T6	142
valid_sources[0x30]	27701	1			T1	39		T3	1		T5	7
valid_sources[0x31]	28766	1			T1	5		T5	2		T6	115
valid_sources[0x32]	26346	1			T3	1		T5	3		T6	128
valid_sources[0x33]	34049	1			T5	5		T6	91		T8	2
valid_sources[0x34]	25601	1			T5	9		T6	120		T8	11
valid_sources[0x35]	27609	1			T5	3		T6	132		T8	1
valid_sources[0x36]	26983	1			T1	23		T5	2		T6	124
valid_sources[0x37]	26346	1			T5	4		T6	113		T7	1
valid_sources[0x38]	25049	1			T4	1		T5	1		T6	125
valid_sources[0x39]	29991	1			T5	3		T6	115		T7	2
valid_sources[0x3a]	25016	1			T3	1		T5	5		T6	124
valid_sources[0x3b]	25770	1			T5	3		T6	154		T8	9
valid_sources[0x3c]	25300	1			T5	3		T6	119		T7	1
valid_sources[0x3d]	27070	1			T1	11		T5	6		T6	114
valid_sources[0x3e]	28727	1			T5	4		T6	126		T8	4
valid_sources[0x3f]	25310	1			T5	3		T6	132		T8	2
valid_sources[0x40]	30037	1			T1	1		T5	9		T6	126
valid_sources[0x41]	29524	1			T1	5		T3	1		T4	10
valid_sources[0x42]	25528	1			T5	6		T6	124		T7	1
valid_sources[0x43]	26651	1			T1	15		T5	4		T6	138
valid_sources[0x44]	24664	1			T1	15		T5	3		T6	144
valid_sources[0x45]	26237	1			T3	1		T5	8		T6	136
valid_sources[0x46]	26635	1			T1	2		T5	2		T6	133
valid_sources[0x47]	25396	1			T1	26		T5	5		T6	132
valid_sources[0x48]	26225	1			T1	1		T5	6		T6	122
valid_sources[0x49]	25983	1			T1	39		T5	1		T6	129
valid_sources[0x4a]	25124	1			T5	5		T6	128		T8	1
valid_sources[0x4b]	27735	1			T5	2		T6	126		T8	3
valid_sources[0x4c]	26528	1			T5	6		T6	118		T7	3
valid_sources[0x4d]	27809	1			T5	9		T6	129		T9	5
valid_sources[0x4e]	26254	1			T1	6		T5	2		T6	124
valid_sources[0x4f]	26583	1			T1	4		T5	5		T6	130
valid_sources[0x50]	25774	1			T5	4		T6	127		T8	2
valid_sources[0x51]	28355	1			T5	6		T6	127		T8	5
valid_sources[0x52]	39112	1			T1	5		T5	2		T6	149
valid_sources[0x53]	29107	1			T1	13		T5	3		T6	123
valid_sources[0x54]	25902	1			T1	8		T6	118		T7	4
valid_sources[0x55]	26657	1			T1	4		T5	7		T6	150
valid_sources[0x56]	28560	1			T5	2		T6	131		T7	1
valid_sources[0x57]	25571	1			T1	11		T5	2		T6	128
valid_sources[0x58]	28498	1			T5	3		T6	131		T8	2
valid_sources[0x59]	29166	1			T1	3		T5	4		T6	151
valid_sources[0x5a]	27950	1			T5	3		T6	136		T7	2
valid_sources[0x5b]	25667	1			T1	1		T3	3		T5	6
valid_sources[0x5c]	29828	1			T3	1		T5	2		T6	136
valid_sources[0x5d]	25591	1			T5	3		T6	119		T7	3
valid_sources[0x5e]	27373	1			T1	7		T5	8		T6	135
valid_sources[0x5f]	23611	1			T1	25		T5	1		T6	142
valid_sources[0x60]	29980	1			T3	1		T5	2		T6	106
valid_sources[0x61]	24108	1			T5	1		T6	136		T8	2
valid_sources[0x62]	26658	1			T1	17		T5	4		T6	127
valid_sources[0x63]	25272	1			T1	2		T3	1		T5	1
valid_sources[0x64]	26522	1			T1	19		T5	1		T6	123
valid_sources[0x65]	25849	1			T5	4		T6	104		T7	1
valid_sources[0x66]	25484	1			T5	6		T6	122		T8	2
valid_sources[0x67]	27086	1			T1	4		T5	6		T6	124
valid_sources[0x68]	29033	1			T5	5		T6	123		T7	1
valid_sources[0x69]	38468	1			T1	13		T2	3		T5	1
valid_sources[0x6a]	26640	1			T5	2		T6	139		T9	3
valid_sources[0x6b]	26684	1			T5	1		T6	110		T7	1
valid_sources[0x6c]	34117	1			T5	1		T6	107		T7	4
valid_sources[0x6d]	28179	1			T1	5		T5	5		T6	126
valid_sources[0x6e]	25267	1			T5	3		T6	130		T7	2
valid_sources[0x6f]	28206	1			T5	5		T6	127		T7	1
valid_sources[0x70]	24935	1			T3	1		T5	1		T6	110
valid_sources[0x71]	25177	1			T1	1		T5	8		T6	117
valid_sources[0x72]	25582	1			T5	7		T6	146		T8	4
valid_sources[0x73]	25974	1			T1	6		T5	2		T6	122
valid_sources[0x74]	28379	1			T5	2		T6	125		T7	3
valid_sources[0x75]	26137	1			T5	6		T6	112		T8	2
valid_sources[0x76]	41817	1			T1	14		T6	117		T7	1
valid_sources[0x77]	29014	1			T1	9		T5	3		T6	149
valid_sources[0x78]	26871	1			T1	10		T5	4		T6	150
valid_sources[0x79]	24878	1			T1	8		T5	5		T6	137
valid_sources[0x7a]	25518	1			T5	2		T6	121		T7	3
valid_sources[0x7b]	24094	1			T5	6		T6	119		T7	1
valid_sources[0x7c]	25134	1			T5	6		T6	129		T7	2
valid_sources[0x7d]	27340	1			T5	9		T6	113		T9	3
valid_sources[0x7e]	26791	1			T5	4		T6	133		T7	1
valid_sources[0x7f]	27664	1			T5	3		T6	147		T7	2
valid_sources[0x80]	28128	1			T4	8		T5	5		T6	123

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

910443

1

T1

68

T2

2

T3

12

values[0x0]

all_enables

biggest_size

1406490

1

T1

445

T3

4

T5

414

values[0x1]

all_enables

biggest_size

1383825

1

T1

441

T3

4

T5

461