Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3390371

1

T1

66

T2

1

T3

26

full_word

3702191

1

T1

954

T2

2

T3

20

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7092192	1			T1	1020		T2	3		T3	46
auto[TlIntgErrCmd]	115	1			T61	8		T86	1		T87	5
auto[TlIntgErrData]	122	1			T61	5		T86	1		T87	11
auto[TlIntgErrBoth]	133	1			T61	7		T86	8		T87	14

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3953856

1

T1

131

T2

3

T3

27

auto[1]

3138706

1

T1

889

T3

19

T5

878

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3042907	1			T1	63		T2	1		T3	15
auto[TlIntgErrNone]	partial	auto[1]	347122	1			T1	3		T3	11		T5	3
auto[TlIntgErrNone]	full_word	auto[0]	910792	1			T1	68		T2	2		T3	12
auto[TlIntgErrNone]	full_word	auto[1]	2791371	1			T1	886		T3	8		T5	875
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T61	2		T86	1		T87	2
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T61	5		T87	3		T158	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T159	1		T160	1		T161	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T61	1		T162	1		T157	3
auto[TlIntgErrData]	partial	auto[0]	54	1			T61	3		T86	1		T87	2
auto[TlIntgErrData]	partial	auto[1]	60	1			T61	2		T87	9		T158	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T163	1		T164	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T162	3		T165	2		T166	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T61	5		T86	3		T87	9
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T61	2		T86	5		T87	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T87	1		T157	1		T165	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T87	2		T160	1		-	-