Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	472881610	2648589	0	0
gen_wmask[1].MaskCheckPortA_A	472881610	2648589	0	0
gen_wmask[2].MaskCheckPortA_A	472881610	2648589	0	0
gen_wmask[3].MaskCheckPortA_A	472881610	2648589	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472881610	2648589	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	2508	39	0	0
T4	1426	0	0	0
T5	111196	832	0	0
T6	292873	33206	0	0
T7	10830	230	0	0
T8	47216	832	0	0
T9	80048	832	0	0
T10	1243342	17175	0	0
T11	720	0	0	0
T12	19121	832	0	0
T13	33252	832	0	0
T18	0	382	0	0
T20	0	2319	0	0
T23	0	2081	0	0
T24	0	396	0	0
T25	0	16	0	0
T26	0	9682	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472881610	2648589	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	2508	39	0	0
T4	1426	0	0	0
T5	111196	832	0	0
T6	292873	33206	0	0
T7	10830	230	0	0
T8	47216	832	0	0
T9	80048	832	0	0
T10	1243342	17175	0	0
T11	720	0	0	0
T12	19121	832	0	0
T13	33252	832	0	0
T18	0	382	0	0
T20	0	2319	0	0
T23	0	2081	0	0
T24	0	396	0	0
T25	0	16	0	0
T26	0	9682	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472881610	2648589	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	2508	39	0	0
T4	1426	0	0	0
T5	111196	832	0	0
T6	292873	33206	0	0
T7	10830	230	0	0
T8	47216	832	0	0
T9	80048	832	0	0
T10	1243342	17175	0	0
T11	720	0	0	0
T12	19121	832	0	0
T13	33252	832	0	0
T18	0	382	0	0
T20	0	2319	0	0
T23	0	2081	0	0
T24	0	396	0	0
T25	0	16	0	0
T26	0	9682	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	472881610	2648589	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	2508	39	0	0
T4	1426	0	0	0
T5	111196	832	0	0
T6	292873	33206	0	0
T7	10830	230	0	0
T8	47216	832	0	0
T9	80048	832	0	0
T10	1243342	17175	0	0
T11	720	0	0	0
T12	19121	832	0	0
T13	33252	832	0	0
T18	0	382	0	0
T20	0	2319	0	0
T23	0	2081	0	0
T24	0	396	0	0
T25	0	16	0	0
T26	0	9682	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T3,T5

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	343305414	1744659	0	0
gen_wmask[1].MaskCheckPortA_A	343305414	1744659	0	0
gen_wmask[2].MaskCheckPortA_A	343305414	1744659	0	0
gen_wmask[3].MaskCheckPortA_A	343305414	1744659	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	1744659	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	1564	5	0	0
T4	1426	0	0	0
T5	90156	832	0	0
T6	150128	14682	0	0
T7	7082	19	0	0
T8	12186	832	0	0
T9	71636	832	0	0
T10	415457	14897	0	0
T12	0	832	0	0
T13	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	1744659	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	1564	5	0	0
T4	1426	0	0	0
T5	90156	832	0	0
T6	150128	14682	0	0
T7	7082	19	0	0
T8	12186	832	0	0
T9	71636	832	0	0
T10	415457	14897	0	0
T12	0	832	0	0
T13	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	1744659	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	1564	5	0	0
T4	1426	0	0	0
T5	90156	832	0	0
T6	150128	14682	0	0
T7	7082	19	0	0
T8	12186	832	0	0
T9	71636	832	0	0
T10	415457	14897	0	0
T12	0	832	0	0
T13	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	1744659	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	1564	5	0	0
T4	1426	0	0	0
T5	90156	832	0	0
T6	150128	14682	0	0
T7	7082	19	0	0
T8	12186	832	0	0
T9	71636	832	0	0
T10	415457	14897	0	0
T12	0	832	0	0
T13	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	129576196	903930	0	0
gen_wmask[1].MaskCheckPortA_A	129576196	903930	0	0
gen_wmask[2].MaskCheckPortA_A	129576196	903930	0	0
gen_wmask[3].MaskCheckPortA_A	129576196	903930	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	903930	0	0
T3	944	34	0	0
T5	21040	0	0	0
T6	142745	18524	0	0
T7	3748	211	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	2278	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T18	0	382	0	0
T20	0	2319	0	0
T23	0	2081	0	0
T24	0	396	0	0
T25	0	16	0	0
T26	0	9682	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	903930	0	0
T3	944	34	0	0
T5	21040	0	0	0
T6	142745	18524	0	0
T7	3748	211	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	2278	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T18	0	382	0	0
T20	0	2319	0	0
T23	0	2081	0	0
T24	0	396	0	0
T25	0	16	0	0
T26	0	9682	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	903930	0	0
T3	944	34	0	0
T5	21040	0	0	0
T6	142745	18524	0	0
T7	3748	211	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	2278	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T18	0	382	0	0
T20	0	2319	0	0
T23	0	2081	0	0
T24	0	396	0	0
T25	0	16	0	0
T26	0	9682	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	903930	0	0
T3	944	34	0	0
T5	21040	0	0	0
T6	142745	18524	0	0
T7	3748	211	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	2278	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T18	0	382	0	0
T20	0	2319	0	0
T23	0	2081	0	0
T24	0	396	0	0
T25	0	16	0	0
T26	0	9682	0	0