Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Unreachable
1	1	Covered	T3,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T10,T18

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T18
1	0	Covered	T6,T10,T18

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Covered	T6,T10,T18

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	602457806	471516132	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	602457806	3018059	0	0
GntImpliesValid_A	602457806	3018059	0	0
GrantKnown_A	602457806	471516132	0	0
IdxKnown_A	602457806	471516132	0	0
IndexIsCorrect_A	602457806	3018059	0	0
LockArbDecision_A	602457806	0	0	0
NoReadyValidNoGrant_A	602457806	0	0	0
ReadyAndValidImplyGrant_A	602457806	3018059	0	0
ReqAndReadyImplyGrant_A	602457806	3018059	0	0
ReqImpliesValid_A	602457806	3018059	0	0
ReqStaysHighUntilGranted0_M	602457806	0	0	0
RoundRobin_A	602457806	4	0	906
ValidKnown_A	602457806	471516132	0	0
gen_data_port_assertion.DataFlow_A	602457806	3018059	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602457806	471516132	0	0
T1	127183	126690	0	0
T2	1180	1123	0	0
T3	3452	2435	0	0
T4	1426	1356	0	0
T5	132236	111130	0	0
T6	435618	485135	0	0
T7	14578	10387	0	0
T8	82246	47163	0	0
T9	88460	79964	0	0
T10	2071227	1234848	0	0
T11	1440	720	0	0
T12	38242	18704	0	0
T13	33252	33252	0	0
T14	0	31904	0	0
T15	0	864	0	0
T17	0	24704	0	0
T18	0	35264	0	0
T19	0	37528	0	0
T20	0	316264	0	0
T23	0	228056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602457806	3018059	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	2508	54	0	0
T4	1426	0	0	0
T5	111196	832	0	0
T6	435618	36402	0	0
T7	14578	304	0	0
T8	82246	832	0	0
T9	88460	832	0	0
T10	2071227	18481	0	0
T11	1440	0	0	0
T12	38242	832	0	0
T13	66504	832	0	0
T14	32622	0	0	0
T18	0	604	0	0
T19	37716	0	0	0
T20	0	3484	0	0
T23	0	3413	0	0
T24	0	449	0	0
T25	0	49	0	0
T26	0	11111	0	0
T28	0	143	0	0
T43	0	2326	0	0
T44	0	4989	0	0
T45	0	2389	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602457806	3018059	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	2508	54	0	0
T4	1426	0	0	0
T5	111196	832	0	0
T6	435618	36402	0	0
T7	14578	304	0	0
T8	82246	832	0	0
T9	88460	832	0	0
T10	2071227	18481	0	0
T11	1440	0	0	0
T12	38242	832	0	0
T13	66504	832	0	0
T14	32622	0	0	0
T18	0	604	0	0
T19	37716	0	0	0
T20	0	3484	0	0
T23	0	3413	0	0
T24	0	449	0	0
T25	0	49	0	0
T26	0	11111	0	0
T28	0	143	0	0
T43	0	2326	0	0
T44	0	4989	0	0
T45	0	2389	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602457806	471516132	0	0
T1	127183	126690	0	0
T2	1180	1123	0	0
T3	3452	2435	0	0
T4	1426	1356	0	0
T5	132236	111130	0	0
T6	435618	485135	0	0
T7	14578	10387	0	0
T8	82246	47163	0	0
T9	88460	79964	0	0
T10	2071227	1234848	0	0
T11	1440	720	0	0
T12	38242	18704	0	0
T13	33252	33252	0	0
T14	0	31904	0	0
T15	0	864	0	0
T17	0	24704	0	0
T18	0	35264	0	0
T19	0	37528	0	0
T20	0	316264	0	0
T23	0	228056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602457806	471516132	0	0
T1	127183	126690	0	0
T2	1180	1123	0	0
T3	3452	2435	0	0
T4	1426	1356	0	0
T5	132236	111130	0	0
T6	435618	485135	0	0
T7	14578	10387	0	0
T8	82246	47163	0	0
T9	88460	79964	0	0
T10	2071227	1234848	0	0
T11	1440	720	0	0
T12	38242	18704	0	0
T13	33252	33252	0	0
T14	0	31904	0	0
T15	0	864	0	0
T17	0	24704	0	0
T18	0	35264	0	0
T19	0	37528	0	0
T20	0	316264	0	0
T23	0	228056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602457806	3018059	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	2508	54	0	0
T4	1426	0	0	0
T5	111196	832	0	0
T6	435618	36402	0	0
T7	14578	304	0	0
T8	82246	832	0	0
T9	88460	832	0	0
T10	2071227	18481	0	0
T11	1440	0	0	0
T12	38242	832	0	0
T13	66504	832	0	0
T14	32622	0	0	0
T18	0	604	0	0
T19	37716	0	0	0
T20	0	3484	0	0
T23	0	3413	0	0
T24	0	449	0	0
T25	0	49	0	0
T26	0	11111	0	0
T28	0	143	0	0
T43	0	2326	0	0
T44	0	4989	0	0
T45	0	2389	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602457806	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602457806	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602457806	3018059	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	2508	54	0	0
T4	1426	0	0	0
T5	111196	832	0	0
T6	435618	36402	0	0
T7	14578	304	0	0
T8	82246	832	0	0
T9	88460	832	0	0
T10	2071227	18481	0	0
T11	1440	0	0	0
T12	38242	832	0	0
T13	66504	832	0	0
T14	32622	0	0	0
T18	0	604	0	0
T19	37716	0	0	0
T20	0	3484	0	0
T23	0	3413	0	0
T24	0	449	0	0
T25	0	49	0	0
T26	0	11111	0	0
T28	0	143	0	0
T43	0	2326	0	0
T44	0	4989	0	0
T45	0	2389	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602457806	3018059	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	2508	54	0	0
T4	1426	0	0	0
T5	111196	832	0	0
T6	435618	36402	0	0
T7	14578	304	0	0
T8	82246	832	0	0
T9	88460	832	0	0
T10	2071227	18481	0	0
T11	1440	0	0	0
T12	38242	832	0	0
T13	66504	832	0	0
T14	32622	0	0	0
T18	0	604	0	0
T19	37716	0	0	0
T20	0	3484	0	0
T23	0	3413	0	0
T24	0	449	0	0
T25	0	49	0	0
T26	0	11111	0	0
T28	0	143	0	0
T43	0	2326	0	0
T44	0	4989	0	0
T45	0	2389	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602457806	3018059	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	2508	54	0	0
T4	1426	0	0	0
T5	111196	832	0	0
T6	435618	36402	0	0
T7	14578	304	0	0
T8	82246	832	0	0
T9	88460	832	0	0
T10	2071227	18481	0	0
T11	1440	0	0	0
T12	38242	832	0	0
T13	66504	832	0	0
T14	32622	0	0	0
T18	0	604	0	0
T19	37716	0	0	0
T20	0	3484	0	0
T23	0	3413	0	0
T24	0	449	0	0
T25	0	49	0	0
T26	0	11111	0	0
T28	0	143	0	0
T43	0	2326	0	0
T44	0	4989	0	0
T45	0	2389	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	602457806	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602457806	4	0	906
T21	0	1	0	0
T34	271557	1	0	1
T35	340677	0	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	2822	0	0	1
T49	3726	0	0	1
T50	62217	0	0	1
T51	1061	0	0	1
T52	91876	0	0	1
T53	75441	0	0	1
T54	211346	0	0	1
T55	84734	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602457806	471516132	0	0
T1	127183	126690	0	0
T2	1180	1123	0	0
T3	3452	2435	0	0
T4	1426	1356	0	0
T5	132236	111130	0	0
T6	435618	485135	0	0
T7	14578	10387	0	0
T8	82246	47163	0	0
T9	88460	79964	0	0
T10	2071227	1234848	0	0
T11	1440	720	0	0
T12	38242	18704	0	0
T13	33252	33252	0	0
T14	0	31904	0	0
T15	0	864	0	0
T17	0	24704	0	0
T18	0	35264	0	0
T19	0	37528	0	0
T20	0	316264	0	0
T23	0	228056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	602457806	3018059	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	2508	54	0	0
T4	1426	0	0	0
T5	111196	832	0	0
T6	435618	36402	0	0
T7	14578	304	0	0
T8	82246	832	0	0
T9	88460	832	0	0
T10	2071227	18481	0	0
T11	1440	0	0	0
T12	38242	832	0	0
T13	66504	832	0	0
T14	32622	0	0	0
T18	0	604	0	0
T19	37716	0	0	0
T20	0	3484	0	0
T23	0	3413	0	0
T24	0	449	0	0
T25	0	49	0	0
T26	0	11111	0	0
T28	0	143	0	0
T43	0	2326	0	0
T44	0	4989	0	0
T45	0	2389	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Unreachable
1	1	Covered	T3,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T6,T7
0	0	1	Unreachable
0	0	0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	129576196	30518925	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	129576196	666144	0	0
GntImpliesValid_A	129576196	666144	0	0
GrantKnown_A	129576196	30518925	0	0
IdxKnown_A	129576196	30518925	0	0
IndexIsCorrect_A	129576196	666144	0	0
LockArbDecision_A	129576196	0	0	0
NoReadyValidNoGrant_A	129576196	0	0	0
ReadyAndValidImplyGrant_A	129576196	666144	0	0
ReqAndReadyImplyGrant_A	129576196	666144	0	0
ReqImpliesValid_A	129576196	666144	0	0
ReqStaysHighUntilGranted0_M	129576196	0	0	0
RoundRobin_A	129576196	0	0	0
ValidKnown_A	129576196	30518925	0	0
gen_data_port_assertion.DataFlow_A	129576196	666144	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	30518925	0	0
T3	944	944	0	0
T5	21040	0	0	0
T6	142745	214816	0	0
T7	3748	3360	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	173584	0	0
T11	720	720	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T15	0	864	0	0
T17	0	24704	0	0
T18	0	35264	0	0
T20	0	316264	0	0
T23	0	228056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	666144	0	0
T3	944	40	0	0
T5	21040	0	0	0
T6	142745	5139	0	0
T7	3748	232	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	1775	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T18	0	602	0	0
T20	0	3215	0	0
T23	0	3273	0	0
T24	0	449	0	0
T25	0	49	0	0
T26	0	4346	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	666144	0	0
T3	944	40	0	0
T5	21040	0	0	0
T6	142745	5139	0	0
T7	3748	232	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	1775	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T18	0	602	0	0
T20	0	3215	0	0
T23	0	3273	0	0
T24	0	449	0	0
T25	0	49	0	0
T26	0	4346	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	30518925	0	0
T3	944	944	0	0
T5	21040	0	0	0
T6	142745	214816	0	0
T7	3748	3360	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	173584	0	0
T11	720	720	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T15	0	864	0	0
T17	0	24704	0	0
T18	0	35264	0	0
T20	0	316264	0	0
T23	0	228056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	30518925	0	0
T3	944	944	0	0
T5	21040	0	0	0
T6	142745	214816	0	0
T7	3748	3360	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	173584	0	0
T11	720	720	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T15	0	864	0	0
T17	0	24704	0	0
T18	0	35264	0	0
T20	0	316264	0	0
T23	0	228056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	666144	0	0
T3	944	40	0	0
T5	21040	0	0	0
T6	142745	5139	0	0
T7	3748	232	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	1775	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T18	0	602	0	0
T20	0	3215	0	0
T23	0	3273	0	0
T24	0	449	0	0
T25	0	49	0	0
T26	0	4346	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	666144	0	0
T3	944	40	0	0
T5	21040	0	0	0
T6	142745	5139	0	0
T7	3748	232	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	1775	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T18	0	602	0	0
T20	0	3215	0	0
T23	0	3273	0	0
T24	0	449	0	0
T25	0	49	0	0
T26	0	4346	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	666144	0	0
T3	944	40	0	0
T5	21040	0	0	0
T6	142745	5139	0	0
T7	3748	232	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	1775	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T18	0	602	0	0
T20	0	3215	0	0
T23	0	3273	0	0
T24	0	449	0	0
T25	0	49	0	0
T26	0	4346	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	666144	0	0
T3	944	40	0	0
T5	21040	0	0	0
T6	142745	5139	0	0
T7	3748	232	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	1775	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T18	0	602	0	0
T20	0	3215	0	0
T23	0	3273	0	0
T24	0	449	0	0
T25	0	49	0	0
T26	0	4346	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	30518925	0	0
T3	944	944	0	0
T5	21040	0	0	0
T6	142745	214816	0	0
T7	3748	3360	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	173584	0	0
T11	720	720	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T15	0	864	0	0
T17	0	24704	0	0
T18	0	35264	0	0
T20	0	316264	0	0
T23	0	228056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	666144	0	0
T3	944	40	0	0
T5	21040	0	0	0
T6	142745	5139	0	0
T7	3748	232	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	1775	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T18	0	602	0	0
T20	0	3215	0	0
T23	0	3273	0	0
T24	0	449	0	0
T25	0	49	0	0
T26	0	4346	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T10,T18

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T18
1	0	Covered	T6,T10,T18

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Covered	T6,T10,T18

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T10,T18
0	0	1	Unreachable
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	129576196	97776275	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	129576196	455984	0	0
GntImpliesValid_A	129576196	455984	0	0
GrantKnown_A	129576196	97776275	0	0
IdxKnown_A	129576196	97776275	0	0
IndexIsCorrect_A	129576196	455984	0	0
LockArbDecision_A	129576196	0	0	0
NoReadyValidNoGrant_A	129576196	0	0	0
ReadyAndValidImplyGrant_A	129576196	455984	0	0
ReqAndReadyImplyGrant_A	129576196	455984	0	0
ReqImpliesValid_A	129576196	455984	0	0
ReqStaysHighUntilGranted0_M	129576196	0	0	0
RoundRobin_A	129576196	0	0	0
ValidKnown_A	129576196	97776275	0	0
gen_data_port_assertion.DataFlow_A	129576196	455984	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	97776275	0	0
T1	59294	58890	0	0
T3	944	0	0	0
T5	21040	21040	0	0
T6	142745	120213	0	0
T7	3748	0	0	0
T8	35030	35030	0	0
T9	8412	8412	0	0
T10	827885	645939	0	0
T11	720	0	0	0
T12	19121	18704	0	0
T13	0	33252	0	0
T14	0	31904	0	0
T19	0	37528	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	455984	0	0
T6	142745	14907	0	0
T7	3748	0	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	1325	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T14	32622	0	0	0
T18	0	2	0	0
T19	37716	0	0	0
T20	0	269	0	0
T23	0	140	0	0
T26	0	6765	0	0
T28	0	143	0	0
T43	0	2326	0	0
T44	0	4989	0	0
T45	0	2389	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	455984	0	0
T6	142745	14907	0	0
T7	3748	0	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	1325	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T14	32622	0	0	0
T18	0	2	0	0
T19	37716	0	0	0
T20	0	269	0	0
T23	0	140	0	0
T26	0	6765	0	0
T28	0	143	0	0
T43	0	2326	0	0
T44	0	4989	0	0
T45	0	2389	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	97776275	0	0
T1	59294	58890	0	0
T3	944	0	0	0
T5	21040	21040	0	0
T6	142745	120213	0	0
T7	3748	0	0	0
T8	35030	35030	0	0
T9	8412	8412	0	0
T10	827885	645939	0	0
T11	720	0	0	0
T12	19121	18704	0	0
T13	0	33252	0	0
T14	0	31904	0	0
T19	0	37528	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	97776275	0	0
T1	59294	58890	0	0
T3	944	0	0	0
T5	21040	21040	0	0
T6	142745	120213	0	0
T7	3748	0	0	0
T8	35030	35030	0	0
T9	8412	8412	0	0
T10	827885	645939	0	0
T11	720	0	0	0
T12	19121	18704	0	0
T13	0	33252	0	0
T14	0	31904	0	0
T19	0	37528	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	455984	0	0
T6	142745	14907	0	0
T7	3748	0	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	1325	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T14	32622	0	0	0
T18	0	2	0	0
T19	37716	0	0	0
T20	0	269	0	0
T23	0	140	0	0
T26	0	6765	0	0
T28	0	143	0	0
T43	0	2326	0	0
T44	0	4989	0	0
T45	0	2389	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	455984	0	0
T6	142745	14907	0	0
T7	3748	0	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	1325	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T14	32622	0	0	0
T18	0	2	0	0
T19	37716	0	0	0
T20	0	269	0	0
T23	0	140	0	0
T26	0	6765	0	0
T28	0	143	0	0
T43	0	2326	0	0
T44	0	4989	0	0
T45	0	2389	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	455984	0	0
T6	142745	14907	0	0
T7	3748	0	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	1325	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T14	32622	0	0	0
T18	0	2	0	0
T19	37716	0	0	0
T20	0	269	0	0
T23	0	140	0	0
T26	0	6765	0	0
T28	0	143	0	0
T43	0	2326	0	0
T44	0	4989	0	0
T45	0	2389	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	455984	0	0
T6	142745	14907	0	0
T7	3748	0	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	1325	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T14	32622	0	0	0
T18	0	2	0	0
T19	37716	0	0	0
T20	0	269	0	0
T23	0	140	0	0
T26	0	6765	0	0
T28	0	143	0	0
T43	0	2326	0	0
T44	0	4989	0	0
T45	0	2389	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	97776275	0	0
T1	59294	58890	0	0
T3	944	0	0	0
T5	21040	21040	0	0
T6	142745	120213	0	0
T7	3748	0	0	0
T8	35030	35030	0	0
T9	8412	8412	0	0
T10	827885	645939	0	0
T11	720	0	0	0
T12	19121	18704	0	0
T13	0	33252	0	0
T14	0	31904	0	0
T19	0	37528	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129576196	455984	0	0
T6	142745	14907	0	0
T7	3748	0	0	0
T8	35030	0	0	0
T9	8412	0	0	0
T10	827885	1325	0	0
T11	720	0	0	0
T12	19121	0	0	0
T13	33252	0	0	0
T14	32622	0	0	0
T18	0	2	0	0
T19	37716	0	0	0
T20	0	269	0	0
T23	0	140	0	0
T26	0	6765	0	0
T28	0	143	0	0
T43	0	2326	0	0
T44	0	4989	0	0
T45	0	2389	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	343305414	343220932	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	343305414	1895931	0	0
GntImpliesValid_A	343305414	1895931	0	0
GrantKnown_A	343305414	343220932	0	0
IdxKnown_A	343305414	343220932	0	0
IndexIsCorrect_A	343305414	1895931	0	0
LockArbDecision_A	343305414	0	0	0
NoReadyValidNoGrant_A	343305414	0	0	0
ReadyAndValidImplyGrant_A	343305414	1895931	0	0
ReqAndReadyImplyGrant_A	343305414	1895931	0	0
ReqImpliesValid_A	343305414	1895931	0	0
ReqStaysHighUntilGranted0_M	343305414	0	0	0
RoundRobin_A	343305414	4	0	906
ValidKnown_A	343305414	343220932	0	0
gen_data_port_assertion.DataFlow_A	343305414	1895931	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	343220932	0	0
T1	67889	67800	0	0
T2	1180	1123	0	0
T3	1564	1491	0	0
T4	1426	1356	0	0
T5	90156	90090	0	0
T6	150128	150106	0	0
T7	7082	7027	0	0
T8	12186	12133	0	0
T9	71636	71552	0	0
T10	415457	415325	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	1895931	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	1564	14	0	0
T4	1426	0	0	0
T5	90156	832	0	0
T6	150128	16356	0	0
T7	7082	72	0	0
T8	12186	832	0	0
T9	71636	832	0	0
T10	415457	15381	0	0
T12	0	832	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	1895931	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	1564	14	0	0
T4	1426	0	0	0
T5	90156	832	0	0
T6	150128	16356	0	0
T7	7082	72	0	0
T8	12186	832	0	0
T9	71636	832	0	0
T10	415457	15381	0	0
T12	0	832	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	343220932	0	0
T1	67889	67800	0	0
T2	1180	1123	0	0
T3	1564	1491	0	0
T4	1426	1356	0	0
T5	90156	90090	0	0
T6	150128	150106	0	0
T7	7082	7027	0	0
T8	12186	12133	0	0
T9	71636	71552	0	0
T10	415457	415325	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	343220932	0	0
T1	67889	67800	0	0
T2	1180	1123	0	0
T3	1564	1491	0	0
T4	1426	1356	0	0
T5	90156	90090	0	0
T6	150128	150106	0	0
T7	7082	7027	0	0
T8	12186	12133	0	0
T9	71636	71552	0	0
T10	415457	415325	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	1895931	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	1564	14	0	0
T4	1426	0	0	0
T5	90156	832	0	0
T6	150128	16356	0	0
T7	7082	72	0	0
T8	12186	832	0	0
T9	71636	832	0	0
T10	415457	15381	0	0
T12	0	832	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	1895931	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	1564	14	0	0
T4	1426	0	0	0
T5	90156	832	0	0
T6	150128	16356	0	0
T7	7082	72	0	0
T8	12186	832	0	0
T9	71636	832	0	0
T10	415457	15381	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	1895931	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	1564	14	0	0
T4	1426	0	0	0
T5	90156	832	0	0
T6	150128	16356	0	0
T7	7082	72	0	0
T8	12186	832	0	0
T9	71636	832	0	0
T10	415457	15381	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	1895931	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	1564	14	0	0
T4	1426	0	0	0
T5	90156	832	0	0
T6	150128	16356	0	0
T7	7082	72	0	0
T8	12186	832	0	0
T9	71636	832	0	0
T10	415457	15381	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	4	0	906
T21	0	1	0	0
T34	271557	1	0	1
T35	340677	0	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	2822	0	0	1
T49	3726	0	0	1
T50	62217	0	0	1
T51	1061	0	0	1
T52	91876	0	0	1
T53	75441	0	0	1
T54	211346	0	0	1
T55	84734	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	343220932	0	0
T1	67889	67800	0	0
T2	1180	1123	0	0
T3	1564	1491	0	0
T4	1426	1356	0	0
T5	90156	90090	0	0
T6	150128	150106	0	0
T7	7082	7027	0	0
T8	12186	12133	0	0
T9	71636	71552	0	0
T10	415457	415325	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343305414	1895931	0	0
T1	67889	832	0	0
T2	1180	0	0	0
T3	1564	14	0	0
T4	1426	0	0	0
T5	90156	832	0	0
T6	150128	16356	0	0
T7	7082	72	0	0
T8	12186	832	0	0
T9	71636	832	0	0
T10	415457	15381	0	0
T12	0	832	0	0
T13	0	832	0	0