| T814 |
/workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1984392202 |
|
|
May 30 03:42:02 PM PDT 24 |
May 30 03:47:43 PM PDT 24 |
64181109424 ps |
| T815 |
/workspace/coverage/default/10.spi_device_alert_test.2279884931 |
|
|
May 30 03:39:44 PM PDT 24 |
May 30 03:39:47 PM PDT 24 |
34833115 ps |
| T816 |
/workspace/coverage/default/14.spi_device_tpm_read_hw_reg.154569496 |
|
|
May 30 03:40:03 PM PDT 24 |
May 30 03:40:10 PM PDT 24 |
1977764728 ps |
| T817 |
/workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2477677854 |
|
|
May 30 03:40:40 PM PDT 24 |
May 30 03:41:13 PM PDT 24 |
22161811027 ps |
| T818 |
/workspace/coverage/default/19.spi_device_csb_read.2975275885 |
|
|
May 30 03:40:16 PM PDT 24 |
May 30 03:40:18 PM PDT 24 |
19309174 ps |
| T819 |
/workspace/coverage/default/7.spi_device_tpm_all.4252283608 |
|
|
May 30 03:39:37 PM PDT 24 |
May 30 03:39:44 PM PDT 24 |
733395562 ps |
| T820 |
/workspace/coverage/default/29.spi_device_cfg_cmd.3726632235 |
|
|
May 30 03:40:50 PM PDT 24 |
May 30 03:40:58 PM PDT 24 |
357906181 ps |
| T821 |
/workspace/coverage/default/46.spi_device_pass_addr_payload_swap.370351529 |
|
|
May 30 03:41:50 PM PDT 24 |
May 30 03:41:59 PM PDT 24 |
937780354 ps |
| T822 |
/workspace/coverage/default/19.spi_device_alert_test.1563925441 |
|
|
May 30 03:40:28 PM PDT 24 |
May 30 03:40:31 PM PDT 24 |
26727199 ps |
| T823 |
/workspace/coverage/default/31.spi_device_upload.149271896 |
|
|
May 30 03:40:53 PM PDT 24 |
May 30 03:40:59 PM PDT 24 |
861822198 ps |
| T824 |
/workspace/coverage/default/44.spi_device_csb_read.938672515 |
|
|
May 30 03:41:38 PM PDT 24 |
May 30 03:41:45 PM PDT 24 |
26550837 ps |
| T825 |
/workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3090390038 |
|
|
May 30 03:41:05 PM PDT 24 |
May 30 03:41:36 PM PDT 24 |
40725350549 ps |
| T826 |
/workspace/coverage/default/12.spi_device_pass_cmd_filtering.668080638 |
|
|
May 30 03:39:51 PM PDT 24 |
May 30 03:39:58 PM PDT 24 |
191832545 ps |
| T827 |
/workspace/coverage/default/22.spi_device_intercept.492705178 |
|
|
May 30 03:40:28 PM PDT 24 |
May 30 03:40:44 PM PDT 24 |
4598027419 ps |
| T828 |
/workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3701255119 |
|
|
May 30 03:39:19 PM PDT 24 |
May 30 03:41:54 PM PDT 24 |
44576565996 ps |
| T829 |
/workspace/coverage/default/40.spi_device_stress_all.2785571148 |
|
|
May 30 03:41:28 PM PDT 24 |
May 30 03:41:34 PM PDT 24 |
74066619 ps |
| T830 |
/workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.207337974 |
|
|
May 30 03:39:43 PM PDT 24 |
May 30 03:44:44 PM PDT 24 |
125887167028 ps |
| T831 |
/workspace/coverage/default/48.spi_device_cfg_cmd.3428387521 |
|
|
May 30 03:42:01 PM PDT 24 |
May 30 03:42:10 PM PDT 24 |
812530427 ps |
| T832 |
/workspace/coverage/default/34.spi_device_flash_and_tpm.2539176755 |
|
|
May 30 03:41:04 PM PDT 24 |
May 30 03:41:46 PM PDT 24 |
4188165167 ps |
| T833 |
/workspace/coverage/default/12.spi_device_tpm_rw.4218344761 |
|
|
May 30 03:39:54 PM PDT 24 |
May 30 03:40:00 PM PDT 24 |
177899756 ps |
| T834 |
/workspace/coverage/default/29.spi_device_pass_cmd_filtering.1090394913 |
|
|
May 30 03:40:54 PM PDT 24 |
May 30 03:41:01 PM PDT 24 |
917463487 ps |
| T835 |
/workspace/coverage/default/5.spi_device_alert_test.3013556784 |
|
|
May 30 03:39:32 PM PDT 24 |
May 30 03:39:35 PM PDT 24 |
107449446 ps |
| T836 |
/workspace/coverage/default/36.spi_device_cfg_cmd.3748541541 |
|
|
May 30 03:41:20 PM PDT 24 |
May 30 03:41:25 PM PDT 24 |
141669489 ps |
| T169 |
/workspace/coverage/default/41.spi_device_stress_all.2085441936 |
|
|
May 30 03:41:27 PM PDT 24 |
May 30 03:44:14 PM PDT 24 |
10564968550 ps |
| T276 |
/workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2370417497 |
|
|
May 30 03:40:28 PM PDT 24 |
May 30 03:41:54 PM PDT 24 |
3918649972 ps |
| T837 |
/workspace/coverage/default/38.spi_device_tpm_sts_read.4084293057 |
|
|
May 30 03:41:23 PM PDT 24 |
May 30 03:41:27 PM PDT 24 |
219831231 ps |
| T838 |
/workspace/coverage/default/36.spi_device_pass_addr_payload_swap.147278553 |
|
|
May 30 03:41:13 PM PDT 24 |
May 30 03:41:22 PM PDT 24 |
331045895 ps |
| T839 |
/workspace/coverage/default/11.spi_device_flash_all.728193836 |
|
|
May 30 03:39:50 PM PDT 24 |
May 30 03:42:49 PM PDT 24 |
140449453456 ps |
| T840 |
/workspace/coverage/default/25.spi_device_tpm_rw.82330324 |
|
|
May 30 03:40:33 PM PDT 24 |
May 30 03:40:38 PM PDT 24 |
101782986 ps |
| T841 |
/workspace/coverage/default/6.spi_device_stress_all.3905535478 |
|
|
May 30 03:39:42 PM PDT 24 |
May 30 03:42:40 PM PDT 24 |
80639780621 ps |
| T842 |
/workspace/coverage/default/46.spi_device_tpm_sts_read.153178612 |
|
|
May 30 03:41:51 PM PDT 24 |
May 30 03:41:56 PM PDT 24 |
48607402 ps |
| T843 |
/workspace/coverage/default/21.spi_device_flash_and_tpm.1523152285 |
|
|
May 30 03:40:20 PM PDT 24 |
May 30 03:41:39 PM PDT 24 |
4782223637 ps |
| T844 |
/workspace/coverage/default/34.spi_device_flash_mode.4054833538 |
|
|
May 30 03:41:03 PM PDT 24 |
May 30 03:41:41 PM PDT 24 |
2111906880 ps |
| T845 |
/workspace/coverage/default/2.spi_device_pass_cmd_filtering.349145831 |
|
|
May 30 03:39:22 PM PDT 24 |
May 30 03:39:28 PM PDT 24 |
1542226433 ps |
| T846 |
/workspace/coverage/default/16.spi_device_read_buffer_direct.2835835527 |
|
|
May 30 03:40:14 PM PDT 24 |
May 30 03:40:21 PM PDT 24 |
255307036 ps |
| T847 |
/workspace/coverage/default/18.spi_device_cfg_cmd.3711454897 |
|
|
May 30 03:40:15 PM PDT 24 |
May 30 03:40:19 PM PDT 24 |
110486018 ps |
| T848 |
/workspace/coverage/default/0.spi_device_alert_test.814808831 |
|
|
May 30 03:39:20 PM PDT 24 |
May 30 03:39:24 PM PDT 24 |
71175548 ps |
| T849 |
/workspace/coverage/default/14.spi_device_intercept.1563927666 |
|
|
May 30 03:40:02 PM PDT 24 |
May 30 03:40:24 PM PDT 24 |
4701784002 ps |
| T850 |
/workspace/coverage/default/9.spi_device_alert_test.2850589885 |
|
|
May 30 03:39:41 PM PDT 24 |
May 30 03:39:43 PM PDT 24 |
15011151 ps |
| T851 |
/workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1972295090 |
|
|
May 30 03:40:41 PM PDT 24 |
May 30 03:40:59 PM PDT 24 |
6020375749 ps |
| T852 |
/workspace/coverage/default/42.spi_device_tpm_all.972506027 |
|
|
May 30 03:41:27 PM PDT 24 |
May 30 03:41:45 PM PDT 24 |
3308720689 ps |
| T146 |
/workspace/coverage/default/19.spi_device_stress_all.3288846359 |
|
|
May 30 03:40:27 PM PDT 24 |
May 30 03:40:30 PM PDT 24 |
84861623 ps |
| T853 |
/workspace/coverage/default/2.spi_device_flash_mode.3840332902 |
|
|
May 30 03:39:17 PM PDT 24 |
May 30 03:39:24 PM PDT 24 |
1049304160 ps |
| T854 |
/workspace/coverage/default/47.spi_device_tpm_sts_read.2901490361 |
|
|
May 30 03:41:59 PM PDT 24 |
May 30 03:42:02 PM PDT 24 |
37130760 ps |
| T855 |
/workspace/coverage/default/37.spi_device_intercept.3876225293 |
|
|
May 30 03:41:12 PM PDT 24 |
May 30 03:41:32 PM PDT 24 |
9715844703 ps |
| T856 |
/workspace/coverage/default/48.spi_device_mailbox.489580229 |
|
|
May 30 03:41:59 PM PDT 24 |
May 30 03:43:31 PM PDT 24 |
10102756677 ps |
| T857 |
/workspace/coverage/default/39.spi_device_tpm_all.386159274 |
|
|
May 30 03:41:22 PM PDT 24 |
May 30 03:41:54 PM PDT 24 |
4165826551 ps |
| T47 |
/workspace/coverage/default/17.spi_device_flash_and_tpm.3866391563 |
|
|
May 30 03:40:12 PM PDT 24 |
May 30 03:41:33 PM PDT 24 |
22539581406 ps |
| T858 |
/workspace/coverage/default/39.spi_device_upload.997649077 |
|
|
May 30 03:41:20 PM PDT 24 |
May 30 03:41:30 PM PDT 24 |
3128545768 ps |
| T859 |
/workspace/coverage/default/16.spi_device_pass_cmd_filtering.309998871 |
|
|
May 30 03:40:01 PM PDT 24 |
May 30 03:40:10 PM PDT 24 |
3783053059 ps |
| T860 |
/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4193093018 |
|
|
May 30 03:39:34 PM PDT 24 |
May 30 03:39:37 PM PDT 24 |
10775695 ps |
| T861 |
/workspace/coverage/default/45.spi_device_stress_all.2094582090 |
|
|
May 30 03:41:51 PM PDT 24 |
May 30 03:42:57 PM PDT 24 |
13396055146 ps |
| T862 |
/workspace/coverage/default/8.spi_device_csb_read.3122603412 |
|
|
May 30 03:39:41 PM PDT 24 |
May 30 03:39:44 PM PDT 24 |
174346329 ps |
| T863 |
/workspace/coverage/default/11.spi_device_pass_cmd_filtering.196077398 |
|
|
May 30 03:39:53 PM PDT 24 |
May 30 03:40:10 PM PDT 24 |
11703073822 ps |
| T864 |
/workspace/coverage/default/43.spi_device_upload.500285465 |
|
|
May 30 03:41:40 PM PDT 24 |
May 30 03:41:51 PM PDT 24 |
611345630 ps |
| T271 |
/workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1257712569 |
|
|
May 30 03:41:27 PM PDT 24 |
May 30 03:41:50 PM PDT 24 |
9968295391 ps |
| T865 |
/workspace/coverage/default/0.spi_device_read_buffer_direct.1381730317 |
|
|
May 30 03:39:20 PM PDT 24 |
May 30 03:39:36 PM PDT 24 |
1811434871 ps |
| T866 |
/workspace/coverage/default/48.spi_device_tpm_all.3355910300 |
|
|
May 30 03:42:00 PM PDT 24 |
May 30 03:42:30 PM PDT 24 |
28066160085 ps |
| T867 |
/workspace/coverage/default/34.spi_device_pass_cmd_filtering.1145620079 |
|
|
May 30 03:41:08 PM PDT 24 |
May 30 03:41:14 PM PDT 24 |
1898456096 ps |
| T868 |
/workspace/coverage/default/38.spi_device_flash_and_tpm.531196148 |
|
|
May 30 03:41:20 PM PDT 24 |
May 30 03:43:23 PM PDT 24 |
10509303842 ps |
| T869 |
/workspace/coverage/default/21.spi_device_mailbox.612921628 |
|
|
May 30 03:40:27 PM PDT 24 |
May 30 03:40:32 PM PDT 24 |
175711086 ps |
| T870 |
/workspace/coverage/default/34.spi_device_stress_all.325953798 |
|
|
May 30 03:41:12 PM PDT 24 |
May 30 03:42:56 PM PDT 24 |
20427712754 ps |
| T871 |
/workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3980238894 |
|
|
May 30 03:40:27 PM PDT 24 |
May 30 03:40:35 PM PDT 24 |
3704509323 ps |
| T872 |
/workspace/coverage/default/33.spi_device_csb_read.441261964 |
|
|
May 30 03:41:05 PM PDT 24 |
May 30 03:41:08 PM PDT 24 |
46927948 ps |
| T873 |
/workspace/coverage/default/35.spi_device_flash_mode.2187487310 |
|
|
May 30 03:41:11 PM PDT 24 |
May 30 03:41:35 PM PDT 24 |
13158973107 ps |
| T874 |
/workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1375176624 |
|
|
May 30 03:39:20 PM PDT 24 |
May 30 03:39:29 PM PDT 24 |
4742764902 ps |
| T875 |
/workspace/coverage/default/42.spi_device_tpm_sts_read.4029984060 |
|
|
May 30 03:41:27 PM PDT 24 |
May 30 03:41:33 PM PDT 24 |
94206161 ps |
| T876 |
/workspace/coverage/default/41.spi_device_tpm_sts_read.1387840960 |
|
|
May 30 03:41:32 PM PDT 24 |
May 30 03:41:38 PM PDT 24 |
28588207 ps |
| T877 |
/workspace/coverage/default/45.spi_device_pass_cmd_filtering.740307426 |
|
|
May 30 03:41:42 PM PDT 24 |
May 30 03:41:56 PM PDT 24 |
2063884155 ps |
| T878 |
/workspace/coverage/default/45.spi_device_tpm_read_hw_reg.237101944 |
|
|
May 30 03:41:44 PM PDT 24 |
May 30 03:41:53 PM PDT 24 |
586745718 ps |
| T879 |
/workspace/coverage/default/27.spi_device_alert_test.1488281490 |
|
|
May 30 03:40:41 PM PDT 24 |
May 30 03:40:45 PM PDT 24 |
47075295 ps |
| T880 |
/workspace/coverage/default/12.spi_device_tpm_all.2951847957 |
|
|
May 30 03:39:51 PM PDT 24 |
May 30 03:40:20 PM PDT 24 |
27935539712 ps |
| T881 |
/workspace/coverage/default/5.spi_device_upload.565588778 |
|
|
May 30 03:39:30 PM PDT 24 |
May 30 03:39:36 PM PDT 24 |
970225600 ps |
| T882 |
/workspace/coverage/default/20.spi_device_tpm_all.692052624 |
|
|
May 30 03:40:26 PM PDT 24 |
May 30 03:41:26 PM PDT 24 |
180982194977 ps |
| T147 |
/workspace/coverage/default/35.spi_device_stress_all.1034054074 |
|
|
May 30 03:41:14 PM PDT 24 |
May 30 03:42:43 PM PDT 24 |
6052343255 ps |
| T883 |
/workspace/coverage/default/31.spi_device_tpm_rw.473884909 |
|
|
May 30 03:40:51 PM PDT 24 |
May 30 03:40:54 PM PDT 24 |
35226224 ps |
| T884 |
/workspace/coverage/default/10.spi_device_mailbox.425350466 |
|
|
May 30 03:39:41 PM PDT 24 |
May 30 03:40:02 PM PDT 24 |
2515246010 ps |
| T885 |
/workspace/coverage/default/17.spi_device_tpm_all.4132346692 |
|
|
May 30 03:40:09 PM PDT 24 |
May 30 03:40:40 PM PDT 24 |
2167695723 ps |
| T886 |
/workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1047984386 |
|
|
May 30 03:40:24 PM PDT 24 |
May 30 03:40:29 PM PDT 24 |
414323595 ps |
| T887 |
/workspace/coverage/default/24.spi_device_upload.1258511998 |
|
|
May 30 03:40:29 PM PDT 24 |
May 30 03:40:39 PM PDT 24 |
3452730999 ps |
| T888 |
/workspace/coverage/default/38.spi_device_tpm_rw.3961428064 |
|
|
May 30 03:41:22 PM PDT 24 |
May 30 03:41:26 PM PDT 24 |
25234865 ps |
| T889 |
/workspace/coverage/default/15.spi_device_pass_cmd_filtering.4005323775 |
|
|
May 30 03:40:02 PM PDT 24 |
May 30 03:40:12 PM PDT 24 |
3107973903 ps |
| T890 |
/workspace/coverage/default/34.spi_device_alert_test.530584038 |
|
|
May 30 03:41:12 PM PDT 24 |
May 30 03:41:15 PM PDT 24 |
11991635 ps |
| T270 |
/workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.4241553047 |
|
|
May 30 03:39:53 PM PDT 24 |
May 30 03:41:12 PM PDT 24 |
67730032682 ps |
| T891 |
/workspace/coverage/default/24.spi_device_csb_read.1459368013 |
|
|
May 30 03:40:34 PM PDT 24 |
May 30 03:40:37 PM PDT 24 |
22257787 ps |
| T892 |
/workspace/coverage/default/4.spi_device_tpm_rw.1536352471 |
|
|
May 30 03:39:31 PM PDT 24 |
May 30 03:39:33 PM PDT 24 |
37615832 ps |
| T893 |
/workspace/coverage/default/19.spi_device_tpm_all.2965442476 |
|
|
May 30 03:40:13 PM PDT 24 |
May 30 03:40:25 PM PDT 24 |
668004260 ps |
| T894 |
/workspace/coverage/default/37.spi_device_flash_and_tpm.1448703891 |
|
|
May 30 03:41:21 PM PDT 24 |
May 30 03:42:02 PM PDT 24 |
6077659918 ps |
| T895 |
/workspace/coverage/default/25.spi_device_upload.759001713 |
|
|
May 30 03:40:31 PM PDT 24 |
May 30 03:40:41 PM PDT 24 |
941457387 ps |
| T896 |
/workspace/coverage/default/19.spi_device_tpm_rw.2412622397 |
|
|
May 30 03:40:13 PM PDT 24 |
May 30 03:40:17 PM PDT 24 |
148016433 ps |
| T897 |
/workspace/coverage/default/33.spi_device_alert_test.1136935693 |
|
|
May 30 03:41:05 PM PDT 24 |
May 30 03:41:08 PM PDT 24 |
29545166 ps |
| T898 |
/workspace/coverage/default/3.spi_device_pass_cmd_filtering.989408529 |
|
|
May 30 03:39:20 PM PDT 24 |
May 30 03:39:53 PM PDT 24 |
44307964465 ps |
| T899 |
/workspace/coverage/default/35.spi_device_flash_all.963928184 |
|
|
May 30 03:41:11 PM PDT 24 |
May 30 03:41:24 PM PDT 24 |
2963928769 ps |
| T900 |
/workspace/coverage/default/26.spi_device_flash_all.3704157732 |
|
|
May 30 03:40:41 PM PDT 24 |
May 30 03:42:40 PM PDT 24 |
49467894560 ps |
| T901 |
/workspace/coverage/default/12.spi_device_csb_read.268265711 |
|
|
May 30 03:39:52 PM PDT 24 |
May 30 03:39:55 PM PDT 24 |
32284090 ps |
| T902 |
/workspace/coverage/default/21.spi_device_alert_test.3504212378 |
|
|
May 30 03:40:41 PM PDT 24 |
May 30 03:40:45 PM PDT 24 |
38974215 ps |
| T256 |
/workspace/coverage/default/43.spi_device_flash_all.3302054033 |
|
|
May 30 03:41:38 PM PDT 24 |
May 30 03:42:30 PM PDT 24 |
1985891255 ps |
| T903 |
/workspace/coverage/default/11.spi_device_flash_mode.1369801478 |
|
|
May 30 03:39:55 PM PDT 24 |
May 30 03:40:00 PM PDT 24 |
402256756 ps |
| T904 |
/workspace/coverage/default/41.spi_device_cfg_cmd.1910997679 |
|
|
May 30 03:41:30 PM PDT 24 |
May 30 03:41:40 PM PDT 24 |
596898980 ps |
| T905 |
/workspace/coverage/default/7.spi_device_cfg_cmd.1013782174 |
|
|
May 30 03:39:34 PM PDT 24 |
May 30 03:39:43 PM PDT 24 |
924375888 ps |
| T906 |
/workspace/coverage/default/9.spi_device_pass_addr_payload_swap.23873105 |
|
|
May 30 03:39:42 PM PDT 24 |
May 30 03:39:56 PM PDT 24 |
4437140133 ps |
| T907 |
/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.237874475 |
|
|
May 30 03:40:14 PM PDT 24 |
May 30 03:40:20 PM PDT 24 |
3052122243 ps |
| T908 |
/workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3979177505 |
|
|
May 30 03:39:27 PM PDT 24 |
May 30 03:39:41 PM PDT 24 |
3109075156 ps |
| T909 |
/workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2503487195 |
|
|
May 30 03:41:08 PM PDT 24 |
May 30 03:41:14 PM PDT 24 |
1267657109 ps |
| T910 |
/workspace/coverage/default/5.spi_device_tpm_all.1270171523 |
|
|
May 30 03:39:26 PM PDT 24 |
May 30 03:39:52 PM PDT 24 |
1573935393 ps |
| T911 |
/workspace/coverage/default/22.spi_device_upload.93606982 |
|
|
May 30 03:40:21 PM PDT 24 |
May 30 03:40:32 PM PDT 24 |
9817546386 ps |
| T912 |
/workspace/coverage/default/32.spi_device_flash_and_tpm.422144099 |
|
|
May 30 03:41:04 PM PDT 24 |
May 30 03:42:11 PM PDT 24 |
11661586300 ps |
| T913 |
/workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2850305461 |
|
|
May 30 03:40:03 PM PDT 24 |
May 30 03:40:11 PM PDT 24 |
707550313 ps |
| T914 |
/workspace/coverage/default/46.spi_device_alert_test.1406262937 |
|
|
May 30 03:41:49 PM PDT 24 |
May 30 03:41:55 PM PDT 24 |
35045985 ps |
| T915 |
/workspace/coverage/default/23.spi_device_cfg_cmd.2556580977 |
|
|
May 30 03:40:33 PM PDT 24 |
May 30 03:40:42 PM PDT 24 |
1254590072 ps |
| T916 |
/workspace/coverage/default/0.spi_device_tpm_rw.3918312239 |
|
|
May 30 03:39:21 PM PDT 24 |
May 30 03:39:27 PM PDT 24 |
883908972 ps |
| T917 |
/workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2497557063 |
|
|
May 30 03:41:18 PM PDT 24 |
May 30 03:41:29 PM PDT 24 |
40909432320 ps |
| T918 |
/workspace/coverage/default/32.spi_device_cfg_cmd.356643719 |
|
|
May 30 03:41:04 PM PDT 24 |
May 30 03:41:27 PM PDT 24 |
5772019032 ps |
| T919 |
/workspace/coverage/default/13.spi_device_flash_mode.1815133413 |
|
|
May 30 03:39:53 PM PDT 24 |
May 30 03:40:00 PM PDT 24 |
117134037 ps |
| T920 |
/workspace/coverage/default/26.spi_device_alert_test.3094663340 |
|
|
May 30 03:40:40 PM PDT 24 |
May 30 03:40:44 PM PDT 24 |
33884756 ps |
| T921 |
/workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2844362023 |
|
|
May 30 03:40:38 PM PDT 24 |
May 30 03:40:43 PM PDT 24 |
162371581 ps |
| T922 |
/workspace/coverage/default/26.spi_device_cfg_cmd.4128739880 |
|
|
May 30 03:40:40 PM PDT 24 |
May 30 03:40:51 PM PDT 24 |
497568882 ps |
| T923 |
/workspace/coverage/default/42.spi_device_upload.2629021167 |
|
|
May 30 03:41:28 PM PDT 24 |
May 30 03:41:38 PM PDT 24 |
2640839897 ps |
| T924 |
/workspace/coverage/default/9.spi_device_tpm_all.2830436205 |
|
|
May 30 03:39:43 PM PDT 24 |
May 30 03:40:10 PM PDT 24 |
3500814489 ps |
| T925 |
/workspace/coverage/default/49.spi_device_flash_all.2948536589 |
|
|
May 30 03:42:02 PM PDT 24 |
May 30 03:45:49 PM PDT 24 |
30208167446 ps |
| T926 |
/workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2155510962 |
|
|
May 30 03:41:43 PM PDT 24 |
May 30 03:41:51 PM PDT 24 |
356989112 ps |
| T927 |
/workspace/coverage/default/43.spi_device_read_buffer_direct.3917873363 |
|
|
May 30 03:41:39 PM PDT 24 |
May 30 03:41:48 PM PDT 24 |
65928828 ps |
| T928 |
/workspace/coverage/default/0.spi_device_flash_mode.2835275976 |
|
|
May 30 03:39:22 PM PDT 24 |
May 30 03:39:35 PM PDT 24 |
1345366146 ps |
| T929 |
/workspace/coverage/default/40.spi_device_alert_test.1087107085 |
|
|
May 30 03:41:29 PM PDT 24 |
May 30 03:41:35 PM PDT 24 |
19716894 ps |
| T930 |
/workspace/coverage/default/25.spi_device_alert_test.1662235382 |
|
|
May 30 03:40:39 PM PDT 24 |
May 30 03:40:43 PM PDT 24 |
24301433 ps |
| T931 |
/workspace/coverage/default/8.spi_device_tpm_rw.3585722482 |
|
|
May 30 03:39:42 PM PDT 24 |
May 30 03:39:45 PM PDT 24 |
22171120 ps |
| T932 |
/workspace/coverage/default/24.spi_device_flash_all.3198510149 |
|
|
May 30 03:40:31 PM PDT 24 |
May 30 03:41:52 PM PDT 24 |
6429581477 ps |
| T933 |
/workspace/coverage/default/4.spi_device_tpm_sts_read.1010867320 |
|
|
May 30 03:39:27 PM PDT 24 |
May 30 03:39:29 PM PDT 24 |
121633537 ps |
| T934 |
/workspace/coverage/default/24.spi_device_pass_cmd_filtering.2365839561 |
|
|
May 30 03:40:34 PM PDT 24 |
May 30 03:40:46 PM PDT 24 |
3167010975 ps |
| T935 |
/workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.813534754 |
|
|
May 30 03:41:05 PM PDT 24 |
May 30 03:41:50 PM PDT 24 |
15023761978 ps |
| T936 |
/workspace/coverage/default/33.spi_device_flash_all.2868293696 |
|
|
May 30 03:41:07 PM PDT 24 |
May 30 03:41:10 PM PDT 24 |
77903842 ps |
| T937 |
/workspace/coverage/default/47.spi_device_flash_mode.424347681 |
|
|
May 30 03:41:59 PM PDT 24 |
May 30 03:42:21 PM PDT 24 |
6626020466 ps |
| T938 |
/workspace/coverage/default/35.spi_device_pass_cmd_filtering.849402700 |
|
|
May 30 03:41:11 PM PDT 24 |
May 30 03:41:25 PM PDT 24 |
14114680800 ps |
| T939 |
/workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1470557755 |
|
|
May 30 03:40:12 PM PDT 24 |
May 30 03:41:52 PM PDT 24 |
33792410717 ps |
| T940 |
/workspace/coverage/default/33.spi_device_stress_all.2594349188 |
|
|
May 30 03:41:05 PM PDT 24 |
May 30 03:49:26 PM PDT 24 |
48035151687 ps |
| T941 |
/workspace/coverage/default/12.spi_device_alert_test.3048488449 |
|
|
May 30 03:39:53 PM PDT 24 |
May 30 03:39:55 PM PDT 24 |
12920587 ps |
| T942 |
/workspace/coverage/default/30.spi_device_tpm_all.766212088 |
|
|
May 30 03:40:51 PM PDT 24 |
May 30 03:41:13 PM PDT 24 |
1183796701 ps |
| T943 |
/workspace/coverage/default/40.spi_device_tpm_rw.390134171 |
|
|
May 30 03:41:20 PM PDT 24 |
May 30 03:41:25 PM PDT 24 |
458602724 ps |
| T944 |
/workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1841361683 |
|
|
May 30 03:41:32 PM PDT 24 |
May 30 03:41:38 PM PDT 24 |
342542602 ps |
| T148 |
/workspace/coverage/default/15.spi_device_stress_all.3976260091 |
|
|
May 30 03:40:01 PM PDT 24 |
May 30 03:41:32 PM PDT 24 |
6908161901 ps |
| T945 |
/workspace/coverage/default/14.spi_device_pass_cmd_filtering.3459223546 |
|
|
May 30 03:40:00 PM PDT 24 |
May 30 03:40:06 PM PDT 24 |
92113826 ps |
| T946 |
/workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1847198062 |
|
|
May 30 03:41:48 PM PDT 24 |
May 30 03:42:07 PM PDT 24 |
20081413966 ps |
| T947 |
/workspace/coverage/default/23.spi_device_intercept.2635195133 |
|
|
May 30 03:40:34 PM PDT 24 |
May 30 03:41:01 PM PDT 24 |
9106499626 ps |
| T948 |
/workspace/coverage/default/40.spi_device_flash_and_tpm.2073694784 |
|
|
May 30 03:41:28 PM PDT 24 |
May 30 03:43:51 PM PDT 24 |
24115344095 ps |
| T949 |
/workspace/coverage/default/4.spi_device_mailbox.2768918703 |
|
|
May 30 03:39:32 PM PDT 24 |
May 30 03:39:42 PM PDT 24 |
622473531 ps |
| T950 |
/workspace/coverage/default/47.spi_device_upload.1471715113 |
|
|
May 30 03:41:58 PM PDT 24 |
May 30 03:42:03 PM PDT 24 |
167593697 ps |
| T951 |
/workspace/coverage/default/26.spi_device_upload.1587291777 |
|
|
May 30 03:40:41 PM PDT 24 |
May 30 03:41:19 PM PDT 24 |
12004631470 ps |
| T952 |
/workspace/coverage/default/25.spi_device_pass_addr_payload_swap.365708466 |
|
|
May 30 03:40:33 PM PDT 24 |
May 30 03:40:43 PM PDT 24 |
3465586574 ps |
| T953 |
/workspace/coverage/default/3.spi_device_flash_mode.399504455 |
|
|
May 30 03:39:30 PM PDT 24 |
May 30 03:39:46 PM PDT 24 |
648131622 ps |
| T954 |
/workspace/coverage/default/44.spi_device_mailbox.385999748 |
|
|
May 30 03:41:38 PM PDT 24 |
May 30 03:42:05 PM PDT 24 |
20252911643 ps |
| T955 |
/workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3827668299 |
|
|
May 30 03:41:38 PM PDT 24 |
May 30 03:41:48 PM PDT 24 |
1008457419 ps |
| T956 |
/workspace/coverage/default/32.spi_device_tpm_all.2975087763 |
|
|
May 30 03:41:03 PM PDT 24 |
May 30 03:41:40 PM PDT 24 |
24940877891 ps |
| T957 |
/workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.396822739 |
|
|
May 30 03:39:22 PM PDT 24 |
May 30 03:40:06 PM PDT 24 |
6916156577 ps |
| T958 |
/workspace/coverage/default/11.spi_device_stress_all.786556304 |
|
|
May 30 03:39:50 PM PDT 24 |
May 30 03:40:42 PM PDT 24 |
4488901627 ps |
| T959 |
/workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.548609632 |
|
|
May 30 03:40:39 PM PDT 24 |
May 30 03:41:50 PM PDT 24 |
4552910368 ps |
| T960 |
/workspace/coverage/default/44.spi_device_alert_test.776437465 |
|
|
May 30 03:41:36 PM PDT 24 |
May 30 03:41:43 PM PDT 24 |
147048590 ps |
| T59 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.801490929 |
|
|
May 30 03:26:06 PM PDT 24 |
May 30 03:26:09 PM PDT 24 |
162210202 ps |
| T60 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1283401707 |
|
|
May 30 03:26:07 PM PDT 24 |
May 30 03:26:11 PM PDT 24 |
116410828 ps |
| T961 |
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.3836522449 |
|
|
May 30 03:26:15 PM PDT 24 |
May 30 03:26:17 PM PDT 24 |
16028747 ps |
| T962 |
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.3811886770 |
|
|
May 30 03:26:58 PM PDT 24 |
May 30 03:27:00 PM PDT 24 |
49411572 ps |
| T963 |
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.830850780 |
|
|
May 30 03:26:06 PM PDT 24 |
May 30 03:26:08 PM PDT 24 |
40806396 ps |
| T61 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4140558959 |
|
|
May 30 03:26:25 PM PDT 24 |
May 30 03:26:40 PM PDT 24 |
2046278029 ps |
| T84 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1154497669 |
|
|
May 30 03:26:24 PM PDT 24 |
May 30 03:26:29 PM PDT 24 |
544657459 ps |
| T121 |
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.853267740 |
|
|
May 30 03:25:54 PM PDT 24 |
May 30 03:25:59 PM PDT 24 |
115969221 ps |
| T85 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.295349227 |
|
|
May 30 03:26:39 PM PDT 24 |
May 30 03:26:45 PM PDT 24 |
274534616 ps |
| T964 |
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.3862323497 |
|
|
May 30 03:26:26 PM PDT 24 |
May 30 03:26:28 PM PDT 24 |
17334877 ps |
| T965 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.3000894341 |
|
|
May 30 03:26:16 PM PDT 24 |
May 30 03:26:18 PM PDT 24 |
32116491 ps |
| T86 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2836693134 |
|
|
May 30 03:25:16 PM PDT 24 |
May 30 03:25:25 PM PDT 24 |
1336384003 ps |
| T966 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.3027856795 |
|
|
May 30 03:26:46 PM PDT 24 |
May 30 03:26:47 PM PDT 24 |
20141897 ps |
| T99 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.5303314 |
|
|
May 30 03:25:54 PM PDT 24 |
May 30 03:25:56 PM PDT 24 |
196902076 ps |
| T88 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2288529414 |
|
|
May 30 03:26:45 PM PDT 24 |
May 30 03:26:51 PM PDT 24 |
641305934 ps |
| T967 |
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.2335407965 |
|
|
May 30 03:26:48 PM PDT 24 |
May 30 03:26:49 PM PDT 24 |
106098453 ps |
| T95 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1278694887 |
|
|
May 30 03:25:13 PM PDT 24 |
May 30 03:25:16 PM PDT 24 |
26734352 ps |
| T122 |
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1468422788 |
|
|
May 30 03:26:05 PM PDT 24 |
May 30 03:26:10 PM PDT 24 |
61513754 ps |
| T96 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1990236540 |
|
|
May 30 03:26:37 PM PDT 24 |
May 30 03:26:40 PM PDT 24 |
46577561 ps |
| T968 |
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.1363589541 |
|
|
May 30 03:26:47 PM PDT 24 |
May 30 03:26:49 PM PDT 24 |
11645353 ps |
| T969 |
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.3864263981 |
|
|
May 30 03:26:58 PM PDT 24 |
May 30 03:27:00 PM PDT 24 |
18390191 ps |
| T100 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2882670013 |
|
|
May 30 03:26:15 PM PDT 24 |
May 30 03:26:18 PM PDT 24 |
62707197 ps |
| T970 |
/workspace/coverage/cover_reg_top/33.spi_device_intr_test.3942224827 |
|
|
May 30 03:27:03 PM PDT 24 |
May 30 03:27:05 PM PDT 24 |
16177914 ps |
| T971 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.2529157575 |
|
|
May 30 03:26:37 PM PDT 24 |
May 30 03:26:40 PM PDT 24 |
28098628 ps |
| T97 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2116944416 |
|
|
May 30 03:26:16 PM PDT 24 |
May 30 03:26:20 PM PDT 24 |
84594295 ps |
| T101 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3350675064 |
|
|
May 30 03:25:27 PM PDT 24 |
May 30 03:25:31 PM PDT 24 |
1072368174 ps |
| T102 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1894947826 |
|
|
May 30 03:25:16 PM PDT 24 |
May 30 03:25:51 PM PDT 24 |
545710738 ps |
| T89 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2450551068 |
|
|
May 30 03:26:25 PM PDT 24 |
May 30 03:26:31 PM PDT 24 |
1853828902 ps |
| T103 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.304156624 |
|
|
May 30 03:26:06 PM PDT 24 |
May 30 03:26:09 PM PDT 24 |
87004688 ps |
| T972 |
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.3508556425 |
|
|
May 30 03:26:54 PM PDT 24 |
May 30 03:26:56 PM PDT 24 |
19984574 ps |
| T123 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2105252289 |
|
|
May 30 03:25:36 PM PDT 24 |
May 30 03:25:41 PM PDT 24 |
651667118 ps |
| T104 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1755100422 |
|
|
May 30 03:26:24 PM PDT 24 |
May 30 03:26:27 PM PDT 24 |
33068757 ps |
| T98 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2383953898 |
|
|
May 30 03:26:14 PM PDT 24 |
May 30 03:26:19 PM PDT 24 |
135275669 ps |
| T124 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4271440764 |
|
|
May 30 03:26:04 PM PDT 24 |
May 30 03:26:08 PM PDT 24 |
412376261 ps |
| T87 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.514396148 |
|
|
May 30 03:25:27 PM PDT 24 |
May 30 03:25:46 PM PDT 24 |
290116651 ps |
| T105 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1559139870 |
|
|
May 30 03:25:14 PM PDT 24 |
May 30 03:25:22 PM PDT 24 |
1490801931 ps |
| T125 |
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3182729941 |
|
|
May 30 03:26:16 PM PDT 24 |
May 30 03:26:21 PM PDT 24 |
315489882 ps |
| T135 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1844505035 |
|
|
May 30 03:26:39 PM PDT 24 |
May 30 03:26:45 PM PDT 24 |
1259150667 ps |
| T106 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.836954087 |
|
|
May 30 03:26:05 PM PDT 24 |
May 30 03:26:27 PM PDT 24 |
763857527 ps |
| T107 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4208859295 |
|
|
May 30 03:25:15 PM PDT 24 |
May 30 03:25:18 PM PDT 24 |
93672587 ps |
| T90 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2771966704 |
|
|
May 30 03:26:06 PM PDT 24 |
May 30 03:26:10 PM PDT 24 |
1052796789 ps |
| T973 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.75812563 |
|
|
May 30 03:26:58 PM PDT 24 |
May 30 03:27:00 PM PDT 24 |
174484825 ps |
| T108 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3170438043 |
|
|
May 30 03:26:27 PM PDT 24 |
May 30 03:26:30 PM PDT 24 |
102882767 ps |
| T109 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2317523319 |
|
|
May 30 03:26:48 PM PDT 24 |
May 30 03:26:52 PM PDT 24 |
47982762 ps |
| T110 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3977796061 |
|
|
May 30 03:25:40 PM PDT 24 |
May 30 03:26:06 PM PDT 24 |
7602647011 ps |
| T974 |
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.1764913061 |
|
|
May 30 03:26:47 PM PDT 24 |
May 30 03:26:49 PM PDT 24 |
26933534 ps |
| T975 |
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2430303665 |
|
|
May 30 03:26:14 PM PDT 24 |
May 30 03:26:17 PM PDT 24 |
300820944 ps |
| T976 |
/workspace/coverage/cover_reg_top/37.spi_device_intr_test.3934883357 |
|
|
May 30 03:27:04 PM PDT 24 |
May 30 03:27:06 PM PDT 24 |
31828592 ps |
| T977 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.156339898 |
|
|
May 30 03:25:25 PM PDT 24 |
May 30 03:25:31 PM PDT 24 |
60823183 ps |
| T978 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.327843706 |
|
|
May 30 03:26:28 PM PDT 24 |
May 30 03:26:30 PM PDT 24 |
31552187 ps |
| T979 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.456692144 |
|
|
May 30 03:26:46 PM PDT 24 |
May 30 03:26:48 PM PDT 24 |
12889306 ps |
| T94 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3767192777 |
|
|
May 30 03:26:25 PM PDT 24 |
May 30 03:26:30 PM PDT 24 |
87884406 ps |
| T92 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3030644175 |
|
|
May 30 03:26:25 PM PDT 24 |
May 30 03:26:30 PM PDT 24 |
93139802 ps |
| T158 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4060717143 |
|
|
May 30 03:26:15 PM PDT 24 |
May 30 03:26:23 PM PDT 24 |
122235707 ps |
| T980 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1135111620 |
|
|
May 30 03:26:25 PM PDT 24 |
May 30 03:26:34 PM PDT 24 |
555101095 ps |
| T91 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1304692984 |
|
|
May 30 03:26:48 PM PDT 24 |
May 30 03:26:54 PM PDT 24 |
240760970 ps |
| T136 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2321732924 |
|
|
May 30 03:25:54 PM PDT 24 |
May 30 03:25:57 PM PDT 24 |
113081138 ps |
| T137 |
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1497221994 |
|
|
May 30 03:26:47 PM PDT 24 |
May 30 03:26:52 PM PDT 24 |
205884745 ps |
| T111 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2644669745 |
|
|
May 30 03:25:40 PM PDT 24 |
May 30 03:25:43 PM PDT 24 |
33368129 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.2126443583 |
|
|
May 30 03:25:26 PM PDT 24 |
May 30 03:25:28 PM PDT 24 |
16061686 ps |
| T982 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2031215959 |
|
|
May 30 03:26:37 PM PDT 24 |
May 30 03:26:41 PM PDT 24 |
458543944 ps |
| T983 |
/workspace/coverage/cover_reg_top/46.spi_device_intr_test.2731291853 |
|
|
May 30 03:26:56 PM PDT 24 |
May 30 03:26:58 PM PDT 24 |
17758577 ps |
| T984 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1745854463 |
|
|
May 30 03:26:04 PM PDT 24 |
May 30 03:26:08 PM PDT 24 |
293330303 ps |
| T985 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1200073556 |
|
|
May 30 03:26:36 PM PDT 24 |
May 30 03:26:41 PM PDT 24 |
285118572 ps |
| T986 |
/workspace/coverage/cover_reg_top/32.spi_device_intr_test.504151875 |
|
|
May 30 03:26:54 PM PDT 24 |
May 30 03:26:56 PM PDT 24 |
174857593 ps |
| T162 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.422503549 |
|
|
May 30 03:26:05 PM PDT 24 |
May 30 03:26:19 PM PDT 24 |
528040812 ps |
| T138 |
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3393441261 |
|
|
May 30 03:26:15 PM PDT 24 |
May 30 03:26:21 PM PDT 24 |
410618137 ps |
| T987 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3107244629 |
|
|
May 30 03:25:37 PM PDT 24 |
May 30 03:26:03 PM PDT 24 |
5025653940 ps |
| T139 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2770391380 |
|
|
May 30 03:26:25 PM PDT 24 |
May 30 03:26:29 PM PDT 24 |
92012803 ps |
| T988 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.270158975 |
|
|
May 30 03:25:15 PM PDT 24 |
May 30 03:25:17 PM PDT 24 |
29919976 ps |
| T989 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3795611863 |
|
|
May 30 03:26:14 PM PDT 24 |
May 30 03:26:18 PM PDT 24 |
58032492 ps |
| T990 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.449604520 |
|
|
May 30 03:26:48 PM PDT 24 |
May 30 03:26:51 PM PDT 24 |
110466377 ps |
| T991 |
/workspace/coverage/cover_reg_top/36.spi_device_intr_test.1824696652 |
|
|
May 30 03:26:57 PM PDT 24 |
May 30 03:26:59 PM PDT 24 |
17279368 ps |
| T992 |
/workspace/coverage/cover_reg_top/9.spi_device_intr_test.3540744133 |
|
|
May 30 03:26:16 PM PDT 24 |
May 30 03:26:18 PM PDT 24 |
44304196 ps |
| T993 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2670572604 |
|
|
May 30 03:26:27 PM PDT 24 |
May 30 03:26:31 PM PDT 24 |
382626846 ps |
| T994 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2082165783 |
|
|
May 30 03:25:27 PM PDT 24 |
May 30 03:25:37 PM PDT 24 |
381781103 ps |
| T995 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2982589470 |
|
|
May 30 03:26:05 PM PDT 24 |
May 30 03:26:10 PM PDT 24 |
723806972 ps |
| T996 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.512146796 |
|
|
May 30 03:25:15 PM PDT 24 |
May 30 03:25:20 PM PDT 24 |
544920482 ps |
| T997 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.606143184 |
|
|
May 30 03:26:04 PM PDT 24 |
May 30 03:26:08 PM PDT 24 |
208374587 ps |
| T93 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3585981295 |
|
|
May 30 03:26:16 PM PDT 24 |
May 30 03:26:20 PM PDT 24 |
170148802 ps |
| T998 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1569774337 |
|
|
May 30 03:26:05 PM PDT 24 |
May 30 03:26:20 PM PDT 24 |
852469702 ps |
| T999 |
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1983448751 |
|
|
May 30 03:26:25 PM PDT 24 |
May 30 03:26:26 PM PDT 24 |
42443129 ps |
| T1000 |
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.213088822 |
|
|
May 30 03:26:05 PM PDT 24 |
May 30 03:26:08 PM PDT 24 |
264742518 ps |
| T159 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2661349286 |
|
|
May 30 03:26:24 PM PDT 24 |
May 30 03:26:45 PM PDT 24 |
906606965 ps |
| T1001 |
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2204349648 |
|
|
May 30 03:26:26 PM PDT 24 |
May 30 03:26:29 PM PDT 24 |
64544959 ps |
| T1002 |
/workspace/coverage/cover_reg_top/44.spi_device_intr_test.3098280214 |
|
|
May 30 03:27:03 PM PDT 24 |
May 30 03:27:05 PM PDT 24 |
17334731 ps |
| T1003 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3289038194 |
|
|
May 30 03:26:04 PM PDT 24 |
May 30 03:26:20 PM PDT 24 |
213707869 ps |
| T1004 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2251197764 |
|
|
May 30 03:25:25 PM PDT 24 |
May 30 03:25:28 PM PDT 24 |
69396220 ps |
| T1005 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3410794809 |
|
|
May 30 03:26:14 PM PDT 24 |
May 30 03:26:19 PM PDT 24 |
110891678 ps |
| T157 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.84383910 |
|
|
May 30 03:26:28 PM PDT 24 |
May 30 03:26:44 PM PDT 24 |
636994685 ps |
| T1006 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.511302165 |
|
|
May 30 03:26:15 PM PDT 24 |
May 30 03:26:18 PM PDT 24 |
250811965 ps |
| T1007 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4241819235 |
|
|
May 30 03:25:25 PM PDT 24 |
May 30 03:25:26 PM PDT 24 |
46065356 ps |
| T1008 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2613717184 |
|
|
May 30 03:26:37 PM PDT 24 |
May 30 03:26:40 PM PDT 24 |
30517371 ps |
| T1009 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1362253271 |
|
|
May 30 03:25:14 PM PDT 24 |
May 30 03:25:16 PM PDT 24 |
231576710 ps |