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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.09 98.30 94.11 98.61 89.36 97.16 95.84 99.25


Total test records in report: 1081
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T1010 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4026049852 May 30 03:26:07 PM PDT 24 May 30 03:26:11 PM PDT 24 135322155 ps
T1011 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3342859632 May 30 03:26:49 PM PDT 24 May 30 03:26:50 PM PDT 24 17191487 ps
T165 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1219755680 May 30 03:26:14 PM PDT 24 May 30 03:26:29 PM PDT 24 214480728 ps
T1012 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.167034462 May 30 03:25:27 PM PDT 24 May 30 03:25:29 PM PDT 24 13509477 ps
T1013 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2957770660 May 30 03:25:38 PM PDT 24 May 30 03:25:52 PM PDT 24 2902722813 ps
T1014 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.854136778 May 30 03:26:48 PM PDT 24 May 30 03:26:49 PM PDT 24 14672495 ps
T1015 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2797160649 May 30 03:25:38 PM PDT 24 May 30 03:25:41 PM PDT 24 396360134 ps
T163 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.262820536 May 30 03:25:26 PM PDT 24 May 30 03:25:41 PM PDT 24 1389191252 ps
T1016 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3965723117 May 30 03:25:38 PM PDT 24 May 30 03:25:42 PM PDT 24 238629621 ps
T1017 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1356732604 May 30 03:25:25 PM PDT 24 May 30 03:25:30 PM PDT 24 119912595 ps
T1018 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2736153986 May 30 03:26:47 PM PDT 24 May 30 03:26:50 PM PDT 24 119829693 ps
T75 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.271696595 May 30 03:25:27 PM PDT 24 May 30 03:25:30 PM PDT 24 52747277 ps
T1019 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4016417521 May 30 03:26:59 PM PDT 24 May 30 03:27:01 PM PDT 24 17375407 ps
T156 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3048684224 May 30 03:25:13 PM PDT 24 May 30 03:25:19 PM PDT 24 1934255342 ps
T1020 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2612646260 May 30 03:26:25 PM PDT 24 May 30 03:26:28 PM PDT 24 135074416 ps
T1021 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.700858365 May 30 03:26:07 PM PDT 24 May 30 03:26:10 PM PDT 24 52271321 ps
T1022 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3627478309 May 30 03:25:26 PM PDT 24 May 30 03:25:40 PM PDT 24 739758434 ps
T1023 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.774583472 May 30 03:26:14 PM PDT 24 May 30 03:26:17 PM PDT 24 49150151 ps
T1024 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3922417915 May 30 03:26:59 PM PDT 24 May 30 03:27:00 PM PDT 24 14091747 ps
T1025 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2397409220 May 30 03:25:37 PM PDT 24 May 30 03:25:39 PM PDT 24 38288708 ps
T1026 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.8905921 May 30 03:25:25 PM PDT 24 May 30 03:25:27 PM PDT 24 32444287 ps
T1027 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1001559762 May 30 03:25:36 PM PDT 24 May 30 03:25:45 PM PDT 24 1213593428 ps
T1028 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2427971136 May 30 03:27:02 PM PDT 24 May 30 03:27:03 PM PDT 24 14723853 ps
T1029 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2674944579 May 30 03:26:04 PM PDT 24 May 30 03:26:09 PM PDT 24 190577138 ps
T1030 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3675075032 May 30 03:26:36 PM PDT 24 May 30 03:26:38 PM PDT 24 12259616 ps
T1031 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2526852953 May 30 03:25:26 PM PDT 24 May 30 03:25:32 PM PDT 24 903010950 ps
T1032 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2042469902 May 30 03:26:14 PM PDT 24 May 30 03:26:17 PM PDT 24 153246948 ps
T1033 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.598876411 May 30 03:26:26 PM PDT 24 May 30 03:26:30 PM PDT 24 345376710 ps
T1034 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1349660088 May 30 03:26:17 PM PDT 24 May 30 03:26:19 PM PDT 24 35896132 ps
T1035 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1067092728 May 30 03:26:17 PM PDT 24 May 30 03:26:27 PM PDT 24 4385573203 ps
T1036 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.938944386 May 30 03:26:27 PM PDT 24 May 30 03:26:31 PM PDT 24 226381397 ps
T1037 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1525746061 May 30 03:26:38 PM PDT 24 May 30 03:26:55 PM PDT 24 2290665001 ps
T1038 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3142251083 May 30 03:25:27 PM PDT 24 May 30 03:25:29 PM PDT 24 11028174 ps
T1039 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3021500271 May 30 03:26:36 PM PDT 24 May 30 03:26:40 PM PDT 24 773686604 ps
T1040 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4125621795 May 30 03:25:39 PM PDT 24 May 30 03:25:41 PM PDT 24 36465213 ps
T160 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2532844677 May 30 03:26:47 PM PDT 24 May 30 03:27:06 PM PDT 24 1165477499 ps
T1041 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.776310903 May 30 03:26:59 PM PDT 24 May 30 03:27:01 PM PDT 24 14093648 ps
T1042 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1831265652 May 30 03:25:53 PM PDT 24 May 30 03:25:55 PM PDT 24 28363438 ps
T1043 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.848179567 May 30 03:25:55 PM PDT 24 May 30 03:25:58 PM PDT 24 40203794 ps
T164 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.828400198 May 30 03:26:47 PM PDT 24 May 30 03:26:55 PM PDT 24 1130944417 ps
T76 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2661797227 May 30 03:25:39 PM PDT 24 May 30 03:25:42 PM PDT 24 413764959 ps
T1044 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.427552783 May 30 03:26:36 PM PDT 24 May 30 03:26:39 PM PDT 24 73527149 ps
T1045 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2840216586 May 30 03:26:07 PM PDT 24 May 30 03:26:10 PM PDT 24 181257561 ps
T1046 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2850789716 May 30 03:26:46 PM PDT 24 May 30 03:26:49 PM PDT 24 144762886 ps
T1047 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2981553756 May 30 03:26:25 PM PDT 24 May 30 03:26:27 PM PDT 24 32464482 ps
T1048 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2561308637 May 30 03:26:46 PM PDT 24 May 30 03:26:48 PM PDT 24 31034679 ps
T1049 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2227518463 May 30 03:25:18 PM PDT 24 May 30 03:25:19 PM PDT 24 15139277 ps
T1050 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3546528499 May 30 03:26:07 PM PDT 24 May 30 03:26:09 PM PDT 24 87964954 ps
T1051 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3919729586 May 30 03:26:56 PM PDT 24 May 30 03:26:58 PM PDT 24 12374839 ps
T1052 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4177816134 May 30 03:26:40 PM PDT 24 May 30 03:26:43 PM PDT 24 210820279 ps
T161 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3497721853 May 30 03:26:15 PM PDT 24 May 30 03:26:40 PM PDT 24 1227255879 ps
T1053 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1595179875 May 30 03:26:15 PM PDT 24 May 30 03:26:20 PM PDT 24 56677548 ps
T1054 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.711563585 May 30 03:26:04 PM PDT 24 May 30 03:26:17 PM PDT 24 677155183 ps
T166 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2604382213 May 30 03:26:36 PM PDT 24 May 30 03:26:44 PM PDT 24 216898603 ps
T1055 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1716891941 May 30 03:26:57 PM PDT 24 May 30 03:26:59 PM PDT 24 14027158 ps
T1056 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.783198656 May 30 03:26:16 PM PDT 24 May 30 03:26:20 PM PDT 24 101437368 ps
T1057 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.392169510 May 30 03:26:58 PM PDT 24 May 30 03:27:00 PM PDT 24 13174900 ps
T1058 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2347878206 May 30 03:26:54 PM PDT 24 May 30 03:26:56 PM PDT 24 11553557 ps
T1059 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3257644361 May 30 03:26:46 PM PDT 24 May 30 03:26:48 PM PDT 24 18276321 ps
T1060 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.33050879 May 30 03:26:06 PM PDT 24 May 30 03:26:08 PM PDT 24 24032281 ps
T1061 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.7508584 May 30 03:26:47 PM PDT 24 May 30 03:26:49 PM PDT 24 14487667 ps
T1062 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3863756991 May 30 03:25:38 PM PDT 24 May 30 03:25:40 PM PDT 24 23982423 ps
T1063 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4051868814 May 30 03:25:25 PM PDT 24 May 30 03:25:28 PM PDT 24 276708408 ps
T1064 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2573499399 May 30 03:25:38 PM PDT 24 May 30 03:25:47 PM PDT 24 211079702 ps
T1065 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.679220047 May 30 03:26:24 PM PDT 24 May 30 03:26:26 PM PDT 24 118169621 ps
T1066 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2587179381 May 30 03:25:38 PM PDT 24 May 30 03:25:40 PM PDT 24 20817205 ps
T1067 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1756796613 May 30 03:25:54 PM PDT 24 May 30 03:25:56 PM PDT 24 12174213 ps
T1068 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4279105531 May 30 03:26:15 PM PDT 24 May 30 03:26:20 PM PDT 24 122035731 ps
T1069 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.997439616 May 30 03:25:39 PM PDT 24 May 30 03:25:44 PM PDT 24 729222837 ps
T1070 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1333826249 May 30 03:26:25 PM PDT 24 May 30 03:26:31 PM PDT 24 155419602 ps
T1071 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1998464308 May 30 03:26:56 PM PDT 24 May 30 03:26:58 PM PDT 24 37417148 ps
T1072 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1943898075 May 30 03:25:14 PM PDT 24 May 30 03:25:16 PM PDT 24 44061808 ps
T1073 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1591653261 May 30 03:26:48 PM PDT 24 May 30 03:26:50 PM PDT 24 19914919 ps
T1074 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3513629082 May 30 03:26:47 PM PDT 24 May 30 03:26:51 PM PDT 24 573909210 ps
T1075 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.241024202 May 30 03:25:55 PM PDT 24 May 30 03:26:09 PM PDT 24 2014789109 ps
T1076 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4286238319 May 30 03:26:49 PM PDT 24 May 30 03:26:51 PM PDT 24 18070752 ps
T1077 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2712946671 May 30 03:26:05 PM PDT 24 May 30 03:26:08 PM PDT 24 299126848 ps
T1078 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1210004606 May 30 03:26:06 PM PDT 24 May 30 03:26:09 PM PDT 24 260540375 ps
T1079 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2975564259 May 30 03:26:05 PM PDT 24 May 30 03:26:07 PM PDT 24 24001299 ps
T1080 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.595373209 May 30 03:26:57 PM PDT 24 May 30 03:26:59 PM PDT 24 17151105 ps
T1081 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4027477097 May 30 03:26:38 PM PDT 24 May 30 03:26:44 PM PDT 24 144538670 ps

Test location /workspace/coverage/default/12.spi_device_stress_all.4243045934
Short name T6
Test name
Test status
Simulation time 83405536052 ps
CPU time 231.44 seconds
Started May 30 03:39:54 PM PDT 24
Finished May 30 03:43:48 PM PDT 24
Peak memory 267244 kb
Host smart-d24ab304-1d7b-4328-b5e0-d75c2728dc7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243045934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.4243045934
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3504638089
Short name T43
Test name
Test status
Simulation time 5599207910 ps
CPU time 49.14 seconds
Started May 30 03:40:24 PM PDT 24
Finished May 30 03:41:14 PM PDT 24
Peak memory 240844 kb
Host smart-6488ca95-4788-4da7-9f7c-3eec880c67a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504638089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3504638089
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1213363282
Short name T62
Test name
Test status
Simulation time 15770394496 ps
CPU time 222.97 seconds
Started May 30 03:41:18 PM PDT 24
Finished May 30 03:45:03 PM PDT 24
Peak memory 264404 kb
Host smart-23f31d9c-b30b-4c7f-bd2e-fb3627b7190f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213363282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1213363282
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1154497669
Short name T84
Test name
Test status
Simulation time 544657459 ps
CPU time 3.73 seconds
Started May 30 03:26:24 PM PDT 24
Finished May 30 03:26:29 PM PDT 24
Peak memory 217072 kb
Host smart-fe8f7c98-d5ee-4f91-8317-5771c500ca98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154497669 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1154497669
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1081504394
Short name T194
Test name
Test status
Simulation time 112417877704 ps
CPU time 558.78 seconds
Started May 30 03:40:28 PM PDT 24
Finished May 30 03:49:49 PM PDT 24
Peak memory 257248 kb
Host smart-0d95adc5-f4b2-4e6b-a7bc-3a483bdfcb8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081504394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1081504394
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.4229497731
Short name T46
Test name
Test status
Simulation time 9143303445 ps
CPU time 209.58 seconds
Started May 30 03:39:44 PM PDT 24
Finished May 30 03:43:16 PM PDT 24
Peak memory 270352 kb
Host smart-72d1867b-558f-4dbb-9202-21be7d908168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229497731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.4229497731
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1244307409
Short name T63
Test name
Test status
Simulation time 33750141 ps
CPU time 0.72 seconds
Started May 30 03:39:18 PM PDT 24
Finished May 30 03:39:21 PM PDT 24
Peak memory 216016 kb
Host smart-ce43afee-1b1b-4d27-ae79-1c5e399534c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244307409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1244307409
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2811842091
Short name T35
Test name
Test status
Simulation time 3512061245 ps
CPU time 95.53 seconds
Started May 30 03:41:56 PM PDT 24
Finished May 30 03:43:34 PM PDT 24
Peak memory 257296 kb
Host smart-5ed6686b-7837-42b8-aa19-d7ea6a32e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811842091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2811842091
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4167640251
Short name T36
Test name
Test status
Simulation time 749922630035 ps
CPU time 642.18 seconds
Started May 30 03:41:19 PM PDT 24
Finished May 30 03:52:04 PM PDT 24
Peak memory 256748 kb
Host smart-9c977cff-19e2-4db0-8b53-33b1e3a0b14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167640251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.4167640251
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1905056595
Short name T65
Test name
Test status
Simulation time 84262099 ps
CPU time 1.16 seconds
Started May 30 03:39:18 PM PDT 24
Finished May 30 03:39:22 PM PDT 24
Peak memory 234964 kb
Host smart-1d21fc77-a3a2-4bff-82b3-b127a6d52d5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905056595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1905056595
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1474465415
Short name T28
Test name
Test status
Simulation time 68856742100 ps
CPU time 354.92 seconds
Started May 30 03:39:19 PM PDT 24
Finished May 30 03:45:17 PM PDT 24
Peak memory 249140 kb
Host smart-19584f60-9011-434a-8117-b3f030f86ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474465415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1474465415
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3502776024
Short name T41
Test name
Test status
Simulation time 3490871071 ps
CPU time 16.74 seconds
Started May 30 03:40:14 PM PDT 24
Finished May 30 03:40:32 PM PDT 24
Peak memory 224464 kb
Host smart-1fb5ecd8-c3a8-4f29-b3e8-90db33e1391e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502776024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3502776024
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2673386763
Short name T22
Test name
Test status
Simulation time 314820685496 ps
CPU time 783.12 seconds
Started May 30 03:40:53 PM PDT 24
Finished May 30 03:53:59 PM PDT 24
Peak memory 281864 kb
Host smart-dda6bf2b-e50f-4cff-bae3-a3faf097f315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673386763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2673386763
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.514396148
Short name T87
Test name
Test status
Simulation time 290116651 ps
CPU time 18.01 seconds
Started May 30 03:25:27 PM PDT 24
Finished May 30 03:25:46 PM PDT 24
Peak memory 215260 kb
Host smart-fdc712fa-ab34-444e-9c41-c6b1fa825759
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514396148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.514396148
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.56196901
Short name T26
Test name
Test status
Simulation time 43802881854 ps
CPU time 138.51 seconds
Started May 30 03:41:37 PM PDT 24
Finished May 30 03:44:02 PM PDT 24
Peak memory 265488 kb
Host smart-b6cd199b-b907-4357-948f-fcbf5df7e2ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56196901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress
_all.56196901
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1559139870
Short name T105
Test name
Test status
Simulation time 1490801931 ps
CPU time 7.48 seconds
Started May 30 03:25:14 PM PDT 24
Finished May 30 03:25:22 PM PDT 24
Peak memory 215164 kb
Host smart-b5fef6d8-e8f9-46ff-8a11-2a0cf53ee965
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559139870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1559139870
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1265319808
Short name T239
Test name
Test status
Simulation time 56232411915 ps
CPU time 361.22 seconds
Started May 30 03:39:24 PM PDT 24
Finished May 30 03:45:28 PM PDT 24
Peak memory 284984 kb
Host smart-9e313a49-0d5a-4831-afad-8b5dbbd2be21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265319808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1265319808
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3030644175
Short name T92
Test name
Test status
Simulation time 93139802 ps
CPU time 3.98 seconds
Started May 30 03:26:25 PM PDT 24
Finished May 30 03:26:30 PM PDT 24
Peak memory 215448 kb
Host smart-6d315b93-595e-4fe6-94a8-657f62d71768
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030644175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3030644175
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.25491006
Short name T37
Test name
Test status
Simulation time 15499480499 ps
CPU time 182.38 seconds
Started May 30 03:39:32 PM PDT 24
Finished May 30 03:42:37 PM PDT 24
Peak memory 254552 kb
Host smart-1d374e52-4e37-4376-a051-ab3ee8ca3f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25491006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.25491006
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2803520635
Short name T34
Test name
Test status
Simulation time 113149988495 ps
CPU time 274.07 seconds
Started May 30 03:40:43 PM PDT 24
Finished May 30 03:45:19 PM PDT 24
Peak memory 264672 kb
Host smart-8633887c-11be-45a0-91ee-0b621423eb66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803520635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2803520635
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2519754705
Short name T236
Test name
Test status
Simulation time 8784358368 ps
CPU time 54.77 seconds
Started May 30 03:41:21 PM PDT 24
Finished May 30 03:42:19 PM PDT 24
Peak memory 252160 kb
Host smart-706010c8-d1cc-42ee-9f4c-dc4467913923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519754705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2519754705
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1873256570
Short name T185
Test name
Test status
Simulation time 752541755225 ps
CPU time 393.84 seconds
Started May 30 03:41:03 PM PDT 24
Finished May 30 03:47:39 PM PDT 24
Peak memory 263772 kb
Host smart-73eae534-f2b0-4fd6-893b-d5af39a72afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873256570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1873256570
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2801973784
Short name T31
Test name
Test status
Simulation time 79797378364 ps
CPU time 261.69 seconds
Started May 30 03:39:51 PM PDT 24
Finished May 30 03:44:15 PM PDT 24
Peak memory 257436 kb
Host smart-2741ba5e-e2da-4ae4-8cfe-1d26b8992d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801973784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2801973784
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2716611555
Short name T218
Test name
Test status
Simulation time 57494609791 ps
CPU time 125.7 seconds
Started May 30 03:40:27 PM PDT 24
Finished May 30 03:42:35 PM PDT 24
Peak memory 249032 kb
Host smart-d6acd105-d19f-43cc-8922-83602682f2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716611555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2716611555
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.731099412
Short name T57
Test name
Test status
Simulation time 35381302 ps
CPU time 0.71 seconds
Started May 30 03:39:55 PM PDT 24
Finished May 30 03:39:57 PM PDT 24
Peak memory 205260 kb
Host smart-712745d0-f1c3-4a7b-9f8b-9c2b3ec0d2d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731099412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.731099412
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.288545339
Short name T184
Test name
Test status
Simulation time 27572241439 ps
CPU time 85.77 seconds
Started May 30 03:39:19 PM PDT 24
Finished May 30 03:40:48 PM PDT 24
Peak memory 256840 kb
Host smart-8f2f7ea6-42b7-4a67-8109-62df844f681d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288545339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.288545339
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.823290689
Short name T173
Test name
Test status
Simulation time 14038628587 ps
CPU time 120.74 seconds
Started May 30 03:39:52 PM PDT 24
Finished May 30 03:41:55 PM PDT 24
Peak memory 250972 kb
Host smart-279ed5a3-891c-4a3e-98cf-cdc05ea1d2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823290689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.823290689
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1869510580
Short name T170
Test name
Test status
Simulation time 27418828861 ps
CPU time 112.57 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:41:58 PM PDT 24
Peak memory 250484 kb
Host smart-5225a7e2-df06-411d-a926-8b66ceaee00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869510580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1869510580
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2827750547
Short name T257
Test name
Test status
Simulation time 72060646824 ps
CPU time 543.12 seconds
Started May 30 03:41:31 PM PDT 24
Finished May 30 03:50:39 PM PDT 24
Peak memory 263620 kb
Host smart-07c53c00-3a82-4f0c-ac8f-103d035b1b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827750547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2827750547
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2771966704
Short name T90
Test name
Test status
Simulation time 1052796789 ps
CPU time 3.27 seconds
Started May 30 03:26:06 PM PDT 24
Finished May 30 03:26:10 PM PDT 24
Peak memory 215456 kb
Host smart-8f8fe400-e984-435d-a762-0c49b5663b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771966704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
771966704
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3802059113
Short name T29
Test name
Test status
Simulation time 682081656247 ps
CPU time 583.87 seconds
Started May 30 03:40:01 PM PDT 24
Finished May 30 03:49:49 PM PDT 24
Peak memory 254756 kb
Host smart-c2c4cab2-46c8-4c5f-864e-916b8b1eee5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802059113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3802059113
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4035534892
Short name T24
Test name
Test status
Simulation time 407998486 ps
CPU time 3.38 seconds
Started May 30 03:40:00 PM PDT 24
Finished May 30 03:40:07 PM PDT 24
Peak memory 216208 kb
Host smart-2718daec-c17e-4a80-9c71-f3c74d3e9414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035534892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4035534892
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3302044986
Short name T141
Test name
Test status
Simulation time 380589546076 ps
CPU time 888.6 seconds
Started May 30 03:40:14 PM PDT 24
Finished May 30 03:55:05 PM PDT 24
Peak memory 256556 kb
Host smart-925d02ae-fd9d-4c10-8207-9784ab29b5b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302044986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3302044986
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2626031908
Short name T281
Test name
Test status
Simulation time 2515959910 ps
CPU time 22.48 seconds
Started May 30 03:40:29 PM PDT 24
Finished May 30 03:40:53 PM PDT 24
Peak memory 234868 kb
Host smart-69bc842a-debe-4e91-9541-324fded863d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626031908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2626031908
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.386657288
Short name T12
Test name
Test status
Simulation time 860229334 ps
CPU time 9.65 seconds
Started May 30 03:41:18 PM PDT 24
Finished May 30 03:41:30 PM PDT 24
Peak memory 219644 kb
Host smart-f966a872-d392-4cef-84f5-408c68d188d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386657288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.386657288
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2604382213
Short name T166
Test name
Test status
Simulation time 216898603 ps
CPU time 6.61 seconds
Started May 30 03:26:36 PM PDT 24
Finished May 30 03:26:44 PM PDT 24
Peak memory 215336 kb
Host smart-ba046448-7328-4c12-8c2a-d089e0ecbf29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604382213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2604382213
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3994914962
Short name T174
Test name
Test status
Simulation time 13159301716 ps
CPU time 141.21 seconds
Started May 30 03:40:01 PM PDT 24
Finished May 30 03:42:26 PM PDT 24
Peak memory 254448 kb
Host smart-cb4b7d22-1e7d-4a27-bd3c-8f8fea7f6980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994914962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3994914962
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.604969208
Short name T211
Test name
Test status
Simulation time 32072080620 ps
CPU time 139.36 seconds
Started May 30 03:41:03 PM PDT 24
Finished May 30 03:43:25 PM PDT 24
Peak memory 273588 kb
Host smart-9aab80eb-a036-4f9d-ae25-894f9f066b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604969208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.604969208
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1595179875
Short name T1053
Test name
Test status
Simulation time 56677548 ps
CPU time 3.61 seconds
Started May 30 03:26:15 PM PDT 24
Finished May 30 03:26:20 PM PDT 24
Peak memory 215316 kb
Host smart-771755fb-2b0a-43ba-ac1a-cae12a69b8fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595179875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1595179875
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2661349286
Short name T159
Test name
Test status
Simulation time 906606965 ps
CPU time 20.24 seconds
Started May 30 03:26:24 PM PDT 24
Finished May 30 03:26:45 PM PDT 24
Peak memory 216024 kb
Host smart-2c3677ec-74f5-4b85-b774-2dbbdadb7969
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661349286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2661349286
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.828400198
Short name T164
Test name
Test status
Simulation time 1130944417 ps
CPU time 7.74 seconds
Started May 30 03:26:47 PM PDT 24
Finished May 30 03:26:55 PM PDT 24
Peak memory 215292 kb
Host smart-484f1c6c-55c5-4ff2-a5dc-d14fbabe328c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828400198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.828400198
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.4283952931
Short name T201
Test name
Test status
Simulation time 78922527191 ps
CPU time 148.63 seconds
Started May 30 03:39:20 PM PDT 24
Finished May 30 03:41:52 PM PDT 24
Peak memory 249048 kb
Host smart-996e4555-899c-4a32-8993-640861ad8b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283952931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.4283952931
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3704304915
Short name T280
Test name
Test status
Simulation time 544058661 ps
CPU time 6.97 seconds
Started May 30 03:39:19 PM PDT 24
Finished May 30 03:39:29 PM PDT 24
Peak memory 224376 kb
Host smart-77d2c55e-bff7-4767-9847-29b7b6bff292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704304915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3704304915
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1370460693
Short name T150
Test name
Test status
Simulation time 24348326543 ps
CPU time 281.95 seconds
Started May 30 03:39:17 PM PDT 24
Finished May 30 03:44:01 PM PDT 24
Peak memory 257272 kb
Host smart-b5fdd52a-23fb-425c-848c-fcccfb680163
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370460693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1370460693
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3858057851
Short name T202
Test name
Test status
Simulation time 4593131921 ps
CPU time 121.2 seconds
Started May 30 03:40:21 PM PDT 24
Finished May 30 03:42:24 PM PDT 24
Peak memory 264220 kb
Host smart-bc7ed5e7-3fae-479d-aa52-f2b4e386a225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858057851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3858057851
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3312157822
Short name T188
Test name
Test status
Simulation time 65019076149 ps
CPU time 123.75 seconds
Started May 30 03:40:24 PM PDT 24
Finished May 30 03:42:29 PM PDT 24
Peak memory 266096 kb
Host smart-045a4c0d-7f2a-4d3a-812f-ee978a6636aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312157822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3312157822
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3198510149
Short name T932
Test name
Test status
Simulation time 6429581477 ps
CPU time 78.08 seconds
Started May 30 03:40:31 PM PDT 24
Finished May 30 03:41:52 PM PDT 24
Peak memory 256320 kb
Host smart-4aa0d430-991d-4eb7-b65f-50500382ec17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198510149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3198510149
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3966313455
Short name T532
Test name
Test status
Simulation time 18540743293 ps
CPU time 37.16 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:41:20 PM PDT 24
Peak memory 240908 kb
Host smart-1ea2f0f9-e804-4f45-8d42-95ef0eb84a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966313455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3966313455
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1852746209
Short name T192
Test name
Test status
Simulation time 22264411391 ps
CPU time 20.41 seconds
Started May 30 03:41:03 PM PDT 24
Finished May 30 03:41:26 PM PDT 24
Peak memory 234240 kb
Host smart-e7b90972-58c2-4aa4-bc22-e246a1241cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852746209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1852746209
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3910071270
Short name T274
Test name
Test status
Simulation time 4610277885 ps
CPU time 62.26 seconds
Started May 30 03:41:26 PM PDT 24
Finished May 30 03:42:33 PM PDT 24
Peak memory 252476 kb
Host smart-8a968a81-9722-4f29-b509-790042b6940e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910071270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3910071270
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2538476937
Short name T260
Test name
Test status
Simulation time 258552409684 ps
CPU time 591.56 seconds
Started May 30 03:39:24 PM PDT 24
Finished May 30 03:49:18 PM PDT 24
Peak memory 255688 kb
Host smart-ab202a02-311f-4723-8e6f-f64620312a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538476937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2538476937
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1399598362
Short name T80
Test name
Test status
Simulation time 1006519340 ps
CPU time 3.15 seconds
Started May 30 03:39:52 PM PDT 24
Finished May 30 03:39:58 PM PDT 24
Peak memory 218348 kb
Host smart-ac1918d8-8707-43cc-9e5a-df0141e80ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399598362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1399598362
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2742798596
Short name T83
Test name
Test status
Simulation time 5017156536 ps
CPU time 7.84 seconds
Started May 30 03:39:52 PM PDT 24
Finished May 30 03:40:02 PM PDT 24
Peak memory 236144 kb
Host smart-420baf09-f5cb-4fa7-bdde-62f9d119bf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742798596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2742798596
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.271696595
Short name T75
Test name
Test status
Simulation time 52747277 ps
CPU time 1.47 seconds
Started May 30 03:25:27 PM PDT 24
Finished May 30 03:25:30 PM PDT 24
Peak memory 207020 kb
Host smart-d71cd507-bef0-4206-bc38-3a95c80ebb6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271696595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.271696595
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.960307627
Short name T45
Test name
Test status
Simulation time 9031614502 ps
CPU time 42.52 seconds
Started May 30 03:40:11 PM PDT 24
Finished May 30 03:40:54 PM PDT 24
Peak memory 252668 kb
Host smart-21453d77-6f53-461c-9273-125086ef20bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960307627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.960307627
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1894947826
Short name T102
Test name
Test status
Simulation time 545710738 ps
CPU time 33.38 seconds
Started May 30 03:25:16 PM PDT 24
Finished May 30 03:25:51 PM PDT 24
Peak memory 206916 kb
Host smart-a774e430-84fb-42a5-af23-b68a514622d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894947826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1894947826
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.270158975
Short name T988
Test name
Test status
Simulation time 29919976 ps
CPU time 1.23 seconds
Started May 30 03:25:15 PM PDT 24
Finished May 30 03:25:17 PM PDT 24
Peak memory 216180 kb
Host smart-3cdb8ae5-bf17-4712-97f8-7fb89dc823c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270158975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.270158975
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1278694887
Short name T95
Test name
Test status
Simulation time 26734352 ps
CPU time 1.84 seconds
Started May 30 03:25:13 PM PDT 24
Finished May 30 03:25:16 PM PDT 24
Peak memory 215268 kb
Host smart-19c46714-b983-4807-b974-fcd2214b9347
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278694887 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1278694887
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4208859295
Short name T107
Test name
Test status
Simulation time 93672587 ps
CPU time 2.21 seconds
Started May 30 03:25:15 PM PDT 24
Finished May 30 03:25:18 PM PDT 24
Peak memory 207012 kb
Host smart-a3ecd5b9-93c9-4a5d-a555-96c7ce0260b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208859295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
208859295
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2227518463
Short name T1049
Test name
Test status
Simulation time 15139277 ps
CPU time 0.73 seconds
Started May 30 03:25:18 PM PDT 24
Finished May 30 03:25:19 PM PDT 24
Peak memory 203616 kb
Host smart-d7af8a32-ac77-4740-9fb9-f0a033dba41b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227518463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
227518463
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1362253271
Short name T1009
Test name
Test status
Simulation time 231576710 ps
CPU time 1.32 seconds
Started May 30 03:25:14 PM PDT 24
Finished May 30 03:25:16 PM PDT 24
Peak memory 215232 kb
Host smart-f656b810-6c10-4f09-a5f9-bc761c58724b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362253271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1362253271
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1943898075
Short name T1072
Test name
Test status
Simulation time 44061808 ps
CPU time 0.69 seconds
Started May 30 03:25:14 PM PDT 24
Finished May 30 03:25:16 PM PDT 24
Peak memory 203524 kb
Host smart-fe5fee42-9279-4416-9967-2aeaa55ffc93
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943898075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1943898075
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.512146796
Short name T996
Test name
Test status
Simulation time 544920482 ps
CPU time 4.14 seconds
Started May 30 03:25:15 PM PDT 24
Finished May 30 03:25:20 PM PDT 24
Peak memory 215156 kb
Host smart-0ddbed50-15fa-4abe-98b8-7856d332b451
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512146796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.512146796
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3048684224
Short name T156
Test name
Test status
Simulation time 1934255342 ps
CPU time 4.86 seconds
Started May 30 03:25:13 PM PDT 24
Finished May 30 03:25:19 PM PDT 24
Peak memory 215672 kb
Host smart-a2c89979-4e2c-43e1-bd96-970d4ea37bea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048684224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
048684224
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2836693134
Short name T86
Test name
Test status
Simulation time 1336384003 ps
CPU time 7.84 seconds
Started May 30 03:25:16 PM PDT 24
Finished May 30 03:25:25 PM PDT 24
Peak memory 215708 kb
Host smart-389f0b6b-c3c1-4249-bceb-df5dff99e87e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836693134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2836693134
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2082165783
Short name T994
Test name
Test status
Simulation time 381781103 ps
CPU time 8.3 seconds
Started May 30 03:25:27 PM PDT 24
Finished May 30 03:25:37 PM PDT 24
Peak memory 215192 kb
Host smart-95c6dbd0-a2d1-4269-9205-f6fb4740ab41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082165783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2082165783
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3627478309
Short name T1022
Test name
Test status
Simulation time 739758434 ps
CPU time 12.1 seconds
Started May 30 03:25:26 PM PDT 24
Finished May 30 03:25:40 PM PDT 24
Peak memory 207024 kb
Host smart-d7c3e997-6c77-4665-832a-530ab623f658
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627478309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3627478309
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.156339898
Short name T977
Test name
Test status
Simulation time 60823183 ps
CPU time 4.09 seconds
Started May 30 03:25:25 PM PDT 24
Finished May 30 03:25:31 PM PDT 24
Peak memory 217464 kb
Host smart-41b5ba33-23b1-4ca7-90db-f89cf2d625ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156339898 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.156339898
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.8905921
Short name T1026
Test name
Test status
Simulation time 32444287 ps
CPU time 1.22 seconds
Started May 30 03:25:25 PM PDT 24
Finished May 30 03:25:27 PM PDT 24
Peak memory 206984 kb
Host smart-99b489bc-a9fb-43bb-8883-466ee4aef3e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8905921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.8905921
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.167034462
Short name T1012
Test name
Test status
Simulation time 13509477 ps
CPU time 0.7 seconds
Started May 30 03:25:27 PM PDT 24
Finished May 30 03:25:29 PM PDT 24
Peak memory 203632 kb
Host smart-bd8c99c7-7de1-4e8a-9aee-0328e89d054b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167034462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.167034462
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2251197764
Short name T1004
Test name
Test status
Simulation time 69396220 ps
CPU time 1.21 seconds
Started May 30 03:25:25 PM PDT 24
Finished May 30 03:25:28 PM PDT 24
Peak memory 215256 kb
Host smart-91e64aa9-e532-4f8a-ad48-666e63e805ba
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251197764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2251197764
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4241819235
Short name T1007
Test name
Test status
Simulation time 46065356 ps
CPU time 0.66 seconds
Started May 30 03:25:25 PM PDT 24
Finished May 30 03:25:26 PM PDT 24
Peak memory 203476 kb
Host smart-995cafed-6e3f-49fe-9792-7bbf697abc11
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241819235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4241819235
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4051868814
Short name T1063
Test name
Test status
Simulation time 276708408 ps
CPU time 1.78 seconds
Started May 30 03:25:25 PM PDT 24
Finished May 30 03:25:28 PM PDT 24
Peak memory 207012 kb
Host smart-fefb2ae4-aee1-4c28-a1c3-58b33b5e3107
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051868814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.4051868814
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1356732604
Short name T1017
Test name
Test status
Simulation time 119912595 ps
CPU time 3.79 seconds
Started May 30 03:25:25 PM PDT 24
Finished May 30 03:25:30 PM PDT 24
Peak memory 216312 kb
Host smart-29d4d2ed-5d27-45b3-a9b8-1f5a1cef4a89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356732604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
356732604
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2116944416
Short name T97
Test name
Test status
Simulation time 84594295 ps
CPU time 2.58 seconds
Started May 30 03:26:16 PM PDT 24
Finished May 30 03:26:20 PM PDT 24
Peak memory 215476 kb
Host smart-0ae1f644-60ad-4566-accf-dbd789a59e5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116944416 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2116944416
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2042469902
Short name T1032
Test name
Test status
Simulation time 153246948 ps
CPU time 1.34 seconds
Started May 30 03:26:14 PM PDT 24
Finished May 30 03:26:17 PM PDT 24
Peak memory 207040 kb
Host smart-cfe54696-8032-4c20-b48f-bfff3ed1503b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042469902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2042469902
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3836522449
Short name T961
Test name
Test status
Simulation time 16028747 ps
CPU time 0.73 seconds
Started May 30 03:26:15 PM PDT 24
Finished May 30 03:26:17 PM PDT 24
Peak memory 203700 kb
Host smart-083566d9-6c6e-4f62-b000-6350454c44eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836522449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3836522449
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2430303665
Short name T975
Test name
Test status
Simulation time 300820944 ps
CPU time 1.69 seconds
Started May 30 03:26:14 PM PDT 24
Finished May 30 03:26:17 PM PDT 24
Peak memory 215156 kb
Host smart-5978bab3-90e0-4d37-b80f-ea410360f4ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430303665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2430303665
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1067092728
Short name T1035
Test name
Test status
Simulation time 4385573203 ps
CPU time 8.47 seconds
Started May 30 03:26:17 PM PDT 24
Finished May 30 03:26:27 PM PDT 24
Peak memory 215908 kb
Host smart-c2fe0ab0-9122-4eca-ba06-4664a35e6310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067092728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1067092728
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.774583472
Short name T1023
Test name
Test status
Simulation time 49150151 ps
CPU time 1.63 seconds
Started May 30 03:26:14 PM PDT 24
Finished May 30 03:26:17 PM PDT 24
Peak memory 215296 kb
Host smart-ebaaad88-7655-4cfa-b7a0-54326a0938d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774583472 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.774583472
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.511302165
Short name T1006
Test name
Test status
Simulation time 250811965 ps
CPU time 1.27 seconds
Started May 30 03:26:15 PM PDT 24
Finished May 30 03:26:18 PM PDT 24
Peak memory 207036 kb
Host smart-82ce4029-c638-4b4c-8ade-846fe4780f18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511302165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.511302165
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3000894341
Short name T965
Test name
Test status
Simulation time 32116491 ps
CPU time 0.74 seconds
Started May 30 03:26:16 PM PDT 24
Finished May 30 03:26:18 PM PDT 24
Peak memory 203656 kb
Host smart-3b1d08b7-4a9c-4f6e-81e0-a1e1b5874d63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000894341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3000894341
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3182729941
Short name T125
Test name
Test status
Simulation time 315489882 ps
CPU time 3.73 seconds
Started May 30 03:26:16 PM PDT 24
Finished May 30 03:26:21 PM PDT 24
Peak memory 215224 kb
Host smart-bc05118d-345b-46c5-acdf-d91331b654cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182729941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3182729941
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3585981295
Short name T93
Test name
Test status
Simulation time 170148802 ps
CPU time 2.29 seconds
Started May 30 03:26:16 PM PDT 24
Finished May 30 03:26:20 PM PDT 24
Peak memory 219028 kb
Host smart-44659ed7-6390-4bf7-8cb0-10b0b62433b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585981295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3585981295
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4060717143
Short name T158
Test name
Test status
Simulation time 122235707 ps
CPU time 6.48 seconds
Started May 30 03:26:15 PM PDT 24
Finished May 30 03:26:23 PM PDT 24
Peak memory 215188 kb
Host smart-1d7283cc-a582-4377-8bca-819d741d703a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060717143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4060717143
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3170438043
Short name T108
Test name
Test status
Simulation time 102882767 ps
CPU time 2.59 seconds
Started May 30 03:26:27 PM PDT 24
Finished May 30 03:26:30 PM PDT 24
Peak memory 206924 kb
Host smart-668b2552-88ee-47aa-bc3c-9e7d6d8490e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170438043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3170438043
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3862323497
Short name T964
Test name
Test status
Simulation time 17334877 ps
CPU time 0.72 seconds
Started May 30 03:26:26 PM PDT 24
Finished May 30 03:26:28 PM PDT 24
Peak memory 203984 kb
Host smart-494c314a-847c-461d-a7a3-86145b9153b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862323497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3862323497
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2612646260
Short name T1020
Test name
Test status
Simulation time 135074416 ps
CPU time 1.84 seconds
Started May 30 03:26:25 PM PDT 24
Finished May 30 03:26:28 PM PDT 24
Peak memory 215248 kb
Host smart-842b194a-cb64-4a31-a492-93d352362c69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612646260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2612646260
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3767192777
Short name T94
Test name
Test status
Simulation time 87884406 ps
CPU time 3.39 seconds
Started May 30 03:26:25 PM PDT 24
Finished May 30 03:26:30 PM PDT 24
Peak memory 218784 kb
Host smart-5aed3629-f682-4f00-99eb-9fe7d07a0107
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767192777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3767192777
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2670572604
Short name T993
Test name
Test status
Simulation time 382626846 ps
CPU time 2.64 seconds
Started May 30 03:26:27 PM PDT 24
Finished May 30 03:26:31 PM PDT 24
Peak memory 216212 kb
Host smart-c3f95854-1794-4a87-a002-1f46fbe58d10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670572604 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2670572604
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1755100422
Short name T104
Test name
Test status
Simulation time 33068757 ps
CPU time 2.26 seconds
Started May 30 03:26:24 PM PDT 24
Finished May 30 03:26:27 PM PDT 24
Peak memory 220060 kb
Host smart-b5562fea-2557-4632-aa3b-3318cc93d190
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755100422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1755100422
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1983448751
Short name T999
Test name
Test status
Simulation time 42443129 ps
CPU time 0.72 seconds
Started May 30 03:26:25 PM PDT 24
Finished May 30 03:26:26 PM PDT 24
Peak memory 203992 kb
Host smart-59a0ac4c-6984-4952-8208-0aaed0bea507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983448751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1983448751
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.938944386
Short name T1036
Test name
Test status
Simulation time 226381397 ps
CPU time 3.7 seconds
Started May 30 03:26:27 PM PDT 24
Finished May 30 03:26:31 PM PDT 24
Peak memory 215180 kb
Host smart-a6e87efc-8363-4652-87f2-2e050137f329
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938944386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.938944386
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1333826249
Short name T1070
Test name
Test status
Simulation time 155419602 ps
CPU time 4.5 seconds
Started May 30 03:26:25 PM PDT 24
Finished May 30 03:26:31 PM PDT 24
Peak memory 216396 kb
Host smart-c18440cd-585c-428e-a315-b2e843f2ce76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333826249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1333826249
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4140558959
Short name T61
Test name
Test status
Simulation time 2046278029 ps
CPU time 13.5 seconds
Started May 30 03:26:25 PM PDT 24
Finished May 30 03:26:40 PM PDT 24
Peak memory 215208 kb
Host smart-ff2e7495-a0cc-41c7-a607-72b238ab9953
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140558959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4140558959
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2770391380
Short name T139
Test name
Test status
Simulation time 92012803 ps
CPU time 2.48 seconds
Started May 30 03:26:25 PM PDT 24
Finished May 30 03:26:29 PM PDT 24
Peak memory 216304 kb
Host smart-85aa77a3-af61-459b-aaaf-6bfc797b3427
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770391380 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2770391380
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.327843706
Short name T978
Test name
Test status
Simulation time 31552187 ps
CPU time 1.32 seconds
Started May 30 03:26:28 PM PDT 24
Finished May 30 03:26:30 PM PDT 24
Peak memory 214856 kb
Host smart-76c8e8c3-8469-4012-bf46-0e9238b742d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327843706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.327843706
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.679220047
Short name T1065
Test name
Test status
Simulation time 118169621 ps
CPU time 0.75 seconds
Started May 30 03:26:24 PM PDT 24
Finished May 30 03:26:26 PM PDT 24
Peak memory 203664 kb
Host smart-73183d6d-9869-46d5-97db-a1dc3da8ef0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679220047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.679220047
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2204349648
Short name T1001
Test name
Test status
Simulation time 64544959 ps
CPU time 1.75 seconds
Started May 30 03:26:26 PM PDT 24
Finished May 30 03:26:29 PM PDT 24
Peak memory 215184 kb
Host smart-972912c8-03a0-45ae-b4b9-7b65320ecb7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204349648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2204349648
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.84383910
Short name T157
Test name
Test status
Simulation time 636994685 ps
CPU time 15.34 seconds
Started May 30 03:26:28 PM PDT 24
Finished May 30 03:26:44 PM PDT 24
Peak memory 215792 kb
Host smart-04bcd851-7b7d-4cf4-92c0-d65dc15c8597
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84383910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_
tl_intg_err.84383910
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2031215959
Short name T982
Test name
Test status
Simulation time 458543944 ps
CPU time 2.94 seconds
Started May 30 03:26:37 PM PDT 24
Finished May 30 03:26:41 PM PDT 24
Peak memory 217524 kb
Host smart-17dcdd0f-b4cd-4c71-b735-8dec4c370028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031215959 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2031215959
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.598876411
Short name T1033
Test name
Test status
Simulation time 345376710 ps
CPU time 2.45 seconds
Started May 30 03:26:26 PM PDT 24
Finished May 30 03:26:30 PM PDT 24
Peak memory 215192 kb
Host smart-63d00754-adf1-4199-af8e-ae333f19074f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598876411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.598876411
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2981553756
Short name T1047
Test name
Test status
Simulation time 32464482 ps
CPU time 0.69 seconds
Started May 30 03:26:25 PM PDT 24
Finished May 30 03:26:27 PM PDT 24
Peak memory 203980 kb
Host smart-a630b22b-91e6-4191-917d-e533be66f7fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981553756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2981553756
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1200073556
Short name T985
Test name
Test status
Simulation time 285118572 ps
CPU time 3.6 seconds
Started May 30 03:26:36 PM PDT 24
Finished May 30 03:26:41 PM PDT 24
Peak memory 215180 kb
Host smart-456235fb-21a2-415c-b435-1df537c35aea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200073556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1200073556
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2450551068
Short name T89
Test name
Test status
Simulation time 1853828902 ps
CPU time 4.33 seconds
Started May 30 03:26:25 PM PDT 24
Finished May 30 03:26:31 PM PDT 24
Peak memory 216364 kb
Host smart-dfa8ac53-40ed-4ad1-b5a6-d2613cce66fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450551068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2450551068
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1135111620
Short name T980
Test name
Test status
Simulation time 555101095 ps
CPU time 7.74 seconds
Started May 30 03:26:25 PM PDT 24
Finished May 30 03:26:34 PM PDT 24
Peak memory 215360 kb
Host smart-771fbc92-8954-4d1e-a064-86e5c0561a52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135111620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1135111620
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1844505035
Short name T135
Test name
Test status
Simulation time 1259150667 ps
CPU time 4.12 seconds
Started May 30 03:26:39 PM PDT 24
Finished May 30 03:26:45 PM PDT 24
Peak memory 218092 kb
Host smart-de71cf21-e2b9-461a-b899-5f4328096d6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844505035 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1844505035
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.427552783
Short name T1044
Test name
Test status
Simulation time 73527149 ps
CPU time 1.35 seconds
Started May 30 03:26:36 PM PDT 24
Finished May 30 03:26:39 PM PDT 24
Peak memory 215208 kb
Host smart-cda87bfe-769e-4805-94bf-9a46230cf911
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427552783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.427552783
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3675075032
Short name T1030
Test name
Test status
Simulation time 12259616 ps
CPU time 0.71 seconds
Started May 30 03:26:36 PM PDT 24
Finished May 30 03:26:38 PM PDT 24
Peak memory 203928 kb
Host smart-18b25e9d-713e-4d32-a721-8787681bfae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675075032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3675075032
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3021500271
Short name T1039
Test name
Test status
Simulation time 773686604 ps
CPU time 2.79 seconds
Started May 30 03:26:36 PM PDT 24
Finished May 30 03:26:40 PM PDT 24
Peak memory 215248 kb
Host smart-05f700fa-ca52-4956-8228-bffff60465f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021500271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3021500271
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4027477097
Short name T1081
Test name
Test status
Simulation time 144538670 ps
CPU time 3.69 seconds
Started May 30 03:26:38 PM PDT 24
Finished May 30 03:26:44 PM PDT 24
Peak memory 216084 kb
Host smart-05e28daa-262d-458f-8957-f8d70a6b7f2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027477097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
4027477097
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1525746061
Short name T1037
Test name
Test status
Simulation time 2290665001 ps
CPU time 13.93 seconds
Started May 30 03:26:38 PM PDT 24
Finished May 30 03:26:55 PM PDT 24
Peak memory 215116 kb
Host smart-a6edb3cc-6367-4de0-8890-864f496fbb6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525746061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1525746061
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1990236540
Short name T96
Test name
Test status
Simulation time 46577561 ps
CPU time 1.54 seconds
Started May 30 03:26:37 PM PDT 24
Finished May 30 03:26:40 PM PDT 24
Peak memory 215180 kb
Host smart-cc3e7507-bb17-4938-b1d8-ab9261ef0b4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990236540 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1990236540
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2613717184
Short name T1008
Test name
Test status
Simulation time 30517371 ps
CPU time 2.01 seconds
Started May 30 03:26:37 PM PDT 24
Finished May 30 03:26:40 PM PDT 24
Peak memory 206920 kb
Host smart-fe6483a9-8d11-4e2f-82a3-234a1173832d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613717184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2613717184
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2529157575
Short name T971
Test name
Test status
Simulation time 28098628 ps
CPU time 0.73 seconds
Started May 30 03:26:37 PM PDT 24
Finished May 30 03:26:40 PM PDT 24
Peak memory 203968 kb
Host smart-5a740db6-6ec2-4aa5-928e-1542ccb91724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529157575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2529157575
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4177816134
Short name T1052
Test name
Test status
Simulation time 210820279 ps
CPU time 1.72 seconds
Started May 30 03:26:40 PM PDT 24
Finished May 30 03:26:43 PM PDT 24
Peak memory 215256 kb
Host smart-3986b1bb-6890-4e34-bbb7-ca2da89a3eea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177816134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.4177816134
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.295349227
Short name T85
Test name
Test status
Simulation time 274534616 ps
CPU time 3.94 seconds
Started May 30 03:26:39 PM PDT 24
Finished May 30 03:26:45 PM PDT 24
Peak memory 215360 kb
Host smart-4b8a0894-03ae-420c-8e12-7368b02949a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295349227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.295349227
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3513629082
Short name T1074
Test name
Test status
Simulation time 573909210 ps
CPU time 2.91 seconds
Started May 30 03:26:47 PM PDT 24
Finished May 30 03:26:51 PM PDT 24
Peak memory 216620 kb
Host smart-50d90694-971b-4b5c-95c3-b313118f43d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513629082 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3513629082
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.449604520
Short name T990
Test name
Test status
Simulation time 110466377 ps
CPU time 1.95 seconds
Started May 30 03:26:48 PM PDT 24
Finished May 30 03:26:51 PM PDT 24
Peak memory 215156 kb
Host smart-336f4803-8cd9-4844-acae-a8c4473e4899
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449604520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.449604520
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.7508584
Short name T1061
Test name
Test status
Simulation time 14487667 ps
CPU time 0.74 seconds
Started May 30 03:26:47 PM PDT 24
Finished May 30 03:26:49 PM PDT 24
Peak memory 203688 kb
Host smart-83b7e326-87e9-483a-b23b-99dd32701eee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7508584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.7508584
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2850789716
Short name T1046
Test name
Test status
Simulation time 144762886 ps
CPU time 2.5 seconds
Started May 30 03:26:46 PM PDT 24
Finished May 30 03:26:49 PM PDT 24
Peak memory 215184 kb
Host smart-95ef9bed-f1f5-496e-9143-5f35c50d0fb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850789716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2850789716
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1304692984
Short name T91
Test name
Test status
Simulation time 240760970 ps
CPU time 5.31 seconds
Started May 30 03:26:48 PM PDT 24
Finished May 30 03:26:54 PM PDT 24
Peak memory 215428 kb
Host smart-1e17a854-428b-4449-98fc-46d47b64ba3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304692984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1304692984
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2532844677
Short name T160
Test name
Test status
Simulation time 1165477499 ps
CPU time 18.45 seconds
Started May 30 03:26:47 PM PDT 24
Finished May 30 03:27:06 PM PDT 24
Peak memory 215196 kb
Host smart-0a98e83f-ebe6-4894-8faf-528ee3f43a62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532844677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2532844677
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2736153986
Short name T1018
Test name
Test status
Simulation time 119829693 ps
CPU time 1.87 seconds
Started May 30 03:26:47 PM PDT 24
Finished May 30 03:26:50 PM PDT 24
Peak memory 215300 kb
Host smart-b32e5c6b-ed20-414c-b227-b253688968ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736153986 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2736153986
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2317523319
Short name T109
Test name
Test status
Simulation time 47982762 ps
CPU time 2.82 seconds
Started May 30 03:26:48 PM PDT 24
Finished May 30 03:26:52 PM PDT 24
Peak memory 215156 kb
Host smart-714539f7-5fe8-41e4-9fb6-414f2e8e4768
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317523319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2317523319
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.456692144
Short name T979
Test name
Test status
Simulation time 12889306 ps
CPU time 0.65 seconds
Started May 30 03:26:46 PM PDT 24
Finished May 30 03:26:48 PM PDT 24
Peak memory 203652 kb
Host smart-8fb057e5-ecb0-4540-b5b5-b0534a474103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456692144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.456692144
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1497221994
Short name T137
Test name
Test status
Simulation time 205884745 ps
CPU time 3.98 seconds
Started May 30 03:26:47 PM PDT 24
Finished May 30 03:26:52 PM PDT 24
Peak memory 215152 kb
Host smart-58908fb9-3818-46cd-a066-6b21f5aa403c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497221994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1497221994
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2288529414
Short name T88
Test name
Test status
Simulation time 641305934 ps
CPU time 4.64 seconds
Started May 30 03:26:45 PM PDT 24
Finished May 30 03:26:51 PM PDT 24
Peak memory 215592 kb
Host smart-ac40551e-4d56-41b6-8d08-9b34f94e0229
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288529414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2288529414
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2573499399
Short name T1064
Test name
Test status
Simulation time 211079702 ps
CPU time 7.67 seconds
Started May 30 03:25:38 PM PDT 24
Finished May 30 03:25:47 PM PDT 24
Peak memory 215220 kb
Host smart-ac2b60dd-94d1-4fb7-9ae0-930985685fa7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573499399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2573499399
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3107244629
Short name T987
Test name
Test status
Simulation time 5025653940 ps
CPU time 25.16 seconds
Started May 30 03:25:37 PM PDT 24
Finished May 30 03:26:03 PM PDT 24
Peak memory 207120 kb
Host smart-9fc44f19-b722-4041-98f0-9f1edac3a552
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107244629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3107244629
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2661797227
Short name T76
Test name
Test status
Simulation time 413764959 ps
CPU time 1.41 seconds
Started May 30 03:25:39 PM PDT 24
Finished May 30 03:25:42 PM PDT 24
Peak memory 206904 kb
Host smart-b5d253bf-4a4d-40e7-8ea3-4bec3742cbc5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661797227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2661797227
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3965723117
Short name T1016
Test name
Test status
Simulation time 238629621 ps
CPU time 1.65 seconds
Started May 30 03:25:38 PM PDT 24
Finished May 30 03:25:42 PM PDT 24
Peak memory 215268 kb
Host smart-075f3714-562e-4066-bfe2-9fd90e111452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965723117 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3965723117
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2797160649
Short name T1015
Test name
Test status
Simulation time 396360134 ps
CPU time 1.76 seconds
Started May 30 03:25:38 PM PDT 24
Finished May 30 03:25:41 PM PDT 24
Peak memory 215092 kb
Host smart-0c29abd1-fbb5-4581-83a3-f9cb175cbc97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797160649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
797160649
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2126443583
Short name T981
Test name
Test status
Simulation time 16061686 ps
CPU time 0.7 seconds
Started May 30 03:25:26 PM PDT 24
Finished May 30 03:25:28 PM PDT 24
Peak memory 203688 kb
Host smart-c68c8469-b420-4a97-9941-45f0c5bcbb5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126443583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
126443583
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3350675064
Short name T101
Test name
Test status
Simulation time 1072368174 ps
CPU time 2.18 seconds
Started May 30 03:25:27 PM PDT 24
Finished May 30 03:25:31 PM PDT 24
Peak memory 215224 kb
Host smart-aa88019c-6746-41d2-8b6d-bbb09b6d8f72
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350675064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3350675064
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3142251083
Short name T1038
Test name
Test status
Simulation time 11028174 ps
CPU time 0.64 seconds
Started May 30 03:25:27 PM PDT 24
Finished May 30 03:25:29 PM PDT 24
Peak memory 203548 kb
Host smart-88fef28a-4ddf-4dec-910c-20d693ece497
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142251083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3142251083
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2105252289
Short name T123
Test name
Test status
Simulation time 651667118 ps
CPU time 4.29 seconds
Started May 30 03:25:36 PM PDT 24
Finished May 30 03:25:41 PM PDT 24
Peak memory 215216 kb
Host smart-c902d978-3416-49a6-8745-0751d4c2d324
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105252289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2105252289
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2526852953
Short name T1031
Test name
Test status
Simulation time 903010950 ps
CPU time 5 seconds
Started May 30 03:25:26 PM PDT 24
Finished May 30 03:25:32 PM PDT 24
Peak memory 215400 kb
Host smart-ca92190c-a9c3-47ea-82b9-57e29f6f5521
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526852953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
526852953
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.262820536
Short name T163
Test name
Test status
Simulation time 1389191252 ps
CPU time 13.97 seconds
Started May 30 03:25:26 PM PDT 24
Finished May 30 03:25:41 PM PDT 24
Peak memory 215652 kb
Host smart-267c25d1-5017-4dd3-a6a6-11a14eec4637
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262820536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.262820536
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3027856795
Short name T966
Test name
Test status
Simulation time 20141897 ps
CPU time 0.7 seconds
Started May 30 03:26:46 PM PDT 24
Finished May 30 03:26:47 PM PDT 24
Peak memory 203984 kb
Host smart-87432490-f269-4978-8963-67d06c31283e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027856795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3027856795
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2561308637
Short name T1048
Test name
Test status
Simulation time 31034679 ps
CPU time 0.76 seconds
Started May 30 03:26:46 PM PDT 24
Finished May 30 03:26:48 PM PDT 24
Peak memory 203604 kb
Host smart-e27e94f3-8d49-43eb-be55-3f970b9e2920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561308637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2561308637
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1764913061
Short name T974
Test name
Test status
Simulation time 26933534 ps
CPU time 0.69 seconds
Started May 30 03:26:47 PM PDT 24
Finished May 30 03:26:49 PM PDT 24
Peak memory 203980 kb
Host smart-75ad96b3-c00a-430a-b687-1e79786ff7eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764913061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1764913061
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2335407965
Short name T967
Test name
Test status
Simulation time 106098453 ps
CPU time 0.73 seconds
Started May 30 03:26:48 PM PDT 24
Finished May 30 03:26:49 PM PDT 24
Peak memory 203996 kb
Host smart-8f888bd9-e69c-46e7-af09-f156757669da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335407965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2335407965
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3257644361
Short name T1059
Test name
Test status
Simulation time 18276321 ps
CPU time 0.7 seconds
Started May 30 03:26:46 PM PDT 24
Finished May 30 03:26:48 PM PDT 24
Peak memory 203696 kb
Host smart-990767ac-7faa-4947-8205-d080352df691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257644361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3257644361
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4286238319
Short name T1076
Test name
Test status
Simulation time 18070752 ps
CPU time 0.67 seconds
Started May 30 03:26:49 PM PDT 24
Finished May 30 03:26:51 PM PDT 24
Peak memory 203968 kb
Host smart-38f2bd80-ae4b-4525-942c-b1a280291732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286238319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
4286238319
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2347878206
Short name T1058
Test name
Test status
Simulation time 11553557 ps
CPU time 0.73 seconds
Started May 30 03:26:54 PM PDT 24
Finished May 30 03:26:56 PM PDT 24
Peak memory 203960 kb
Host smart-01566bfe-c572-4f22-9027-cad554ea9f77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347878206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2347878206
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3508556425
Short name T972
Test name
Test status
Simulation time 19984574 ps
CPU time 0.78 seconds
Started May 30 03:26:54 PM PDT 24
Finished May 30 03:26:56 PM PDT 24
Peak memory 203964 kb
Host smart-b95305b7-847c-432c-873b-0ef4b7a09c78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508556425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3508556425
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1363589541
Short name T968
Test name
Test status
Simulation time 11645353 ps
CPU time 0.72 seconds
Started May 30 03:26:47 PM PDT 24
Finished May 30 03:26:49 PM PDT 24
Peak memory 203636 kb
Host smart-dd438bb8-9c7b-4ebb-b8cd-07be1ca19c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363589541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1363589541
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3342859632
Short name T1011
Test name
Test status
Simulation time 17191487 ps
CPU time 0.73 seconds
Started May 30 03:26:49 PM PDT 24
Finished May 30 03:26:50 PM PDT 24
Peak memory 203660 kb
Host smart-3daf7cb2-0cf6-4df8-8cdd-d7e21f68cda2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342859632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3342859632
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3977796061
Short name T110
Test name
Test status
Simulation time 7602647011 ps
CPU time 25.22 seconds
Started May 30 03:25:40 PM PDT 24
Finished May 30 03:26:06 PM PDT 24
Peak memory 215320 kb
Host smart-955ce5a5-14fb-48b5-ad07-f1e4eb0a923d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977796061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3977796061
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2957770660
Short name T1013
Test name
Test status
Simulation time 2902722813 ps
CPU time 12.98 seconds
Started May 30 03:25:38 PM PDT 24
Finished May 30 03:25:52 PM PDT 24
Peak memory 215264 kb
Host smart-cbc1ccba-d3e9-4473-992a-1cbfda579234
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957770660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2957770660
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3863756991
Short name T1062
Test name
Test status
Simulation time 23982423 ps
CPU time 0.98 seconds
Started May 30 03:25:38 PM PDT 24
Finished May 30 03:25:40 PM PDT 24
Peak memory 206596 kb
Host smart-a4458558-df58-4aa0-9f73-211b6674aac0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863756991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3863756991
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2321732924
Short name T136
Test name
Test status
Simulation time 113081138 ps
CPU time 2.62 seconds
Started May 30 03:25:54 PM PDT 24
Finished May 30 03:25:57 PM PDT 24
Peak memory 216580 kb
Host smart-8b9f7f87-6c8b-4a1b-aa30-6bf1afd3c392
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321732924 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2321732924
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2644669745
Short name T111
Test name
Test status
Simulation time 33368129 ps
CPU time 1.62 seconds
Started May 30 03:25:40 PM PDT 24
Finished May 30 03:25:43 PM PDT 24
Peak memory 215124 kb
Host smart-d597b36a-1bfc-4799-b327-9a83f5d406b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644669745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
644669745
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2587179381
Short name T1066
Test name
Test status
Simulation time 20817205 ps
CPU time 0.67 seconds
Started May 30 03:25:38 PM PDT 24
Finished May 30 03:25:40 PM PDT 24
Peak memory 203652 kb
Host smart-ca4b0379-f993-4342-a263-1369cf3171cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587179381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
587179381
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4125621795
Short name T1040
Test name
Test status
Simulation time 36465213 ps
CPU time 1.29 seconds
Started May 30 03:25:39 PM PDT 24
Finished May 30 03:25:41 PM PDT 24
Peak memory 215328 kb
Host smart-2766d5de-a482-4223-9275-59b39b42c5f7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125621795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4125621795
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2397409220
Short name T1025
Test name
Test status
Simulation time 38288708 ps
CPU time 0.65 seconds
Started May 30 03:25:37 PM PDT 24
Finished May 30 03:25:39 PM PDT 24
Peak memory 203564 kb
Host smart-2fb7d3f7-95fe-4490-a27f-6d690fca2b1c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397409220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2397409220
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.853267740
Short name T121
Test name
Test status
Simulation time 115969221 ps
CPU time 3.54 seconds
Started May 30 03:25:54 PM PDT 24
Finished May 30 03:25:59 PM PDT 24
Peak memory 215160 kb
Host smart-940fa10f-536f-4977-b114-06a5c18b6723
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853267740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.853267740
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.997439616
Short name T1069
Test name
Test status
Simulation time 729222837 ps
CPU time 4.16 seconds
Started May 30 03:25:39 PM PDT 24
Finished May 30 03:25:44 PM PDT 24
Peak memory 215240 kb
Host smart-16df7e56-ad7c-409d-b509-1c8ab5518e16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997439616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.997439616
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1001559762
Short name T1027
Test name
Test status
Simulation time 1213593428 ps
CPU time 8.03 seconds
Started May 30 03:25:36 PM PDT 24
Finished May 30 03:25:45 PM PDT 24
Peak memory 215280 kb
Host smart-b96f21d9-2f34-42ed-8d24-729ce4f1edea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001559762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1001559762
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1591653261
Short name T1073
Test name
Test status
Simulation time 19914919 ps
CPU time 0.7 seconds
Started May 30 03:26:48 PM PDT 24
Finished May 30 03:26:50 PM PDT 24
Peak memory 203628 kb
Host smart-60ed5149-addc-49d1-af2e-a14385c31f69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591653261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1591653261
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.854136778
Short name T1014
Test name
Test status
Simulation time 14672495 ps
CPU time 0.7 seconds
Started May 30 03:26:48 PM PDT 24
Finished May 30 03:26:49 PM PDT 24
Peak memory 203944 kb
Host smart-9fe45e52-48c3-4831-81b0-1adae15cb498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854136778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.854136778
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.504151875
Short name T986
Test name
Test status
Simulation time 174857593 ps
CPU time 0.69 seconds
Started May 30 03:26:54 PM PDT 24
Finished May 30 03:26:56 PM PDT 24
Peak memory 203656 kb
Host smart-dd0fe18d-4ddd-4a24-a4ab-ddfca80f5c4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504151875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.504151875
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3942224827
Short name T970
Test name
Test status
Simulation time 16177914 ps
CPU time 0.73 seconds
Started May 30 03:27:03 PM PDT 24
Finished May 30 03:27:05 PM PDT 24
Peak memory 203988 kb
Host smart-4cb74a31-fe07-4d21-8c5a-7b440cf4662a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942224827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3942224827
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1998464308
Short name T1071
Test name
Test status
Simulation time 37417148 ps
CPU time 0.69 seconds
Started May 30 03:26:56 PM PDT 24
Finished May 30 03:26:58 PM PDT 24
Peak memory 203668 kb
Host smart-02125d60-47b5-44eb-b03d-f1da760a1179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998464308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1998464308
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3864263981
Short name T969
Test name
Test status
Simulation time 18390191 ps
CPU time 0.68 seconds
Started May 30 03:26:58 PM PDT 24
Finished May 30 03:27:00 PM PDT 24
Peak memory 203660 kb
Host smart-215dbb6e-9a6c-4ce1-bd4e-eda7cef53a70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864263981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3864263981
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1824696652
Short name T991
Test name
Test status
Simulation time 17279368 ps
CPU time 0.8 seconds
Started May 30 03:26:57 PM PDT 24
Finished May 30 03:26:59 PM PDT 24
Peak memory 203672 kb
Host smart-c0f506b8-1416-4613-ac6c-aca5dcdc4dce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824696652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1824696652
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3934883357
Short name T976
Test name
Test status
Simulation time 31828592 ps
CPU time 0.73 seconds
Started May 30 03:27:04 PM PDT 24
Finished May 30 03:27:06 PM PDT 24
Peak memory 203708 kb
Host smart-213216e3-3af7-4862-9289-f95f898370d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934883357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3934883357
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2427971136
Short name T1028
Test name
Test status
Simulation time 14723853 ps
CPU time 0.72 seconds
Started May 30 03:27:02 PM PDT 24
Finished May 30 03:27:03 PM PDT 24
Peak memory 203656 kb
Host smart-e4f7ab3a-7925-4401-acbf-25c54a77d658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427971136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2427971136
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.75812563
Short name T973
Test name
Test status
Simulation time 174484825 ps
CPU time 0.72 seconds
Started May 30 03:26:58 PM PDT 24
Finished May 30 03:27:00 PM PDT 24
Peak memory 203972 kb
Host smart-2ea5816a-8192-440b-944c-ed9f7b2f3d76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75812563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.75812563
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3289038194
Short name T1003
Test name
Test status
Simulation time 213707869 ps
CPU time 15.2 seconds
Started May 30 03:26:04 PM PDT 24
Finished May 30 03:26:20 PM PDT 24
Peak memory 215176 kb
Host smart-003ccb29-d276-4cc6-a4af-370807c214f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289038194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3289038194
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.836954087
Short name T106
Test name
Test status
Simulation time 763857527 ps
CPU time 21.54 seconds
Started May 30 03:26:05 PM PDT 24
Finished May 30 03:26:27 PM PDT 24
Peak memory 207024 kb
Host smart-3b40d178-8498-4e65-97e5-fa49613bb44d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836954087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.836954087
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.33050879
Short name T1060
Test name
Test status
Simulation time 24032281 ps
CPU time 0.94 seconds
Started May 30 03:26:06 PM PDT 24
Finished May 30 03:26:08 PM PDT 24
Peak memory 206788 kb
Host smart-a1c480d0-1972-49f7-85a7-310cc9b0b7db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33050879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
hw_reset.33050879
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.606143184
Short name T997
Test name
Test status
Simulation time 208374587 ps
CPU time 3.55 seconds
Started May 30 03:26:04 PM PDT 24
Finished May 30 03:26:08 PM PDT 24
Peak memory 216788 kb
Host smart-f123ad75-2438-4eed-a5b2-1f8b52653452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606143184 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.606143184
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1745854463
Short name T984
Test name
Test status
Simulation time 293330303 ps
CPU time 2.86 seconds
Started May 30 03:26:04 PM PDT 24
Finished May 30 03:26:08 PM PDT 24
Peak memory 215200 kb
Host smart-fc624698-1262-4aa6-b306-dbb7b9c044af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745854463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
745854463
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1831265652
Short name T1042
Test name
Test status
Simulation time 28363438 ps
CPU time 0.74 seconds
Started May 30 03:25:53 PM PDT 24
Finished May 30 03:25:55 PM PDT 24
Peak memory 203688 kb
Host smart-30c4c6ca-3c63-47bc-9d73-5599f9cc9366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831265652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
831265652
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.5303314
Short name T99
Test name
Test status
Simulation time 196902076 ps
CPU time 1.68 seconds
Started May 30 03:25:54 PM PDT 24
Finished May 30 03:25:56 PM PDT 24
Peak memory 215232 kb
Host smart-f310254a-1760-4734-9460-5af56978d24a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5303314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_
device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_de
vice_mem_partial_access.5303314
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1756796613
Short name T1067
Test name
Test status
Simulation time 12174213 ps
CPU time 0.67 seconds
Started May 30 03:25:54 PM PDT 24
Finished May 30 03:25:56 PM PDT 24
Peak memory 203564 kb
Host smart-5539d580-430f-4f31-a054-7d1a3d373e91
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756796613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1756796613
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2674944579
Short name T1029
Test name
Test status
Simulation time 190577138 ps
CPU time 3.52 seconds
Started May 30 03:26:04 PM PDT 24
Finished May 30 03:26:09 PM PDT 24
Peak memory 215052 kb
Host smart-1fa1e052-6676-44d8-a61d-1a641699f501
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674944579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2674944579
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.848179567
Short name T1043
Test name
Test status
Simulation time 40203794 ps
CPU time 2.53 seconds
Started May 30 03:25:55 PM PDT 24
Finished May 30 03:25:58 PM PDT 24
Peak memory 215352 kb
Host smart-346a883e-fbd2-4147-bb3b-272e77d45a74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848179567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.848179567
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.241024202
Short name T1075
Test name
Test status
Simulation time 2014789109 ps
CPU time 13.57 seconds
Started May 30 03:25:55 PM PDT 24
Finished May 30 03:26:09 PM PDT 24
Peak memory 215160 kb
Host smart-e1eb4f50-72e2-4093-b4f0-eb4e27046537
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241024202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.241024202
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3919729586
Short name T1051
Test name
Test status
Simulation time 12374839 ps
CPU time 0.68 seconds
Started May 30 03:26:56 PM PDT 24
Finished May 30 03:26:58 PM PDT 24
Peak memory 203948 kb
Host smart-861f4c62-2b71-45b2-a7bf-e0e34ed81281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919729586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3919729586
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3811886770
Short name T962
Test name
Test status
Simulation time 49411572 ps
CPU time 0.71 seconds
Started May 30 03:26:58 PM PDT 24
Finished May 30 03:27:00 PM PDT 24
Peak memory 203676 kb
Host smart-da8d814e-d844-4770-9f7a-4fa14099212f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811886770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3811886770
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1716891941
Short name T1055
Test name
Test status
Simulation time 14027158 ps
CPU time 0.72 seconds
Started May 30 03:26:57 PM PDT 24
Finished May 30 03:26:59 PM PDT 24
Peak memory 203944 kb
Host smart-39f98190-424b-466a-875c-9ff1b60b056f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716891941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1716891941
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3922417915
Short name T1024
Test name
Test status
Simulation time 14091747 ps
CPU time 0.75 seconds
Started May 30 03:26:59 PM PDT 24
Finished May 30 03:27:00 PM PDT 24
Peak memory 203672 kb
Host smart-64ca4fd9-7fbb-4808-adce-cb28e82650c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922417915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3922417915
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3098280214
Short name T1002
Test name
Test status
Simulation time 17334731 ps
CPU time 0.77 seconds
Started May 30 03:27:03 PM PDT 24
Finished May 30 03:27:05 PM PDT 24
Peak memory 203684 kb
Host smart-ad8989a2-95bc-4393-b957-a7c2835d4952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098280214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3098280214
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.776310903
Short name T1041
Test name
Test status
Simulation time 14093648 ps
CPU time 0.68 seconds
Started May 30 03:26:59 PM PDT 24
Finished May 30 03:27:01 PM PDT 24
Peak memory 203660 kb
Host smart-b4c1eef3-bb5b-4c28-a72a-2951b1d2e95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776310903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.776310903
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2731291853
Short name T983
Test name
Test status
Simulation time 17758577 ps
CPU time 0.73 seconds
Started May 30 03:26:56 PM PDT 24
Finished May 30 03:26:58 PM PDT 24
Peak memory 203980 kb
Host smart-6a908fab-de68-4924-855c-e178042c0940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731291853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2731291853
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.595373209
Short name T1080
Test name
Test status
Simulation time 17151105 ps
CPU time 0.7 seconds
Started May 30 03:26:57 PM PDT 24
Finished May 30 03:26:59 PM PDT 24
Peak memory 203688 kb
Host smart-b7b97e28-23ea-4447-bc8e-7ff4aba5231d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595373209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.595373209
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4016417521
Short name T1019
Test name
Test status
Simulation time 17375407 ps
CPU time 0.71 seconds
Started May 30 03:26:59 PM PDT 24
Finished May 30 03:27:01 PM PDT 24
Peak memory 203652 kb
Host smart-8fad84b4-3d41-4000-acb2-09211a2fd9d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016417521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
4016417521
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.392169510
Short name T1057
Test name
Test status
Simulation time 13174900 ps
CPU time 0.72 seconds
Started May 30 03:26:58 PM PDT 24
Finished May 30 03:27:00 PM PDT 24
Peak memory 203668 kb
Host smart-8ef6d327-137b-4124-8ac0-cd6ac2ea6c90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392169510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.392169510
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2712946671
Short name T1077
Test name
Test status
Simulation time 299126848 ps
CPU time 1.88 seconds
Started May 30 03:26:05 PM PDT 24
Finished May 30 03:26:08 PM PDT 24
Peak memory 216296 kb
Host smart-7a3b722f-1aba-4198-86a3-9ec80db529ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712946671 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2712946671
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.304156624
Short name T103
Test name
Test status
Simulation time 87004688 ps
CPU time 2.46 seconds
Started May 30 03:26:06 PM PDT 24
Finished May 30 03:26:09 PM PDT 24
Peak memory 206924 kb
Host smart-f2b5579c-07cd-417c-b149-2c2149b8e829
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304156624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.304156624
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3546528499
Short name T1050
Test name
Test status
Simulation time 87964954 ps
CPU time 0.68 seconds
Started May 30 03:26:07 PM PDT 24
Finished May 30 03:26:09 PM PDT 24
Peak memory 203976 kb
Host smart-3cc4ccd2-dc50-4017-af01-b5a3449750b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546528499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
546528499
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1468422788
Short name T122
Test name
Test status
Simulation time 61513754 ps
CPU time 3.75 seconds
Started May 30 03:26:05 PM PDT 24
Finished May 30 03:26:10 PM PDT 24
Peak memory 215600 kb
Host smart-5851af7e-4ab5-41a2-b969-c2a0535ed513
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468422788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1468422788
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.711563585
Short name T1054
Test name
Test status
Simulation time 677155183 ps
CPU time 12.03 seconds
Started May 30 03:26:04 PM PDT 24
Finished May 30 03:26:17 PM PDT 24
Peak memory 215184 kb
Host smart-36567323-d0db-4aea-9956-138b73d33ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711563585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.711563585
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2840216586
Short name T1045
Test name
Test status
Simulation time 181257561 ps
CPU time 1.76 seconds
Started May 30 03:26:07 PM PDT 24
Finished May 30 03:26:10 PM PDT 24
Peak memory 215248 kb
Host smart-39ef6010-c7d8-457a-ac99-9a13202e3bf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840216586 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2840216586
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4271440764
Short name T124
Test name
Test status
Simulation time 412376261 ps
CPU time 2.5 seconds
Started May 30 03:26:04 PM PDT 24
Finished May 30 03:26:08 PM PDT 24
Peak memory 215144 kb
Host smart-6d5667d0-e7ea-4439-9f03-b33fe12434d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271440764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
271440764
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2975564259
Short name T1079
Test name
Test status
Simulation time 24001299 ps
CPU time 0.77 seconds
Started May 30 03:26:05 PM PDT 24
Finished May 30 03:26:07 PM PDT 24
Peak memory 203992 kb
Host smart-ce7e9cb8-a8cd-4d12-a9ba-17ea9e5d95c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975564259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
975564259
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1210004606
Short name T1078
Test name
Test status
Simulation time 260540375 ps
CPU time 1.81 seconds
Started May 30 03:26:06 PM PDT 24
Finished May 30 03:26:09 PM PDT 24
Peak memory 215172 kb
Host smart-15c4ffe5-d4a0-45a6-8865-7acb61e0d0eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210004606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1210004606
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2982589470
Short name T995
Test name
Test status
Simulation time 723806972 ps
CPU time 4.02 seconds
Started May 30 03:26:05 PM PDT 24
Finished May 30 03:26:10 PM PDT 24
Peak memory 215372 kb
Host smart-bd88d6c8-dcfe-45cf-84d2-225352a93b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982589470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
982589470
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.422503549
Short name T162
Test name
Test status
Simulation time 528040812 ps
CPU time 12.86 seconds
Started May 30 03:26:05 PM PDT 24
Finished May 30 03:26:19 PM PDT 24
Peak memory 215180 kb
Host smart-0808cc70-d621-4d86-80b0-49c22b8f31b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422503549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.422503549
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4026049852
Short name T1010
Test name
Test status
Simulation time 135322155 ps
CPU time 2.43 seconds
Started May 30 03:26:07 PM PDT 24
Finished May 30 03:26:11 PM PDT 24
Peak memory 216324 kb
Host smart-8d45ff13-a07e-4319-a7cd-4100b6a92ef0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026049852 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.4026049852
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.700858365
Short name T1021
Test name
Test status
Simulation time 52271321 ps
CPU time 1.64 seconds
Started May 30 03:26:07 PM PDT 24
Finished May 30 03:26:10 PM PDT 24
Peak memory 207000 kb
Host smart-2683e54d-9c45-4e34-82db-ab7c92134af9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700858365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.700858365
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.830850780
Short name T963
Test name
Test status
Simulation time 40806396 ps
CPU time 0.71 seconds
Started May 30 03:26:06 PM PDT 24
Finished May 30 03:26:08 PM PDT 24
Peak memory 203636 kb
Host smart-872ffcbf-6f17-47e5-aaf3-b451d96355c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830850780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.830850780
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.213088822
Short name T1000
Test name
Test status
Simulation time 264742518 ps
CPU time 1.83 seconds
Started May 30 03:26:05 PM PDT 24
Finished May 30 03:26:08 PM PDT 24
Peak memory 206984 kb
Host smart-863a4381-05de-42f7-a253-eb5dda2a8426
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213088822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.213088822
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1283401707
Short name T60
Test name
Test status
Simulation time 116410828 ps
CPU time 2.05 seconds
Started May 30 03:26:07 PM PDT 24
Finished May 30 03:26:11 PM PDT 24
Peak memory 215380 kb
Host smart-7f952df2-3823-44e2-ac5d-88502a4cf067
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283401707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
283401707
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1569774337
Short name T998
Test name
Test status
Simulation time 852469702 ps
CPU time 12.97 seconds
Started May 30 03:26:05 PM PDT 24
Finished May 30 03:26:20 PM PDT 24
Peak memory 215844 kb
Host smart-f6dd24d3-03eb-484c-8097-86ca751e8ed5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569774337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1569774337
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3410794809
Short name T1005
Test name
Test status
Simulation time 110891678 ps
CPU time 3.76 seconds
Started May 30 03:26:14 PM PDT 24
Finished May 30 03:26:19 PM PDT 24
Peak memory 217464 kb
Host smart-71ee8019-ed7d-45df-abbd-db2d6458bc31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410794809 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3410794809
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3795611863
Short name T989
Test name
Test status
Simulation time 58032492 ps
CPU time 1.81 seconds
Started May 30 03:26:14 PM PDT 24
Finished May 30 03:26:18 PM PDT 24
Peak memory 207008 kb
Host smart-7039a47b-5989-4762-bbd4-d04e0ffe2853
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795611863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
795611863
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1349660088
Short name T1034
Test name
Test status
Simulation time 35896132 ps
CPU time 0.73 seconds
Started May 30 03:26:17 PM PDT 24
Finished May 30 03:26:19 PM PDT 24
Peak memory 203620 kb
Host smart-9e098f0d-ac70-40bf-a3b5-2d379c1b562c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349660088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
349660088
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3393441261
Short name T138
Test name
Test status
Simulation time 410618137 ps
CPU time 4.28 seconds
Started May 30 03:26:15 PM PDT 24
Finished May 30 03:26:21 PM PDT 24
Peak memory 215244 kb
Host smart-b8e98c06-70f2-4623-85e5-c5931ea46df8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393441261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3393441261
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.801490929
Short name T59
Test name
Test status
Simulation time 162210202 ps
CPU time 1.78 seconds
Started May 30 03:26:06 PM PDT 24
Finished May 30 03:26:09 PM PDT 24
Peak memory 216464 kb
Host smart-880596f7-b2c0-4068-a047-13903a7c4c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801490929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.801490929
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3497721853
Short name T161
Test name
Test status
Simulation time 1227255879 ps
CPU time 22.81 seconds
Started May 30 03:26:15 PM PDT 24
Finished May 30 03:26:40 PM PDT 24
Peak memory 215268 kb
Host smart-a93064db-d8a2-4355-b5e3-c8426a13a8ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497721853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3497721853
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2383953898
Short name T98
Test name
Test status
Simulation time 135275669 ps
CPU time 3.54 seconds
Started May 30 03:26:14 PM PDT 24
Finished May 30 03:26:19 PM PDT 24
Peak memory 217336 kb
Host smart-7bae2e62-a995-4b1d-a380-ae53b49e32b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383953898 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2383953898
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2882670013
Short name T100
Test name
Test status
Simulation time 62707197 ps
CPU time 1.35 seconds
Started May 30 03:26:15 PM PDT 24
Finished May 30 03:26:18 PM PDT 24
Peak memory 206968 kb
Host smart-5d2dd1a2-b8c9-4bd3-9efb-03e518caf56f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882670013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
882670013
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3540744133
Short name T992
Test name
Test status
Simulation time 44304196 ps
CPU time 0.68 seconds
Started May 30 03:26:16 PM PDT 24
Finished May 30 03:26:18 PM PDT 24
Peak memory 203688 kb
Host smart-90b62e7b-c0d0-46ae-b364-4534ca0fe2ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540744133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
540744133
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.783198656
Short name T1056
Test name
Test status
Simulation time 101437368 ps
CPU time 2.87 seconds
Started May 30 03:26:16 PM PDT 24
Finished May 30 03:26:20 PM PDT 24
Peak memory 215132 kb
Host smart-a16e61f1-7e4d-4c64-ae00-5855590c15d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783198656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.783198656
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4279105531
Short name T1068
Test name
Test status
Simulation time 122035731 ps
CPU time 3.5 seconds
Started May 30 03:26:15 PM PDT 24
Finished May 30 03:26:20 PM PDT 24
Peak memory 215296 kb
Host smart-c7ab5b25-3c20-4fac-9303-905451f3a53e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279105531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
279105531
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1219755680
Short name T165
Test name
Test status
Simulation time 214480728 ps
CPU time 13.03 seconds
Started May 30 03:26:14 PM PDT 24
Finished May 30 03:26:29 PM PDT 24
Peak memory 222316 kb
Host smart-6fd0981e-bcd9-4304-b776-ab0822f0867b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219755680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1219755680
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.814808831
Short name T848
Test name
Test status
Simulation time 71175548 ps
CPU time 0.73 seconds
Started May 30 03:39:20 PM PDT 24
Finished May 30 03:39:24 PM PDT 24
Peak memory 204868 kb
Host smart-82d63248-8e3a-4430-8973-b22b1da34e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814808831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.814808831
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.906726938
Short name T615
Test name
Test status
Simulation time 161881406 ps
CPU time 3.67 seconds
Started May 30 03:39:22 PM PDT 24
Finished May 30 03:39:28 PM PDT 24
Peak memory 218380 kb
Host smart-8950f53d-d459-4609-9395-3f78a2173eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906726938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.906726938
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2250380240
Short name T633
Test name
Test status
Simulation time 18178722 ps
CPU time 0.8 seconds
Started May 30 03:39:17 PM PDT 24
Finished May 30 03:39:20 PM PDT 24
Peak memory 206472 kb
Host smart-e036aedf-7d85-4480-9417-4ca0b5b94aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250380240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2250380240
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.224161792
Short name T698
Test name
Test status
Simulation time 4695590476 ps
CPU time 39.01 seconds
Started May 30 03:39:17 PM PDT 24
Finished May 30 03:39:59 PM PDT 24
Peak memory 235448 kb
Host smart-c02823de-2104-4e6e-9321-a65e0d641f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224161792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.224161792
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.332586917
Short name T296
Test name
Test status
Simulation time 3440914687 ps
CPU time 42.74 seconds
Started May 30 03:39:17 PM PDT 24
Finished May 30 03:40:02 PM PDT 24
Peak memory 222664 kb
Host smart-4479b675-7ccd-4c7a-a3f9-03648ddedd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332586917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.332586917
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2835275976
Short name T928
Test name
Test status
Simulation time 1345366146 ps
CPU time 9.85 seconds
Started May 30 03:39:22 PM PDT 24
Finished May 30 03:39:35 PM PDT 24
Peak memory 224384 kb
Host smart-d7b44928-3366-4457-93dc-4d1387daf2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835275976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2835275976
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3923236555
Short name T223
Test name
Test status
Simulation time 25120738391 ps
CPU time 12.27 seconds
Started May 30 03:39:16 PM PDT 24
Finished May 30 03:39:29 PM PDT 24
Peak memory 235036 kb
Host smart-9ed09c83-89c0-4600-b5eb-ce72b7ee7730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923236555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3923236555
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3940244636
Short name T234
Test name
Test status
Simulation time 6241215236 ps
CPU time 55.98 seconds
Started May 30 03:39:15 PM PDT 24
Finished May 30 03:40:12 PM PDT 24
Peak memory 219384 kb
Host smart-0693507e-faf8-41b9-869f-7b7407340cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940244636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3940244636
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.336778887
Short name T473
Test name
Test status
Simulation time 220671882 ps
CPU time 2.65 seconds
Started May 30 03:39:20 PM PDT 24
Finished May 30 03:39:25 PM PDT 24
Peak memory 235180 kb
Host smart-9fff6e07-f649-4b30-89d3-f24767f6228e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336778887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
336778887
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3109331200
Short name T640
Test name
Test status
Simulation time 716659557 ps
CPU time 5.59 seconds
Started May 30 03:39:21 PM PDT 24
Finished May 30 03:39:30 PM PDT 24
Peak memory 218592 kb
Host smart-ecaaa38f-7a63-46a3-b389-10b43f710d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109331200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3109331200
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1381730317
Short name T865
Test name
Test status
Simulation time 1811434871 ps
CPU time 12.97 seconds
Started May 30 03:39:20 PM PDT 24
Finished May 30 03:39:36 PM PDT 24
Peak memory 222952 kb
Host smart-d0cec26d-83e7-4ab9-baf5-d78e89ccc1ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1381730317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1381730317
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1387738948
Short name T67
Test name
Test status
Simulation time 273063573 ps
CPU time 1.21 seconds
Started May 30 03:39:18 PM PDT 24
Finished May 30 03:39:22 PM PDT 24
Peak memory 235108 kb
Host smart-18323f40-6809-4c2c-a4ef-f377937d4ba8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387738948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1387738948
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3968718893
Short name T424
Test name
Test status
Simulation time 57340632 ps
CPU time 1.1 seconds
Started May 30 03:39:20 PM PDT 24
Finished May 30 03:39:24 PM PDT 24
Peak memory 206964 kb
Host smart-c19ac143-ca9a-4ca6-af01-c94f68429e58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968718893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3968718893
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1361783053
Short name T526
Test name
Test status
Simulation time 7196217754 ps
CPU time 24.24 seconds
Started May 30 03:39:20 PM PDT 24
Finished May 30 03:39:48 PM PDT 24
Peak memory 220028 kb
Host smart-53ece34b-d721-48a1-b65e-a032a130911f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361783053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1361783053
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1737308178
Short name T17
Test name
Test status
Simulation time 1121961727 ps
CPU time 2.54 seconds
Started May 30 03:39:19 PM PDT 24
Finished May 30 03:39:25 PM PDT 24
Peak memory 215892 kb
Host smart-6c24a9f5-293f-4658-ae96-86d603144913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737308178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1737308178
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3918312239
Short name T916
Test name
Test status
Simulation time 883908972 ps
CPU time 3.01 seconds
Started May 30 03:39:21 PM PDT 24
Finished May 30 03:39:27 PM PDT 24
Peak memory 216216 kb
Host smart-0fcd8d65-240b-4035-93f1-283ce88d674f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918312239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3918312239
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1950520956
Short name T596
Test name
Test status
Simulation time 27753033 ps
CPU time 0.81 seconds
Started May 30 03:39:21 PM PDT 24
Finished May 30 03:39:25 PM PDT 24
Peak memory 205392 kb
Host smart-21a84e6a-59c5-4263-8ee9-6f391003f06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950520956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1950520956
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3390772473
Short name T708
Test name
Test status
Simulation time 6983291351 ps
CPU time 31.05 seconds
Started May 30 03:39:22 PM PDT 24
Finished May 30 03:39:56 PM PDT 24
Peak memory 240820 kb
Host smart-7fe2745d-0915-4af3-ab7f-87d41beda086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390772473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3390772473
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2966880850
Short name T309
Test name
Test status
Simulation time 14024758 ps
CPU time 0.82 seconds
Started May 30 03:39:16 PM PDT 24
Finished May 30 03:39:18 PM PDT 24
Peak memory 205376 kb
Host smart-e8dc6308-f6b3-4ce0-9d6e-bec28133cf39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966880850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
966880850
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.123914955
Short name T592
Test name
Test status
Simulation time 3252893731 ps
CPU time 6.33 seconds
Started May 30 03:39:21 PM PDT 24
Finished May 30 03:39:30 PM PDT 24
Peak memory 234256 kb
Host smart-e5b41b47-4174-4c4b-acc3-23e66b694b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123914955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.123914955
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4093737705
Short name T316
Test name
Test status
Simulation time 41640285 ps
CPU time 0.75 seconds
Started May 30 03:39:18 PM PDT 24
Finished May 30 03:39:21 PM PDT 24
Peak memory 206440 kb
Host smart-fb33144e-ea12-4307-a0eb-280223debc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093737705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4093737705
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3911368985
Short name T52
Test name
Test status
Simulation time 13125253289 ps
CPU time 20.6 seconds
Started May 30 03:39:20 PM PDT 24
Finished May 30 03:39:44 PM PDT 24
Peak memory 240872 kb
Host smart-2504b2d6-d393-437d-90f4-4511d2ea0695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911368985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3911368985
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.396822739
Short name T957
Test name
Test status
Simulation time 6916156577 ps
CPU time 41.02 seconds
Started May 30 03:39:22 PM PDT 24
Finished May 30 03:40:06 PM PDT 24
Peak memory 239612 kb
Host smart-f02cbee6-7430-4a6a-93a6-9226f14fc986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396822739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
396822739
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_intercept.169168961
Short name T550
Test name
Test status
Simulation time 433263010 ps
CPU time 5.13 seconds
Started May 30 03:39:21 PM PDT 24
Finished May 30 03:39:29 PM PDT 24
Peak memory 233756 kb
Host smart-dcd7d275-6b87-4a2c-b41a-1469f8ca1b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169168961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.169168961
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3289940823
Short name T610
Test name
Test status
Simulation time 305509953 ps
CPU time 3.96 seconds
Started May 30 03:39:21 PM PDT 24
Finished May 30 03:39:28 PM PDT 24
Peak memory 218740 kb
Host smart-f798acc9-3fa5-441f-a607-fdaf1234bd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289940823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3289940823
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4229511673
Short name T240
Test name
Test status
Simulation time 7241367117 ps
CPU time 11.13 seconds
Started May 30 03:39:20 PM PDT 24
Finished May 30 03:39:34 PM PDT 24
Peak memory 216984 kb
Host smart-f5f7bfaa-bb5a-4af6-a14c-07aaf8eb0983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229511673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4229511673
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3335765213
Short name T670
Test name
Test status
Simulation time 834341043 ps
CPU time 2.3 seconds
Started May 30 03:39:18 PM PDT 24
Finished May 30 03:39:23 PM PDT 24
Peak memory 224408 kb
Host smart-37a2e939-02f3-46c0-9bdc-2d5927b4a881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335765213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3335765213
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2609639918
Short name T503
Test name
Test status
Simulation time 19441954112 ps
CPU time 12.35 seconds
Started May 30 03:39:21 PM PDT 24
Finished May 30 03:39:36 PM PDT 24
Peak memory 219176 kb
Host smart-d04011d2-c292-48fa-80ec-6b29ab5cfcce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2609639918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2609639918
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.774053931
Short name T635
Test name
Test status
Simulation time 7349974553 ps
CPU time 22.13 seconds
Started May 30 03:39:16 PM PDT 24
Finished May 30 03:39:40 PM PDT 24
Peak memory 216228 kb
Host smart-0e3fa887-3823-4e48-baa4-41ee128fb848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774053931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.774053931
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1375176624
Short name T874
Test name
Test status
Simulation time 4742764902 ps
CPU time 5.99 seconds
Started May 30 03:39:20 PM PDT 24
Finished May 30 03:39:29 PM PDT 24
Peak memory 216132 kb
Host smart-304a1f15-9b09-4881-9a10-87a913f46532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375176624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1375176624
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.792786015
Short name T682
Test name
Test status
Simulation time 16113371 ps
CPU time 1 seconds
Started May 30 03:39:21 PM PDT 24
Finished May 30 03:39:25 PM PDT 24
Peak memory 206736 kb
Host smart-9a8912e0-183d-4cd6-ac54-0b822c0f8c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792786015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.792786015
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3780828443
Short name T728
Test name
Test status
Simulation time 47796745 ps
CPU time 0.88 seconds
Started May 30 03:39:20 PM PDT 24
Finished May 30 03:39:24 PM PDT 24
Peak memory 205688 kb
Host smart-d30128d1-e9d9-4472-bb3a-0018780a74ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780828443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3780828443
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3257035218
Short name T494
Test name
Test status
Simulation time 51390554700 ps
CPU time 12.37 seconds
Started May 30 03:39:19 PM PDT 24
Finished May 30 03:39:35 PM PDT 24
Peak memory 217532 kb
Host smart-3b0ff0aa-b4f1-45b1-8174-2cb9cb42cf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257035218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3257035218
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2279884931
Short name T815
Test name
Test status
Simulation time 34833115 ps
CPU time 0.71 seconds
Started May 30 03:39:44 PM PDT 24
Finished May 30 03:39:47 PM PDT 24
Peak memory 205344 kb
Host smart-710859be-3a9e-4c74-b0de-24b00841db07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279884931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2279884931
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2712800112
Short name T221
Test name
Test status
Simulation time 467833828 ps
CPU time 2.2 seconds
Started May 30 03:39:47 PM PDT 24
Finished May 30 03:39:51 PM PDT 24
Peak memory 218300 kb
Host smart-00bca7c1-89c6-4f37-9ddb-43302c1dc312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712800112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2712800112
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1961657078
Short name T690
Test name
Test status
Simulation time 47012408 ps
CPU time 0.76 seconds
Started May 30 03:39:44 PM PDT 24
Finished May 30 03:39:47 PM PDT 24
Peak memory 206420 kb
Host smart-6727cf96-c26c-4222-8c8f-2419e374a292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961657078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1961657078
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1686190821
Short name T265
Test name
Test status
Simulation time 18732260330 ps
CPU time 164.29 seconds
Started May 30 03:39:45 PM PDT 24
Finished May 30 03:42:31 PM PDT 24
Peak memory 253552 kb
Host smart-405ebf89-0902-4422-8cd0-1641dabed406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686190821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1686190821
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.551969097
Short name T457
Test name
Test status
Simulation time 20607417122 ps
CPU time 76.48 seconds
Started May 30 03:39:41 PM PDT 24
Finished May 30 03:40:59 PM PDT 24
Peak memory 231308 kb
Host smart-56b020ac-030c-4944-b185-9ec8bdb869ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551969097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.551969097
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.203983042
Short name T151
Test name
Test status
Simulation time 519816082136 ps
CPU time 363.34 seconds
Started May 30 03:39:45 PM PDT 24
Finished May 30 03:45:50 PM PDT 24
Peak memory 255576 kb
Host smart-bc58eb14-5853-4aa3-a4af-994b95ec9d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203983042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.203983042
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3790119298
Short name T738
Test name
Test status
Simulation time 4844524934 ps
CPU time 41.22 seconds
Started May 30 03:39:43 PM PDT 24
Finished May 30 03:40:26 PM PDT 24
Peak memory 224508 kb
Host smart-25f022ad-30a2-482c-9691-8ffbb58e17cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790119298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3790119298
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3328391408
Short name T462
Test name
Test status
Simulation time 5139186512 ps
CPU time 8.97 seconds
Started May 30 03:39:49 PM PDT 24
Finished May 30 03:39:59 PM PDT 24
Peak memory 219324 kb
Host smart-26e0c3e9-7317-4d5c-af55-65c9f4d4ba5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328391408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3328391408
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.425350466
Short name T884
Test name
Test status
Simulation time 2515246010 ps
CPU time 19.23 seconds
Started May 30 03:39:41 PM PDT 24
Finished May 30 03:40:02 PM PDT 24
Peak memory 234608 kb
Host smart-997c2da5-4b8b-4e17-9015-6f4df3eb24a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425350466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.425350466
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1160223293
Short name T325
Test name
Test status
Simulation time 2140393757 ps
CPU time 9.33 seconds
Started May 30 03:39:41 PM PDT 24
Finished May 30 03:39:52 PM PDT 24
Peak memory 219396 kb
Host smart-dc6c8966-a080-4450-b490-7223def8c697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160223293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1160223293
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2034783785
Short name T600
Test name
Test status
Simulation time 6452068424 ps
CPU time 14.42 seconds
Started May 30 03:39:41 PM PDT 24
Finished May 30 03:39:57 PM PDT 24
Peak memory 249964 kb
Host smart-d1e921a3-9116-4f32-a413-07a7c2e78796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034783785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2034783785
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1599211925
Short name T736
Test name
Test status
Simulation time 719165749 ps
CPU time 7.94 seconds
Started May 30 03:39:44 PM PDT 24
Finished May 30 03:39:54 PM PDT 24
Peak memory 219048 kb
Host smart-58bffdbc-2a1f-4e3b-95f8-142c771c6831
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1599211925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1599211925
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2788161739
Short name T402
Test name
Test status
Simulation time 17707681 ps
CPU time 0.73 seconds
Started May 30 03:39:47 PM PDT 24
Finished May 30 03:39:49 PM PDT 24
Peak memory 205868 kb
Host smart-7339081c-ea2f-41cc-bf9c-e3808f968bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788161739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2788161739
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3221970525
Short name T386
Test name
Test status
Simulation time 1465582999 ps
CPU time 4.23 seconds
Started May 30 03:39:43 PM PDT 24
Finished May 30 03:39:49 PM PDT 24
Peak memory 216036 kb
Host smart-de075fae-a937-4fda-846d-92507f2a0e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221970525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3221970525
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.320555122
Short name T665
Test name
Test status
Simulation time 40728798 ps
CPU time 0.72 seconds
Started May 30 03:39:44 PM PDT 24
Finished May 30 03:39:47 PM PDT 24
Peak memory 205444 kb
Host smart-2c9b3397-f7b0-46c9-9f57-51df125172c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320555122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.320555122
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2058297400
Short name T548
Test name
Test status
Simulation time 10640647 ps
CPU time 0.68 seconds
Started May 30 03:39:42 PM PDT 24
Finished May 30 03:39:45 PM PDT 24
Peak memory 205376 kb
Host smart-a1e2c865-cab6-40e7-8886-f98c9c27b9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058297400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2058297400
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.291093597
Short name T222
Test name
Test status
Simulation time 334654343 ps
CPU time 5.36 seconds
Started May 30 03:39:47 PM PDT 24
Finished May 30 03:39:54 PM PDT 24
Peak memory 217284 kb
Host smart-30c65424-7083-48f6-a17b-58eee054e3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291093597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.291093597
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3262586139
Short name T447
Test name
Test status
Simulation time 1448498223 ps
CPU time 8.39 seconds
Started May 30 03:39:51 PM PDT 24
Finished May 30 03:40:02 PM PDT 24
Peak memory 233408 kb
Host smart-0e767c3e-ca01-47f7-8c28-f964db3ac465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262586139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3262586139
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.102211182
Short name T379
Test name
Test status
Simulation time 69693636 ps
CPU time 0.79 seconds
Started May 30 03:39:45 PM PDT 24
Finished May 30 03:39:48 PM PDT 24
Peak memory 206392 kb
Host smart-fbe7fa52-b5bc-44d6-82d1-5f17f546d200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102211182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.102211182
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.728193836
Short name T839
Test name
Test status
Simulation time 140449453456 ps
CPU time 178.2 seconds
Started May 30 03:39:50 PM PDT 24
Finished May 30 03:42:49 PM PDT 24
Peak memory 249088 kb
Host smart-df9bb297-9092-4bbc-85ac-f1963978801c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728193836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.728193836
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.518078852
Short name T249
Test name
Test status
Simulation time 132217096944 ps
CPU time 170.79 seconds
Started May 30 03:39:55 PM PDT 24
Finished May 30 03:42:48 PM PDT 24
Peak memory 251328 kb
Host smart-ae68cc85-2338-4f74-bd64-ae898c9fcfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518078852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.518078852
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1369801478
Short name T903
Test name
Test status
Simulation time 402256756 ps
CPU time 3.4 seconds
Started May 30 03:39:55 PM PDT 24
Finished May 30 03:40:00 PM PDT 24
Peak memory 232588 kb
Host smart-341c7bd5-81de-4cdc-b7f4-e5bf468bc104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369801478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1369801478
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.4141648683
Short name T653
Test name
Test status
Simulation time 19452226656 ps
CPU time 138.76 seconds
Started May 30 03:39:53 PM PDT 24
Finished May 30 03:42:15 PM PDT 24
Peak memory 250588 kb
Host smart-647afd67-41ad-46ce-951d-5ca557cb711f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141648683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4141648683
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.4128235430
Short name T523
Test name
Test status
Simulation time 1420674959 ps
CPU time 8.82 seconds
Started May 30 03:39:52 PM PDT 24
Finished May 30 03:40:03 PM PDT 24
Peak memory 226728 kb
Host smart-bce4d6bd-93c2-4ea0-958a-cb065d336bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128235430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.4128235430
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.196077398
Short name T863
Test name
Test status
Simulation time 11703073822 ps
CPU time 14.54 seconds
Started May 30 03:39:53 PM PDT 24
Finished May 30 03:40:10 PM PDT 24
Peak memory 233728 kb
Host smart-d9c88b67-1adf-4881-8b2f-c8af68189996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196077398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.196077398
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1163356238
Short name T751
Test name
Test status
Simulation time 1335820073 ps
CPU time 11.19 seconds
Started May 30 03:39:55 PM PDT 24
Finished May 30 03:40:08 PM PDT 24
Peak memory 218628 kb
Host smart-eae6e106-675d-4efc-b195-2961c3e0cfeb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1163356238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1163356238
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.786556304
Short name T958
Test name
Test status
Simulation time 4488901627 ps
CPU time 50.03 seconds
Started May 30 03:39:50 PM PDT 24
Finished May 30 03:40:42 PM PDT 24
Peak memory 249088 kb
Host smart-337ea3fb-d014-4f4f-9941-b9da4b5ad590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786556304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.786556304
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2449896230
Short name T288
Test name
Test status
Simulation time 10496503219 ps
CPU time 24.17 seconds
Started May 30 03:39:43 PM PDT 24
Finished May 30 03:40:09 PM PDT 24
Peak memory 216220 kb
Host smart-58486a5a-1e28-454a-aafa-cfe9fecbc981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449896230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2449896230
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2599811138
Short name T684
Test name
Test status
Simulation time 337914155 ps
CPU time 1.71 seconds
Started May 30 03:39:43 PM PDT 24
Finished May 30 03:39:47 PM PDT 24
Peak memory 207664 kb
Host smart-4bdd1c12-2c16-4c24-81a8-bea107f566ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599811138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2599811138
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1342689021
Short name T782
Test name
Test status
Simulation time 1113891376 ps
CPU time 6.93 seconds
Started May 30 03:39:53 PM PDT 24
Finished May 30 03:40:02 PM PDT 24
Peak memory 216240 kb
Host smart-dd764243-c1fb-45ba-b461-97b631823847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342689021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1342689021
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3108942950
Short name T691
Test name
Test status
Simulation time 33892029 ps
CPU time 0.75 seconds
Started May 30 03:39:50 PM PDT 24
Finished May 30 03:39:53 PM PDT 24
Peak memory 205652 kb
Host smart-5579b2f7-5c7a-4547-aba2-8bc99dae8c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108942950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3108942950
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1495939668
Short name T430
Test name
Test status
Simulation time 284456689 ps
CPU time 4.21 seconds
Started May 30 03:39:52 PM PDT 24
Finished May 30 03:39:58 PM PDT 24
Peak memory 224368 kb
Host smart-0043ea5e-d659-4aa1-95f0-330e3310a8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495939668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1495939668
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3048488449
Short name T941
Test name
Test status
Simulation time 12920587 ps
CPU time 0.72 seconds
Started May 30 03:39:53 PM PDT 24
Finished May 30 03:39:55 PM PDT 24
Peak memory 205456 kb
Host smart-6e70eda4-46e8-4869-b7c7-b84db4dba0d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048488449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3048488449
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.558852606
Short name T721
Test name
Test status
Simulation time 1861052680 ps
CPU time 4.64 seconds
Started May 30 03:39:52 PM PDT 24
Finished May 30 03:39:59 PM PDT 24
Peak memory 233700 kb
Host smart-ee6d5207-d495-48a4-a266-40bd959a13b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558852606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.558852606
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.268265711
Short name T901
Test name
Test status
Simulation time 32284090 ps
CPU time 0.74 seconds
Started May 30 03:39:52 PM PDT 24
Finished May 30 03:39:55 PM PDT 24
Peak memory 205716 kb
Host smart-e748c3a3-3ae9-447e-944b-f02f0f4cdb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268265711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.268265711
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.96135000
Short name T808
Test name
Test status
Simulation time 25763370714 ps
CPU time 96.05 seconds
Started May 30 03:39:53 PM PDT 24
Finished May 30 03:41:31 PM PDT 24
Peak memory 250088 kb
Host smart-d1f6f066-cdd7-4b47-b2ce-3d9cab3ce3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96135000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.96135000
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.4241553047
Short name T270
Test name
Test status
Simulation time 67730032682 ps
CPU time 75.85 seconds
Started May 30 03:39:53 PM PDT 24
Finished May 30 03:41:12 PM PDT 24
Peak memory 239916 kb
Host smart-5e7b0111-87c9-47e2-84e2-53c7b6258972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241553047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.4241553047
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1430052961
Short name T130
Test name
Test status
Simulation time 569648060 ps
CPU time 6.51 seconds
Started May 30 03:39:53 PM PDT 24
Finished May 30 03:40:02 PM PDT 24
Peak memory 240632 kb
Host smart-8fd87788-12e1-421a-a3c3-3c4408e64e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430052961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1430052961
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3898740652
Short name T546
Test name
Test status
Simulation time 58531116 ps
CPU time 2.54 seconds
Started May 30 03:40:12 PM PDT 24
Finished May 30 03:40:16 PM PDT 24
Peak memory 220984 kb
Host smart-69561e78-b1c6-40f4-b2f6-5fd8da066758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898740652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3898740652
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3579311754
Short name T82
Test name
Test status
Simulation time 471247011 ps
CPU time 3.11 seconds
Started May 30 03:39:49 PM PDT 24
Finished May 30 03:39:54 PM PDT 24
Peak memory 232652 kb
Host smart-01943489-5929-4ec7-8bba-0aabc50f757f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579311754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3579311754
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.901018914
Short name T445
Test name
Test status
Simulation time 1993550429 ps
CPU time 4.41 seconds
Started May 30 03:39:50 PM PDT 24
Finished May 30 03:39:55 PM PDT 24
Peak memory 218912 kb
Host smart-9cc162ad-90b2-4311-8113-c6f6160488e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901018914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.901018914
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.668080638
Short name T826
Test name
Test status
Simulation time 191832545 ps
CPU time 4.75 seconds
Started May 30 03:39:51 PM PDT 24
Finished May 30 03:39:58 PM PDT 24
Peak memory 233628 kb
Host smart-10662eff-5ca7-4ae1-a4c5-da0ce27fbcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668080638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.668080638
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1233482433
Short name T718
Test name
Test status
Simulation time 1304346757 ps
CPU time 20.32 seconds
Started May 30 03:39:52 PM PDT 24
Finished May 30 03:40:14 PM PDT 24
Peak memory 219996 kb
Host smart-d4ba275e-19d7-4ead-a943-e3228e4dc97b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1233482433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1233482433
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2951847957
Short name T880
Test name
Test status
Simulation time 27935539712 ps
CPU time 26.98 seconds
Started May 30 03:39:51 PM PDT 24
Finished May 30 03:40:20 PM PDT 24
Peak memory 216244 kb
Host smart-937b6cc8-075a-4b1a-96ba-18ab79075113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951847957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2951847957
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2089189666
Short name T750
Test name
Test status
Simulation time 181677897 ps
CPU time 1.69 seconds
Started May 30 03:39:51 PM PDT 24
Finished May 30 03:39:54 PM PDT 24
Peak memory 207748 kb
Host smart-840521e8-8e79-4a31-9e96-d51785bf460c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089189666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2089189666
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.4218344761
Short name T833
Test name
Test status
Simulation time 177899756 ps
CPU time 3.52 seconds
Started May 30 03:39:54 PM PDT 24
Finished May 30 03:40:00 PM PDT 24
Peak memory 216236 kb
Host smart-ced73951-ad56-4828-9098-bb6101ec612a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218344761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4218344761
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2437647770
Short name T11
Test name
Test status
Simulation time 226119944 ps
CPU time 0.87 seconds
Started May 30 03:39:52 PM PDT 24
Finished May 30 03:39:56 PM PDT 24
Peak memory 205664 kb
Host smart-cb680645-9a22-4544-b2d7-5c5ea7d39fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437647770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2437647770
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.970296832
Short name T614
Test name
Test status
Simulation time 1723045147 ps
CPU time 9.96 seconds
Started May 30 03:39:52 PM PDT 24
Finished May 30 03:40:04 PM PDT 24
Peak memory 248996 kb
Host smart-b6d73d0b-c508-4835-bd09-03534f66c3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970296832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.970296832
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1748666483
Short name T654
Test name
Test status
Simulation time 103911490 ps
CPU time 0.7 seconds
Started May 30 03:40:00 PM PDT 24
Finished May 30 03:40:05 PM PDT 24
Peak memory 204792 kb
Host smart-2313a195-b44c-46c6-aecb-432364a92864
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748666483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1748666483
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.357711940
Short name T639
Test name
Test status
Simulation time 3543803773 ps
CPU time 28.17 seconds
Started May 30 03:39:56 PM PDT 24
Finished May 30 03:40:25 PM PDT 24
Peak memory 235044 kb
Host smart-3693d115-9d81-476f-a765-14f2ab6920c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357711940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.357711940
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2659108904
Short name T564
Test name
Test status
Simulation time 19093292 ps
CPU time 0.77 seconds
Started May 30 03:39:52 PM PDT 24
Finished May 30 03:39:56 PM PDT 24
Peak memory 205704 kb
Host smart-754f4710-83f4-4357-ba4c-1344ae240583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659108904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2659108904
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3993374883
Short name T175
Test name
Test status
Simulation time 6447442761 ps
CPU time 79.23 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:41:25 PM PDT 24
Peak memory 255772 kb
Host smart-cdf7d8ea-93d1-47d9-8cd1-96bc6723de82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993374883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3993374883
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3221961777
Short name T264
Test name
Test status
Simulation time 1508664543 ps
CPU time 37.28 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:40:43 PM PDT 24
Peak memory 250912 kb
Host smart-81592b88-cebc-48ae-8794-cb2580fb1dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221961777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3221961777
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1815133413
Short name T919
Test name
Test status
Simulation time 117134037 ps
CPU time 4.23 seconds
Started May 30 03:39:53 PM PDT 24
Finished May 30 03:40:00 PM PDT 24
Peak memory 232636 kb
Host smart-74f058f4-022f-4915-ba2a-ba889efea64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815133413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1815133413
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.805490371
Short name T765
Test name
Test status
Simulation time 1832950029 ps
CPU time 6.82 seconds
Started May 30 03:39:52 PM PDT 24
Finished May 30 03:40:01 PM PDT 24
Peak memory 219596 kb
Host smart-1e96337f-6f23-4838-a9cc-14accf6b3e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805490371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.805490371
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2773870635
Short name T196
Test name
Test status
Simulation time 326456515 ps
CPU time 3.3 seconds
Started May 30 03:39:53 PM PDT 24
Finished May 30 03:39:58 PM PDT 24
Peak memory 219684 kb
Host smart-c87d7399-81d7-43ea-a76c-3cd1a85c378a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773870635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2773870635
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1579095336
Short name T730
Test name
Test status
Simulation time 2829354248 ps
CPU time 10 seconds
Started May 30 03:39:53 PM PDT 24
Finished May 30 03:40:05 PM PDT 24
Peak memory 218308 kb
Host smart-6765c68b-e92b-47c5-b3fc-259468ff1484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579095336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1579095336
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3921099914
Short name T351
Test name
Test status
Simulation time 90649561 ps
CPU time 3.92 seconds
Started May 30 03:39:53 PM PDT 24
Finished May 30 03:40:00 PM PDT 24
Peak memory 222888 kb
Host smart-860625a3-5f35-40e4-84c5-911f1eb70536
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3921099914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3921099914
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3400401745
Short name T576
Test name
Test status
Simulation time 56120720796 ps
CPU time 61.27 seconds
Started May 30 03:40:01 PM PDT 24
Finished May 30 03:41:06 PM PDT 24
Peak memory 249228 kb
Host smart-dd08afa7-a738-427d-aca4-165b3a44153a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400401745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3400401745
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3267348643
Short name T650
Test name
Test status
Simulation time 6248497396 ps
CPU time 13.01 seconds
Started May 30 03:39:55 PM PDT 24
Finished May 30 03:40:10 PM PDT 24
Peak memory 216228 kb
Host smart-19508e5d-244c-4ed0-bf6c-732f53fb256a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267348643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3267348643
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.119841646
Short name T778
Test name
Test status
Simulation time 1615507753 ps
CPU time 9.09 seconds
Started May 30 03:39:53 PM PDT 24
Finished May 30 03:40:04 PM PDT 24
Peak memory 216216 kb
Host smart-a2da8dad-c26b-4543-a4a0-20e29e73bf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119841646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.119841646
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1092435277
Short name T3
Test name
Test status
Simulation time 16322874 ps
CPU time 0.84 seconds
Started May 30 03:39:53 PM PDT 24
Finished May 30 03:39:56 PM PDT 24
Peak memory 205732 kb
Host smart-01b75d2d-0a6d-46cb-917a-efa3e8054a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092435277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1092435277
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3923425027
Short name T624
Test name
Test status
Simulation time 358978678 ps
CPU time 0.89 seconds
Started May 30 03:39:52 PM PDT 24
Finished May 30 03:39:56 PM PDT 24
Peak memory 205676 kb
Host smart-2e8287da-6c14-41bd-9212-3b91aa7e7f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923425027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3923425027
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1998515143
Short name T1
Test name
Test status
Simulation time 4243210549 ps
CPU time 5.57 seconds
Started May 30 03:39:51 PM PDT 24
Finished May 30 03:39:58 PM PDT 24
Peak memory 217576 kb
Host smart-255b83a5-69ba-448e-8f1e-bd469f39a3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998515143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1998515143
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2202349964
Short name T613
Test name
Test status
Simulation time 21307758 ps
CPU time 0.73 seconds
Started May 30 03:40:00 PM PDT 24
Finished May 30 03:40:05 PM PDT 24
Peak memory 205368 kb
Host smart-2c375fa7-e0c6-42e0-b8c7-791b34a498ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202349964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2202349964
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1311574083
Short name T513
Test name
Test status
Simulation time 103810812 ps
CPU time 2.24 seconds
Started May 30 03:40:04 PM PDT 24
Finished May 30 03:40:09 PM PDT 24
Peak memory 218652 kb
Host smart-5961a48a-7725-40dd-8b11-1a02b0f430e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311574083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1311574083
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3295779592
Short name T521
Test name
Test status
Simulation time 15484768 ps
CPU time 0.81 seconds
Started May 30 03:39:59 PM PDT 24
Finished May 30 03:40:04 PM PDT 24
Peak memory 206420 kb
Host smart-2c4ba57b-8ab7-4a27-a46a-1f0450d648f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295779592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3295779592
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3380047967
Short name T155
Test name
Test status
Simulation time 9240137990 ps
CPU time 81.41 seconds
Started May 30 03:40:00 PM PDT 24
Finished May 30 03:41:25 PM PDT 24
Peak memory 239740 kb
Host smart-3b9b78fb-d6d9-40b9-8464-7915ff8d1719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380047967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3380047967
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3921493948
Short name T727
Test name
Test status
Simulation time 41683206441 ps
CPU time 92.78 seconds
Started May 30 03:40:03 PM PDT 24
Finished May 30 03:41:40 PM PDT 24
Peak memory 232736 kb
Host smart-12e0d4cf-1b44-4c43-8895-31341a2c7805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921493948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3921493948
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3413895765
Short name T641
Test name
Test status
Simulation time 235575368 ps
CPU time 6.34 seconds
Started May 30 03:39:59 PM PDT 24
Finished May 30 03:40:08 PM PDT 24
Peak memory 224464 kb
Host smart-e12b5c4a-bd82-4c37-a6e6-31dfc28b8b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413895765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3413895765
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1563927666
Short name T849
Test name
Test status
Simulation time 4701784002 ps
CPU time 17.78 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:40:24 PM PDT 24
Peak memory 234456 kb
Host smart-e88ad907-f47c-43de-8d28-3cf5b60953ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563927666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1563927666
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3987532156
Short name T681
Test name
Test status
Simulation time 568592282 ps
CPU time 11.06 seconds
Started May 30 03:40:01 PM PDT 24
Finished May 30 03:40:17 PM PDT 24
Peak memory 224336 kb
Host smart-4bf94bff-7165-4330-bd86-2c41268b067c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987532156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3987532156
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3122318149
Short name T742
Test name
Test status
Simulation time 1249262012 ps
CPU time 11.23 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:40:17 PM PDT 24
Peak memory 244936 kb
Host smart-7a2c7d4d-58e2-4cce-bbf7-efc1fe3e9259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122318149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3122318149
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3459223546
Short name T945
Test name
Test status
Simulation time 92113826 ps
CPU time 2.43 seconds
Started May 30 03:40:00 PM PDT 24
Finished May 30 03:40:06 PM PDT 24
Peak memory 233192 kb
Host smart-9573c556-8bd2-41bc-b0de-6e006fa72eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459223546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3459223546
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4235019378
Short name T507
Test name
Test status
Simulation time 122355094 ps
CPU time 4.45 seconds
Started May 30 03:40:01 PM PDT 24
Finished May 30 03:40:09 PM PDT 24
Peak memory 223004 kb
Host smart-59f65f53-c193-46d7-a02a-1eac84d2b195
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4235019378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4235019378
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3811341199
Short name T571
Test name
Test status
Simulation time 5216211940 ps
CPU time 47.26 seconds
Started May 30 03:40:01 PM PDT 24
Finished May 30 03:40:53 PM PDT 24
Peak memory 249100 kb
Host smart-ab6d4dd0-cb29-4c14-8ea9-6955df7e8c85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811341199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3811341199
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.154569496
Short name T816
Test name
Test status
Simulation time 1977764728 ps
CPU time 3.72 seconds
Started May 30 03:40:03 PM PDT 24
Finished May 30 03:40:10 PM PDT 24
Peak memory 216096 kb
Host smart-fdd47dc9-fa48-483b-9ed6-ed0583ecd828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154569496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.154569496
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1005421706
Short name T664
Test name
Test status
Simulation time 10349672 ps
CPU time 0.71 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:40:07 PM PDT 24
Peak memory 205472 kb
Host smart-adfafd55-9da6-4a09-b06d-8ee7a27b699e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005421706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1005421706
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1824134284
Short name T508
Test name
Test status
Simulation time 31531699 ps
CPU time 0.86 seconds
Started May 30 03:40:04 PM PDT 24
Finished May 30 03:40:08 PM PDT 24
Peak memory 205680 kb
Host smart-f44f2a7e-a053-4580-95dd-4a85115aed37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824134284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1824134284
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1862377106
Short name T595
Test name
Test status
Simulation time 1615540886 ps
CPU time 10.68 seconds
Started May 30 03:40:01 PM PDT 24
Finished May 30 03:40:16 PM PDT 24
Peak memory 234716 kb
Host smart-7de1234a-0d2a-42b3-976a-e0db7a8c0c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862377106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1862377106
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3316649005
Short name T399
Test name
Test status
Simulation time 22186857 ps
CPU time 0.73 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:40:06 PM PDT 24
Peak memory 205756 kb
Host smart-ddb4d5e5-0a3d-4c57-bbc6-4851406f6b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316649005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3316649005
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1913191234
Short name T418
Test name
Test status
Simulation time 45204971 ps
CPU time 2.48 seconds
Started May 30 03:40:03 PM PDT 24
Finished May 30 03:40:09 PM PDT 24
Peak memory 233372 kb
Host smart-f0836ffc-c3ab-490d-bbc5-b260d05ef735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913191234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1913191234
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1594899344
Short name T320
Test name
Test status
Simulation time 65219272 ps
CPU time 0.83 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:40:07 PM PDT 24
Peak memory 206412 kb
Host smart-29ccdc84-59ab-44d6-94d1-955ade279111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594899344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1594899344
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2620875232
Short name T232
Test name
Test status
Simulation time 4484711329 ps
CPU time 28.3 seconds
Started May 30 03:40:00 PM PDT 24
Finished May 30 03:40:32 PM PDT 24
Peak memory 232716 kb
Host smart-cb3d004e-e43e-43c4-b51e-2d00c3e7393a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620875232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2620875232
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1291501888
Short name T154
Test name
Test status
Simulation time 143595563725 ps
CPU time 227.45 seconds
Started May 30 03:40:01 PM PDT 24
Finished May 30 03:43:52 PM PDT 24
Peak memory 249164 kb
Host smart-10dd2431-aef3-4690-9cb5-4d90771a179f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291501888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1291501888
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.779929232
Short name T286
Test name
Test status
Simulation time 3055124482 ps
CPU time 14.49 seconds
Started May 30 03:40:04 PM PDT 24
Finished May 30 03:40:21 PM PDT 24
Peak memory 240824 kb
Host smart-5551395d-e468-41b9-805b-c514354317c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779929232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.779929232
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.146773815
Short name T757
Test name
Test status
Simulation time 1046109675 ps
CPU time 5.5 seconds
Started May 30 03:40:03 PM PDT 24
Finished May 30 03:40:12 PM PDT 24
Peak memory 233380 kb
Host smart-c8f5048e-15b1-4930-bb05-16e878e69fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146773815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.146773815
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3717055745
Short name T64
Test name
Test status
Simulation time 2922776646 ps
CPU time 25.59 seconds
Started May 30 03:40:01 PM PDT 24
Finished May 30 03:40:30 PM PDT 24
Peak memory 218668 kb
Host smart-5d75ad1a-b693-4815-ab8a-b326037eca1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717055745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3717055745
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2850305461
Short name T913
Test name
Test status
Simulation time 707550313 ps
CPU time 4.35 seconds
Started May 30 03:40:03 PM PDT 24
Finished May 30 03:40:11 PM PDT 24
Peak memory 218524 kb
Host smart-71bbd30b-a6ed-4115-a9e6-be435440dca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850305461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2850305461
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.4005323775
Short name T889
Test name
Test status
Simulation time 3107973903 ps
CPU time 5.92 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:40:12 PM PDT 24
Peak memory 235144 kb
Host smart-95844dfc-4f1b-49c8-a8ad-dbc9fc014a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005323775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.4005323775
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3741614368
Short name T460
Test name
Test status
Simulation time 120150114 ps
CPU time 3.42 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:40:10 PM PDT 24
Peak memory 220000 kb
Host smart-5f14f2b5-614e-4bfd-9060-4fd4dba92fd2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3741614368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3741614368
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3976260091
Short name T148
Test name
Test status
Simulation time 6908161901 ps
CPU time 86.13 seconds
Started May 30 03:40:01 PM PDT 24
Finished May 30 03:41:32 PM PDT 24
Peak memory 249112 kb
Host smart-ed929f1b-1cef-4e10-a6f8-d970a970d4b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976260091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3976260091
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3461075036
Short name T327
Test name
Test status
Simulation time 43093905 ps
CPU time 0.73 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:40:07 PM PDT 24
Peak memory 205572 kb
Host smart-fed77a1c-c95a-41a5-92cb-2b3503ee2c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461075036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3461075036
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1751735140
Short name T312
Test name
Test status
Simulation time 64510415 ps
CPU time 1.07 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:40:07 PM PDT 24
Peak memory 207504 kb
Host smart-50c55659-e8d6-4312-b7af-9ec8224390a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751735140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1751735140
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.646329331
Short name T482
Test name
Test status
Simulation time 127087388 ps
CPU time 2.15 seconds
Started May 30 03:40:03 PM PDT 24
Finished May 30 03:40:09 PM PDT 24
Peak memory 216180 kb
Host smart-03caebc4-9ed3-4eb5-94f2-ed76fce368cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646329331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.646329331
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1808941047
Short name T804
Test name
Test status
Simulation time 14872554 ps
CPU time 0.75 seconds
Started May 30 03:40:01 PM PDT 24
Finished May 30 03:40:05 PM PDT 24
Peak memory 205644 kb
Host smart-aeb9f16f-1f2a-4f3b-a3e0-e8c6379bc9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808941047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1808941047
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2848931881
Short name T660
Test name
Test status
Simulation time 1457741762 ps
CPU time 5.81 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:40:12 PM PDT 24
Peak memory 237048 kb
Host smart-811b1344-fa92-4251-be00-605b6d719936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848931881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2848931881
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2746595440
Short name T561
Test name
Test status
Simulation time 20473536 ps
CPU time 0.72 seconds
Started May 30 03:40:11 PM PDT 24
Finished May 30 03:40:13 PM PDT 24
Peak memory 205436 kb
Host smart-14c9a0b7-7c3d-462a-9f21-a92f24a0cf78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746595440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2746595440
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.360525313
Short name T133
Test name
Test status
Simulation time 121224999 ps
CPU time 3.02 seconds
Started May 30 03:40:11 PM PDT 24
Finished May 30 03:40:15 PM PDT 24
Peak memory 218572 kb
Host smart-851f7fde-7656-454c-b48f-53a33ad61dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360525313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.360525313
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3115468456
Short name T337
Test name
Test status
Simulation time 52674884 ps
CPU time 0.78 seconds
Started May 30 03:40:04 PM PDT 24
Finished May 30 03:40:08 PM PDT 24
Peak memory 206472 kb
Host smart-992af765-c428-4ac0-ac59-95344ddefc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115468456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3115468456
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1988520432
Short name T626
Test name
Test status
Simulation time 6816216368 ps
CPU time 87.27 seconds
Started May 30 03:40:13 PM PDT 24
Finished May 30 03:41:42 PM PDT 24
Peak memory 250060 kb
Host smart-743f2f3b-7f0a-41c1-a51a-a952fddfe87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988520432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1988520432
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3679987098
Short name T350
Test name
Test status
Simulation time 5726537859 ps
CPU time 38.24 seconds
Started May 30 03:40:11 PM PDT 24
Finished May 30 03:40:51 PM PDT 24
Peak memory 224552 kb
Host smart-fc46201b-f9cd-4c36-a450-7031cabb03f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679987098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3679987098
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1482749935
Short name T553
Test name
Test status
Simulation time 669592398 ps
CPU time 7.58 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:40:14 PM PDT 24
Peak memory 232620 kb
Host smart-1c28223f-8874-4686-9294-1e052bb68c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482749935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1482749935
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3904270743
Short name T338
Test name
Test status
Simulation time 318642509 ps
CPU time 6.89 seconds
Started May 30 03:40:01 PM PDT 24
Finished May 30 03:40:12 PM PDT 24
Peak memory 218616 kb
Host smart-884b2e20-019b-4c2b-a6e1-72cb85fa98b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904270743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3904270743
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.608511980
Short name T709
Test name
Test status
Simulation time 568814594 ps
CPU time 2.51 seconds
Started May 30 03:40:03 PM PDT 24
Finished May 30 03:40:09 PM PDT 24
Peak memory 218856 kb
Host smart-0439a23b-6d97-4ae7-9f16-a1ff11d542c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608511980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.608511980
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.309998871
Short name T859
Test name
Test status
Simulation time 3783053059 ps
CPU time 4.78 seconds
Started May 30 03:40:01 PM PDT 24
Finished May 30 03:40:10 PM PDT 24
Peak memory 218728 kb
Host smart-33e4ef48-1b41-4a07-8e1d-9c52137287af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309998871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.309998871
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2835835527
Short name T846
Test name
Test status
Simulation time 255307036 ps
CPU time 4.76 seconds
Started May 30 03:40:14 PM PDT 24
Finished May 30 03:40:21 PM PDT 24
Peak memory 219664 kb
Host smart-8626ecdc-e6e1-470c-9e95-0d4d4fe68320
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2835835527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2835835527
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1863053751
Short name T145
Test name
Test status
Simulation time 48844299523 ps
CPU time 148.4 seconds
Started May 30 03:40:15 PM PDT 24
Finished May 30 03:42:46 PM PDT 24
Peak memory 250224 kb
Host smart-f224ef96-e63e-4175-80be-9a23a4d6ef0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863053751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1863053751
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3355233064
Short name T398
Test name
Test status
Simulation time 1617178449 ps
CPU time 4.73 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:40:11 PM PDT 24
Peak memory 216208 kb
Host smart-9032546f-0a7e-4d81-8915-0315a1380952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355233064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3355233064
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3633769927
Short name T623
Test name
Test status
Simulation time 1597595624 ps
CPU time 6.42 seconds
Started May 30 03:40:02 PM PDT 24
Finished May 30 03:40:13 PM PDT 24
Peak memory 216076 kb
Host smart-f5e056db-1bc4-4fe6-b1ce-9dd1fa0af5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633769927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3633769927
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1908429656
Short name T786
Test name
Test status
Simulation time 28181630 ps
CPU time 0.9 seconds
Started May 30 03:40:04 PM PDT 24
Finished May 30 03:40:08 PM PDT 24
Peak memory 206328 kb
Host smart-e0cf3a8d-8514-4c61-9c5c-2dfe5c14c8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908429656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1908429656
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2261547565
Short name T116
Test name
Test status
Simulation time 50433085 ps
CPU time 0.86 seconds
Started May 30 03:40:00 PM PDT 24
Finished May 30 03:40:04 PM PDT 24
Peak memory 205700 kb
Host smart-242d705f-0cab-4a01-bab6-d6bebbcab55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261547565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2261547565
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1788160797
Short name T231
Test name
Test status
Simulation time 528730745 ps
CPU time 2.5 seconds
Started May 30 03:40:12 PM PDT 24
Finished May 30 03:40:17 PM PDT 24
Peak memory 224388 kb
Host smart-ff315764-f5b7-437a-ada3-c70ee14c55f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788160797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1788160797
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2678559025
Short name T798
Test name
Test status
Simulation time 15687094 ps
CPU time 0.8 seconds
Started May 30 03:40:11 PM PDT 24
Finished May 30 03:40:14 PM PDT 24
Peak memory 205728 kb
Host smart-6b6c470e-2a2c-49d7-95ba-6df8f77b1adb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678559025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2678559025
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2801948655
Short name T326
Test name
Test status
Simulation time 539065338 ps
CPU time 3.21 seconds
Started May 30 03:40:14 PM PDT 24
Finished May 30 03:40:19 PM PDT 24
Peak memory 233588 kb
Host smart-50f7fb20-670d-4122-a811-194ff84715b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801948655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2801948655
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1482286298
Short name T427
Test name
Test status
Simulation time 46908430 ps
CPU time 0.74 seconds
Started May 30 03:40:12 PM PDT 24
Finished May 30 03:40:14 PM PDT 24
Peak memory 205416 kb
Host smart-258cba81-f2a6-4d99-81f4-0a33429b3821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482286298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1482286298
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.4134888139
Short name T607
Test name
Test status
Simulation time 10951549007 ps
CPU time 82.67 seconds
Started May 30 03:40:10 PM PDT 24
Finished May 30 03:41:34 PM PDT 24
Peak memory 249360 kb
Host smart-c0a8468b-d3f6-4a27-a555-1c5411353b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134888139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.4134888139
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3866391563
Short name T47
Test name
Test status
Simulation time 22539581406 ps
CPU time 79.61 seconds
Started May 30 03:40:12 PM PDT 24
Finished May 30 03:41:33 PM PDT 24
Peak memory 252340 kb
Host smart-e0a9afd3-a31d-47ea-974e-71b63c00241c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866391563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3866391563
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.571406795
Short name T266
Test name
Test status
Simulation time 47759707639 ps
CPU time 381.62 seconds
Started May 30 03:40:13 PM PDT 24
Finished May 30 03:46:36 PM PDT 24
Peak memory 250128 kb
Host smart-b099eefb-4b60-491d-afdc-91a72811583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571406795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.571406795
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1368024412
Short name T702
Test name
Test status
Simulation time 15854334054 ps
CPU time 28.46 seconds
Started May 30 03:40:15 PM PDT 24
Finished May 30 03:40:45 PM PDT 24
Peak memory 249072 kb
Host smart-e6b4d6f9-1fc0-480f-9272-3c3af56acb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368024412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1368024412
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3801131291
Short name T498
Test name
Test status
Simulation time 5827107997 ps
CPU time 26.88 seconds
Started May 30 03:40:11 PM PDT 24
Finished May 30 03:40:39 PM PDT 24
Peak memory 219564 kb
Host smart-d18f1e39-0a08-483c-af22-0897e8742961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801131291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3801131291
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1190696263
Short name T215
Test name
Test status
Simulation time 958014497 ps
CPU time 7.56 seconds
Started May 30 03:40:11 PM PDT 24
Finished May 30 03:40:21 PM PDT 24
Peak memory 219456 kb
Host smart-dc1fd7e0-9655-42b8-a2ef-c7f826ecb6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190696263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1190696263
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1969854222
Short name T261
Test name
Test status
Simulation time 7186237418 ps
CPU time 16.36 seconds
Started May 30 03:40:13 PM PDT 24
Finished May 30 03:40:32 PM PDT 24
Peak memory 219524 kb
Host smart-05b98930-0863-4bfd-aee6-0acaba7004e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969854222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1969854222
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1179847353
Short name T644
Test name
Test status
Simulation time 5418227396 ps
CPU time 11.23 seconds
Started May 30 03:40:13 PM PDT 24
Finished May 30 03:40:26 PM PDT 24
Peak memory 249272 kb
Host smart-7e6c0fdb-26b0-41a3-94cc-023a458e128c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179847353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1179847353
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.214707844
Short name T719
Test name
Test status
Simulation time 1258598206 ps
CPU time 15.27 seconds
Started May 30 03:40:12 PM PDT 24
Finished May 30 03:40:29 PM PDT 24
Peak memory 222372 kb
Host smart-fc46567f-aaeb-44df-91e4-9f294eb487a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=214707844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.214707844
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1600418362
Short name T140
Test name
Test status
Simulation time 135071961 ps
CPU time 1.26 seconds
Started May 30 03:40:14 PM PDT 24
Finished May 30 03:40:17 PM PDT 24
Peak memory 207056 kb
Host smart-73ed8f28-44a0-4ce6-9fc0-60349210e074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600418362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1600418362
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4132346692
Short name T885
Test name
Test status
Simulation time 2167695723 ps
CPU time 29.36 seconds
Started May 30 03:40:09 PM PDT 24
Finished May 30 03:40:40 PM PDT 24
Peak memory 216268 kb
Host smart-3aa6ec54-110e-4ff4-ae1c-8d95bb0cc26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132346692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4132346692
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4130216010
Short name T367
Test name
Test status
Simulation time 3018674760 ps
CPU time 10 seconds
Started May 30 03:40:11 PM PDT 24
Finished May 30 03:40:23 PM PDT 24
Peak memory 216140 kb
Host smart-028874f3-1b55-4c15-946c-6cacd07b45df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130216010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4130216010
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2354118385
Short name T480
Test name
Test status
Simulation time 309628462 ps
CPU time 1.49 seconds
Started May 30 03:40:16 PM PDT 24
Finished May 30 03:40:19 PM PDT 24
Peak memory 208088 kb
Host smart-c98d6a79-5577-4f63-a9fe-8cd65dd9342e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354118385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2354118385
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4190516778
Short name T673
Test name
Test status
Simulation time 14634811 ps
CPU time 0.78 seconds
Started May 30 03:40:13 PM PDT 24
Finished May 30 03:40:16 PM PDT 24
Peak memory 205656 kb
Host smart-9b039474-9b55-4d00-a0c9-425e00fbb8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190516778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4190516778
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.143829281
Short name T247
Test name
Test status
Simulation time 2145211211 ps
CPU time 10.73 seconds
Started May 30 03:40:12 PM PDT 24
Finished May 30 03:40:25 PM PDT 24
Peak memory 233888 kb
Host smart-1a4a9063-53b7-411b-88dd-e53eaf41bea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143829281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.143829281
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3794434689
Short name T465
Test name
Test status
Simulation time 13202485 ps
CPU time 0.74 seconds
Started May 30 03:40:16 PM PDT 24
Finished May 30 03:40:19 PM PDT 24
Peak memory 204808 kb
Host smart-1d750155-cece-48d0-a42a-11b0e1a68212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794434689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3794434689
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3711454897
Short name T847
Test name
Test status
Simulation time 110486018 ps
CPU time 2.4 seconds
Started May 30 03:40:15 PM PDT 24
Finished May 30 03:40:19 PM PDT 24
Peak memory 216016 kb
Host smart-857e6e21-243f-45c6-b3eb-d3ad5bc8c214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711454897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3711454897
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1798984635
Short name T587
Test name
Test status
Simulation time 169560298 ps
CPU time 0.73 seconds
Started May 30 03:40:12 PM PDT 24
Finished May 30 03:40:15 PM PDT 24
Peak memory 205748 kb
Host smart-0a10ad50-cf06-4348-b6df-22d24bea50db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798984635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1798984635
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.497928269
Short name T254
Test name
Test status
Simulation time 92614497647 ps
CPU time 277.64 seconds
Started May 30 03:40:12 PM PDT 24
Finished May 30 03:44:51 PM PDT 24
Peak memory 256592 kb
Host smart-c9c92260-157e-4581-a13c-3ed6d0bf43bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497928269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.497928269
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.947716381
Short name T54
Test name
Test status
Simulation time 21134684251 ps
CPU time 217.26 seconds
Started May 30 03:40:14 PM PDT 24
Finished May 30 03:43:53 PM PDT 24
Peak memory 253792 kb
Host smart-4b2e6d82-16fd-4ef7-b540-5f937ea3c50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947716381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.947716381
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1470557755
Short name T939
Test name
Test status
Simulation time 33792410717 ps
CPU time 99.2 seconds
Started May 30 03:40:12 PM PDT 24
Finished May 30 03:41:52 PM PDT 24
Peak memory 240820 kb
Host smart-7567d314-2cd0-47e7-aa85-3f553ae9b835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470557755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1470557755
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4080555405
Short name T282
Test name
Test status
Simulation time 4092919828 ps
CPU time 33.25 seconds
Started May 30 03:40:10 PM PDT 24
Finished May 30 03:40:44 PM PDT 24
Peak memory 235000 kb
Host smart-5685b2b5-d169-409c-a7c2-db386a4f7cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080555405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4080555405
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.994813853
Short name T176
Test name
Test status
Simulation time 396839596 ps
CPU time 7.58 seconds
Started May 30 03:40:14 PM PDT 24
Finished May 30 03:40:23 PM PDT 24
Peak memory 233108 kb
Host smart-ad549893-7627-4bb0-b227-b8c82414cee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994813853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.994813853
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.28474469
Short name T699
Test name
Test status
Simulation time 386280668 ps
CPU time 8.14 seconds
Started May 30 03:40:12 PM PDT 24
Finished May 30 03:40:22 PM PDT 24
Peak memory 236692 kb
Host smart-a15f0cc2-0ce0-4598-9602-97a9835a77a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28474469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.28474469
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2241003762
Short name T177
Test name
Test status
Simulation time 1204222961 ps
CPU time 3.72 seconds
Started May 30 03:40:12 PM PDT 24
Finished May 30 03:40:17 PM PDT 24
Peak memory 233976 kb
Host smart-6909ae3a-f160-4d3d-b068-5ba107f25ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241003762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2241003762
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2994644918
Short name T245
Test name
Test status
Simulation time 296227017 ps
CPU time 5.78 seconds
Started May 30 03:40:14 PM PDT 24
Finished May 30 03:40:21 PM PDT 24
Peak memory 240808 kb
Host smart-ed8feb7c-6746-48f7-b051-b4c4c1446f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994644918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2994644918
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2959672776
Short name T634
Test name
Test status
Simulation time 850044222 ps
CPU time 9.45 seconds
Started May 30 03:40:13 PM PDT 24
Finished May 30 03:40:24 PM PDT 24
Peak memory 222028 kb
Host smart-f0190f6f-8950-4d6a-8e8e-9d32341486ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2959672776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2959672776
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.517701805
Short name T426
Test name
Test status
Simulation time 3316078234 ps
CPU time 22.04 seconds
Started May 30 03:40:14 PM PDT 24
Finished May 30 03:40:38 PM PDT 24
Peak memory 216432 kb
Host smart-c5dcc014-64a3-47a4-aa15-77eb601a8fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517701805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.517701805
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3602592236
Short name T413
Test name
Test status
Simulation time 4984446111 ps
CPU time 16.37 seconds
Started May 30 03:40:12 PM PDT 24
Finished May 30 03:40:30 PM PDT 24
Peak memory 216208 kb
Host smart-7231d1a5-6c1b-4290-92fc-00f2f669801b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602592236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3602592236
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2201564061
Short name T477
Test name
Test status
Simulation time 1093636874 ps
CPU time 6.59 seconds
Started May 30 03:40:14 PM PDT 24
Finished May 30 03:40:22 PM PDT 24
Peak memory 216348 kb
Host smart-1cad35b3-9617-4eac-8ff7-077fc6671f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201564061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2201564061
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.483155805
Short name T475
Test name
Test status
Simulation time 261732006 ps
CPU time 0.89 seconds
Started May 30 03:40:12 PM PDT 24
Finished May 30 03:40:14 PM PDT 24
Peak memory 206056 kb
Host smart-e1545bfd-db85-4cc5-9dfc-71d00c7640eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483155805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.483155805
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2274870233
Short name T796
Test name
Test status
Simulation time 284270372 ps
CPU time 3.27 seconds
Started May 30 03:40:12 PM PDT 24
Finished May 30 03:40:17 PM PDT 24
Peak memory 233416 kb
Host smart-dddb1b75-746c-4d7b-b921-c3ee472211f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274870233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2274870233
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1563925441
Short name T822
Test name
Test status
Simulation time 26727199 ps
CPU time 0.74 seconds
Started May 30 03:40:28 PM PDT 24
Finished May 30 03:40:31 PM PDT 24
Peak memory 204820 kb
Host smart-06f39957-b072-42b6-a94a-e00e89b976d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563925441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1563925441
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3981116015
Short name T530
Test name
Test status
Simulation time 126918814 ps
CPU time 2.58 seconds
Started May 30 03:40:22 PM PDT 24
Finished May 30 03:40:26 PM PDT 24
Peak memory 221580 kb
Host smart-ec203b09-2b8f-467b-be52-2c952f08d4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981116015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3981116015
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2975275885
Short name T818
Test name
Test status
Simulation time 19309174 ps
CPU time 0.78 seconds
Started May 30 03:40:16 PM PDT 24
Finished May 30 03:40:18 PM PDT 24
Peak memory 206420 kb
Host smart-016ec211-d76c-4863-a294-ff9a956a8652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975275885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2975275885
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3910186523
Short name T187
Test name
Test status
Simulation time 7707722522 ps
CPU time 59.37 seconds
Started May 30 03:40:22 PM PDT 24
Finished May 30 03:41:23 PM PDT 24
Peak memory 240864 kb
Host smart-06cd6ea1-ec40-4b24-8717-0219fa6e28c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910186523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3910186523
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3452510524
Short name T643
Test name
Test status
Simulation time 2323160719 ps
CPU time 55.75 seconds
Started May 30 03:40:28 PM PDT 24
Finished May 30 03:41:26 PM PDT 24
Peak memory 253584 kb
Host smart-2d40080d-ca4d-466d-b813-208cc96e0f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452510524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3452510524
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2733858956
Short name T292
Test name
Test status
Simulation time 10300401639 ps
CPU time 44.03 seconds
Started May 30 03:40:20 PM PDT 24
Finished May 30 03:41:06 PM PDT 24
Peak memory 249684 kb
Host smart-da2ad79f-5006-411c-affc-eebe8630d836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733858956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2733858956
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2723343963
Short name T767
Test name
Test status
Simulation time 3314257289 ps
CPU time 27.29 seconds
Started May 30 03:40:28 PM PDT 24
Finished May 30 03:40:57 PM PDT 24
Peak memory 232636 kb
Host smart-5888ae9f-0a14-4337-b3d8-144416782acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723343963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2723343963
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2091964141
Short name T321
Test name
Test status
Simulation time 4385704088 ps
CPU time 11.6 seconds
Started May 30 03:40:14 PM PDT 24
Finished May 30 03:40:27 PM PDT 24
Peak memory 233000 kb
Host smart-070468b3-0943-465c-8f7e-3d3225193f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091964141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2091964141
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1066909990
Short name T542
Test name
Test status
Simulation time 673627358 ps
CPU time 10.72 seconds
Started May 30 03:40:14 PM PDT 24
Finished May 30 03:40:27 PM PDT 24
Peak memory 228436 kb
Host smart-01d3def5-f0c4-4800-a762-542ad429e33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066909990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1066909990
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2362337992
Short name T675
Test name
Test status
Simulation time 435961515 ps
CPU time 2.55 seconds
Started May 30 03:40:15 PM PDT 24
Finished May 30 03:40:20 PM PDT 24
Peak memory 218708 kb
Host smart-563e46de-1232-4926-b709-08dadb99d2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362337992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2362337992
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.808102129
Short name T706
Test name
Test status
Simulation time 9038421357 ps
CPU time 11.68 seconds
Started May 30 03:40:16 PM PDT 24
Finished May 30 03:40:30 PM PDT 24
Peak memory 233624 kb
Host smart-3baa8cb9-6408-4acb-9398-e288b4c80e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808102129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.808102129
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.231892573
Short name T741
Test name
Test status
Simulation time 2597791837 ps
CPU time 12.04 seconds
Started May 30 03:40:22 PM PDT 24
Finished May 30 03:40:36 PM PDT 24
Peak memory 222908 kb
Host smart-a69f2fbe-751a-4aaa-b56b-11c3b6004295
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=231892573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.231892573
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3288846359
Short name T146
Test name
Test status
Simulation time 84861623 ps
CPU time 1.1 seconds
Started May 30 03:40:27 PM PDT 24
Finished May 30 03:40:30 PM PDT 24
Peak memory 207012 kb
Host smart-1e7d76dd-9c4c-4336-bab8-3409183f7738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288846359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3288846359
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2965442476
Short name T893
Test name
Test status
Simulation time 668004260 ps
CPU time 9.63 seconds
Started May 30 03:40:13 PM PDT 24
Finished May 30 03:40:25 PM PDT 24
Peak memory 216188 kb
Host smart-9893efdc-dd64-4a54-aab8-de9f5406d7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965442476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2965442476
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.237874475
Short name T907
Test name
Test status
Simulation time 3052122243 ps
CPU time 4.46 seconds
Started May 30 03:40:14 PM PDT 24
Finished May 30 03:40:20 PM PDT 24
Peak memory 215928 kb
Host smart-0f7ddb9e-3931-4653-8b67-2c0ba7975277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237874475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.237874475
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2412622397
Short name T896
Test name
Test status
Simulation time 148016433 ps
CPU time 1.55 seconds
Started May 30 03:40:13 PM PDT 24
Finished May 30 03:40:17 PM PDT 24
Peak memory 208012 kb
Host smart-9f838b0d-b4d4-4f5c-8bde-490b06a2221f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412622397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2412622397
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2183634127
Short name T433
Test name
Test status
Simulation time 120209827 ps
CPU time 0.84 seconds
Started May 30 03:40:16 PM PDT 24
Finished May 30 03:40:18 PM PDT 24
Peak memory 205648 kb
Host smart-f5a3f9f4-1095-4ab0-8636-ee72d4edeca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183634127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2183634127
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2922911862
Short name T377
Test name
Test status
Simulation time 530587237 ps
CPU time 6.49 seconds
Started May 30 03:40:26 PM PDT 24
Finished May 30 03:40:34 PM PDT 24
Peak memory 234428 kb
Host smart-e7c2db21-078a-4c8f-9df7-53ef39237c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922911862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2922911862
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3514156924
Short name T376
Test name
Test status
Simulation time 24749956 ps
CPU time 0.79 seconds
Started May 30 03:39:17 PM PDT 24
Finished May 30 03:39:21 PM PDT 24
Peak memory 205732 kb
Host smart-5d185ee8-1ed0-4054-ad91-f5df7256754d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514156924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
514156924
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1969800937
Short name T731
Test name
Test status
Simulation time 71535003 ps
CPU time 2.58 seconds
Started May 30 03:39:15 PM PDT 24
Finished May 30 03:39:20 PM PDT 24
Peak memory 233448 kb
Host smart-73e60a08-8a45-43d8-b17e-236b73c6c4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969800937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1969800937
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2125417182
Short name T330
Test name
Test status
Simulation time 35390381 ps
CPU time 0.83 seconds
Started May 30 03:39:21 PM PDT 24
Finished May 30 03:39:24 PM PDT 24
Peak memory 206428 kb
Host smart-9191186c-5160-4435-bcf7-56a45116e028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125417182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2125417182
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.357074652
Short name T667
Test name
Test status
Simulation time 13148952338 ps
CPU time 25.56 seconds
Started May 30 03:39:21 PM PDT 24
Finished May 30 03:39:49 PM PDT 24
Peak memory 224472 kb
Host smart-0a58193f-fb7c-4dbb-8547-89db9132455c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357074652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.357074652
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3701255119
Short name T828
Test name
Test status
Simulation time 44576565996 ps
CPU time 151.82 seconds
Started May 30 03:39:19 PM PDT 24
Finished May 30 03:41:54 PM PDT 24
Peak memory 256940 kb
Host smart-5d264660-c47b-45cf-8610-09cc120e1bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701255119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3701255119
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3840332902
Short name T853
Test name
Test status
Simulation time 1049304160 ps
CPU time 4.16 seconds
Started May 30 03:39:17 PM PDT 24
Finished May 30 03:39:24 PM PDT 24
Peak memory 224396 kb
Host smart-6c4c9b6b-4e87-43a2-a4d1-75d1c25bbc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840332902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3840332902
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.292587625
Short name T332
Test name
Test status
Simulation time 1614953082 ps
CPU time 11.68 seconds
Started May 30 03:39:15 PM PDT 24
Finished May 30 03:39:29 PM PDT 24
Peak memory 218740 kb
Host smart-4b459d8d-1f39-4666-a3cf-fa69dedc7866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292587625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.292587625
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1027388970
Short name T370
Test name
Test status
Simulation time 4428452069 ps
CPU time 4.63 seconds
Started May 30 03:39:14 PM PDT 24
Finished May 30 03:39:19 PM PDT 24
Peak memory 223664 kb
Host smart-92cfdaf9-d21e-45ee-b74a-f0db8c44dcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027388970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1027388970
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3472587054
Short name T501
Test name
Test status
Simulation time 3563827024 ps
CPU time 6.34 seconds
Started May 30 03:39:19 PM PDT 24
Finished May 30 03:39:28 PM PDT 24
Peak memory 233304 kb
Host smart-01b8a2d8-b18f-4734-8c42-4104649dbcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472587054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3472587054
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.349145831
Short name T845
Test name
Test status
Simulation time 1542226433 ps
CPU time 3.61 seconds
Started May 30 03:39:22 PM PDT 24
Finished May 30 03:39:28 PM PDT 24
Peak memory 216652 kb
Host smart-eba4e052-1b4b-49ee-8fd0-d137b32998cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349145831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.349145831
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1333665119
Short name T726
Test name
Test status
Simulation time 804286803 ps
CPU time 4.32 seconds
Started May 30 03:39:16 PM PDT 24
Finished May 30 03:39:23 PM PDT 24
Peak memory 220352 kb
Host smart-f94398d4-4663-453a-bea9-66d7dcf966e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1333665119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1333665119
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1247463967
Short name T68
Test name
Test status
Simulation time 223128726 ps
CPU time 1.1 seconds
Started May 30 03:39:18 PM PDT 24
Finished May 30 03:39:22 PM PDT 24
Peak memory 235136 kb
Host smart-b97ba4ab-42a2-4556-8aca-8b9ddb04e344
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247463967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1247463967
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1225247872
Short name T179
Test name
Test status
Simulation time 21195700108 ps
CPU time 166.07 seconds
Started May 30 03:39:21 PM PDT 24
Finished May 30 03:42:11 PM PDT 24
Peak memory 240872 kb
Host smart-baf4a179-9d0a-4c25-babb-1c043edafd67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225247872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1225247872
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.645213711
Short name T438
Test name
Test status
Simulation time 2970833442 ps
CPU time 20.93 seconds
Started May 30 03:39:17 PM PDT 24
Finished May 30 03:39:40 PM PDT 24
Peak memory 216236 kb
Host smart-92a7dccd-5866-4ca6-a4d0-e74396bb6be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645213711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.645213711
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1705540710
Short name T467
Test name
Test status
Simulation time 3961387679 ps
CPU time 4.1 seconds
Started May 30 03:39:21 PM PDT 24
Finished May 30 03:39:28 PM PDT 24
Peak memory 216168 kb
Host smart-fd1ca490-2d36-42c8-b5a6-8e7f3c185c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705540710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1705540710
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3010388912
Short name T300
Test name
Test status
Simulation time 26618160 ps
CPU time 1.27 seconds
Started May 30 03:39:21 PM PDT 24
Finished May 30 03:39:26 PM PDT 24
Peak memory 216208 kb
Host smart-43ad60de-104b-494b-88c9-6a6c084415aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010388912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3010388912
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2016600489
Short name T677
Test name
Test status
Simulation time 65304877 ps
CPU time 0.73 seconds
Started May 30 03:39:22 PM PDT 24
Finished May 30 03:39:26 PM PDT 24
Peak memory 205676 kb
Host smart-25ec8c83-fc94-4e2e-9d7d-494366d3f046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016600489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2016600489
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.4249755741
Short name T514
Test name
Test status
Simulation time 16891451314 ps
CPU time 15.15 seconds
Started May 30 03:39:19 PM PDT 24
Finished May 30 03:39:37 PM PDT 24
Peak memory 226888 kb
Host smart-1cc500a7-e76b-40c8-bae8-554d5e0aa1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249755741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.4249755741
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3493369215
Short name T510
Test name
Test status
Simulation time 38720265 ps
CPU time 0.71 seconds
Started May 30 03:40:26 PM PDT 24
Finished May 30 03:40:28 PM PDT 24
Peak memory 204800 kb
Host smart-8840634b-17c0-4456-ba07-ee5eee0b0f86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493369215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3493369215
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3890683240
Short name T811
Test name
Test status
Simulation time 115703098 ps
CPU time 2.11 seconds
Started May 30 03:40:28 PM PDT 24
Finished May 30 03:40:32 PM PDT 24
Peak memory 216072 kb
Host smart-99d87ca8-c78c-413f-88d9-2c9dbbb5d037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890683240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3890683240
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2120860423
Short name T306
Test name
Test status
Simulation time 14430180 ps
CPU time 0.74 seconds
Started May 30 03:40:21 PM PDT 24
Finished May 30 03:40:23 PM PDT 24
Peak memory 205444 kb
Host smart-261774c5-ce51-4c5c-8692-5436e889992b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120860423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2120860423
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2846577431
Short name T771
Test name
Test status
Simulation time 2895692467 ps
CPU time 59.02 seconds
Started May 30 03:40:28 PM PDT 24
Finished May 30 03:41:29 PM PDT 24
Peak memory 252808 kb
Host smart-57c68e25-fefc-436b-9bfd-5ced02a9e5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846577431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2846577431
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.891370041
Short name T517
Test name
Test status
Simulation time 511954323 ps
CPU time 6.36 seconds
Started May 30 03:40:25 PM PDT 24
Finished May 30 03:40:33 PM PDT 24
Peak memory 240696 kb
Host smart-10ec4d0b-7a73-46a8-9140-689a89565d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891370041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.891370041
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.540791256
Short name T423
Test name
Test status
Simulation time 897936722 ps
CPU time 10.13 seconds
Started May 30 03:40:29 PM PDT 24
Finished May 30 03:40:42 PM PDT 24
Peak memory 217456 kb
Host smart-e7d5c3b3-6995-4dd1-b2d6-88ce130c6441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540791256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.540791256
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2411134117
Short name T625
Test name
Test status
Simulation time 496826986 ps
CPU time 7.03 seconds
Started May 30 03:40:21 PM PDT 24
Finished May 30 03:40:30 PM PDT 24
Peak memory 223088 kb
Host smart-a7e0d810-021f-41c7-9e4c-a736e0bffc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411134117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2411134117
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3985733552
Short name T554
Test name
Test status
Simulation time 829659747 ps
CPU time 4.35 seconds
Started May 30 03:40:30 PM PDT 24
Finished May 30 03:40:37 PM PDT 24
Peak memory 235776 kb
Host smart-88ab5744-c67c-4f1b-8bed-974c09600e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985733552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3985733552
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.938230569
Short name T481
Test name
Test status
Simulation time 4357256338 ps
CPU time 8.74 seconds
Started May 30 03:40:26 PM PDT 24
Finished May 30 03:40:36 PM PDT 24
Peak memory 218484 kb
Host smart-4cda7ca4-3a01-4b35-8d2c-6751e74bf363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938230569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.938230569
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1873773016
Short name T421
Test name
Test status
Simulation time 4220925026 ps
CPU time 4.86 seconds
Started May 30 03:40:31 PM PDT 24
Finished May 30 03:40:39 PM PDT 24
Peak memory 219068 kb
Host smart-29d4a03d-fd98-4a79-a88c-0c248bc703f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1873773016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1873773016
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.692052624
Short name T882
Test name
Test status
Simulation time 180982194977 ps
CPU time 58.2 seconds
Started May 30 03:40:26 PM PDT 24
Finished May 30 03:41:26 PM PDT 24
Peak memory 216300 kb
Host smart-76baae59-ac9c-492f-8054-81c9c4b21092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692052624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.692052624
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2424097294
Short name T711
Test name
Test status
Simulation time 28829940219 ps
CPU time 21.69 seconds
Started May 30 03:40:28 PM PDT 24
Finished May 30 03:40:52 PM PDT 24
Peak memory 217220 kb
Host smart-6f9674e2-92cc-4e0d-bf21-9a77f4425160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424097294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2424097294
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1561030447
Short name T324
Test name
Test status
Simulation time 168759842 ps
CPU time 2.93 seconds
Started May 30 03:40:21 PM PDT 24
Finished May 30 03:40:26 PM PDT 24
Peak memory 216208 kb
Host smart-f67ba3f0-d144-4461-b9e1-8046d039becf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561030447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1561030447
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2409613176
Short name T415
Test name
Test status
Simulation time 325224369 ps
CPU time 1 seconds
Started May 30 03:40:24 PM PDT 24
Finished May 30 03:40:27 PM PDT 24
Peak memory 206136 kb
Host smart-96be24b6-d78b-4c80-99b8-478cff22f9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409613176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2409613176
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3730241154
Short name T645
Test name
Test status
Simulation time 131860993 ps
CPU time 2.73 seconds
Started May 30 03:40:24 PM PDT 24
Finished May 30 03:40:28 PM PDT 24
Peak memory 212972 kb
Host smart-102b80fe-e817-43bb-86e0-4793485ee43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730241154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3730241154
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3504212378
Short name T902
Test name
Test status
Simulation time 38974215 ps
CPU time 0.7 seconds
Started May 30 03:40:41 PM PDT 24
Finished May 30 03:40:45 PM PDT 24
Peak memory 205368 kb
Host smart-af2de63d-5b6c-41f4-9268-93773da14633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504212378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3504212378
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2584874638
Short name T661
Test name
Test status
Simulation time 170367325 ps
CPU time 4.05 seconds
Started May 30 03:40:28 PM PDT 24
Finished May 30 03:40:34 PM PDT 24
Peak memory 233924 kb
Host smart-66f19f14-395a-4a3b-94a5-e7ef6dbc7ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584874638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2584874638
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3941834774
Short name T412
Test name
Test status
Simulation time 65943355 ps
CPU time 0.77 seconds
Started May 30 03:40:26 PM PDT 24
Finished May 30 03:40:29 PM PDT 24
Peak memory 206444 kb
Host smart-6f406e7f-4829-4cf1-a2fe-1a399e1f5b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941834774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3941834774
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1523152285
Short name T843
Test name
Test status
Simulation time 4782223637 ps
CPU time 77.25 seconds
Started May 30 03:40:20 PM PDT 24
Finished May 30 03:41:39 PM PDT 24
Peak memory 265424 kb
Host smart-73ef9c85-ba54-409c-8efd-3ca707474868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523152285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1523152285
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1541911445
Short name T285
Test name
Test status
Simulation time 1149266076 ps
CPU time 16.72 seconds
Started May 30 03:40:23 PM PDT 24
Finished May 30 03:40:41 PM PDT 24
Peak memory 240772 kb
Host smart-c4e73840-743c-4fc7-ae54-901d9632be98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541911445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1541911445
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1144039036
Short name T593
Test name
Test status
Simulation time 667311773 ps
CPU time 4.74 seconds
Started May 30 03:40:29 PM PDT 24
Finished May 30 03:40:36 PM PDT 24
Peak memory 232588 kb
Host smart-3abab8e3-d206-417a-97f0-dce6d0bae22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144039036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1144039036
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.612921628
Short name T869
Test name
Test status
Simulation time 175711086 ps
CPU time 2.56 seconds
Started May 30 03:40:27 PM PDT 24
Finished May 30 03:40:32 PM PDT 24
Peak memory 232636 kb
Host smart-f8344575-ca47-4ab2-b26f-d24446bd5a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612921628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.612921628
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.487424086
Short name T414
Test name
Test status
Simulation time 21030094951 ps
CPU time 15.76 seconds
Started May 30 03:40:23 PM PDT 24
Finished May 30 03:40:40 PM PDT 24
Peak memory 233772 kb
Host smart-22817249-0cc3-49c6-bb13-85e8fc2ade07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487424086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.487424086
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1201894899
Short name T437
Test name
Test status
Simulation time 106836667 ps
CPU time 2.31 seconds
Started May 30 03:40:28 PM PDT 24
Finished May 30 03:40:33 PM PDT 24
Peak memory 218584 kb
Host smart-0ce22b67-4c63-428d-b717-270306998ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201894899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1201894899
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3724708654
Short name T725
Test name
Test status
Simulation time 1001189071 ps
CPU time 5.06 seconds
Started May 30 03:40:26 PM PDT 24
Finished May 30 03:40:33 PM PDT 24
Peak memory 222816 kb
Host smart-b7ea6f81-fcf8-406d-b6f7-7aee5f34daa9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3724708654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3724708654
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3585867916
Short name T181
Test name
Test status
Simulation time 150404341421 ps
CPU time 337.94 seconds
Started May 30 03:40:26 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 249120 kb
Host smart-92cda3fb-cf4c-4fdb-96fc-e7b45631916d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585867916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3585867916
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1483604550
Short name T704
Test name
Test status
Simulation time 12861549159 ps
CPU time 23.92 seconds
Started May 30 03:40:24 PM PDT 24
Finished May 30 03:40:50 PM PDT 24
Peak memory 219800 kb
Host smart-98b7b606-c2ae-43bd-be05-09b889f8ddc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483604550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1483604550
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2401940606
Short name T442
Test name
Test status
Simulation time 52623934730 ps
CPU time 15.64 seconds
Started May 30 03:40:25 PM PDT 24
Finished May 30 03:40:41 PM PDT 24
Peak memory 216152 kb
Host smart-c6e0ae0c-fd7b-4027-b551-df5b703a4ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401940606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2401940606
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1914577836
Short name T495
Test name
Test status
Simulation time 104563503 ps
CPU time 0.86 seconds
Started May 30 03:40:21 PM PDT 24
Finished May 30 03:40:24 PM PDT 24
Peak memory 206348 kb
Host smart-69a586b2-2de8-4e85-a9d7-3b8e7cf8f247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914577836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1914577836
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2119617022
Short name T362
Test name
Test status
Simulation time 74696202 ps
CPU time 0.9 seconds
Started May 30 03:40:27 PM PDT 24
Finished May 30 03:40:31 PM PDT 24
Peak memory 205436 kb
Host smart-b473b882-6682-41f9-81d5-17a69a387ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119617022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2119617022
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.807699122
Short name T220
Test name
Test status
Simulation time 1357659627 ps
CPU time 5.98 seconds
Started May 30 03:40:26 PM PDT 24
Finished May 30 03:40:33 PM PDT 24
Peak memory 218796 kb
Host smart-10f99456-3cb2-4cc8-b0e7-6f63ce7c0fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807699122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.807699122
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2929415951
Short name T799
Test name
Test status
Simulation time 12600178 ps
CPU time 0.69 seconds
Started May 30 03:40:32 PM PDT 24
Finished May 30 03:40:35 PM PDT 24
Peak memory 205712 kb
Host smart-f8edf16e-4316-42ee-9cd1-fead59a11db3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929415951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2929415951
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3203015114
Short name T807
Test name
Test status
Simulation time 78321208 ps
CPU time 2.33 seconds
Started May 30 03:40:23 PM PDT 24
Finished May 30 03:40:26 PM PDT 24
Peak memory 218232 kb
Host smart-c0c15f37-f7ed-431c-9aa3-1cd77e35b21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203015114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3203015114
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.4286093670
Short name T552
Test name
Test status
Simulation time 72084522 ps
CPU time 0.74 seconds
Started May 30 03:40:27 PM PDT 24
Finished May 30 03:40:30 PM PDT 24
Peak memory 206256 kb
Host smart-ae940b82-5446-4c76-a1d9-8735bd8849e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286093670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4286093670
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1988599107
Short name T30
Test name
Test status
Simulation time 18222383359 ps
CPU time 60.21 seconds
Started May 30 03:40:28 PM PDT 24
Finished May 30 03:41:30 PM PDT 24
Peak memory 240836 kb
Host smart-22360d81-f561-4a20-b3ba-effee12efe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988599107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1988599107
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3028070041
Short name T636
Test name
Test status
Simulation time 76964002723 ps
CPU time 197.75 seconds
Started May 30 03:40:24 PM PDT 24
Finished May 30 03:43:43 PM PDT 24
Peak memory 253272 kb
Host smart-9b371fde-9a2d-4cd9-8194-3800915d7f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028070041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3028070041
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3527670189
Short name T259
Test name
Test status
Simulation time 40926685119 ps
CPU time 207.44 seconds
Started May 30 03:40:30 PM PDT 24
Finished May 30 03:44:00 PM PDT 24
Peak memory 253600 kb
Host smart-351595cd-2671-4854-8fd0-428647435229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527670189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3527670189
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1028369276
Short name T287
Test name
Test status
Simulation time 943392809 ps
CPU time 6.65 seconds
Started May 30 03:40:27 PM PDT 24
Finished May 30 03:40:36 PM PDT 24
Peak memory 232644 kb
Host smart-5acda7c9-031b-4626-a6f8-33a8d931ac88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028369276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1028369276
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.492705178
Short name T827
Test name
Test status
Simulation time 4598027419 ps
CPU time 13.57 seconds
Started May 30 03:40:28 PM PDT 24
Finished May 30 03:40:44 PM PDT 24
Peak memory 234736 kb
Host smart-4e6ef016-73a0-4cbe-90bb-77cd449f8bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492705178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.492705178
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2883979206
Short name T409
Test name
Test status
Simulation time 109014224 ps
CPU time 2.23 seconds
Started May 30 03:40:22 PM PDT 24
Finished May 30 03:40:25 PM PDT 24
Peak memory 221508 kb
Host smart-643ef892-c9b5-4396-81a4-9103a6fdf1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883979206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2883979206
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1047984386
Short name T886
Test name
Test status
Simulation time 414323595 ps
CPU time 3.59 seconds
Started May 30 03:40:24 PM PDT 24
Finished May 30 03:40:29 PM PDT 24
Peak memory 233028 kb
Host smart-266e2c89-6558-42b1-99b7-434b3dce8899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047984386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1047984386
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3627825970
Short name T621
Test name
Test status
Simulation time 35533506 ps
CPU time 2.57 seconds
Started May 30 03:40:30 PM PDT 24
Finished May 30 03:40:35 PM PDT 24
Peak memory 232648 kb
Host smart-7142962e-b18e-44c5-bafc-f5f5e6e3489c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627825970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3627825970
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2237320694
Short name T516
Test name
Test status
Simulation time 310905786 ps
CPU time 6.62 seconds
Started May 30 03:40:32 PM PDT 24
Finished May 30 03:40:41 PM PDT 24
Peak memory 222920 kb
Host smart-3c84fa2b-42f5-42d0-b61a-69abdf86a043
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2237320694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2237320694
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3414254147
Short name T263
Test name
Test status
Simulation time 11497950827 ps
CPU time 110.93 seconds
Started May 30 03:40:29 PM PDT 24
Finished May 30 03:42:22 PM PDT 24
Peak memory 257260 kb
Host smart-7cc71ebe-95b7-4ea6-a8c6-b491c77031e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414254147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3414254147
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.707386479
Short name T484
Test name
Test status
Simulation time 6838137024 ps
CPU time 29.82 seconds
Started May 30 03:40:27 PM PDT 24
Finished May 30 03:40:59 PM PDT 24
Peak memory 216348 kb
Host smart-9baedb7e-66be-42c1-b8f5-b0e50a01fad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707386479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.707386479
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3466026518
Short name T440
Test name
Test status
Simulation time 2236259124 ps
CPU time 9.04 seconds
Started May 30 03:40:30 PM PDT 24
Finished May 30 03:40:41 PM PDT 24
Peak memory 216116 kb
Host smart-b7629cb2-0dac-4ecf-af3e-c6a1f453c392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466026518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3466026518
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.4195099842
Short name T629
Test name
Test status
Simulation time 610246055 ps
CPU time 1.35 seconds
Started May 30 03:40:27 PM PDT 24
Finished May 30 03:40:31 PM PDT 24
Peak memory 216208 kb
Host smart-383c3232-3621-4d9a-86cd-d14fecaa9b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195099842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.4195099842
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3373787530
Short name T781
Test name
Test status
Simulation time 12133484 ps
CPU time 0.7 seconds
Started May 30 03:40:30 PM PDT 24
Finished May 30 03:40:33 PM PDT 24
Peak memory 205600 kb
Host smart-a52ea330-0314-40b6-84ac-698f88311535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373787530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3373787530
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.93606982
Short name T911
Test name
Test status
Simulation time 9817546386 ps
CPU time 8.85 seconds
Started May 30 03:40:21 PM PDT 24
Finished May 30 03:40:32 PM PDT 24
Peak memory 219520 kb
Host smart-b812329f-beaf-4243-bc85-de7185ee19ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93606982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.93606982
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.948828399
Short name T400
Test name
Test status
Simulation time 49959017 ps
CPU time 0.7 seconds
Started May 30 03:40:30 PM PDT 24
Finished May 30 03:40:33 PM PDT 24
Peak memory 204804 kb
Host smart-90a305e8-2ab6-407c-997b-2b831a16a690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948828399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.948828399
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2556580977
Short name T915
Test name
Test status
Simulation time 1254590072 ps
CPU time 6.9 seconds
Started May 30 03:40:33 PM PDT 24
Finished May 30 03:40:42 PM PDT 24
Peak memory 224396 kb
Host smart-77463a88-b217-4ae8-98cb-0b38237b39d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556580977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2556580977
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.791480547
Short name T563
Test name
Test status
Simulation time 24912903 ps
CPU time 0.77 seconds
Started May 30 03:40:30 PM PDT 24
Finished May 30 03:40:34 PM PDT 24
Peak memory 205380 kb
Host smart-4eefe28e-b5be-4558-9b54-70a91ace6c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791480547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.791480547
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1071133578
Short name T253
Test name
Test status
Simulation time 5561913061 ps
CPU time 84.25 seconds
Started May 30 03:40:33 PM PDT 24
Finished May 30 03:42:00 PM PDT 24
Peak memory 256788 kb
Host smart-bde3bf18-4ec3-4fc7-977b-edb5d6ecc714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071133578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1071133578
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1880583682
Short name T693
Test name
Test status
Simulation time 8262778064 ps
CPU time 109.23 seconds
Started May 30 03:40:29 PM PDT 24
Finished May 30 03:42:21 PM PDT 24
Peak memory 249124 kb
Host smart-54c65ce5-b213-491f-be50-527dc4caf1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880583682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1880583682
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2370417497
Short name T276
Test name
Test status
Simulation time 3918649972 ps
CPU time 83.73 seconds
Started May 30 03:40:28 PM PDT 24
Finished May 30 03:41:54 PM PDT 24
Peak memory 272664 kb
Host smart-06a90385-fe6e-47d7-aa80-99e1c5b8a4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370417497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2370417497
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3768008311
Short name T425
Test name
Test status
Simulation time 1906887677 ps
CPU time 5.12 seconds
Started May 30 03:40:33 PM PDT 24
Finished May 30 03:40:40 PM PDT 24
Peak memory 233740 kb
Host smart-c9ef0f38-9143-41c8-9762-0b5e8cbdd80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768008311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3768008311
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2635195133
Short name T947
Test name
Test status
Simulation time 9106499626 ps
CPU time 24.96 seconds
Started May 30 03:40:34 PM PDT 24
Finished May 30 03:41:01 PM PDT 24
Peak memory 219568 kb
Host smart-872c267d-0648-43be-a635-399b350c6987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635195133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2635195133
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2774777595
Short name T581
Test name
Test status
Simulation time 88758349 ps
CPU time 2.63 seconds
Started May 30 03:40:34 PM PDT 24
Finished May 30 03:40:39 PM PDT 24
Peak memory 234212 kb
Host smart-dd5febb3-e308-49cf-8f09-9fdf75ef8c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774777595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2774777595
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3294616715
Short name T328
Test name
Test status
Simulation time 108488649 ps
CPU time 2.41 seconds
Started May 30 03:40:33 PM PDT 24
Finished May 30 03:40:38 PM PDT 24
Peak memory 218388 kb
Host smart-d84a0498-6704-4d43-bf01-8e0ac9a8e40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294616715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3294616715
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.267634631
Short name T602
Test name
Test status
Simulation time 598306669 ps
CPU time 2.83 seconds
Started May 30 03:40:32 PM PDT 24
Finished May 30 03:40:37 PM PDT 24
Peak memory 232600 kb
Host smart-e74efadc-b7f1-403a-87bd-705561c1c51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267634631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.267634631
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1184007362
Short name T357
Test name
Test status
Simulation time 1840650020 ps
CPU time 8.17 seconds
Started May 30 03:40:30 PM PDT 24
Finished May 30 03:40:41 PM PDT 24
Peak memory 220208 kb
Host smart-b55e8508-9883-407e-b04a-a3456b983d72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1184007362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1184007362
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3701810865
Short name T269
Test name
Test status
Simulation time 47331996072 ps
CPU time 258.18 seconds
Started May 30 03:40:35 PM PDT 24
Finished May 30 03:44:55 PM PDT 24
Peak memory 254740 kb
Host smart-aef5b929-ef03-4f89-ab4b-8709061bf918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701810865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3701810865
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2295589471
Short name T335
Test name
Test status
Simulation time 26833235568 ps
CPU time 36.93 seconds
Started May 30 03:40:29 PM PDT 24
Finished May 30 03:41:08 PM PDT 24
Peak memory 216276 kb
Host smart-5cd33353-de50-446d-b225-747ed31bb5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295589471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2295589471
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3980238894
Short name T871
Test name
Test status
Simulation time 3704509323 ps
CPU time 5.39 seconds
Started May 30 03:40:27 PM PDT 24
Finished May 30 03:40:35 PM PDT 24
Peak memory 216196 kb
Host smart-04fad43e-cedd-41af-ae3a-cb8fef55dc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980238894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3980238894
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1469911440
Short name T311
Test name
Test status
Simulation time 1353628794 ps
CPU time 3.34 seconds
Started May 30 03:40:37 PM PDT 24
Finished May 30 03:40:42 PM PDT 24
Peak memory 216116 kb
Host smart-42f61078-9f7e-4ec6-9a0d-f0165d1ed058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469911440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1469911440
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2903751119
Short name T594
Test name
Test status
Simulation time 31867432 ps
CPU time 0.9 seconds
Started May 30 03:40:35 PM PDT 24
Finished May 30 03:40:37 PM PDT 24
Peak memory 206672 kb
Host smart-f80715a5-8a54-4313-af86-9e10c960dfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903751119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2903751119
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3060789740
Short name T785
Test name
Test status
Simulation time 790745253 ps
CPU time 6.77 seconds
Started May 30 03:40:36 PM PDT 24
Finished May 30 03:40:45 PM PDT 24
Peak memory 232456 kb
Host smart-ef1a3e25-258a-408c-bf7f-af78f5982bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060789740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3060789740
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1641878235
Short name T657
Test name
Test status
Simulation time 13578184 ps
CPU time 0.77 seconds
Started May 30 03:40:33 PM PDT 24
Finished May 30 03:40:36 PM PDT 24
Peak memory 204808 kb
Host smart-86382d0e-696b-40f8-a44a-bb3206cd9da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641878235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1641878235
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2715960552
Short name T383
Test name
Test status
Simulation time 214900615 ps
CPU time 3.39 seconds
Started May 30 03:40:33 PM PDT 24
Finished May 30 03:40:39 PM PDT 24
Peak memory 235136 kb
Host smart-2ccf8ab0-c83f-4914-91b5-48c62d8ccc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715960552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2715960552
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1459368013
Short name T891
Test name
Test status
Simulation time 22257787 ps
CPU time 0.79 seconds
Started May 30 03:40:34 PM PDT 24
Finished May 30 03:40:37 PM PDT 24
Peak memory 206452 kb
Host smart-fbfeadfa-eed8-4835-b174-bc241dc8ab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459368013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1459368013
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3070506583
Short name T212
Test name
Test status
Simulation time 36393757161 ps
CPU time 128.64 seconds
Started May 30 03:40:35 PM PDT 24
Finished May 30 03:42:45 PM PDT 24
Peak memory 253420 kb
Host smart-df4a8b90-9f47-440c-9026-fa49d70e905e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070506583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3070506583
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2496820247
Short name T213
Test name
Test status
Simulation time 15856462980 ps
CPU time 70.52 seconds
Started May 30 03:40:29 PM PDT 24
Finished May 30 03:41:42 PM PDT 24
Peak memory 249124 kb
Host smart-0ba076e9-c41b-4e21-9efa-55e2ff1953ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496820247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2496820247
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3280376912
Short name T186
Test name
Test status
Simulation time 6541719236 ps
CPU time 18.09 seconds
Started May 30 03:40:30 PM PDT 24
Finished May 30 03:40:51 PM PDT 24
Peak memory 218564 kb
Host smart-7fab1c56-3cf7-443d-9612-341ff6cf86d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280376912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3280376912
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.344336854
Short name T117
Test name
Test status
Simulation time 40587341546 ps
CPU time 49.94 seconds
Started May 30 03:40:32 PM PDT 24
Finished May 30 03:41:24 PM PDT 24
Peak memory 245864 kb
Host smart-51176d90-129f-4ffc-98df-43311beeec0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344336854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.344336854
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2394603168
Short name T631
Test name
Test status
Simulation time 650435910 ps
CPU time 2.66 seconds
Started May 30 03:40:30 PM PDT 24
Finished May 30 03:40:35 PM PDT 24
Peak memory 217824 kb
Host smart-ffd15110-f452-46d3-aed7-a87ac43bc24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394603168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2394603168
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2365839561
Short name T934
Test name
Test status
Simulation time 3167010975 ps
CPU time 9.27 seconds
Started May 30 03:40:34 PM PDT 24
Finished May 30 03:40:46 PM PDT 24
Peak memory 240808 kb
Host smart-a0c37470-8d84-4c00-a832-291155fa9388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365839561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2365839561
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2236416660
Short name T469
Test name
Test status
Simulation time 151649000 ps
CPU time 3.75 seconds
Started May 30 03:40:32 PM PDT 24
Finished May 30 03:40:38 PM PDT 24
Peak memory 219164 kb
Host smart-d06322c5-a953-4d23-99d2-ccf7d0e76d10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2236416660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2236416660
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.4086332028
Short name T143
Test name
Test status
Simulation time 39951062055 ps
CPU time 112.17 seconds
Started May 30 03:40:31 PM PDT 24
Finished May 30 03:42:25 PM PDT 24
Peak memory 240976 kb
Host smart-c56c9cf5-41a0-44a5-8688-ad3d0bb2e728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086332028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4086332028
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3125739180
Short name T439
Test name
Test status
Simulation time 10994251629 ps
CPU time 17.69 seconds
Started May 30 03:40:32 PM PDT 24
Finished May 30 03:40:52 PM PDT 24
Peak memory 216604 kb
Host smart-1e0aef63-2365-43e9-94e6-ff23ca4de3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125739180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3125739180
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.332292715
Short name T662
Test name
Test status
Simulation time 2120957219 ps
CPU time 2.38 seconds
Started May 30 03:40:31 PM PDT 24
Finished May 30 03:40:36 PM PDT 24
Peak memory 207792 kb
Host smart-4d987223-fe22-4d95-ab23-830bcddf7392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332292715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.332292715
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.4287194922
Short name T373
Test name
Test status
Simulation time 101160934 ps
CPU time 4.83 seconds
Started May 30 03:40:33 PM PDT 24
Finished May 30 03:40:40 PM PDT 24
Peak memory 216056 kb
Host smart-6dd14b8f-d49c-4600-a885-03b6fb42d95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287194922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4287194922
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.320534052
Short name T366
Test name
Test status
Simulation time 66194713 ps
CPU time 0.75 seconds
Started May 30 03:40:37 PM PDT 24
Finished May 30 03:40:39 PM PDT 24
Peak memory 205584 kb
Host smart-20ce1fb2-52d5-4f76-8a3b-58f7ed44a7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320534052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.320534052
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1258511998
Short name T887
Test name
Test status
Simulation time 3452730999 ps
CPU time 6.76 seconds
Started May 30 03:40:29 PM PDT 24
Finished May 30 03:40:39 PM PDT 24
Peak memory 233512 kb
Host smart-5dd3072d-73c1-4be1-bea7-967bc22efe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258511998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1258511998
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1662235382
Short name T930
Test name
Test status
Simulation time 24301433 ps
CPU time 0.7 seconds
Started May 30 03:40:39 PM PDT 24
Finished May 30 03:40:43 PM PDT 24
Peak memory 204840 kb
Host smart-c42a6f91-855f-4aff-9a8b-dc0e617f00a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662235382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1662235382
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.57572642
Short name T78
Test name
Test status
Simulation time 573729758 ps
CPU time 5.91 seconds
Started May 30 03:40:33 PM PDT 24
Finished May 30 03:40:42 PM PDT 24
Peak memory 218532 kb
Host smart-bbbccae0-1330-4895-8cca-614129c80ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57572642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.57572642
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4023507339
Short name T334
Test name
Test status
Simulation time 72341338 ps
CPU time 0.82 seconds
Started May 30 03:40:28 PM PDT 24
Finished May 30 03:40:32 PM PDT 24
Peak memory 206368 kb
Host smart-a03f7341-f8db-4b72-84db-455d3041daa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023507339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4023507339
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.85003624
Short name T374
Test name
Test status
Simulation time 280153030 ps
CPU time 0.93 seconds
Started May 30 03:40:37 PM PDT 24
Finished May 30 03:40:40 PM PDT 24
Peak memory 215904 kb
Host smart-97a6def0-9943-4de6-b1b0-a5ebe72989ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85003624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.85003624
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.548609632
Short name T959
Test name
Test status
Simulation time 4552910368 ps
CPU time 68.07 seconds
Started May 30 03:40:39 PM PDT 24
Finished May 30 03:41:50 PM PDT 24
Peak memory 252660 kb
Host smart-9f98ebce-9e20-4da5-a846-0a133b29acaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548609632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.548609632
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1852952994
Short name T601
Test name
Test status
Simulation time 1718814335 ps
CPU time 15.73 seconds
Started May 30 03:40:33 PM PDT 24
Finished May 30 03:40:51 PM PDT 24
Peak memory 232608 kb
Host smart-c0d6bb13-7f62-42d6-80f4-565ca815adf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852952994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1852952994
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.369628959
Short name T401
Test name
Test status
Simulation time 342476019 ps
CPU time 2.41 seconds
Started May 30 03:40:34 PM PDT 24
Finished May 30 03:40:39 PM PDT 24
Peak memory 232616 kb
Host smart-10bb2a34-3324-40cd-be51-f0bbfc91b7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369628959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.369628959
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1239153128
Short name T243
Test name
Test status
Simulation time 2086071740 ps
CPU time 15.01 seconds
Started May 30 03:40:32 PM PDT 24
Finished May 30 03:40:49 PM PDT 24
Peak memory 237508 kb
Host smart-fd370cec-ae16-4f5c-933d-24cf6a72e18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239153128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1239153128
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.365708466
Short name T952
Test name
Test status
Simulation time 3465586574 ps
CPU time 8.07 seconds
Started May 30 03:40:33 PM PDT 24
Finished May 30 03:40:43 PM PDT 24
Peak memory 218540 kb
Host smart-bc0a33bd-b321-4ba7-a41e-5a11b674fb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365708466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.365708466
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3178329054
Short name T417
Test name
Test status
Simulation time 9044554375 ps
CPU time 13.73 seconds
Started May 30 03:40:29 PM PDT 24
Finished May 30 03:40:46 PM PDT 24
Peak memory 233504 kb
Host smart-da2dd305-1cdd-409d-a085-6005a727c36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178329054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3178329054
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.128662657
Short name T746
Test name
Test status
Simulation time 150714398 ps
CPU time 3.88 seconds
Started May 30 03:40:36 PM PDT 24
Finished May 30 03:40:42 PM PDT 24
Peak memory 222776 kb
Host smart-47e8f639-15d3-45b5-974b-c7b30c3c5407
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=128662657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.128662657
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3912363701
Short name T10
Test name
Test status
Simulation time 8655230040 ps
CPU time 86.93 seconds
Started May 30 03:40:42 PM PDT 24
Finished May 30 03:42:12 PM PDT 24
Peak memory 250320 kb
Host smart-ad0e2d31-939c-422c-979f-8b59be2fcf62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912363701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3912363701
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4126390253
Short name T308
Test name
Test status
Simulation time 565587796 ps
CPU time 4.05 seconds
Started May 30 03:40:33 PM PDT 24
Finished May 30 03:40:40 PM PDT 24
Peak memory 217164 kb
Host smart-ce16940e-f7bc-4008-8676-1ef0d956fe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126390253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4126390253
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2071320879
Short name T388
Test name
Test status
Simulation time 1317041648 ps
CPU time 7.6 seconds
Started May 30 03:40:34 PM PDT 24
Finished May 30 03:40:43 PM PDT 24
Peak memory 216112 kb
Host smart-6e9a6984-be10-430d-9bf5-185965aa5677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071320879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2071320879
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.82330324
Short name T840
Test name
Test status
Simulation time 101782986 ps
CPU time 2.14 seconds
Started May 30 03:40:33 PM PDT 24
Finished May 30 03:40:38 PM PDT 24
Peak memory 216184 kb
Host smart-7d4ce687-3e31-4928-8852-aac756484497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82330324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.82330324
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2154957110
Short name T743
Test name
Test status
Simulation time 84831196 ps
CPU time 0.74 seconds
Started May 30 03:40:31 PM PDT 24
Finished May 30 03:40:34 PM PDT 24
Peak memory 205624 kb
Host smart-d60e2af0-72bc-4879-8527-aa1a154dfb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154957110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2154957110
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.759001713
Short name T895
Test name
Test status
Simulation time 941457387 ps
CPU time 7.63 seconds
Started May 30 03:40:31 PM PDT 24
Finished May 30 03:40:41 PM PDT 24
Peak memory 235088 kb
Host smart-0e50ded6-b8cb-4f91-bb34-21fb95cf98fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759001713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.759001713
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3094663340
Short name T920
Test name
Test status
Simulation time 33884756 ps
CPU time 0.7 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:40:44 PM PDT 24
Peak memory 205720 kb
Host smart-4b38516e-0842-43ff-b4a5-750024eadfa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094663340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3094663340
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4128739880
Short name T922
Test name
Test status
Simulation time 497568882 ps
CPU time 7.98 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:40:51 PM PDT 24
Peak memory 235324 kb
Host smart-ec1c8f17-5644-490b-b278-6a7fd53eef69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128739880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4128739880
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1004298944
Short name T16
Test name
Test status
Simulation time 14981716 ps
CPU time 0.8 seconds
Started May 30 03:40:38 PM PDT 24
Finished May 30 03:40:42 PM PDT 24
Peak memory 206368 kb
Host smart-050dd74c-7e94-4f8e-acae-46eca2d2ea61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004298944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1004298944
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3704157732
Short name T900
Test name
Test status
Simulation time 49467894560 ps
CPU time 115.22 seconds
Started May 30 03:40:41 PM PDT 24
Finished May 30 03:42:40 PM PDT 24
Peak memory 251128 kb
Host smart-6d033d64-8a0d-4b62-87c8-67fd296af871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704157732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3704157732
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3974009760
Short name T23
Test name
Test status
Simulation time 11811649299 ps
CPU time 64.14 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:41:48 PM PDT 24
Peak memory 252332 kb
Host smart-0a4f913d-8644-46fe-9d14-6aa90d5e56ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974009760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3974009760
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2975470372
Short name T687
Test name
Test status
Simulation time 45957992382 ps
CPU time 309.65 seconds
Started May 30 03:40:39 PM PDT 24
Finished May 30 03:45:52 PM PDT 24
Peak memory 252196 kb
Host smart-3851f56d-bf6f-4b42-9c9f-b0a41e2846f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975470372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2975470372
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4009336241
Short name T217
Test name
Test status
Simulation time 807207699 ps
CPU time 10.89 seconds
Started May 30 03:40:39 PM PDT 24
Finished May 30 03:40:53 PM PDT 24
Peak memory 224364 kb
Host smart-3b67095a-fa85-4954-988b-e876e0803c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009336241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4009336241
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1579095364
Short name T489
Test name
Test status
Simulation time 3124952244 ps
CPU time 6.85 seconds
Started May 30 03:40:39 PM PDT 24
Finished May 30 03:40:49 PM PDT 24
Peak memory 217912 kb
Host smart-93921777-429b-4565-86ff-906137558183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579095364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1579095364
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2718953542
Short name T79
Test name
Test status
Simulation time 6864474130 ps
CPU time 20.05 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:41:04 PM PDT 24
Peak memory 240200 kb
Host smart-3555f729-e429-4bb2-91d9-7247a0fe1f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718953542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2718953542
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2477677854
Short name T817
Test name
Test status
Simulation time 22161811027 ps
CPU time 29.09 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:41:13 PM PDT 24
Peak memory 217776 kb
Host smart-3645f229-672a-432d-a65d-6d3eefc72c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477677854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2477677854
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.114579840
Short name T689
Test name
Test status
Simulation time 4336905542 ps
CPU time 11.58 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:40:55 PM PDT 24
Peak memory 233592 kb
Host smart-d545f06e-04e6-4b65-8bab-e80b074607f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114579840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.114579840
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2880555681
Short name T598
Test name
Test status
Simulation time 368980426 ps
CPU time 5.92 seconds
Started May 30 03:40:43 PM PDT 24
Finished May 30 03:40:51 PM PDT 24
Peak memory 218712 kb
Host smart-07d54b62-83ca-4aa5-8aa8-7700abac33a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2880555681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2880555681
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.36951702
Short name T144
Test name
Test status
Simulation time 20619350763 ps
CPU time 185.71 seconds
Started May 30 03:40:42 PM PDT 24
Finished May 30 03:43:51 PM PDT 24
Peak memory 250844 kb
Host smart-9f6cf270-6a8f-49ac-8dd0-558a76ca5e76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36951702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress
_all.36951702
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3342223431
Short name T291
Test name
Test status
Simulation time 4035851092 ps
CPU time 12.05 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:40:56 PM PDT 24
Peak memory 216352 kb
Host smart-fd69d21c-3367-449e-b892-1865f450b06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342223431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3342223431
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1243281104
Short name T695
Test name
Test status
Simulation time 1025044953 ps
CPU time 7.18 seconds
Started May 30 03:40:37 PM PDT 24
Finished May 30 03:40:47 PM PDT 24
Peak memory 216124 kb
Host smart-1d30e3f7-a380-4b0b-abbf-3c38578c92a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243281104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1243281104
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.658462946
Short name T297
Test name
Test status
Simulation time 158411747 ps
CPU time 1.93 seconds
Started May 30 03:40:42 PM PDT 24
Finished May 30 03:40:47 PM PDT 24
Peak memory 216180 kb
Host smart-b697e8fd-dc22-4710-b73d-ae2880bbfbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658462946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.658462946
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1218446033
Short name T77
Test name
Test status
Simulation time 86941757 ps
CPU time 0.96 seconds
Started May 30 03:40:41 PM PDT 24
Finished May 30 03:40:45 PM PDT 24
Peak memory 205672 kb
Host smart-de5b30bc-4cee-462f-9ba0-6c2617304c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218446033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1218446033
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1587291777
Short name T951
Test name
Test status
Simulation time 12004631470 ps
CPU time 35.19 seconds
Started May 30 03:40:41 PM PDT 24
Finished May 30 03:41:19 PM PDT 24
Peak memory 230008 kb
Host smart-286a4264-5b56-41cc-9671-582026300e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587291777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1587291777
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1488281490
Short name T879
Test name
Test status
Simulation time 47075295 ps
CPU time 0.72 seconds
Started May 30 03:40:41 PM PDT 24
Finished May 30 03:40:45 PM PDT 24
Peak memory 205688 kb
Host smart-e6619480-8ecc-453a-8328-9637ba6d5784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488281490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1488281490
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.897032819
Short name T713
Test name
Test status
Simulation time 175102379 ps
CPU time 2.76 seconds
Started May 30 03:40:38 PM PDT 24
Finished May 30 03:40:44 PM PDT 24
Peak memory 233332 kb
Host smart-b863c7e9-b43e-4c7b-9a6d-4a8264e19755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897032819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.897032819
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1136361328
Short name T51
Test name
Test status
Simulation time 48357728 ps
CPU time 0.79 seconds
Started May 30 03:40:41 PM PDT 24
Finished May 30 03:40:45 PM PDT 24
Peak memory 206376 kb
Host smart-c13bcd96-7b95-4c38-b5fb-ce4085da17b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136361328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1136361328
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.106278874
Short name T113
Test name
Test status
Simulation time 8002189982 ps
CPU time 51.9 seconds
Started May 30 03:40:39 PM PDT 24
Finished May 30 03:41:34 PM PDT 24
Peak memory 237840 kb
Host smart-d3279aa6-a1b6-4a96-9546-20dd8db5e0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106278874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.106278874
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.874050242
Short name T458
Test name
Test status
Simulation time 42130623280 ps
CPU time 78.86 seconds
Started May 30 03:40:41 PM PDT 24
Finished May 30 03:42:03 PM PDT 24
Peak memory 224496 kb
Host smart-bc2b7492-ef05-4b40-8371-daa008be9d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874050242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.874050242
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3645733506
Short name T216
Test name
Test status
Simulation time 3618010391 ps
CPU time 33.86 seconds
Started May 30 03:40:41 PM PDT 24
Finished May 30 03:41:18 PM PDT 24
Peak memory 240872 kb
Host smart-2e72438a-0c36-4a81-b056-38c380e7a827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645733506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3645733506
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.428382717
Short name T519
Test name
Test status
Simulation time 2125690958 ps
CPU time 6.94 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:40:50 PM PDT 24
Peak memory 240752 kb
Host smart-b85696aa-15ff-453b-8ab8-23c02ccc4b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428382717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.428382717
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1303346774
Short name T50
Test name
Test status
Simulation time 634884288 ps
CPU time 8.7 seconds
Started May 30 03:40:41 PM PDT 24
Finished May 30 03:40:53 PM PDT 24
Peak memory 218624 kb
Host smart-2edf9d1b-fd56-4ce5-b5e1-2cb5766a253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303346774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1303346774
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1384186880
Short name T488
Test name
Test status
Simulation time 6468340477 ps
CPU time 69.96 seconds
Started May 30 03:40:37 PM PDT 24
Finished May 30 03:41:48 PM PDT 24
Peak memory 228140 kb
Host smart-7de93288-7d5f-4b39-a1b5-61dff19c351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384186880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1384186880
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2844362023
Short name T921
Test name
Test status
Simulation time 162371581 ps
CPU time 2.27 seconds
Started May 30 03:40:38 PM PDT 24
Finished May 30 03:40:43 PM PDT 24
Peak memory 216480 kb
Host smart-42b8807a-58ea-417d-b270-299cff45f23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844362023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2844362023
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3503682530
Short name T454
Test name
Test status
Simulation time 126737247 ps
CPU time 3.15 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:40:46 PM PDT 24
Peak memory 232652 kb
Host smart-263e1644-a0e5-4bc6-886b-0ea727ed55d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503682530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3503682530
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.983511979
Short name T531
Test name
Test status
Simulation time 6338841435 ps
CPU time 12.77 seconds
Started May 30 03:40:46 PM PDT 24
Finished May 30 03:41:00 PM PDT 24
Peak memory 222772 kb
Host smart-784bf290-5c49-4c85-a8e3-5815e290d53e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=983511979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.983511979
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2318911371
Short name T290
Test name
Test status
Simulation time 8846391516 ps
CPU time 47.81 seconds
Started May 30 03:40:39 PM PDT 24
Finished May 30 03:41:30 PM PDT 24
Peak memory 216280 kb
Host smart-71428b2a-3c73-4361-ade3-d380fbcfd7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318911371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2318911371
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1972295090
Short name T851
Test name
Test status
Simulation time 6020375749 ps
CPU time 14.51 seconds
Started May 30 03:40:41 PM PDT 24
Finished May 30 03:40:59 PM PDT 24
Peak memory 216184 kb
Host smart-d34a088c-ff3f-4fca-9c73-ea9ff89f80a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972295090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1972295090
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2096416362
Short name T339
Test name
Test status
Simulation time 87075167 ps
CPU time 1.35 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:40:44 PM PDT 24
Peak memory 216248 kb
Host smart-327c5b9f-2b22-4c6a-bf79-3eee57877ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096416362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2096416362
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.270320768
Short name T740
Test name
Test status
Simulation time 398093904 ps
CPU time 0.98 seconds
Started May 30 03:40:39 PM PDT 24
Finished May 30 03:40:43 PM PDT 24
Peak memory 206672 kb
Host smart-29c127d8-edd5-42ba-a2e7-938cb08759cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270320768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.270320768
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.416132588
Short name T579
Test name
Test status
Simulation time 2551168070 ps
CPU time 3.63 seconds
Started May 30 03:40:39 PM PDT 24
Finished May 30 03:40:46 PM PDT 24
Peak memory 219696 kb
Host smart-8bee63df-8cac-4966-8d7a-181ca2ff7dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416132588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.416132588
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3857821449
Short name T637
Test name
Test status
Simulation time 133619663 ps
CPU time 0.73 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:40:56 PM PDT 24
Peak memory 205428 kb
Host smart-667e7f63-5874-4c85-a211-6e6dcbb9d259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857821449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3857821449
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1917246932
Short name T422
Test name
Test status
Simulation time 1377350859 ps
CPU time 9.71 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:40:53 PM PDT 24
Peak memory 233468 kb
Host smart-b86ad9b3-db88-4389-a697-e211fa35def9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917246932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1917246932
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1231130869
Short name T463
Test name
Test status
Simulation time 25047798 ps
CPU time 0.79 seconds
Started May 30 03:40:42 PM PDT 24
Finished May 30 03:40:46 PM PDT 24
Peak memory 205756 kb
Host smart-b142dce9-39e2-4b77-aa5e-9545da0afda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231130869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1231130869
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.4129132166
Short name T118
Test name
Test status
Simulation time 56184424593 ps
CPU time 177.65 seconds
Started May 30 03:40:42 PM PDT 24
Finished May 30 03:43:43 PM PDT 24
Peak memory 254588 kb
Host smart-8c766545-8011-47f8-934a-80254c45db06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129132166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4129132166
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3472266784
Short name T273
Test name
Test status
Simulation time 7117300296 ps
CPU time 48.76 seconds
Started May 30 03:40:46 PM PDT 24
Finished May 30 03:41:36 PM PDT 24
Peak memory 224460 kb
Host smart-dd91701e-b0de-4ed5-b7b0-9beb478537dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472266784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3472266784
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2639996462
Short name T361
Test name
Test status
Simulation time 3877456581 ps
CPU time 21.05 seconds
Started May 30 03:40:50 PM PDT 24
Finished May 30 03:41:13 PM PDT 24
Peak memory 236692 kb
Host smart-9715fc7e-997a-4c61-acf0-bede009832c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639996462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2639996462
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3085748386
Short name T478
Test name
Test status
Simulation time 285204435 ps
CPU time 7.24 seconds
Started May 30 03:40:46 PM PDT 24
Finished May 30 03:40:55 PM PDT 24
Peak memory 232540 kb
Host smart-ac6244e0-2710-42e1-a9c8-8c3b675c1b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085748386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3085748386
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.294880393
Short name T558
Test name
Test status
Simulation time 380607494 ps
CPU time 7.91 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:40:51 PM PDT 24
Peak memory 218644 kb
Host smart-b40a8f06-15a7-43d6-8473-e885f757d2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294880393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.294880393
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.626209560
Short name T761
Test name
Test status
Simulation time 2473624150 ps
CPU time 10.37 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:40:54 PM PDT 24
Peak memory 233388 kb
Host smart-4c5d6cb7-367c-494b-be3c-e0eee93cef11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626209560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.626209560
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.4277076669
Short name T570
Test name
Test status
Simulation time 2027763691 ps
CPU time 3.3 seconds
Started May 30 03:40:39 PM PDT 24
Finished May 30 03:40:46 PM PDT 24
Peak memory 233588 kb
Host smart-3dc8dd9b-614c-4b47-bffb-315043e618bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277076669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.4277076669
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3651897287
Short name T228
Test name
Test status
Simulation time 830475226 ps
CPU time 4.44 seconds
Started May 30 03:40:38 PM PDT 24
Finished May 30 03:40:46 PM PDT 24
Peak memory 224524 kb
Host smart-82d5a296-d3c7-4efe-90e8-c5282aabfe3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651897287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3651897287
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.605959735
Short name T406
Test name
Test status
Simulation time 355426352 ps
CPU time 4.86 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:40:49 PM PDT 24
Peak memory 223040 kb
Host smart-a5d82eff-57e8-4a69-a638-4563bcc34671
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=605959735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.605959735
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1116592016
Short name T244
Test name
Test status
Simulation time 89327932025 ps
CPU time 193.95 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:44:09 PM PDT 24
Peak memory 224496 kb
Host smart-81154770-6f9a-4e29-ab31-be2a90bf5860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116592016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1116592016
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3437891063
Short name T394
Test name
Test status
Simulation time 5023256003 ps
CPU time 15.36 seconds
Started May 30 03:40:39 PM PDT 24
Finished May 30 03:40:58 PM PDT 24
Peak memory 216280 kb
Host smart-3334a66c-8c2d-4d92-af05-9231b2bd7d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437891063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3437891063
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3019586889
Short name T313
Test name
Test status
Simulation time 1558930668 ps
CPU time 3.77 seconds
Started May 30 03:40:40 PM PDT 24
Finished May 30 03:40:47 PM PDT 24
Peak memory 216072 kb
Host smart-68df913e-fb4a-4e6e-bd13-f7dbd7145f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019586889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3019586889
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3954143535
Short name T749
Test name
Test status
Simulation time 13266544 ps
CPU time 0.71 seconds
Started May 30 03:40:39 PM PDT 24
Finished May 30 03:40:43 PM PDT 24
Peak memory 205480 kb
Host smart-3d0d55b9-119e-4a5c-ba76-1cd12b95b2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954143535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3954143535
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.727454697
Short name T492
Test name
Test status
Simulation time 36896179 ps
CPU time 0.91 seconds
Started May 30 03:40:39 PM PDT 24
Finished May 30 03:40:44 PM PDT 24
Peak memory 205668 kb
Host smart-12dc452f-f0dc-4156-8319-62e6c235bc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727454697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.727454697
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.483752807
Short name T496
Test name
Test status
Simulation time 438423022 ps
CPU time 2.68 seconds
Started May 30 03:40:39 PM PDT 24
Finished May 30 03:40:45 PM PDT 24
Peak memory 232628 kb
Host smart-fff0b251-afe3-449a-a61a-4c60c9bc3f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483752807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.483752807
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3175450440
Short name T314
Test name
Test status
Simulation time 34589523 ps
CPU time 0.76 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:40:56 PM PDT 24
Peak memory 205412 kb
Host smart-840fcd9e-ab5a-4034-933c-564fd90653e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175450440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3175450440
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3726632235
Short name T820
Test name
Test status
Simulation time 357906181 ps
CPU time 6.36 seconds
Started May 30 03:40:50 PM PDT 24
Finished May 30 03:40:58 PM PDT 24
Peak memory 218824 kb
Host smart-84c19632-fe82-4440-abf6-56d4f84839cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726632235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3726632235
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1325434082
Short name T506
Test name
Test status
Simulation time 70189149 ps
CPU time 0.81 seconds
Started May 30 03:40:51 PM PDT 24
Finished May 30 03:40:53 PM PDT 24
Peak memory 206420 kb
Host smart-f68456aa-54a6-4b3b-92d0-dec36570b581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325434082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1325434082
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1402088203
Short name T668
Test name
Test status
Simulation time 2684109679 ps
CPU time 56.08 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:41:51 PM PDT 24
Peak memory 250968 kb
Host smart-cee8d1db-64a3-46f8-b105-cc1c659bef35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402088203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1402088203
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3635582421
Short name T33
Test name
Test status
Simulation time 10590444576 ps
CPU time 110.5 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:42:45 PM PDT 24
Peak memory 233740 kb
Host smart-0cec4bbf-fb0a-45e2-a4b6-81659eac0348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635582421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3635582421
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.154546004
Short name T588
Test name
Test status
Simulation time 764155955 ps
CPU time 16.79 seconds
Started May 30 03:40:49 PM PDT 24
Finished May 30 03:41:07 PM PDT 24
Peak memory 235372 kb
Host smart-1b674a90-4508-41ee-8d5b-6b3767032ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154546004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.154546004
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1441256255
Short name T368
Test name
Test status
Simulation time 4681965375 ps
CPU time 24.91 seconds
Started May 30 03:40:51 PM PDT 24
Finished May 30 03:41:18 PM PDT 24
Peak memory 252388 kb
Host smart-86cbde69-64bb-43cd-bd76-924d1a229d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441256255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1441256255
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3515037062
Short name T795
Test name
Test status
Simulation time 153315091 ps
CPU time 3.11 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:40:58 PM PDT 24
Peak memory 218368 kb
Host smart-58fcfb39-0ba6-417c-9132-74f6a5e52caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515037062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3515037062
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.699050673
Short name T700
Test name
Test status
Simulation time 6659752026 ps
CPU time 41.79 seconds
Started May 30 03:40:51 PM PDT 24
Finished May 30 03:41:35 PM PDT 24
Peak memory 234084 kb
Host smart-bdcbd55c-2e35-437c-9712-c8614b0a43c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699050673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.699050673
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3932932966
Short name T628
Test name
Test status
Simulation time 159923240 ps
CPU time 2.13 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:40:57 PM PDT 24
Peak memory 216000 kb
Host smart-79849c88-fa77-44e1-8dae-d43b4031b11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932932966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3932932966
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1090394913
Short name T834
Test name
Test status
Simulation time 917463487 ps
CPU time 3.96 seconds
Started May 30 03:40:54 PM PDT 24
Finished May 30 03:41:01 PM PDT 24
Peak memory 234056 kb
Host smart-79c52e0d-64ce-4c1e-901a-1aabae9d3983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090394913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1090394913
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.898780779
Short name T432
Test name
Test status
Simulation time 234781003 ps
CPU time 3.59 seconds
Started May 30 03:40:50 PM PDT 24
Finished May 30 03:40:55 PM PDT 24
Peak memory 222708 kb
Host smart-37a1fe53-ba15-405a-ab7a-0377ce401d9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=898780779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.898780779
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3255780101
Short name T369
Test name
Test status
Simulation time 216730223 ps
CPU time 1.07 seconds
Started May 30 03:40:53 PM PDT 24
Finished May 30 03:40:58 PM PDT 24
Peak memory 207000 kb
Host smart-bbe0752a-7eba-4607-8d90-d2768dee9d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255780101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3255780101
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4238687673
Short name T537
Test name
Test status
Simulation time 9712141605 ps
CPU time 14.36 seconds
Started May 30 03:40:50 PM PDT 24
Finished May 30 03:41:07 PM PDT 24
Peak memory 216296 kb
Host smart-e00b60d6-5c04-497e-a4bd-8cd664c414a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238687673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4238687673
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3695033707
Short name T302
Test name
Test status
Simulation time 2489989614 ps
CPU time 5.32 seconds
Started May 30 03:40:50 PM PDT 24
Finished May 30 03:40:57 PM PDT 24
Peak memory 216176 kb
Host smart-7d3f4e99-41ba-4360-b288-797734b41b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695033707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3695033707
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1433366942
Short name T753
Test name
Test status
Simulation time 10363415 ps
CPU time 0.7 seconds
Started May 30 03:40:51 PM PDT 24
Finished May 30 03:40:55 PM PDT 24
Peak memory 205432 kb
Host smart-ca9b389b-dc58-4be9-814e-d2e3dfd4992c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433366942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1433366942
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3619837419
Short name T717
Test name
Test status
Simulation time 88877188 ps
CPU time 0.83 seconds
Started May 30 03:40:50 PM PDT 24
Finished May 30 03:40:53 PM PDT 24
Peak memory 205648 kb
Host smart-848ff12e-fabc-4f4f-af67-983b153dec86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619837419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3619837419
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3680949029
Short name T233
Test name
Test status
Simulation time 1564596648 ps
CPU time 5.73 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:41:01 PM PDT 24
Peak memory 217624 kb
Host smart-7c243320-24a7-4231-a349-33235032a554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680949029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3680949029
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3523701109
Short name T305
Test name
Test status
Simulation time 28064895 ps
CPU time 0.71 seconds
Started May 30 03:39:23 PM PDT 24
Finished May 30 03:39:27 PM PDT 24
Peak memory 205796 kb
Host smart-b27d5a5f-d2f5-479f-bea5-4beb3fcb6bea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523701109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
523701109
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1248342528
Short name T572
Test name
Test status
Simulation time 1670192968 ps
CPU time 20.66 seconds
Started May 30 03:39:33 PM PDT 24
Finished May 30 03:39:56 PM PDT 24
Peak memory 219764 kb
Host smart-d14d3a02-93ff-4b35-9f80-f47604d9dbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248342528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1248342528
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2628784593
Short name T803
Test name
Test status
Simulation time 19328234 ps
CPU time 0.78 seconds
Started May 30 03:39:20 PM PDT 24
Finished May 30 03:39:24 PM PDT 24
Peak memory 205376 kb
Host smart-29ad1e06-b4f7-4723-b9e5-17d47152a16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628784593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2628784593
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.657368572
Short name T679
Test name
Test status
Simulation time 14607937459 ps
CPU time 88.28 seconds
Started May 30 03:39:27 PM PDT 24
Finished May 30 03:40:57 PM PDT 24
Peak memory 249084 kb
Host smart-036047b5-3290-4012-83ad-e70ac193cd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657368572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.657368572
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2944468456
Short name T474
Test name
Test status
Simulation time 8707996867 ps
CPU time 77.28 seconds
Started May 30 03:39:33 PM PDT 24
Finished May 30 03:40:53 PM PDT 24
Peak memory 224524 kb
Host smart-1b8a8aed-9fdc-4859-ad2e-796423d95bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944468456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2944468456
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3078402084
Short name T428
Test name
Test status
Simulation time 6378197529 ps
CPU time 39.81 seconds
Started May 30 03:39:32 PM PDT 24
Finished May 30 03:40:14 PM PDT 24
Peak memory 249000 kb
Host smart-97bcb273-996a-43d2-bbe0-188f80141b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078402084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3078402084
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.399504455
Short name T953
Test name
Test status
Simulation time 648131622 ps
CPU time 15.4 seconds
Started May 30 03:39:30 PM PDT 24
Finished May 30 03:39:46 PM PDT 24
Peak memory 240352 kb
Host smart-f21aeac1-6c0d-45fc-9e08-3f2df2f4a1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399504455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.399504455
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2620850726
Short name T774
Test name
Test status
Simulation time 413542397 ps
CPU time 6.7 seconds
Started May 30 03:39:27 PM PDT 24
Finished May 30 03:39:35 PM PDT 24
Peak memory 233580 kb
Host smart-ed28149e-6386-41ce-b3e9-0f7b6ae795f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620850726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2620850726
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.411068248
Short name T520
Test name
Test status
Simulation time 794547063 ps
CPU time 11.12 seconds
Started May 30 03:39:25 PM PDT 24
Finished May 30 03:39:39 PM PDT 24
Peak memory 233752 kb
Host smart-8ab0446d-ca90-413f-8e40-569147c09920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411068248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.411068248
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3875530069
Short name T512
Test name
Test status
Simulation time 1168731458 ps
CPU time 5.42 seconds
Started May 30 03:39:28 PM PDT 24
Finished May 30 03:39:34 PM PDT 24
Peak memory 233720 kb
Host smart-23bab9d4-92bc-46b1-8871-b8f37418bb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875530069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3875530069
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.989408529
Short name T898
Test name
Test status
Simulation time 44307964465 ps
CPU time 30.12 seconds
Started May 30 03:39:20 PM PDT 24
Finished May 30 03:39:53 PM PDT 24
Peak memory 233472 kb
Host smart-c46463bd-fb96-406a-a881-7d45a0d5289f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989408529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.989408529
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2033956749
Short name T686
Test name
Test status
Simulation time 3176865467 ps
CPU time 9.65 seconds
Started May 30 03:39:27 PM PDT 24
Finished May 30 03:39:38 PM PDT 24
Peak memory 222816 kb
Host smart-56ded9ab-cd35-4cc2-bbad-e87a18f6f719
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2033956749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2033956749
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1581151794
Short name T66
Test name
Test status
Simulation time 86124495 ps
CPU time 1.25 seconds
Started May 30 03:39:25 PM PDT 24
Finished May 30 03:39:29 PM PDT 24
Peak memory 235104 kb
Host smart-5ff2db49-d12d-43fa-a5bb-a7ca87f08780
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581151794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1581151794
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1976568800
Short name T112
Test name
Test status
Simulation time 20093439790 ps
CPU time 81.52 seconds
Started May 30 03:39:22 PM PDT 24
Finished May 30 03:40:47 PM PDT 24
Peak memory 253004 kb
Host smart-28fc4bd3-954d-4cbf-acdd-b05ad9e9edb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976568800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1976568800
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2853729525
Short name T404
Test name
Test status
Simulation time 808550303 ps
CPU time 13.52 seconds
Started May 30 03:39:20 PM PDT 24
Finished May 30 03:39:36 PM PDT 24
Peak memory 216444 kb
Host smart-6edf3bd4-e2ce-4c20-b86b-aa8b3db8ed45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853729525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2853729525
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4142723008
Short name T722
Test name
Test status
Simulation time 13336284 ps
CPU time 0.72 seconds
Started May 30 03:39:20 PM PDT 24
Finished May 30 03:39:24 PM PDT 24
Peak memory 205524 kb
Host smart-4270df01-e25d-4535-add2-f5d6d245644c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142723008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4142723008
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3934573378
Short name T500
Test name
Test status
Simulation time 318570952 ps
CPU time 1.36 seconds
Started May 30 03:39:18 PM PDT 24
Finished May 30 03:39:22 PM PDT 24
Peak memory 207800 kb
Host smart-415699e5-61e2-41fd-93f6-21ededb75c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934573378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3934573378
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.955704850
Short name T672
Test name
Test status
Simulation time 26022509 ps
CPU time 0.81 seconds
Started May 30 03:39:22 PM PDT 24
Finished May 30 03:39:26 PM PDT 24
Peak memory 205652 kb
Host smart-cfa9f752-d009-47ac-8580-3bd48adcc26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955704850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.955704850
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.953326556
Short name T797
Test name
Test status
Simulation time 809170819 ps
CPU time 5.46 seconds
Started May 30 03:39:32 PM PDT 24
Finished May 30 03:39:40 PM PDT 24
Peak memory 232612 kb
Host smart-cfe7a83d-c498-499e-904e-4a167632768b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953326556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.953326556
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2349547121
Short name T307
Test name
Test status
Simulation time 12708582 ps
CPU time 0.71 seconds
Started May 30 03:40:53 PM PDT 24
Finished May 30 03:40:57 PM PDT 24
Peak memory 205420 kb
Host smart-867d94e7-b423-48ac-82b2-1964f9bb4650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349547121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2349547121
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.694610568
Short name T707
Test name
Test status
Simulation time 334440242 ps
CPU time 4.62 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:40:59 PM PDT 24
Peak memory 218516 kb
Host smart-d2457871-5a7a-4dcb-99b8-cd2c55ec5e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694610568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.694610568
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1336768370
Short name T603
Test name
Test status
Simulation time 15962220 ps
CPU time 0.76 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:40:56 PM PDT 24
Peak memory 205384 kb
Host smart-547adef8-7c18-4111-a11b-e8a634818f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336768370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1336768370
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.4021030549
Short name T171
Test name
Test status
Simulation time 10564471484 ps
CPU time 86.19 seconds
Started May 30 03:40:53 PM PDT 24
Finished May 30 03:42:23 PM PDT 24
Peak memory 249548 kb
Host smart-4613452b-ca10-4b43-8857-f40ab67fb05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021030549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.4021030549
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.4292721786
Short name T262
Test name
Test status
Simulation time 32742293980 ps
CPU time 321.84 seconds
Started May 30 03:40:50 PM PDT 24
Finished May 30 03:46:13 PM PDT 24
Peak memory 270756 kb
Host smart-d5651dfe-ea3a-4f35-8afe-f2344e9b74f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292721786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4292721786
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.100823773
Short name T616
Test name
Test status
Simulation time 13616380327 ps
CPU time 183.68 seconds
Started May 30 03:40:51 PM PDT 24
Finished May 30 03:43:56 PM PDT 24
Peak memory 261640 kb
Host smart-e2c528b8-65c7-4f56-a3a0-4c6bb71ffd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100823773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.100823773
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2986308803
Short name T694
Test name
Test status
Simulation time 7590975050 ps
CPU time 24.37 seconds
Started May 30 03:40:53 PM PDT 24
Finished May 30 03:41:20 PM PDT 24
Peak memory 234736 kb
Host smart-212eda9f-4a3e-4ec9-ba4a-0450d8456828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986308803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2986308803
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.306995918
Short name T555
Test name
Test status
Simulation time 25067970501 ps
CPU time 11.95 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:41:06 PM PDT 24
Peak memory 218588 kb
Host smart-baa2c2a4-d928-4c21-924b-a0c8c56eabc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306995918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.306995918
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2089624929
Short name T48
Test name
Test status
Simulation time 57614663 ps
CPU time 2.38 seconds
Started May 30 03:40:51 PM PDT 24
Finished May 30 03:40:55 PM PDT 24
Peak memory 232628 kb
Host smart-7bb5eb04-717c-4646-ad78-b1ce9ab3df45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089624929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2089624929
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1601593419
Short name T242
Test name
Test status
Simulation time 2022389806 ps
CPU time 11.27 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:41:06 PM PDT 24
Peak memory 227448 kb
Host smart-83877983-8b87-43c4-8039-acc40d562169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601593419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1601593419
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.698785893
Short name T455
Test name
Test status
Simulation time 426943310 ps
CPU time 6.88 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:41:02 PM PDT 24
Peak memory 219008 kb
Host smart-e0a362be-376d-4a6c-aa35-0d5c08db6dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698785893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.698785893
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.859803865
Short name T444
Test name
Test status
Simulation time 3704092598 ps
CPU time 23.06 seconds
Started May 30 03:40:51 PM PDT 24
Finished May 30 03:41:16 PM PDT 24
Peak memory 219192 kb
Host smart-38ccf362-a16e-46aa-b1be-d9017abab169
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=859803865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.859803865
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.766212088
Short name T942
Test name
Test status
Simulation time 1183796701 ps
CPU time 20.08 seconds
Started May 30 03:40:51 PM PDT 24
Finished May 30 03:41:13 PM PDT 24
Peak memory 219828 kb
Host smart-ede657ab-ef81-4736-ab7e-252b8d83a63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766212088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.766212088
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2966387119
Short name T420
Test name
Test status
Simulation time 2443810376 ps
CPU time 5.82 seconds
Started May 30 03:40:51 PM PDT 24
Finished May 30 03:40:59 PM PDT 24
Peak memory 216088 kb
Host smart-35f1aee2-c638-4a33-b12c-28ccf6bd08d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966387119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2966387119
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2172631910
Short name T805
Test name
Test status
Simulation time 913424843 ps
CPU time 6.42 seconds
Started May 30 03:40:50 PM PDT 24
Finished May 30 03:40:57 PM PDT 24
Peak memory 216196 kb
Host smart-c489c7ff-0423-4e65-9a26-f507c15e964c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172631910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2172631910
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2397212323
Short name T407
Test name
Test status
Simulation time 40852843 ps
CPU time 0.79 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:40:55 PM PDT 24
Peak memory 205632 kb
Host smart-42f187ce-c72a-4208-8f3f-be847029c2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397212323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2397212323
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2061592987
Short name T208
Test name
Test status
Simulation time 421681817 ps
CPU time 7.56 seconds
Started May 30 03:40:51 PM PDT 24
Finished May 30 03:41:01 PM PDT 24
Peak memory 238548 kb
Host smart-342b1551-81aa-4ce8-bf42-cd04a80cc79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061592987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2061592987
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3394638037
Short name T535
Test name
Test status
Simulation time 55167928 ps
CPU time 0.71 seconds
Started May 30 03:41:07 PM PDT 24
Finished May 30 03:41:10 PM PDT 24
Peak memory 205728 kb
Host smart-952c1284-1f69-439b-8cb4-fa160af4d34d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394638037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3394638037
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.754866028
Short name T345
Test name
Test status
Simulation time 984067833 ps
CPU time 7.02 seconds
Started May 30 03:40:51 PM PDT 24
Finished May 30 03:41:00 PM PDT 24
Peak memory 236920 kb
Host smart-e7b1bd0c-ee28-4264-b8a3-55ffe8bae011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754866028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.754866028
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.4278376204
Short name T443
Test name
Test status
Simulation time 15206350 ps
CPU time 0.73 seconds
Started May 30 03:40:53 PM PDT 24
Finished May 30 03:40:57 PM PDT 24
Peak memory 206756 kb
Host smart-f02c5b19-a2c4-4cc2-ade3-d5220ca7c29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278376204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.4278376204
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3158386596
Short name T207
Test name
Test status
Simulation time 2878530993 ps
CPU time 56.67 seconds
Started May 30 03:41:01 PM PDT 24
Finished May 30 03:42:00 PM PDT 24
Peak memory 239276 kb
Host smart-c4d5ca19-cf6b-4d5f-a208-27acc5c166cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158386596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3158386596
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3862655816
Short name T658
Test name
Test status
Simulation time 40440796992 ps
CPU time 351.83 seconds
Started May 30 03:41:02 PM PDT 24
Finished May 30 03:46:56 PM PDT 24
Peak memory 257356 kb
Host smart-1ee030ac-a07e-47cb-aba0-a85c56ace01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862655816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3862655816
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2153878056
Short name T341
Test name
Test status
Simulation time 85220472 ps
CPU time 3.7 seconds
Started May 30 03:41:02 PM PDT 24
Finished May 30 03:41:08 PM PDT 24
Peak memory 232284 kb
Host smart-e9fca5a9-352c-4f8b-97f7-ec7eed808e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153878056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2153878056
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.830898828
Short name T167
Test name
Test status
Simulation time 1209851665 ps
CPU time 10.25 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:41:05 PM PDT 24
Peak memory 218308 kb
Host smart-23b75d26-2876-4c3a-be05-ef03dd49b6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830898828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.830898828
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1444709520
Short name T559
Test name
Test status
Simulation time 7719835315 ps
CPU time 17.27 seconds
Started May 30 03:40:53 PM PDT 24
Finished May 30 03:41:14 PM PDT 24
Peak memory 233688 kb
Host smart-53b02ded-22b8-4f4c-a5a0-2a5a4d675052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444709520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1444709520
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3907021860
Short name T120
Test name
Test status
Simulation time 713288548 ps
CPU time 7.39 seconds
Started May 30 03:40:52 PM PDT 24
Finished May 30 03:41:03 PM PDT 24
Peak memory 240724 kb
Host smart-80aee0b1-1984-44b2-8f02-dcba5fd5ee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907021860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3907021860
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2388006861
Short name T333
Test name
Test status
Simulation time 9441324452 ps
CPU time 7.79 seconds
Started May 30 03:40:53 PM PDT 24
Finished May 30 03:41:04 PM PDT 24
Peak memory 220684 kb
Host smart-76a8ae83-a567-4e65-b09f-6c8250c9653a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388006861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2388006861
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.916631764
Short name T651
Test name
Test status
Simulation time 1070959359 ps
CPU time 12.8 seconds
Started May 30 03:41:03 PM PDT 24
Finished May 30 03:41:19 PM PDT 24
Peak memory 219264 kb
Host smart-4ba41b7e-a24f-4290-8387-8843fcfb784d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=916631764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.916631764
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3307756805
Short name T299
Test name
Test status
Simulation time 384309150702 ps
CPU time 169.07 seconds
Started May 30 03:41:03 PM PDT 24
Finished May 30 03:43:55 PM PDT 24
Peak memory 256920 kb
Host smart-6c1c1705-6638-457f-bd5c-f922a4bb7637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307756805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3307756805
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2934765922
Short name T762
Test name
Test status
Simulation time 2319765417 ps
CPU time 16.52 seconds
Started May 30 03:40:51 PM PDT 24
Finished May 30 03:41:10 PM PDT 24
Peak memory 219312 kb
Host smart-add670cc-b8d0-41f0-a53a-c093582c7759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934765922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2934765922
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3922444492
Short name T453
Test name
Test status
Simulation time 7654291067 ps
CPU time 22.92 seconds
Started May 30 03:40:53 PM PDT 24
Finished May 30 03:41:19 PM PDT 24
Peak memory 216108 kb
Host smart-211b9225-0d73-47f7-b837-3716fc3bd2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922444492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3922444492
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.473884909
Short name T883
Test name
Test status
Simulation time 35226224 ps
CPU time 0.87 seconds
Started May 30 03:40:51 PM PDT 24
Finished May 30 03:40:54 PM PDT 24
Peak memory 206760 kb
Host smart-de8351ff-8392-4d3f-b25b-dced221f17e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473884909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.473884909
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.4073114509
Short name T754
Test name
Test status
Simulation time 11793789 ps
CPU time 0.69 seconds
Started May 30 03:40:53 PM PDT 24
Finished May 30 03:40:57 PM PDT 24
Peak memory 205444 kb
Host smart-ac0881e5-1634-41a5-b022-c89638efe330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073114509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4073114509
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.149271896
Short name T823
Test name
Test status
Simulation time 861822198 ps
CPU time 2.35 seconds
Started May 30 03:40:53 PM PDT 24
Finished May 30 03:40:59 PM PDT 24
Peak memory 207824 kb
Host smart-49f627ec-da0d-43d3-b226-a1f386642326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149271896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.149271896
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1834513319
Short name T599
Test name
Test status
Simulation time 16011729 ps
CPU time 0.73 seconds
Started May 30 03:41:05 PM PDT 24
Finished May 30 03:41:08 PM PDT 24
Peak memory 204824 kb
Host smart-916c81da-a445-4e95-a9fd-996643292fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834513319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1834513319
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.356643719
Short name T918
Test name
Test status
Simulation time 5772019032 ps
CPU time 20.74 seconds
Started May 30 03:41:04 PM PDT 24
Finished May 30 03:41:27 PM PDT 24
Peak memory 219964 kb
Host smart-8e0a81cb-7c01-4f3b-8ba7-7fb959a178b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356643719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.356643719
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1091927232
Short name T812
Test name
Test status
Simulation time 38992351 ps
CPU time 0.86 seconds
Started May 30 03:41:02 PM PDT 24
Finished May 30 03:41:05 PM PDT 24
Peak memory 206736 kb
Host smart-5c3b7b61-fb74-4900-8a0e-c1248884f820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091927232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1091927232
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.422144099
Short name T912
Test name
Test status
Simulation time 11661586300 ps
CPU time 64.7 seconds
Started May 30 03:41:04 PM PDT 24
Finished May 30 03:42:11 PM PDT 24
Peak memory 240000 kb
Host smart-fd74cc3c-be2d-4978-bafd-fe8e5e395584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422144099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.422144099
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2426591658
Short name T235
Test name
Test status
Simulation time 24330532099 ps
CPU time 268.77 seconds
Started May 30 03:41:03 PM PDT 24
Finished May 30 03:45:35 PM PDT 24
Peak memory 253908 kb
Host smart-d66ba09e-d607-4d56-b79a-a0e87b6306cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426591658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2426591658
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.442581544
Short name T583
Test name
Test status
Simulation time 2988065815 ps
CPU time 16.9 seconds
Started May 30 03:41:03 PM PDT 24
Finished May 30 03:41:23 PM PDT 24
Peak memory 232588 kb
Host smart-83b42e4b-3128-44b3-a30b-d3613134e603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442581544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.442581544
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.129159764
Short name T49
Test name
Test status
Simulation time 37286473 ps
CPU time 2.78 seconds
Started May 30 03:41:04 PM PDT 24
Finished May 30 03:41:09 PM PDT 24
Peak memory 232552 kb
Host smart-f1cd6916-0ca2-49bf-a7f0-276371b6f24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129159764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.129159764
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.305637821
Short name T429
Test name
Test status
Simulation time 1887501508 ps
CPU time 24.31 seconds
Started May 30 03:41:06 PM PDT 24
Finished May 30 03:41:33 PM PDT 24
Peak memory 233720 kb
Host smart-4f2f6066-63bd-40c0-8968-49085ad94e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305637821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.305637821
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3090390038
Short name T825
Test name
Test status
Simulation time 40725350549 ps
CPU time 29.49 seconds
Started May 30 03:41:05 PM PDT 24
Finished May 30 03:41:36 PM PDT 24
Peak memory 232632 kb
Host smart-1b3f57fa-44fc-4fc7-93c8-961b0ca11b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090390038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3090390038
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3632430261
Short name T197
Test name
Test status
Simulation time 6468084779 ps
CPU time 17.81 seconds
Started May 30 03:41:03 PM PDT 24
Finished May 30 03:41:23 PM PDT 24
Peak memory 238576 kb
Host smart-ddb35871-d9e1-41d8-a6ab-ae29f6ee2b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632430261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3632430261
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.752416992
Short name T434
Test name
Test status
Simulation time 198679121 ps
CPU time 4.56 seconds
Started May 30 03:41:02 PM PDT 24
Finished May 30 03:41:08 PM PDT 24
Peak memory 219128 kb
Host smart-8e0abcd1-8462-4dd3-bdd8-9db2e4cc818c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=752416992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.752416992
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1027306188
Short name T255
Test name
Test status
Simulation time 79017667926 ps
CPU time 438.01 seconds
Started May 30 03:41:02 PM PDT 24
Finished May 30 03:48:22 PM PDT 24
Peak memory 271052 kb
Host smart-d108ac56-1fda-41fc-923c-684b066e74ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027306188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1027306188
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2975087763
Short name T956
Test name
Test status
Simulation time 24940877891 ps
CPU time 34.33 seconds
Started May 30 03:41:03 PM PDT 24
Finished May 30 03:41:40 PM PDT 24
Peak memory 216236 kb
Host smart-65e126f6-b697-4af8-9a9d-f5d9379c7490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975087763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2975087763
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.568855120
Short name T541
Test name
Test status
Simulation time 1750973336 ps
CPU time 3.87 seconds
Started May 30 03:41:02 PM PDT 24
Finished May 30 03:41:09 PM PDT 24
Peak memory 216100 kb
Host smart-cac8ed40-1745-4ef9-a098-ad5842391a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568855120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.568855120
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3364158437
Short name T585
Test name
Test status
Simulation time 147376347 ps
CPU time 4.24 seconds
Started May 30 03:41:02 PM PDT 24
Finished May 30 03:41:08 PM PDT 24
Peak memory 216352 kb
Host smart-562dc0e0-dc78-4764-a2dc-77a39d8272e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364158437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3364158437
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2517672774
Short name T322
Test name
Test status
Simulation time 257508537 ps
CPU time 0.99 seconds
Started May 30 03:41:00 PM PDT 24
Finished May 30 03:41:02 PM PDT 24
Peak memory 206092 kb
Host smart-03f9cb43-88ab-450b-946a-c8de46d4b8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517672774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2517672774
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.96465142
Short name T560
Test name
Test status
Simulation time 1865277518 ps
CPU time 6.24 seconds
Started May 30 03:41:04 PM PDT 24
Finished May 30 03:41:13 PM PDT 24
Peak memory 240760 kb
Host smart-2e3edbaf-d4e6-4bca-b1c1-6939ca50dc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96465142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.96465142
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1136935693
Short name T897
Test name
Test status
Simulation time 29545166 ps
CPU time 0.72 seconds
Started May 30 03:41:05 PM PDT 24
Finished May 30 03:41:08 PM PDT 24
Peak memory 205376 kb
Host smart-1d0a18b3-5051-4b79-85a6-3dee83d0d811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136935693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1136935693
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.448851047
Short name T770
Test name
Test status
Simulation time 85563029 ps
CPU time 2.38 seconds
Started May 30 03:41:03 PM PDT 24
Finished May 30 03:41:08 PM PDT 24
Peak memory 218512 kb
Host smart-a0a45e2c-864a-4315-9d92-6c601ce83092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448851047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.448851047
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.441261964
Short name T872
Test name
Test status
Simulation time 46927948 ps
CPU time 0.84 seconds
Started May 30 03:41:05 PM PDT 24
Finished May 30 03:41:08 PM PDT 24
Peak memory 206440 kb
Host smart-47f1c614-db02-4971-a409-28a0a56bd2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441261964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.441261964
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2868293696
Short name T936
Test name
Test status
Simulation time 77903842 ps
CPU time 0.87 seconds
Started May 30 03:41:07 PM PDT 24
Finished May 30 03:41:10 PM PDT 24
Peak memory 215952 kb
Host smart-d2812779-9976-4e25-a0fa-2111db43771c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868293696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2868293696
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2890818699
Short name T528
Test name
Test status
Simulation time 22953780616 ps
CPU time 202.98 seconds
Started May 30 03:41:06 PM PDT 24
Finished May 30 03:44:32 PM PDT 24
Peak memory 240908 kb
Host smart-9512f60e-d6ab-42c3-a484-de01b2a460b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890818699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2890818699
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.813534754
Short name T935
Test name
Test status
Simulation time 15023761978 ps
CPU time 41.79 seconds
Started May 30 03:41:05 PM PDT 24
Finished May 30 03:41:50 PM PDT 24
Peak memory 231140 kb
Host smart-7e542617-0e5d-468f-bc5c-f41e800cd16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813534754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.813534754
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2818962882
Short name T703
Test name
Test status
Simulation time 629193852 ps
CPU time 12.54 seconds
Started May 30 03:41:07 PM PDT 24
Finished May 30 03:41:22 PM PDT 24
Peak memory 224392 kb
Host smart-1f98247c-4f67-418c-8260-ee594f3fb01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818962882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2818962882
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2402917683
Short name T696
Test name
Test status
Simulation time 54122316556 ps
CPU time 161.19 seconds
Started May 30 03:41:07 PM PDT 24
Finished May 30 03:43:50 PM PDT 24
Peak memory 230008 kb
Host smart-d567fade-60e0-48ba-86a2-a632f7075128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402917683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2402917683
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3568495870
Short name T238
Test name
Test status
Simulation time 2286844979 ps
CPU time 9.88 seconds
Started May 30 03:41:07 PM PDT 24
Finished May 30 03:41:19 PM PDT 24
Peak memory 237548 kb
Host smart-eba9b571-8ae2-4c0c-a98f-aaefe0bc579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568495870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3568495870
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3429054258
Short name T466
Test name
Test status
Simulation time 525409737 ps
CPU time 3.57 seconds
Started May 30 03:41:05 PM PDT 24
Finished May 30 03:41:11 PM PDT 24
Peak memory 218468 kb
Host smart-baa93f8f-57a4-4b02-8b17-6ffb9a71c0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429054258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3429054258
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2736799020
Short name T40
Test name
Test status
Simulation time 380299590 ps
CPU time 7.32 seconds
Started May 30 03:41:05 PM PDT 24
Finished May 30 03:41:15 PM PDT 24
Peak memory 219104 kb
Host smart-0baf1552-ae5f-4517-b6e3-a553b8603f75
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2736799020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2736799020
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2594349188
Short name T940
Test name
Test status
Simulation time 48035151687 ps
CPU time 499.04 seconds
Started May 30 03:41:05 PM PDT 24
Finished May 30 03:49:26 PM PDT 24
Peak memory 256656 kb
Host smart-fd414366-3f91-4a96-95e1-12690a62b426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594349188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2594349188
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2049613037
Short name T293
Test name
Test status
Simulation time 6016288518 ps
CPU time 12.93 seconds
Started May 30 03:41:07 PM PDT 24
Finished May 30 03:41:22 PM PDT 24
Peak memory 216336 kb
Host smart-753cd661-1a04-46fe-a8cf-f657ebbeceaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049613037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2049613037
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1104562403
Short name T701
Test name
Test status
Simulation time 1818936796 ps
CPU time 6.6 seconds
Started May 30 03:41:04 PM PDT 24
Finished May 30 03:41:13 PM PDT 24
Peak memory 216164 kb
Host smart-0fea0fa8-2e6c-41e0-ba5f-ce2b9acbd8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104562403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1104562403
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1343544936
Short name T356
Test name
Test status
Simulation time 53708337 ps
CPU time 1.3 seconds
Started May 30 03:41:06 PM PDT 24
Finished May 30 03:41:09 PM PDT 24
Peak memory 216280 kb
Host smart-06e130c6-103d-4e81-b61e-5d10490f85f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343544936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1343544936
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1658086434
Short name T323
Test name
Test status
Simulation time 40708757 ps
CPU time 0.76 seconds
Started May 30 03:41:02 PM PDT 24
Finished May 30 03:41:06 PM PDT 24
Peak memory 205656 kb
Host smart-7afb383f-aee7-4fdf-9e7c-8309f7c4053e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658086434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1658086434
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.928980658
Short name T747
Test name
Test status
Simulation time 165617403 ps
CPU time 2.71 seconds
Started May 30 03:41:07 PM PDT 24
Finished May 30 03:41:12 PM PDT 24
Peak memory 235468 kb
Host smart-4e0daa69-74c5-4ee5-a55b-f672d7fb9b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928980658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.928980658
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.530584038
Short name T890
Test name
Test status
Simulation time 11991635 ps
CPU time 0.78 seconds
Started May 30 03:41:12 PM PDT 24
Finished May 30 03:41:15 PM PDT 24
Peak memory 205448 kb
Host smart-785c1fe9-4065-49cc-b12f-3fcde191feca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530584038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.530584038
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.717903826
Short name T724
Test name
Test status
Simulation time 160403055 ps
CPU time 2.16 seconds
Started May 30 03:41:04 PM PDT 24
Finished May 30 03:41:09 PM PDT 24
Peak memory 221580 kb
Host smart-2e458e98-4bdf-4f30-9ef6-8fae7711ee13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717903826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.717903826
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2632462807
Short name T4
Test name
Test status
Simulation time 64874273 ps
CPU time 0.82 seconds
Started May 30 03:41:07 PM PDT 24
Finished May 30 03:41:10 PM PDT 24
Peak memory 206448 kb
Host smart-b7230cef-e10b-4ca0-ab49-c450656c4c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632462807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2632462807
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3527410375
Short name T209
Test name
Test status
Simulation time 66566155123 ps
CPU time 121.17 seconds
Started May 30 03:41:05 PM PDT 24
Finished May 30 03:43:09 PM PDT 24
Peak memory 249436 kb
Host smart-62fc18bf-8085-49e6-b9b9-084000cde038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527410375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3527410375
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2539176755
Short name T832
Test name
Test status
Simulation time 4188165167 ps
CPU time 39.86 seconds
Started May 30 03:41:04 PM PDT 24
Finished May 30 03:41:46 PM PDT 24
Peak memory 250120 kb
Host smart-62bf93e6-332d-4ae1-89a3-fb5e4c998256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539176755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2539176755
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.647874939
Short name T210
Test name
Test status
Simulation time 5229862454 ps
CPU time 71.93 seconds
Started May 30 03:41:14 PM PDT 24
Finished May 30 03:42:28 PM PDT 24
Peak memory 249268 kb
Host smart-8b7e6809-df37-44db-8f2e-51f2b5076360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647874939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.647874939
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.4054833538
Short name T844
Test name
Test status
Simulation time 2111906880 ps
CPU time 35.17 seconds
Started May 30 03:41:03 PM PDT 24
Finished May 30 03:41:41 PM PDT 24
Peak memory 232632 kb
Host smart-62a7dcba-c7ce-45d7-a6d0-aa86a9a4a020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054833538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.4054833538
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2060500569
Short name T716
Test name
Test status
Simulation time 9997266032 ps
CPU time 25.19 seconds
Started May 30 03:41:08 PM PDT 24
Finished May 30 03:41:36 PM PDT 24
Peak memory 219904 kb
Host smart-779081b2-0465-4fd8-b25f-e80bc5dbe77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060500569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2060500569
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3611792072
Short name T182
Test name
Test status
Simulation time 4777479274 ps
CPU time 16.73 seconds
Started May 30 03:41:08 PM PDT 24
Finished May 30 03:41:27 PM PDT 24
Peak memory 233208 kb
Host smart-5f096ab0-77c5-4752-abe4-999cfec5c0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611792072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3611792072
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.60861790
Short name T540
Test name
Test status
Simulation time 8761243558 ps
CPU time 10.9 seconds
Started May 30 03:41:08 PM PDT 24
Finished May 30 03:41:21 PM PDT 24
Peak memory 218752 kb
Host smart-ec8551f3-1985-45c1-a796-5ba020366d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60861790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.60861790
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1145620079
Short name T867
Test name
Test status
Simulation time 1898456096 ps
CPU time 3.42 seconds
Started May 30 03:41:08 PM PDT 24
Finished May 30 03:41:14 PM PDT 24
Peak memory 218648 kb
Host smart-eddb8391-6b95-4c6b-a83d-4dce1e51ccff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145620079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1145620079
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.363625501
Short name T788
Test name
Test status
Simulation time 1840013900 ps
CPU time 6.06 seconds
Started May 30 03:41:07 PM PDT 24
Finished May 30 03:41:15 PM PDT 24
Peak memory 220160 kb
Host smart-96750b55-1895-4929-823e-613185ad9c9b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=363625501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.363625501
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.325953798
Short name T870
Test name
Test status
Simulation time 20427712754 ps
CPU time 100.84 seconds
Started May 30 03:41:12 PM PDT 24
Finished May 30 03:42:56 PM PDT 24
Peak memory 240928 kb
Host smart-a99d0ee7-e448-4155-994f-39bfe8c8be92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325953798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.325953798
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1357787622
Short name T586
Test name
Test status
Simulation time 17786339490 ps
CPU time 26.75 seconds
Started May 30 03:41:07 PM PDT 24
Finished May 30 03:41:36 PM PDT 24
Peak memory 216240 kb
Host smart-0e63d48f-b2a8-441f-8f52-70dd34ffd9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357787622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1357787622
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2503487195
Short name T909
Test name
Test status
Simulation time 1267657109 ps
CPU time 3.82 seconds
Started May 30 03:41:08 PM PDT 24
Finished May 30 03:41:14 PM PDT 24
Peak memory 216064 kb
Host smart-908889c6-f23a-407e-95f5-888cb98ac20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503487195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2503487195
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1980201600
Short name T745
Test name
Test status
Simulation time 70071495 ps
CPU time 1.11 seconds
Started May 30 03:41:07 PM PDT 24
Finished May 30 03:41:11 PM PDT 24
Peak memory 207780 kb
Host smart-ad9f47ff-4eeb-48bd-821c-fadecd72c1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980201600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1980201600
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2454230249
Short name T524
Test name
Test status
Simulation time 104535274 ps
CPU time 0.84 seconds
Started May 30 03:41:09 PM PDT 24
Finished May 30 03:41:12 PM PDT 24
Peak memory 205684 kb
Host smart-ae3b5029-e12b-4b2f-960e-d87888b9ff54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454230249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2454230249
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.813814322
Short name T9
Test name
Test status
Simulation time 738510945 ps
CPU time 4.05 seconds
Started May 30 03:41:08 PM PDT 24
Finished May 30 03:41:15 PM PDT 24
Peak memory 218608 kb
Host smart-7703c3b8-7962-489f-8d0d-c32ecc50a26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813814322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.813814322
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.822830823
Short name T787
Test name
Test status
Simulation time 109076988 ps
CPU time 0.75 seconds
Started May 30 03:41:11 PM PDT 24
Finished May 30 03:41:14 PM PDT 24
Peak memory 205724 kb
Host smart-5dcdf691-026b-4446-9846-a73b7e3bfe57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822830823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.822830823
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1547818206
Short name T318
Test name
Test status
Simulation time 637514370 ps
CPU time 6.39 seconds
Started May 30 03:41:12 PM PDT 24
Finished May 30 03:41:21 PM PDT 24
Peak memory 232620 kb
Host smart-40726deb-b7e7-4a72-b169-bab583259756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547818206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1547818206
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.708633632
Short name T769
Test name
Test status
Simulation time 50437612 ps
CPU time 0.8 seconds
Started May 30 03:41:11 PM PDT 24
Finished May 30 03:41:14 PM PDT 24
Peak memory 206716 kb
Host smart-d5f10a62-d644-44d0-8ff7-d9bdb1fba126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708633632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.708633632
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.963928184
Short name T899
Test name
Test status
Simulation time 2963928769 ps
CPU time 10.9 seconds
Started May 30 03:41:11 PM PDT 24
Finished May 30 03:41:24 PM PDT 24
Peak memory 224404 kb
Host smart-31fae4d2-be5d-4900-af41-98e486fff9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963928184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.963928184
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2293650188
Short name T21
Test name
Test status
Simulation time 71748736874 ps
CPU time 330.44 seconds
Started May 30 03:41:12 PM PDT 24
Finished May 30 03:46:45 PM PDT 24
Peak memory 254828 kb
Host smart-7027be5c-610e-4338-a662-f7b309deaa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293650188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2293650188
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1857797045
Short name T203
Test name
Test status
Simulation time 65250363443 ps
CPU time 125.2 seconds
Started May 30 03:41:11 PM PDT 24
Finished May 30 03:43:18 PM PDT 24
Peak memory 252044 kb
Host smart-4a2c4aec-8d57-4dc3-bc88-b4775ba7eb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857797045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1857797045
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2187487310
Short name T873
Test name
Test status
Simulation time 13158973107 ps
CPU time 21.89 seconds
Started May 30 03:41:11 PM PDT 24
Finished May 30 03:41:35 PM PDT 24
Peak memory 224456 kb
Host smart-5c844627-158a-4a51-b8ce-992478e10b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187487310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2187487310
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.975210238
Short name T573
Test name
Test status
Simulation time 7236212114 ps
CPU time 14.29 seconds
Started May 30 03:41:14 PM PDT 24
Finished May 30 03:41:30 PM PDT 24
Peak memory 218060 kb
Host smart-f09a8649-a88d-4553-b748-ce0254f5448d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975210238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.975210238
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1918041716
Short name T669
Test name
Test status
Simulation time 1105534864 ps
CPU time 9.64 seconds
Started May 30 03:41:11 PM PDT 24
Finished May 30 03:41:22 PM PDT 24
Peak memory 219720 kb
Host smart-e0f7d468-8966-42bd-91e5-76d0d8f919f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918041716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1918041716
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.117943051
Short name T627
Test name
Test status
Simulation time 1765481230 ps
CPU time 8.48 seconds
Started May 30 03:41:11 PM PDT 24
Finished May 30 03:41:22 PM PDT 24
Peak memory 233756 kb
Host smart-93de8af5-9610-4b89-9138-0f158f336907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117943051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.117943051
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.849402700
Short name T938
Test name
Test status
Simulation time 14114680800 ps
CPU time 12.27 seconds
Started May 30 03:41:11 PM PDT 24
Finished May 30 03:41:25 PM PDT 24
Peak memory 218696 kb
Host smart-40b38996-ce4e-4e9d-b879-f0e94110b3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849402700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.849402700
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3304794502
Short name T446
Test name
Test status
Simulation time 507957564 ps
CPU time 7.08 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:30 PM PDT 24
Peak memory 219968 kb
Host smart-8f35d874-ac99-4bd0-a5ad-fdf325054b82
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3304794502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3304794502
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1034054074
Short name T147
Test name
Test status
Simulation time 6052343255 ps
CPU time 86.51 seconds
Started May 30 03:41:14 PM PDT 24
Finished May 30 03:42:43 PM PDT 24
Peak memory 250664 kb
Host smart-97f5385a-1066-49a5-a94b-d38279d64abb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034054074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1034054074
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3725736455
Short name T71
Test name
Test status
Simulation time 2760760006 ps
CPU time 15.61 seconds
Started May 30 03:41:11 PM PDT 24
Finished May 30 03:41:29 PM PDT 24
Peak memory 219152 kb
Host smart-d5966b0b-3065-4209-b45a-25c5c6fee0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725736455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3725736455
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.529261965
Short name T491
Test name
Test status
Simulation time 6099011266 ps
CPU time 17.26 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:41 PM PDT 24
Peak memory 216228 kb
Host smart-a13282b5-88eb-4022-8821-248a29da8378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529261965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.529261965
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2985016062
Short name T758
Test name
Test status
Simulation time 898289596 ps
CPU time 10.14 seconds
Started May 30 03:41:10 PM PDT 24
Finished May 30 03:41:22 PM PDT 24
Peak memory 216200 kb
Host smart-eb072e9d-360e-4f1f-b566-a889c409cec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985016062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2985016062
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3045373845
Short name T354
Test name
Test status
Simulation time 56729977 ps
CPU time 0.72 seconds
Started May 30 03:41:11 PM PDT 24
Finished May 30 03:41:14 PM PDT 24
Peak memory 205652 kb
Host smart-9d6a6811-7690-4fde-9aed-e66a0712e503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045373845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3045373845
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2891425352
Short name T5
Test name
Test status
Simulation time 1839920049 ps
CPU time 5.03 seconds
Started May 30 03:41:11 PM PDT 24
Finished May 30 03:41:18 PM PDT 24
Peak memory 217676 kb
Host smart-8023437f-aeb8-4bf6-b4da-a1c6aecd5e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891425352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2891425352
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1779492172
Short name T56
Test name
Test status
Simulation time 37338148 ps
CPU time 0.69 seconds
Started May 30 03:41:13 PM PDT 24
Finished May 30 03:41:16 PM PDT 24
Peak memory 205632 kb
Host smart-8e73e5f3-bdca-4659-9a6a-621e3a143e28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779492172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1779492172
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3748541541
Short name T836
Test name
Test status
Simulation time 141669489 ps
CPU time 2.76 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:25 PM PDT 24
Peak memory 218740 kb
Host smart-32684ba6-f970-4fa8-88c1-470cb7cda685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748541541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3748541541
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2146209100
Short name T349
Test name
Test status
Simulation time 58204636 ps
CPU time 0.8 seconds
Started May 30 03:41:11 PM PDT 24
Finished May 30 03:41:13 PM PDT 24
Peak memory 206780 kb
Host smart-b19cb119-6f80-49c7-9e3c-b8ec1e736e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146209100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2146209100
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.428060685
Short name T451
Test name
Test status
Simulation time 11588307 ps
CPU time 0.8 seconds
Started May 30 03:41:14 PM PDT 24
Finished May 30 03:41:17 PM PDT 24
Peak memory 215748 kb
Host smart-2d4e36ab-3b35-4b49-8546-f66660d5b14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428060685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.428060685
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.892270579
Short name T246
Test name
Test status
Simulation time 39464611308 ps
CPU time 367.98 seconds
Started May 30 03:41:12 PM PDT 24
Finished May 30 03:47:22 PM PDT 24
Peak memory 250088 kb
Host smart-efeec512-7824-4790-9a10-85fd55216fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892270579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.892270579
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2975650859
Short name T346
Test name
Test status
Simulation time 230808579 ps
CPU time 4.55 seconds
Started May 30 03:41:13 PM PDT 24
Finished May 30 03:41:20 PM PDT 24
Peak memory 224352 kb
Host smart-53979c95-6ac5-4c77-98db-68ee3b6ca414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975650859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2975650859
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3833934698
Short name T13
Test name
Test status
Simulation time 6797276665 ps
CPU time 14.28 seconds
Started May 30 03:41:14 PM PDT 24
Finished May 30 03:41:30 PM PDT 24
Peak memory 233956 kb
Host smart-2c2e4803-b62c-400a-b7b3-648cb73ff5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833934698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3833934698
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.101836549
Short name T193
Test name
Test status
Simulation time 3769564288 ps
CPU time 15.62 seconds
Started May 30 03:41:12 PM PDT 24
Finished May 30 03:41:30 PM PDT 24
Peak memory 235788 kb
Host smart-f39afe75-0be1-4fc3-a3ba-393a35da211f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101836549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.101836549
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.147278553
Short name T838
Test name
Test status
Simulation time 331045895 ps
CPU time 6.83 seconds
Started May 30 03:41:13 PM PDT 24
Finished May 30 03:41:22 PM PDT 24
Peak memory 237280 kb
Host smart-0f420e07-b4ef-47b1-a83f-209239630ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147278553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.147278553
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2910487554
Short name T252
Test name
Test status
Simulation time 3567110082 ps
CPU time 7.58 seconds
Started May 30 03:41:11 PM PDT 24
Finished May 30 03:41:20 PM PDT 24
Peak memory 237656 kb
Host smart-0ddb6d54-077a-404a-aa60-aa610967252f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910487554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2910487554
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2452832903
Short name T132
Test name
Test status
Simulation time 2923596017 ps
CPU time 6.71 seconds
Started May 30 03:41:12 PM PDT 24
Finished May 30 03:41:21 PM PDT 24
Peak memory 223004 kb
Host smart-9106ee06-7dcc-4173-b0ed-73de338de2ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2452832903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2452832903
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3945528296
Short name T277
Test name
Test status
Simulation time 384205609035 ps
CPU time 486.53 seconds
Started May 30 03:41:13 PM PDT 24
Finished May 30 03:49:22 PM PDT 24
Peak memory 250180 kb
Host smart-2867f795-e8a4-4c9a-92ca-4f12fb237431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945528296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3945528296
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1327529538
Short name T289
Test name
Test status
Simulation time 1825710040 ps
CPU time 23.33 seconds
Started May 30 03:41:13 PM PDT 24
Finished May 30 03:41:38 PM PDT 24
Peak memory 219044 kb
Host smart-a01a7e93-bd82-4617-ad46-fdc1b2427052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327529538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1327529538
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2164114435
Short name T119
Test name
Test status
Simulation time 1142182134 ps
CPU time 2.79 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:26 PM PDT 24
Peak memory 216196 kb
Host smart-69a4350b-ca13-4cf5-9465-e17a40a8b710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164114435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2164114435
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3842095950
Short name T315
Test name
Test status
Simulation time 993498553 ps
CPU time 15.08 seconds
Started May 30 03:41:12 PM PDT 24
Finished May 30 03:41:29 PM PDT 24
Peak memory 216220 kb
Host smart-f3c7ef40-d00c-4873-8f24-068d6b8569b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842095950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3842095950
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.234986526
Short name T779
Test name
Test status
Simulation time 16777232 ps
CPU time 0.73 seconds
Started May 30 03:41:14 PM PDT 24
Finished May 30 03:41:17 PM PDT 24
Peak memory 205692 kb
Host smart-12879295-280e-4ed9-bb41-f3c419501a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234986526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.234986526
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1654144373
Short name T549
Test name
Test status
Simulation time 933115781 ps
CPU time 3.54 seconds
Started May 30 03:41:12 PM PDT 24
Finished May 30 03:41:17 PM PDT 24
Peak memory 217200 kb
Host smart-c9e7f2e3-f514-4a8a-a5d5-ca1fe6ef2412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654144373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1654144373
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1728879429
Short name T472
Test name
Test status
Simulation time 44615771 ps
CPU time 0.71 seconds
Started May 30 03:41:24 PM PDT 24
Finished May 30 03:41:29 PM PDT 24
Peak memory 205348 kb
Host smart-dd8b10b1-c19d-4aaa-bb40-22db43d36b8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728879429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1728879429
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4131521058
Short name T714
Test name
Test status
Simulation time 60380757 ps
CPU time 0.79 seconds
Started May 30 03:41:11 PM PDT 24
Finished May 30 03:41:13 PM PDT 24
Peak memory 206764 kb
Host smart-30a51946-f8b8-4d67-a015-9a32c7416f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131521058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4131521058
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.4187803821
Short name T189
Test name
Test status
Simulation time 51498416873 ps
CPU time 380.02 seconds
Started May 30 03:41:21 PM PDT 24
Finished May 30 03:47:44 PM PDT 24
Peak memory 265792 kb
Host smart-3d7ce888-1869-49cb-b40b-ff683251b4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187803821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.4187803821
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1448703891
Short name T894
Test name
Test status
Simulation time 6077659918 ps
CPU time 38 seconds
Started May 30 03:41:21 PM PDT 24
Finished May 30 03:42:02 PM PDT 24
Peak memory 248788 kb
Host smart-5285025a-f785-464f-ba0f-9fdfe21bb4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448703891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1448703891
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2074829759
Short name T219
Test name
Test status
Simulation time 99692964524 ps
CPU time 184.41 seconds
Started May 30 03:41:18 PM PDT 24
Finished May 30 03:44:24 PM PDT 24
Peak memory 253828 kb
Host smart-5247259c-5028-4c29-8f19-d798a52358c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074829759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2074829759
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.69381525
Short name T497
Test name
Test status
Simulation time 360690736 ps
CPU time 4.22 seconds
Started May 30 03:41:21 PM PDT 24
Finished May 30 03:41:29 PM PDT 24
Peak memory 232392 kb
Host smart-a6c9297c-702b-402e-ac9c-55a5cfb38054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69381525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.69381525
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3876225293
Short name T855
Test name
Test status
Simulation time 9715844703 ps
CPU time 17.39 seconds
Started May 30 03:41:12 PM PDT 24
Finished May 30 03:41:32 PM PDT 24
Peak memory 218736 kb
Host smart-f8503911-c80e-4b7b-805e-db5df541bfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876225293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3876225293
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3008570505
Short name T53
Test name
Test status
Simulation time 3017719330 ps
CPU time 7.08 seconds
Started May 30 03:41:11 PM PDT 24
Finished May 30 03:41:20 PM PDT 24
Peak memory 218400 kb
Host smart-ebc2bd2e-2f6a-4670-9a10-e05f68779668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008570505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3008570505
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3237237717
Short name T697
Test name
Test status
Simulation time 209130163 ps
CPU time 2.3 seconds
Started May 30 03:41:13 PM PDT 24
Finished May 30 03:41:18 PM PDT 24
Peak memory 216020 kb
Host smart-f3f1565c-dd41-4f2c-a390-e7a39daeaedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237237717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3237237717
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.786765360
Short name T794
Test name
Test status
Simulation time 325785613 ps
CPU time 3.82 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:26 PM PDT 24
Peak memory 235144 kb
Host smart-f977bef6-769a-4af7-807b-a3d6c04e49bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786765360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.786765360
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.453735132
Short name T129
Test name
Test status
Simulation time 15971201646 ps
CPU time 10.24 seconds
Started May 30 03:41:19 PM PDT 24
Finished May 30 03:41:31 PM PDT 24
Peak memory 218980 kb
Host smart-32bc958c-3c21-4990-a5b8-5e33155bd2e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=453735132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.453735132
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.4282272282
Short name T647
Test name
Test status
Simulation time 56651190355 ps
CPU time 29.67 seconds
Started May 30 03:41:13 PM PDT 24
Finished May 30 03:41:45 PM PDT 24
Peak memory 216320 kb
Host smart-8b122a89-c9d4-4326-b355-9d703634aeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282272282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4282272282
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3985454627
Short name T450
Test name
Test status
Simulation time 1611854684 ps
CPU time 5.81 seconds
Started May 30 03:41:10 PM PDT 24
Finished May 30 03:41:18 PM PDT 24
Peak memory 216100 kb
Host smart-1ed3cb71-5ac2-4c98-8ceb-d065cd340bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985454627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3985454627
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2302823899
Short name T776
Test name
Test status
Simulation time 12948203 ps
CPU time 0.7 seconds
Started May 30 03:41:14 PM PDT 24
Finished May 30 03:41:16 PM PDT 24
Peak memory 205480 kb
Host smart-4187de46-e077-4e77-9f7d-9c2e4cdaa036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302823899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2302823899
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1115722132
Short name T301
Test name
Test status
Simulation time 24642161 ps
CPU time 0.77 seconds
Started May 30 03:41:19 PM PDT 24
Finished May 30 03:41:22 PM PDT 24
Peak memory 205440 kb
Host smart-d5ad4fbd-7ca0-4e4a-a986-4326f1c7e3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115722132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1115722132
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.673801809
Short name T395
Test name
Test status
Simulation time 915289347 ps
CPU time 4.71 seconds
Started May 30 03:41:21 PM PDT 24
Finished May 30 03:41:29 PM PDT 24
Peak memory 216204 kb
Host smart-ae562bc7-d16c-411b-bbd8-e16749766be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673801809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.673801809
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3322205663
Short name T436
Test name
Test status
Simulation time 11978000 ps
CPU time 0.72 seconds
Started May 30 03:41:21 PM PDT 24
Finished May 30 03:41:25 PM PDT 24
Peak memory 205420 kb
Host smart-10e1fd9f-d21d-4f69-b7ef-81b73c95ef5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322205663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3322205663
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3263789572
Short name T378
Test name
Test status
Simulation time 378617268 ps
CPU time 4.28 seconds
Started May 30 03:41:17 PM PDT 24
Finished May 30 03:41:23 PM PDT 24
Peak memory 233776 kb
Host smart-04b5b422-57c5-49cc-8093-9578160ce9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263789572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3263789572
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.994672354
Short name T342
Test name
Test status
Simulation time 14572163 ps
CPU time 0.75 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:23 PM PDT 24
Peak memory 205432 kb
Host smart-78cfdeab-38e1-440a-90c3-39c0f0ed0914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994672354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.994672354
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.531196148
Short name T868
Test name
Test status
Simulation time 10509303842 ps
CPU time 119.02 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:43:23 PM PDT 24
Peak memory 249088 kb
Host smart-fb4e6590-d2b4-4309-b783-92479d0a8f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531196148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.531196148
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3091621548
Short name T674
Test name
Test status
Simulation time 36083958701 ps
CPU time 145.69 seconds
Started May 30 03:41:22 PM PDT 24
Finished May 30 03:43:51 PM PDT 24
Peak memory 240332 kb
Host smart-9cec5b3c-1a51-47cf-90dd-627466939e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091621548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3091621548
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3330312205
Short name T38
Test name
Test status
Simulation time 5079519102 ps
CPU time 11.26 seconds
Started May 30 03:41:19 PM PDT 24
Finished May 30 03:41:33 PM PDT 24
Peak memory 224400 kb
Host smart-7d5fe131-2b25-409b-88a1-f00b3c2500d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330312205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3330312205
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1456303722
Short name T365
Test name
Test status
Simulation time 349409169 ps
CPU time 3.72 seconds
Started May 30 03:41:21 PM PDT 24
Finished May 30 03:41:28 PM PDT 24
Peak memory 224380 kb
Host smart-bd52bf63-0e55-4374-8353-6a9273b7d4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456303722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1456303722
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2837382359
Short name T591
Test name
Test status
Simulation time 479959889 ps
CPU time 9.94 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:33 PM PDT 24
Peak memory 248240 kb
Host smart-798451a9-a8e3-492f-8944-c40d73d893a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837382359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2837382359
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2262717457
Short name T419
Test name
Test status
Simulation time 12305334989 ps
CPU time 12.1 seconds
Started May 30 03:41:24 PM PDT 24
Finished May 30 03:41:39 PM PDT 24
Peak memory 233420 kb
Host smart-821101ce-d992-47ae-afbb-b7f4d1446354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262717457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2262717457
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.4277055287
Short name T568
Test name
Test status
Simulation time 623237849 ps
CPU time 5.81 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:28 PM PDT 24
Peak memory 233096 kb
Host smart-a756aec3-0a80-4388-b27d-70b8b3688483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277055287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4277055287
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1948269578
Short name T777
Test name
Test status
Simulation time 500911275 ps
CPU time 3.77 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:27 PM PDT 24
Peak memory 222248 kb
Host smart-07442e21-ad08-441b-8807-e4da324f77b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1948269578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1948269578
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2905295107
Short name T142
Test name
Test status
Simulation time 38326074792 ps
CPU time 105.77 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:43:09 PM PDT 24
Peak memory 250152 kb
Host smart-f411810b-47a8-4f7b-9283-2a0d3037c572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905295107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2905295107
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.778867563
Short name T363
Test name
Test status
Simulation time 50943019505 ps
CPU time 40.51 seconds
Started May 30 03:41:21 PM PDT 24
Finished May 30 03:42:05 PM PDT 24
Peak memory 216224 kb
Host smart-4062897c-6185-46cb-af7e-c628e4426966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778867563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.778867563
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4128355345
Short name T744
Test name
Test status
Simulation time 654667880 ps
CPU time 4.01 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:27 PM PDT 24
Peak memory 216148 kb
Host smart-c4dccf4e-94b2-4221-8bf9-bb8b553459a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128355345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4128355345
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3961428064
Short name T888
Test name
Test status
Simulation time 25234865 ps
CPU time 1.01 seconds
Started May 30 03:41:22 PM PDT 24
Finished May 30 03:41:26 PM PDT 24
Peak memory 206768 kb
Host smart-28dab4ff-052c-48ea-a716-d0115e60d498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961428064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3961428064
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.4084293057
Short name T837
Test name
Test status
Simulation time 219831231 ps
CPU time 0.81 seconds
Started May 30 03:41:23 PM PDT 24
Finished May 30 03:41:27 PM PDT 24
Peak memory 205672 kb
Host smart-d8637ef0-e58c-4837-9646-4acdc7daaa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084293057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4084293057
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.4006045079
Short name T493
Test name
Test status
Simulation time 4535153654 ps
CPU time 5.17 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:27 PM PDT 24
Peak memory 218496 kb
Host smart-86952b96-504f-4feb-b893-389270e2bc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006045079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.4006045079
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1839559642
Short name T355
Test name
Test status
Simulation time 12908832 ps
CPU time 0.71 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:23 PM PDT 24
Peak memory 204852 kb
Host smart-1cc66fb8-e27a-4b6e-81de-ca5f07e6096f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839559642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1839559642
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.60856749
Short name T14
Test name
Test status
Simulation time 802726236 ps
CPU time 7.87 seconds
Started May 30 03:41:21 PM PDT 24
Finished May 30 03:41:32 PM PDT 24
Peak memory 218892 kb
Host smart-7621acb5-95a9-4dd9-8901-c1d6900a2b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60856749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.60856749
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1935530223
Short name T642
Test name
Test status
Simulation time 23360933 ps
CPU time 0.8 seconds
Started May 30 03:41:24 PM PDT 24
Finished May 30 03:41:27 PM PDT 24
Peak memory 206348 kb
Host smart-d4f5eefd-4622-40aa-99d7-31152acbd1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935530223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1935530223
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1250711664
Short name T772
Test name
Test status
Simulation time 5861035829 ps
CPU time 43.05 seconds
Started May 30 03:41:23 PM PDT 24
Finished May 30 03:42:09 PM PDT 24
Peak memory 224468 kb
Host smart-196a7a9a-43e5-45ad-9f39-3659f3044e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250711664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1250711664
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1304197089
Short name T206
Test name
Test status
Simulation time 2423922833 ps
CPU time 35.95 seconds
Started May 30 03:41:22 PM PDT 24
Finished May 30 03:42:01 PM PDT 24
Peak memory 238776 kb
Host smart-f33433ab-1489-4762-9212-4f1d18a57b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304197089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1304197089
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3214285053
Short name T190
Test name
Test status
Simulation time 10819965860 ps
CPU time 165.93 seconds
Started May 30 03:41:24 PM PDT 24
Finished May 30 03:44:14 PM PDT 24
Peak memory 254092 kb
Host smart-fbf1a1f8-147a-4381-9db5-65bb44dee8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214285053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3214285053
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3332758406
Short name T39
Test name
Test status
Simulation time 6805138804 ps
CPU time 13.11 seconds
Started May 30 03:41:22 PM PDT 24
Finished May 30 03:41:38 PM PDT 24
Peak memory 235792 kb
Host smart-8d1699ba-5848-4935-bc47-79903b31a487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332758406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3332758406
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1615318582
Short name T590
Test name
Test status
Simulation time 1997656340 ps
CPU time 5.05 seconds
Started May 30 03:41:18 PM PDT 24
Finished May 30 03:41:26 PM PDT 24
Peak memory 224460 kb
Host smart-269a13e9-d908-4393-aab9-9afb855ccde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615318582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1615318582
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.712208748
Short name T81
Test name
Test status
Simulation time 1683053950 ps
CPU time 9.97 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:32 PM PDT 24
Peak memory 240240 kb
Host smart-4a4e648d-6ec1-472f-91ff-e2e6ed7df01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712208748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.712208748
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2497557063
Short name T917
Test name
Test status
Simulation time 40909432320 ps
CPU time 8.98 seconds
Started May 30 03:41:18 PM PDT 24
Finished May 30 03:41:29 PM PDT 24
Peak memory 222460 kb
Host smart-14e4dda8-8cb9-445f-91fa-e671f0a8a6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497557063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2497557063
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3175798675
Short name T408
Test name
Test status
Simulation time 479937761 ps
CPU time 2.67 seconds
Started May 30 03:41:21 PM PDT 24
Finished May 30 03:41:27 PM PDT 24
Peak memory 216808 kb
Host smart-297fd9fa-51d1-4e1a-84fb-d8308466cb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175798675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3175798675
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1030425074
Short name T127
Test name
Test status
Simulation time 239431631 ps
CPU time 3.35 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:26 PM PDT 24
Peak memory 222444 kb
Host smart-744747c4-91bf-4834-b349-c52574c6e7a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1030425074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1030425074
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3351353784
Short name T180
Test name
Test status
Simulation time 22030879254 ps
CPU time 167.93 seconds
Started May 30 03:41:21 PM PDT 24
Finished May 30 03:44:12 PM PDT 24
Peak memory 265508 kb
Host smart-ed82433b-369d-4ee6-af7d-11bbedc9d9f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351353784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3351353784
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.386159274
Short name T857
Test name
Test status
Simulation time 4165826551 ps
CPU time 29.04 seconds
Started May 30 03:41:22 PM PDT 24
Finished May 30 03:41:54 PM PDT 24
Peak memory 216280 kb
Host smart-6a53a035-cf6b-4d82-8d09-8bb200f470c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386159274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.386159274
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1797429953
Short name T441
Test name
Test status
Simulation time 1916166745 ps
CPU time 3.49 seconds
Started May 30 03:41:18 PM PDT 24
Finished May 30 03:41:23 PM PDT 24
Peak memory 216088 kb
Host smart-bfd0c75f-eef3-44e4-ab85-02506913eca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797429953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1797429953
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3419994388
Short name T329
Test name
Test status
Simulation time 704650994 ps
CPU time 2.51 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:25 PM PDT 24
Peak memory 216200 kb
Host smart-ece76499-28ec-410f-812d-6eddded23efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419994388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3419994388
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1938113870
Short name T15
Test name
Test status
Simulation time 47571804 ps
CPU time 0.91 seconds
Started May 30 03:41:22 PM PDT 24
Finished May 30 03:41:26 PM PDT 24
Peak memory 205648 kb
Host smart-fc615cd6-38a8-47d0-ae11-100f11b657fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938113870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1938113870
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.997649077
Short name T858
Test name
Test status
Simulation time 3128545768 ps
CPU time 7.34 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:30 PM PDT 24
Peak memory 217772 kb
Host smart-c64d916d-e03e-4634-8ceb-e3f423b56294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997649077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.997649077
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2391850841
Short name T27
Test name
Test status
Simulation time 39677247 ps
CPU time 0.77 seconds
Started May 30 03:39:33 PM PDT 24
Finished May 30 03:39:35 PM PDT 24
Peak memory 205452 kb
Host smart-3d9f44c1-d7ff-4877-92ba-5b2e82240e55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391850841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
391850841
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2774714584
Short name T525
Test name
Test status
Simulation time 5388969945 ps
CPU time 6.73 seconds
Started May 30 03:39:32 PM PDT 24
Finished May 30 03:39:41 PM PDT 24
Peak memory 236672 kb
Host smart-b6917f33-ec0b-4991-88e8-80cfc62f8e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774714584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2774714584
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.4043976010
Short name T479
Test name
Test status
Simulation time 48074006 ps
CPU time 0.74 seconds
Started May 30 03:39:24 PM PDT 24
Finished May 30 03:39:27 PM PDT 24
Peak memory 205372 kb
Host smart-aa29a8fc-60cd-4acf-bb0a-4a1157df84a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043976010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.4043976010
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3707548635
Short name T584
Test name
Test status
Simulation time 3491271904 ps
CPU time 55.12 seconds
Started May 30 03:39:27 PM PDT 24
Finished May 30 03:40:23 PM PDT 24
Peak memory 251176 kb
Host smart-d9f50086-d871-4a35-9a14-b147ab80e301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707548635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3707548635
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3294562312
Short name T18
Test name
Test status
Simulation time 1087650764 ps
CPU time 20.25 seconds
Started May 30 03:39:25 PM PDT 24
Finished May 30 03:39:47 PM PDT 24
Peak memory 240844 kb
Host smart-94ba3060-75ab-4194-9405-3dc6ba39f484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294562312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3294562312
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1140190676
Short name T630
Test name
Test status
Simulation time 234489638 ps
CPU time 6.25 seconds
Started May 30 03:39:33 PM PDT 24
Finished May 30 03:39:41 PM PDT 24
Peak memory 232640 kb
Host smart-3db2b757-3f5e-4fe2-bacf-b70c134d6c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140190676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1140190676
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2392119779
Short name T55
Test name
Test status
Simulation time 3530725218 ps
CPU time 16.12 seconds
Started May 30 03:39:26 PM PDT 24
Finished May 30 03:39:44 PM PDT 24
Peak memory 249000 kb
Host smart-5bbd1c74-35e4-4889-ac7e-b4aaa303bf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392119779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2392119779
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1627196707
Short name T632
Test name
Test status
Simulation time 10437983882 ps
CPU time 13.16 seconds
Started May 30 03:39:33 PM PDT 24
Finished May 30 03:39:48 PM PDT 24
Peak memory 219160 kb
Host smart-1f9f7e51-f2ac-4b66-82f8-0a6ea2f5b4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627196707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1627196707
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2768918703
Short name T949
Test name
Test status
Simulation time 622473531 ps
CPU time 8.53 seconds
Started May 30 03:39:32 PM PDT 24
Finished May 30 03:39:42 PM PDT 24
Peak memory 219528 kb
Host smart-5af9321d-3452-4c50-b0d2-0f658adc92ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768918703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2768918703
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2994371384
Short name T676
Test name
Test status
Simulation time 76803722 ps
CPU time 2.6 seconds
Started May 30 03:39:28 PM PDT 24
Finished May 30 03:39:32 PM PDT 24
Peak memory 232624 kb
Host smart-82c80bef-19b7-497a-9da1-27cbfe9c1335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994371384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2994371384
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1700681634
Short name T250
Test name
Test status
Simulation time 51711122886 ps
CPU time 11.46 seconds
Started May 30 03:39:32 PM PDT 24
Finished May 30 03:39:45 PM PDT 24
Peak memory 233640 kb
Host smart-eaa3f24d-3fd4-440d-abdf-e718e0bd1c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700681634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1700681634
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2591526227
Short name T649
Test name
Test status
Simulation time 417275071 ps
CPU time 5.12 seconds
Started May 30 03:39:33 PM PDT 24
Finished May 30 03:39:40 PM PDT 24
Peak memory 219112 kb
Host smart-6f5e4254-b87a-4efc-a08f-5a024c29e311
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2591526227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2591526227
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1117891313
Short name T69
Test name
Test status
Simulation time 554416513 ps
CPU time 1.06 seconds
Started May 30 03:39:23 PM PDT 24
Finished May 30 03:39:27 PM PDT 24
Peak memory 235088 kb
Host smart-58af039a-9e5e-4e85-a440-5884b11ee32d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117891313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1117891313
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3282647814
Short name T464
Test name
Test status
Simulation time 125038328 ps
CPU time 1.09 seconds
Started May 30 03:39:24 PM PDT 24
Finished May 30 03:39:28 PM PDT 24
Peak memory 207068 kb
Host smart-1bbd2e83-c547-467e-b70b-0d16d72348ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282647814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3282647814
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1346100612
Short name T648
Test name
Test status
Simulation time 1749702096 ps
CPU time 15.36 seconds
Started May 30 03:39:25 PM PDT 24
Finished May 30 03:39:42 PM PDT 24
Peak memory 216620 kb
Host smart-512883e7-c632-4b0e-b4f6-ee5e040d32c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346100612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1346100612
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1671687692
Short name T391
Test name
Test status
Simulation time 2637061641 ps
CPU time 11.49 seconds
Started May 30 03:39:24 PM PDT 24
Finished May 30 03:39:38 PM PDT 24
Peak memory 216192 kb
Host smart-0fd3322d-88bc-462e-82f5-6767e5e4913e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671687692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1671687692
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1536352471
Short name T892
Test name
Test status
Simulation time 37615832 ps
CPU time 1.42 seconds
Started May 30 03:39:31 PM PDT 24
Finished May 30 03:39:33 PM PDT 24
Peak memory 216252 kb
Host smart-d328117a-8c79-42de-b03d-5fb0f5c1f0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536352471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1536352471
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1010867320
Short name T933
Test name
Test status
Simulation time 121633537 ps
CPU time 1.11 seconds
Started May 30 03:39:27 PM PDT 24
Finished May 30 03:39:29 PM PDT 24
Peak memory 206704 kb
Host smart-97da3d81-9b0e-4477-859c-8ee4cb57a2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010867320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1010867320
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.800589348
Short name T230
Test name
Test status
Simulation time 4003272863 ps
CPU time 8.02 seconds
Started May 30 03:39:24 PM PDT 24
Finished May 30 03:39:34 PM PDT 24
Peak memory 234336 kb
Host smart-cd0b38e2-af00-4a47-b987-dea12e339f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800589348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.800589348
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1087107085
Short name T929
Test name
Test status
Simulation time 19716894 ps
CPU time 0.74 seconds
Started May 30 03:41:29 PM PDT 24
Finished May 30 03:41:35 PM PDT 24
Peak memory 204844 kb
Host smart-6722adb5-9037-4563-aa58-b47508cd318b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087107085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1087107085
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2171514791
Short name T387
Test name
Test status
Simulation time 5927906076 ps
CPU time 5.63 seconds
Started May 30 03:41:33 PM PDT 24
Finished May 30 03:41:45 PM PDT 24
Peak memory 220000 kb
Host smart-5f204b33-3b36-490c-be6b-f77922251575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171514791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2171514791
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1892531763
Short name T608
Test name
Test status
Simulation time 38999710 ps
CPU time 0.73 seconds
Started May 30 03:41:23 PM PDT 24
Finished May 30 03:41:26 PM PDT 24
Peak memory 205432 kb
Host smart-1d59dfff-3e0e-4f01-86dd-597b0ded862f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892531763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1892531763
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2073694784
Short name T948
Test name
Test status
Simulation time 24115344095 ps
CPU time 138.62 seconds
Started May 30 03:41:28 PM PDT 24
Finished May 30 03:43:51 PM PDT 24
Peak memory 262040 kb
Host smart-5d8883d9-8012-45dd-bc0e-cc63daaba002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073694784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2073694784
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3193533036
Short name T227
Test name
Test status
Simulation time 2809466945 ps
CPU time 51.91 seconds
Started May 30 03:41:28 PM PDT 24
Finished May 30 03:42:25 PM PDT 24
Peak memory 235812 kb
Host smart-a9450691-37d4-41d9-9325-45b550b7eb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193533036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3193533036
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3994278090
Short name T715
Test name
Test status
Simulation time 138465099 ps
CPU time 3.42 seconds
Started May 30 03:41:28 PM PDT 24
Finished May 30 03:41:36 PM PDT 24
Peak memory 224440 kb
Host smart-70c9bf51-d3a7-43f7-a746-392eeaea5d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994278090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3994278090
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1456009604
Short name T191
Test name
Test status
Simulation time 5596299958 ps
CPU time 14.2 seconds
Started May 30 03:41:28 PM PDT 24
Finished May 30 03:41:47 PM PDT 24
Peak memory 233808 kb
Host smart-939ce1f2-e5f1-4699-a53b-8c6803d0382c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456009604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1456009604
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1472120802
Short name T502
Test name
Test status
Simulation time 394477760 ps
CPU time 7.61 seconds
Started May 30 03:41:32 PM PDT 24
Finished May 30 03:41:45 PM PDT 24
Peak memory 236040 kb
Host smart-88f8686a-5179-4599-867c-3ab152eba868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472120802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1472120802
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1257712569
Short name T271
Test name
Test status
Simulation time 9968295391 ps
CPU time 17.71 seconds
Started May 30 03:41:27 PM PDT 24
Finished May 30 03:41:50 PM PDT 24
Peak memory 238788 kb
Host smart-ec7db69d-5c8a-46db-8c48-ce8f5f69d800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257712569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1257712569
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2183677998
Short name T806
Test name
Test status
Simulation time 9523586675 ps
CPU time 16.38 seconds
Started May 30 03:41:31 PM PDT 24
Finished May 30 03:41:52 PM PDT 24
Peak memory 229892 kb
Host smart-74815675-c6ca-4957-b734-9f4a0f3d9969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183677998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2183677998
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4115301580
Short name T364
Test name
Test status
Simulation time 24548358437 ps
CPU time 18.65 seconds
Started May 30 03:41:31 PM PDT 24
Finished May 30 03:41:54 PM PDT 24
Peak memory 218720 kb
Host smart-eec192fd-c15b-4aba-bcf8-d7bbbe84bc51
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4115301580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4115301580
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2785571148
Short name T829
Test name
Test status
Simulation time 74066619 ps
CPU time 0.97 seconds
Started May 30 03:41:28 PM PDT 24
Finished May 30 03:41:34 PM PDT 24
Peak memory 206852 kb
Host smart-07ec616d-56a1-4100-84f9-127c9fce353a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785571148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2785571148
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3508492008
Short name T298
Test name
Test status
Simulation time 597834213 ps
CPU time 2.51 seconds
Started May 30 03:41:19 PM PDT 24
Finished May 30 03:41:24 PM PDT 24
Peak memory 216168 kb
Host smart-f2425acc-63ba-42c9-a45e-d841fd0809fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508492008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3508492008
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1671218187
Short name T683
Test name
Test status
Simulation time 2125482601 ps
CPU time 5.43 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:28 PM PDT 24
Peak memory 216164 kb
Host smart-63f1215d-3d04-455e-91e3-584e133fead0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671218187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1671218187
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.390134171
Short name T943
Test name
Test status
Simulation time 458602724 ps
CPU time 1.52 seconds
Started May 30 03:41:20 PM PDT 24
Finished May 30 03:41:25 PM PDT 24
Peak memory 216248 kb
Host smart-a02b0585-7b6e-4d6b-bebd-e937c72fc3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390134171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.390134171
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3122144104
Short name T340
Test name
Test status
Simulation time 106482468 ps
CPU time 0.8 seconds
Started May 30 03:41:19 PM PDT 24
Finished May 30 03:41:22 PM PDT 24
Peak memory 205628 kb
Host smart-a832562a-ff6b-4378-bb03-97b02ad7d8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122144104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3122144104
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.4240558440
Short name T522
Test name
Test status
Simulation time 110581067 ps
CPU time 2.42 seconds
Started May 30 03:41:32 PM PDT 24
Finished May 30 03:41:40 PM PDT 24
Peak memory 218744 kb
Host smart-f8101c94-3df6-4a23-91dd-d4dc068b5380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240558440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.4240558440
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.865275048
Short name T347
Test name
Test status
Simulation time 32401325 ps
CPU time 0.71 seconds
Started May 30 03:41:30 PM PDT 24
Finished May 30 03:41:36 PM PDT 24
Peak memory 205724 kb
Host smart-d1efffca-1f61-4ddf-937f-be027d4a3c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865275048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.865275048
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1910997679
Short name T904
Test name
Test status
Simulation time 596898980 ps
CPU time 4.48 seconds
Started May 30 03:41:30 PM PDT 24
Finished May 30 03:41:40 PM PDT 24
Peak memory 218616 kb
Host smart-574ca422-bf82-4506-b1a8-125d50d5689b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910997679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1910997679
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3980268878
Short name T115
Test name
Test status
Simulation time 29967538 ps
CPU time 0.77 seconds
Started May 30 03:41:26 PM PDT 24
Finished May 30 03:41:32 PM PDT 24
Peak memory 206428 kb
Host smart-8cbf9910-2c6c-4d2e-a0eb-f3307f8f2d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980268878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3980268878
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.100350138
Short name T589
Test name
Test status
Simulation time 15053305016 ps
CPU time 67.1 seconds
Started May 30 03:41:29 PM PDT 24
Finished May 30 03:42:41 PM PDT 24
Peak memory 254464 kb
Host smart-782c30d0-973a-41b3-8123-39b6942b6222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100350138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.100350138
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3707046821
Short name T449
Test name
Test status
Simulation time 850915944 ps
CPU time 12.09 seconds
Started May 30 03:41:30 PM PDT 24
Finished May 30 03:41:47 PM PDT 24
Peak memory 234144 kb
Host smart-f90cd48e-123e-4f29-9a64-39b022e1c74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707046821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3707046821
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2152106146
Short name T775
Test name
Test status
Simulation time 3708908489 ps
CPU time 54.86 seconds
Started May 30 03:41:32 PM PDT 24
Finished May 30 03:42:33 PM PDT 24
Peak memory 232632 kb
Host smart-2bd5be02-541f-4365-9fe6-92178711e2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152106146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2152106146
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2754792192
Short name T380
Test name
Test status
Simulation time 33208447 ps
CPU time 2.38 seconds
Started May 30 03:41:29 PM PDT 24
Finished May 30 03:41:36 PM PDT 24
Peak memory 221568 kb
Host smart-1bee303d-75a5-4307-b949-7f10fd1aaad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754792192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2754792192
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.71680172
Short name T529
Test name
Test status
Simulation time 11015044419 ps
CPU time 27.19 seconds
Started May 30 03:41:30 PM PDT 24
Finished May 30 03:42:02 PM PDT 24
Peak memory 229400 kb
Host smart-8dfa0ee1-14f6-424c-a098-5fcac9446875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71680172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.71680172
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3175599394
Short name T556
Test name
Test status
Simulation time 2744167597 ps
CPU time 4.22 seconds
Started May 30 03:41:28 PM PDT 24
Finished May 30 03:41:37 PM PDT 24
Peak memory 234040 kb
Host smart-c0c0e491-9b5b-465f-a8eb-7466ecbead37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175599394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3175599394
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1802724723
Short name T543
Test name
Test status
Simulation time 3980404564 ps
CPU time 5.33 seconds
Started May 30 03:41:32 PM PDT 24
Finished May 30 03:41:43 PM PDT 24
Peak memory 227804 kb
Host smart-26b91118-c04b-4f69-82a8-24d743efe3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802724723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1802724723
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2068997271
Short name T619
Test name
Test status
Simulation time 1980478323 ps
CPU time 19.03 seconds
Started May 30 03:41:29 PM PDT 24
Finished May 30 03:41:53 PM PDT 24
Peak memory 218644 kb
Host smart-11467fc1-0291-4795-939e-d084cbb3c660
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2068997271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2068997271
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2085441936
Short name T169
Test name
Test status
Simulation time 10564968550 ps
CPU time 162.34 seconds
Started May 30 03:41:27 PM PDT 24
Finished May 30 03:44:14 PM PDT 24
Peak memory 257256 kb
Host smart-0e2fce7e-107f-4849-966b-9dba02c77251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085441936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2085441936
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2666157812
Short name T582
Test name
Test status
Simulation time 2986379450 ps
CPU time 21.41 seconds
Started May 30 03:41:40 PM PDT 24
Finished May 30 03:42:07 PM PDT 24
Peak memory 219772 kb
Host smart-17e9265e-bdd0-4867-8c47-14ded00b137c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666157812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2666157812
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1841361683
Short name T944
Test name
Test status
Simulation time 342542602 ps
CPU time 1.2 seconds
Started May 30 03:41:32 PM PDT 24
Finished May 30 03:41:38 PM PDT 24
Peak memory 206676 kb
Host smart-74a86b74-caf9-46ef-b783-4406cd2c4f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841361683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1841361683
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1186211002
Short name T534
Test name
Test status
Simulation time 14452197 ps
CPU time 0.68 seconds
Started May 30 03:41:27 PM PDT 24
Finished May 30 03:41:33 PM PDT 24
Peak memory 205476 kb
Host smart-d29bf57b-8f18-4fa6-aad3-f73b3687af7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186211002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1186211002
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1387840960
Short name T876
Test name
Test status
Simulation time 28588207 ps
CPU time 0.8 seconds
Started May 30 03:41:32 PM PDT 24
Finished May 30 03:41:38 PM PDT 24
Peak memory 205656 kb
Host smart-559b8e55-ad4c-406b-931c-f480bc584a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387840960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1387840960
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2592931888
Short name T551
Test name
Test status
Simulation time 5976485880 ps
CPU time 9.56 seconds
Started May 30 03:41:30 PM PDT 24
Finished May 30 03:41:44 PM PDT 24
Peak memory 228412 kb
Host smart-c8820208-7c29-4503-af56-7b04e2188b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592931888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2592931888
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1749460357
Short name T389
Test name
Test status
Simulation time 41444232 ps
CPU time 0.71 seconds
Started May 30 03:41:36 PM PDT 24
Finished May 30 03:41:43 PM PDT 24
Peak memory 205440 kb
Host smart-e5f3b9d3-6edb-422e-b93f-c89019bae894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749460357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1749460357
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1336161404
Short name T499
Test name
Test status
Simulation time 578172631 ps
CPU time 2.93 seconds
Started May 30 03:41:27 PM PDT 24
Finished May 30 03:41:35 PM PDT 24
Peak memory 224380 kb
Host smart-d512709e-a612-459e-aef1-91fbc141ae3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336161404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1336161404
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2157726521
Short name T319
Test name
Test status
Simulation time 66672884 ps
CPU time 0.82 seconds
Started May 30 03:41:31 PM PDT 24
Finished May 30 03:41:37 PM PDT 24
Peak memory 206388 kb
Host smart-9c4ac364-dc5c-4959-bbf4-d17482ebbc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157726521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2157726521
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3896488986
Short name T435
Test name
Test status
Simulation time 12443253 ps
CPU time 0.76 seconds
Started May 30 03:41:37 PM PDT 24
Finished May 30 03:41:44 PM PDT 24
Peak memory 215728 kb
Host smart-b1d335be-8506-40ce-bbf3-00dcec06abd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896488986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3896488986
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1906477300
Short name T278
Test name
Test status
Simulation time 2295551401 ps
CPU time 64.69 seconds
Started May 30 03:41:43 PM PDT 24
Finished May 30 03:42:54 PM PDT 24
Peak memory 252232 kb
Host smart-9b139d61-f919-4301-96be-2a2ca2cd320d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906477300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1906477300
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2404729391
Short name T152
Test name
Test status
Simulation time 54429039095 ps
CPU time 291.49 seconds
Started May 30 03:41:38 PM PDT 24
Finished May 30 03:46:35 PM PDT 24
Peak memory 256124 kb
Host smart-58a399a8-0d32-4683-8061-3293ad40b335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404729391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2404729391
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.982636176
Short name T284
Test name
Test status
Simulation time 2777295113 ps
CPU time 12.28 seconds
Started May 30 03:41:28 PM PDT 24
Finished May 30 03:41:45 PM PDT 24
Peak memory 237916 kb
Host smart-5b78c20b-a727-4e13-beb9-a14c4aa3293d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982636176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.982636176
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.19108447
Short name T789
Test name
Test status
Simulation time 123983093 ps
CPU time 2.2 seconds
Started May 30 03:41:31 PM PDT 24
Finished May 30 03:41:38 PM PDT 24
Peak memory 221236 kb
Host smart-11928f69-eb67-43bc-98ee-77a326ea6f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19108447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.19108447
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3794301211
Short name T505
Test name
Test status
Simulation time 8146665899 ps
CPU time 20.76 seconds
Started May 30 03:41:27 PM PDT 24
Finished May 30 03:41:53 PM PDT 24
Peak memory 221400 kb
Host smart-98491907-9c2f-425b-a889-d4a04a5af44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794301211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3794301211
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3849059092
Short name T622
Test name
Test status
Simulation time 3010225245 ps
CPU time 8.44 seconds
Started May 30 03:41:28 PM PDT 24
Finished May 30 03:41:41 PM PDT 24
Peak memory 233544 kb
Host smart-45db4c26-9e54-402f-8d40-cfdfb4693e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849059092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3849059092
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.881541796
Short name T533
Test name
Test status
Simulation time 896409437 ps
CPU time 4.41 seconds
Started May 30 03:41:31 PM PDT 24
Finished May 30 03:41:40 PM PDT 24
Peak memory 233812 kb
Host smart-3bb56577-e8f0-45f2-8ecd-1c2be64db6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881541796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.881541796
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3909563962
Short name T659
Test name
Test status
Simulation time 2843629452 ps
CPU time 3.7 seconds
Started May 30 03:41:39 PM PDT 24
Finished May 30 03:41:48 PM PDT 24
Peak memory 220392 kb
Host smart-6b993987-b9bf-4566-ab01-4d30747b8760
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3909563962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3909563962
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.972506027
Short name T852
Test name
Test status
Simulation time 3308720689 ps
CPU time 13.64 seconds
Started May 30 03:41:27 PM PDT 24
Finished May 30 03:41:45 PM PDT 24
Peak memory 216544 kb
Host smart-e6665b98-21cd-4f5c-aa38-d18e902691d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972506027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.972506027
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1905306278
Short name T359
Test name
Test status
Simulation time 3273556879 ps
CPU time 11.95 seconds
Started May 30 03:41:30 PM PDT 24
Finished May 30 03:41:47 PM PDT 24
Peak memory 216148 kb
Host smart-d738cfc7-12b4-4312-9dde-ebaf71670260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905306278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1905306278
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3395998196
Short name T739
Test name
Test status
Simulation time 64432250 ps
CPU time 0.94 seconds
Started May 30 03:41:31 PM PDT 24
Finished May 30 03:41:37 PM PDT 24
Peak memory 206892 kb
Host smart-6815d230-0e96-464d-97a1-82333119d187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395998196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3395998196
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.4029984060
Short name T875
Test name
Test status
Simulation time 94206161 ps
CPU time 0.95 seconds
Started May 30 03:41:27 PM PDT 24
Finished May 30 03:41:33 PM PDT 24
Peak memory 206068 kb
Host smart-bd585272-e150-4d53-a2c0-3e454e60032b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029984060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.4029984060
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2629021167
Short name T923
Test name
Test status
Simulation time 2640839897 ps
CPU time 5.49 seconds
Started May 30 03:41:28 PM PDT 24
Finished May 30 03:41:38 PM PDT 24
Peak memory 234544 kb
Host smart-5223d39f-d09a-4c0e-8421-f73f99d43118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629021167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2629021167
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3774787172
Short name T705
Test name
Test status
Simulation time 75080586 ps
CPU time 0.73 seconds
Started May 30 03:41:40 PM PDT 24
Finished May 30 03:41:47 PM PDT 24
Peak memory 204848 kb
Host smart-a4dca5b0-fd77-46fe-9fde-97ac4214d413
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774787172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3774787172
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3551876434
Short name T251
Test name
Test status
Simulation time 500752079 ps
CPU time 3.76 seconds
Started May 30 03:41:37 PM PDT 24
Finished May 30 03:41:47 PM PDT 24
Peak memory 220624 kb
Host smart-90adc4a5-8a7b-4d4e-8842-4d3203c36dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551876434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3551876434
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2655707708
Short name T569
Test name
Test status
Simulation time 49460271 ps
CPU time 0.75 seconds
Started May 30 03:41:41 PM PDT 24
Finished May 30 03:41:47 PM PDT 24
Peak memory 205420 kb
Host smart-805cc899-b492-48f7-8242-373ce4057b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655707708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2655707708
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3302054033
Short name T256
Test name
Test status
Simulation time 1985891255 ps
CPU time 45.83 seconds
Started May 30 03:41:38 PM PDT 24
Finished May 30 03:42:30 PM PDT 24
Peak memory 251036 kb
Host smart-be45824c-f8cd-4b2e-8ee7-e059ef0c2aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302054033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3302054033
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4205120889
Short name T336
Test name
Test status
Simulation time 7502524830 ps
CPU time 129.58 seconds
Started May 30 03:41:43 PM PDT 24
Finished May 30 03:43:59 PM PDT 24
Peak memory 255328 kb
Host smart-13c2545d-2308-4094-8db5-fba7815164d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205120889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4205120889
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2408202506
Short name T272
Test name
Test status
Simulation time 576396589712 ps
CPU time 483.33 seconds
Started May 30 03:41:39 PM PDT 24
Finished May 30 03:49:49 PM PDT 24
Peak memory 256740 kb
Host smart-33cb1f2c-437c-4df5-9687-fa3d51560da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408202506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2408202506
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3333967715
Short name T42
Test name
Test status
Simulation time 312635492 ps
CPU time 2.67 seconds
Started May 30 03:41:48 PM PDT 24
Finished May 30 03:41:56 PM PDT 24
Peak memory 232584 kb
Host smart-4d6eba8c-cf06-43c7-a32a-e901492a404f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333967715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3333967715
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.709650184
Short name T792
Test name
Test status
Simulation time 1063681589 ps
CPU time 2.38 seconds
Started May 30 03:41:37 PM PDT 24
Finished May 30 03:41:45 PM PDT 24
Peak memory 218588 kb
Host smart-fa43c77f-c0c0-4445-b362-bad9ddf233fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709650184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.709650184
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3413805795
Short name T195
Test name
Test status
Simulation time 2876039194 ps
CPU time 27.78 seconds
Started May 30 03:41:44 PM PDT 24
Finished May 30 03:42:17 PM PDT 24
Peak memory 226136 kb
Host smart-c7835d7f-5681-4dcd-8954-b8454e8bbac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413805795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3413805795
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2155510962
Short name T926
Test name
Test status
Simulation time 356989112 ps
CPU time 2.41 seconds
Started May 30 03:41:43 PM PDT 24
Finished May 30 03:41:51 PM PDT 24
Peak memory 218508 kb
Host smart-6c64ee54-dac3-480b-af9b-c3903e075565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155510962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2155510962
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2394202811
Short name T8
Test name
Test status
Simulation time 259315602 ps
CPU time 4.5 seconds
Started May 30 03:41:37 PM PDT 24
Finished May 30 03:41:48 PM PDT 24
Peak memory 235416 kb
Host smart-835a7b09-a29d-4db5-b83c-c82591b9c63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394202811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2394202811
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3917873363
Short name T927
Test name
Test status
Simulation time 65928828 ps
CPU time 3.31 seconds
Started May 30 03:41:39 PM PDT 24
Finished May 30 03:41:48 PM PDT 24
Peak memory 222936 kb
Host smart-7ad0ebb5-1d05-4bc7-8ff6-e3755ddaa4c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3917873363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3917873363
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3275424218
Short name T793
Test name
Test status
Simulation time 34070249 ps
CPU time 1 seconds
Started May 30 03:41:38 PM PDT 24
Finished May 30 03:41:46 PM PDT 24
Peak memory 206668 kb
Host smart-1d97998a-c501-42d9-998a-28e867e16f8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275424218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3275424218
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1973184024
Short name T348
Test name
Test status
Simulation time 5823838136 ps
CPU time 8.93 seconds
Started May 30 03:41:41 PM PDT 24
Finished May 30 03:41:55 PM PDT 24
Peak memory 216252 kb
Host smart-16c9b924-4d6e-4919-982a-8b5ce6a78883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973184024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1973184024
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.292142610
Short name T393
Test name
Test status
Simulation time 1842312604 ps
CPU time 3.49 seconds
Started May 30 03:41:39 PM PDT 24
Finished May 30 03:41:49 PM PDT 24
Peak memory 207600 kb
Host smart-11f342c1-c5a7-4729-a8c4-3f0281926d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292142610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.292142610
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2784178560
Short name T25
Test name
Test status
Simulation time 114262551 ps
CPU time 2.37 seconds
Started May 30 03:41:37 PM PDT 24
Finished May 30 03:41:46 PM PDT 24
Peak memory 216320 kb
Host smart-b3ebfd81-f889-4259-b10a-c47d3ce468d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784178560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2784178560
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3941291241
Short name T486
Test name
Test status
Simulation time 269309713 ps
CPU time 0.94 seconds
Started May 30 03:41:38 PM PDT 24
Finished May 30 03:41:45 PM PDT 24
Peak memory 206104 kb
Host smart-f9b0528d-b53a-4c6e-9ad5-ffed85fed070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941291241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3941291241
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.500285465
Short name T864
Test name
Test status
Simulation time 611345630 ps
CPU time 5.15 seconds
Started May 30 03:41:40 PM PDT 24
Finished May 30 03:41:51 PM PDT 24
Peak memory 218596 kb
Host smart-441e7644-d105-47da-8b2e-96c418be6b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500285465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.500285465
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.776437465
Short name T960
Test name
Test status
Simulation time 147048590 ps
CPU time 0.71 seconds
Started May 30 03:41:36 PM PDT 24
Finished May 30 03:41:43 PM PDT 24
Peak memory 205756 kb
Host smart-d0f5cfdd-40f7-4ed0-a337-fabd1edb560e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776437465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.776437465
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1128499923
Short name T557
Test name
Test status
Simulation time 741513692 ps
CPU time 9.85 seconds
Started May 30 03:41:37 PM PDT 24
Finished May 30 03:41:53 PM PDT 24
Peak memory 233716 kb
Host smart-8c57b4f2-788d-4623-91fe-80ddaa60a0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128499923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1128499923
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.938672515
Short name T824
Test name
Test status
Simulation time 26550837 ps
CPU time 0.78 seconds
Started May 30 03:41:38 PM PDT 24
Finished May 30 03:41:45 PM PDT 24
Peak memory 206408 kb
Host smart-12538ea3-8ab0-4159-9130-f8aa2ef89af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938672515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.938672515
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1738804673
Short name T485
Test name
Test status
Simulation time 8199518973 ps
CPU time 10.54 seconds
Started May 30 03:41:37 PM PDT 24
Finished May 30 03:41:54 PM PDT 24
Peak memory 224468 kb
Host smart-67f837c2-1b57-4be0-84fc-c2839b4f6656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738804673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1738804673
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1564307847
Short name T448
Test name
Test status
Simulation time 5573126276 ps
CPU time 51.68 seconds
Started May 30 03:41:39 PM PDT 24
Finished May 30 03:42:37 PM PDT 24
Peak memory 233820 kb
Host smart-c5f4946f-00c5-4cbd-b686-d8d03c715bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564307847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1564307847
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1702214304
Short name T32
Test name
Test status
Simulation time 6748590735 ps
CPU time 101 seconds
Started May 30 03:41:39 PM PDT 24
Finished May 30 03:43:26 PM PDT 24
Peak memory 253420 kb
Host smart-a485b010-06b5-4506-8804-602c7c859904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702214304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1702214304
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3930631794
Short name T574
Test name
Test status
Simulation time 4033252023 ps
CPU time 30.76 seconds
Started May 30 03:41:44 PM PDT 24
Finished May 30 03:42:20 PM PDT 24
Peak memory 237276 kb
Host smart-d6602eb0-0982-4139-b894-e969db23fe5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930631794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3930631794
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.317599412
Short name T74
Test name
Test status
Simulation time 66466518 ps
CPU time 3.71 seconds
Started May 30 03:41:42 PM PDT 24
Finished May 30 03:41:51 PM PDT 24
Peak memory 233472 kb
Host smart-e9b7c5da-da5d-4632-9859-b6b1dac17b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317599412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.317599412
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.385999748
Short name T954
Test name
Test status
Simulation time 20252911643 ps
CPU time 20.44 seconds
Started May 30 03:41:38 PM PDT 24
Finished May 30 03:42:05 PM PDT 24
Peak memory 246236 kb
Host smart-53b8a338-db16-4e48-a63e-7c59969746c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385999748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.385999748
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3827668299
Short name T955
Test name
Test status
Simulation time 1008457419 ps
CPU time 3.91 seconds
Started May 30 03:41:38 PM PDT 24
Finished May 30 03:41:48 PM PDT 24
Peak memory 233672 kb
Host smart-dc2ac199-ebbe-408f-b784-be8577d4ec62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827668299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3827668299
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3845290648
Short name T19
Test name
Test status
Simulation time 549023050 ps
CPU time 4.68 seconds
Started May 30 03:41:38 PM PDT 24
Finished May 30 03:41:49 PM PDT 24
Peak memory 218916 kb
Host smart-74b2d5c4-5f87-4d70-a60a-a27101042409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845290648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3845290648
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1411893184
Short name T509
Test name
Test status
Simulation time 309684041 ps
CPU time 5.32 seconds
Started May 30 03:41:39 PM PDT 24
Finished May 30 03:41:50 PM PDT 24
Peak memory 218764 kb
Host smart-f4f10fa3-1cc2-427b-83bd-8d1aa3f9cd22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1411893184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1411893184
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1790794771
Short name T470
Test name
Test status
Simulation time 2457603821 ps
CPU time 42.68 seconds
Started May 30 03:41:40 PM PDT 24
Finished May 30 03:42:28 PM PDT 24
Peak memory 240896 kb
Host smart-7d9689b8-87d4-4f67-ad93-79b37d97fbb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790794771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1790794771
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2292352803
Short name T295
Test name
Test status
Simulation time 2761139173 ps
CPU time 8.61 seconds
Started May 30 03:41:49 PM PDT 24
Finished May 30 03:42:03 PM PDT 24
Peak memory 216352 kb
Host smart-0a906fab-8317-489d-ad16-a3dfaa949e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292352803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2292352803
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.686064718
Short name T382
Test name
Test status
Simulation time 4418440812 ps
CPU time 3.92 seconds
Started May 30 03:41:38 PM PDT 24
Finished May 30 03:41:49 PM PDT 24
Peak memory 207716 kb
Host smart-1e1914b4-7382-4129-8c81-ae1d4c9c761a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686064718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.686064718
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2349073444
Short name T134
Test name
Test status
Simulation time 130828743 ps
CPU time 1.78 seconds
Started May 30 03:41:37 PM PDT 24
Finished May 30 03:41:45 PM PDT 24
Peak memory 216352 kb
Host smart-cfe1ebd3-3e9c-4e17-93c8-fcd1fd5ed107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349073444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2349073444
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2918453821
Short name T666
Test name
Test status
Simulation time 108102777 ps
CPU time 0.69 seconds
Started May 30 03:41:38 PM PDT 24
Finished May 30 03:41:45 PM PDT 24
Peak memory 205460 kb
Host smart-02d2e60b-41cb-489f-bca3-609a3d7b52c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918453821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2918453821
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1503683097
Short name T224
Test name
Test status
Simulation time 828149496 ps
CPU time 5.38 seconds
Started May 30 03:41:41 PM PDT 24
Finished May 30 03:41:52 PM PDT 24
Peak memory 218952 kb
Host smart-b5472fbd-e130-45dd-97bb-43256ff195f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503683097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1503683097
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.134151382
Short name T58
Test name
Test status
Simulation time 12279764 ps
CPU time 0.71 seconds
Started May 30 03:41:47 PM PDT 24
Finished May 30 03:41:53 PM PDT 24
Peak memory 204780 kb
Host smart-519dc27a-8d7b-4711-b82e-feea7d75a982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134151382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.134151382
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.836421433
Short name T611
Test name
Test status
Simulation time 1226160700 ps
CPU time 2.74 seconds
Started May 30 03:41:46 PM PDT 24
Finished May 30 03:41:54 PM PDT 24
Peak memory 218604 kb
Host smart-8e3b9f46-0dd7-4401-846c-8f9debaa5ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836421433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.836421433
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3017938479
Short name T612
Test name
Test status
Simulation time 26340622 ps
CPU time 0.8 seconds
Started May 30 03:41:44 PM PDT 24
Finished May 30 03:41:51 PM PDT 24
Peak memory 206384 kb
Host smart-ac78ac7c-2863-4109-b3ef-06f80f437fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017938479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3017938479
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.813317811
Short name T605
Test name
Test status
Simulation time 17223973661 ps
CPU time 137.52 seconds
Started May 30 03:41:50 PM PDT 24
Finished May 30 03:44:12 PM PDT 24
Peak memory 249112 kb
Host smart-b9f4a335-60ce-4590-911e-31a67b5e7d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813317811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.813317811
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4034789395
Short name T153
Test name
Test status
Simulation time 15517311338 ps
CPU time 82.28 seconds
Started May 30 03:41:49 PM PDT 24
Finished May 30 03:43:16 PM PDT 24
Peak memory 238776 kb
Host smart-b7cdd1db-9c33-4bce-a073-b179a73c6ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034789395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4034789395
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4205893995
Short name T294
Test name
Test status
Simulation time 15144869950 ps
CPU time 16.52 seconds
Started May 30 03:41:45 PM PDT 24
Finished May 30 03:42:07 PM PDT 24
Peak memory 249092 kb
Host smart-f9cb7321-b537-44df-8ceb-c448dff8ca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205893995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4205893995
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1363854927
Short name T578
Test name
Test status
Simulation time 816838878 ps
CPU time 5.17 seconds
Started May 30 03:41:47 PM PDT 24
Finished May 30 03:41:58 PM PDT 24
Peak memory 224500 kb
Host smart-9246c8fe-3860-4ce9-ac61-60617a325104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363854927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1363854927
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.229766528
Short name T655
Test name
Test status
Simulation time 309155132 ps
CPU time 5.02 seconds
Started May 30 03:41:49 PM PDT 24
Finished May 30 03:41:59 PM PDT 24
Peak memory 234928 kb
Host smart-adac556f-a8df-4a74-bb4d-d3d85c001a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229766528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.229766528
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3742349093
Short name T183
Test name
Test status
Simulation time 2855153013 ps
CPU time 30.65 seconds
Started May 30 03:41:52 PM PDT 24
Finished May 30 03:42:27 PM PDT 24
Peak memory 239328 kb
Host smart-6f13e939-af0f-4212-9762-c0cd6cf965c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742349093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3742349093
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.4262982921
Short name T241
Test name
Test status
Simulation time 824171830 ps
CPU time 3.38 seconds
Started May 30 03:41:49 PM PDT 24
Finished May 30 03:41:58 PM PDT 24
Peak memory 218368 kb
Host smart-701c7dce-9af0-41b4-b0e5-eb12c2a1efcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262982921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.4262982921
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.740307426
Short name T877
Test name
Test status
Simulation time 2063884155 ps
CPU time 7.84 seconds
Started May 30 03:41:42 PM PDT 24
Finished May 30 03:41:56 PM PDT 24
Peak memory 237740 kb
Host smart-006ec2d2-21b4-444f-b7cc-1adaf291ad1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740307426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.740307426
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2448869812
Short name T128
Test name
Test status
Simulation time 6763056582 ps
CPU time 14.82 seconds
Started May 30 03:41:47 PM PDT 24
Finished May 30 03:42:08 PM PDT 24
Peak memory 220384 kb
Host smart-a0d7d860-cf56-449b-a0a5-6e0a53564ebc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2448869812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2448869812
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2094582090
Short name T861
Test name
Test status
Simulation time 13396055146 ps
CPU time 60.97 seconds
Started May 30 03:41:51 PM PDT 24
Finished May 30 03:42:57 PM PDT 24
Peak memory 232688 kb
Host smart-2559c0e3-f616-4f7d-b20c-927e5b485f01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094582090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2094582090
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.715008629
Short name T384
Test name
Test status
Simulation time 1202852659 ps
CPU time 14.82 seconds
Started May 30 03:41:44 PM PDT 24
Finished May 30 03:42:05 PM PDT 24
Peak memory 217992 kb
Host smart-3d40b888-8304-4e6f-ba03-ca6bc6fc2862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715008629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.715008629
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.237101944
Short name T878
Test name
Test status
Simulation time 586745718 ps
CPU time 3.66 seconds
Started May 30 03:41:44 PM PDT 24
Finished May 30 03:41:53 PM PDT 24
Peak memory 216032 kb
Host smart-75958089-a9da-4383-bb35-459516cebbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237101944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.237101944
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1606226551
Short name T343
Test name
Test status
Simulation time 38993617 ps
CPU time 0.74 seconds
Started May 30 03:41:44 PM PDT 24
Finished May 30 03:41:50 PM PDT 24
Peak memory 205424 kb
Host smart-1d5ce4f6-4db1-4567-ab37-dc62dd75ba55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606226551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1606226551
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1854911542
Short name T371
Test name
Test status
Simulation time 31118937 ps
CPU time 0.7 seconds
Started May 30 03:41:43 PM PDT 24
Finished May 30 03:41:49 PM PDT 24
Peak memory 205424 kb
Host smart-839d1d48-782e-4359-83f5-95f5978fc22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854911542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1854911542
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1654830450
Short name T396
Test name
Test status
Simulation time 1367831696 ps
CPU time 3.06 seconds
Started May 30 03:41:50 PM PDT 24
Finished May 30 03:41:58 PM PDT 24
Peak memory 218508 kb
Host smart-23c7824c-c9ab-42d6-8d83-14e684dabfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654830450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1654830450
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1406262937
Short name T914
Test name
Test status
Simulation time 35045985 ps
CPU time 0.75 seconds
Started May 30 03:41:49 PM PDT 24
Finished May 30 03:41:55 PM PDT 24
Peak memory 205416 kb
Host smart-32ccc59e-7da8-4655-830b-e36e8f6a9752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406262937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1406262937
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2302479907
Short name T656
Test name
Test status
Simulation time 5148771729 ps
CPU time 14.65 seconds
Started May 30 03:41:49 PM PDT 24
Finished May 30 03:42:09 PM PDT 24
Peak memory 219640 kb
Host smart-7c3e2170-e5de-40e4-8e81-23d1fdeea828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302479907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2302479907
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2275278620
Short name T490
Test name
Test status
Simulation time 46164203 ps
CPU time 0.75 seconds
Started May 30 03:41:48 PM PDT 24
Finished May 30 03:41:54 PM PDT 24
Peak memory 205372 kb
Host smart-7814a84f-b0f4-41e0-b466-32854274749d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275278620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2275278620
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1803796429
Short name T527
Test name
Test status
Simulation time 64771573063 ps
CPU time 252.12 seconds
Started May 30 03:41:47 PM PDT 24
Finished May 30 03:46:05 PM PDT 24
Peak memory 249300 kb
Host smart-70e68cec-5272-4d33-b319-a05e454724b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803796429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1803796429
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.254487319
Short name T20
Test name
Test status
Simulation time 3234013640 ps
CPU time 81.85 seconds
Started May 30 03:41:48 PM PDT 24
Finished May 30 03:43:16 PM PDT 24
Peak memory 255560 kb
Host smart-d0527bd2-a7fe-454d-bfaa-c0b27f105cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254487319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.254487319
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1363320408
Short name T225
Test name
Test status
Simulation time 44789874808 ps
CPU time 77.73 seconds
Started May 30 03:41:49 PM PDT 24
Finished May 30 03:43:12 PM PDT 24
Peak memory 256688 kb
Host smart-8dac3e06-c8f0-4430-abce-2cf49d22ffa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363320408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1363320408
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1098446883
Short name T126
Test name
Test status
Simulation time 22441405233 ps
CPU time 49.11 seconds
Started May 30 03:41:49 PM PDT 24
Finished May 30 03:42:43 PM PDT 24
Peak memory 240832 kb
Host smart-ba6e4a44-f0a4-451e-a68b-f20383e64e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098446883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1098446883
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1993077764
Short name T372
Test name
Test status
Simulation time 118208011 ps
CPU time 2.16 seconds
Started May 30 03:41:47 PM PDT 24
Finished May 30 03:41:55 PM PDT 24
Peak memory 221444 kb
Host smart-582f06ec-39e4-4deb-b141-849296bb5855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993077764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1993077764
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2775192991
Short name T544
Test name
Test status
Simulation time 5881742184 ps
CPU time 15.48 seconds
Started May 30 03:41:47 PM PDT 24
Finished May 30 03:42:08 PM PDT 24
Peak memory 219616 kb
Host smart-e16bdfe3-1496-405d-932c-1bc946f38cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775192991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2775192991
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.370351529
Short name T821
Test name
Test status
Simulation time 937780354 ps
CPU time 4.57 seconds
Started May 30 03:41:50 PM PDT 24
Finished May 30 03:41:59 PM PDT 24
Peak memory 233228 kb
Host smart-0bd0fe5b-bec3-4509-b9b5-fb222153e6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370351529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.370351529
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.4013289712
Short name T504
Test name
Test status
Simulation time 1906426383 ps
CPU time 15.75 seconds
Started May 30 03:41:49 PM PDT 24
Finished May 30 03:42:10 PM PDT 24
Peak memory 245932 kb
Host smart-0a4bac81-1080-4df7-8a79-60f03d67c8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013289712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4013289712
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.453040463
Short name T483
Test name
Test status
Simulation time 2112115219 ps
CPU time 8.94 seconds
Started May 30 03:41:49 PM PDT 24
Finished May 30 03:42:03 PM PDT 24
Peak memory 219844 kb
Host smart-4678352a-65b7-41e2-b04a-468018bacdfd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=453040463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.453040463
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3059133899
Short name T536
Test name
Test status
Simulation time 41290124320 ps
CPU time 50.04 seconds
Started May 30 03:41:49 PM PDT 24
Finished May 30 03:42:44 PM PDT 24
Peak memory 217400 kb
Host smart-3700f082-cc1b-4772-8c73-7c65ce0349e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059133899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3059133899
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1847132397
Short name T471
Test name
Test status
Simulation time 1156585606 ps
CPU time 2.93 seconds
Started May 30 03:41:49 PM PDT 24
Finished May 30 03:41:57 PM PDT 24
Peak memory 216188 kb
Host smart-dd955092-32bf-4653-aa9d-b3e69236dea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847132397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1847132397
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1847198062
Short name T946
Test name
Test status
Simulation time 20081413966 ps
CPU time 13.81 seconds
Started May 30 03:41:48 PM PDT 24
Finished May 30 03:42:07 PM PDT 24
Peak memory 217200 kb
Host smart-0b15c8a4-50c8-410b-b5d1-132cf2a123e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847198062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1847198062
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2572355043
Short name T7
Test name
Test status
Simulation time 71553193 ps
CPU time 1.3 seconds
Started May 30 03:41:52 PM PDT 24
Finished May 30 03:41:57 PM PDT 24
Peak memory 215996 kb
Host smart-f62cac58-ddef-457f-becc-132abab7ec26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572355043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2572355043
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.153178612
Short name T842
Test name
Test status
Simulation time 48607402 ps
CPU time 0.85 seconds
Started May 30 03:41:51 PM PDT 24
Finished May 30 03:41:56 PM PDT 24
Peak memory 205628 kb
Host smart-e00c4cdb-cc05-42e6-a94f-bf2194319ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153178612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.153178612
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1965345000
Short name T381
Test name
Test status
Simulation time 1294834540 ps
CPU time 5.72 seconds
Started May 30 03:41:51 PM PDT 24
Finished May 30 03:42:01 PM PDT 24
Peak memory 240796 kb
Host smart-ffb0ab98-4628-41f1-ba68-1df5ab8f7a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965345000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1965345000
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2082435735
Short name T416
Test name
Test status
Simulation time 14777226 ps
CPU time 0.81 seconds
Started May 30 03:41:59 PM PDT 24
Finished May 30 03:42:04 PM PDT 24
Peak memory 204820 kb
Host smart-ce3363a0-7490-4287-9602-730cacb728e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082435735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2082435735
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2938249569
Short name T431
Test name
Test status
Simulation time 1174338566 ps
CPU time 4.32 seconds
Started May 30 03:42:08 PM PDT 24
Finished May 30 03:42:15 PM PDT 24
Peak memory 234176 kb
Host smart-032160a6-44c7-410a-972a-43abb38f0f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938249569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2938249569
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.856566069
Short name T760
Test name
Test status
Simulation time 29216084 ps
CPU time 0.78 seconds
Started May 30 03:41:54 PM PDT 24
Finished May 30 03:41:58 PM PDT 24
Peak memory 206408 kb
Host smart-6266ae23-9893-41f9-8639-a11080b41bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856566069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.856566069
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.906968083
Short name T205
Test name
Test status
Simulation time 5332932336 ps
CPU time 30.7 seconds
Started May 30 03:41:59 PM PDT 24
Finished May 30 03:42:32 PM PDT 24
Peak memory 249068 kb
Host smart-963973b3-ed03-4101-8463-f05ed069b13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906968083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.906968083
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.186088697
Short name T712
Test name
Test status
Simulation time 108898894 ps
CPU time 1.08 seconds
Started May 30 03:41:59 PM PDT 24
Finished May 30 03:42:03 PM PDT 24
Peak memory 216912 kb
Host smart-64f74ed8-c6b1-4e49-9d8f-232a4b9de774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186088697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.186088697
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.424347681
Short name T937
Test name
Test status
Simulation time 6626020466 ps
CPU time 18.04 seconds
Started May 30 03:41:59 PM PDT 24
Finished May 30 03:42:21 PM PDT 24
Peak memory 232696 kb
Host smart-45a578b0-6d2e-4b9f-a028-2f3d0c50b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424347681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.424347681
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3740901536
Short name T790
Test name
Test status
Simulation time 2876337370 ps
CPU time 18.85 seconds
Started May 30 03:42:00 PM PDT 24
Finished May 30 03:42:23 PM PDT 24
Peak memory 233988 kb
Host smart-15169655-5dc9-4bd4-89e3-db320a6c6e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740901536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3740901536
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1941562267
Short name T248
Test name
Test status
Simulation time 4013369327 ps
CPU time 10.32 seconds
Started May 30 03:41:59 PM PDT 24
Finished May 30 03:42:14 PM PDT 24
Peak memory 218540 kb
Host smart-e0238fd7-6a34-4146-9aff-1d36b143712a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941562267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1941562267
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3236137967
Short name T783
Test name
Test status
Simulation time 9982319124 ps
CPU time 16.28 seconds
Started May 30 03:42:05 PM PDT 24
Finished May 30 03:42:24 PM PDT 24
Peak memory 239168 kb
Host smart-8374fc15-b03d-47b4-a6d7-3067d5addb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236137967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3236137967
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1005644132
Short name T692
Test name
Test status
Simulation time 1001318900 ps
CPU time 8.47 seconds
Started May 30 03:42:01 PM PDT 24
Finished May 30 03:42:14 PM PDT 24
Peak memory 229464 kb
Host smart-2af7b7f4-698f-4ce7-8e3f-581fab7ec57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005644132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1005644132
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.110055302
Short name T515
Test name
Test status
Simulation time 579057702 ps
CPU time 9.39 seconds
Started May 30 03:42:01 PM PDT 24
Finished May 30 03:42:15 PM PDT 24
Peak memory 222892 kb
Host smart-970b21f1-9b60-4814-8806-e4491e2b2f11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=110055302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.110055302
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2002108087
Short name T734
Test name
Test status
Simulation time 16559882968 ps
CPU time 124.06 seconds
Started May 30 03:41:59 PM PDT 24
Finished May 30 03:44:06 PM PDT 24
Peak memory 249120 kb
Host smart-4ce103bb-ca3a-4213-a45b-124cbadcead7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002108087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2002108087
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.138675868
Short name T802
Test name
Test status
Simulation time 4576089939 ps
CPU time 15.25 seconds
Started May 30 03:41:47 PM PDT 24
Finished May 30 03:42:08 PM PDT 24
Peak memory 216260 kb
Host smart-24b45772-f79a-4978-ac8d-2a3873c6c166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138675868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.138675868
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.77347668
Short name T566
Test name
Test status
Simulation time 493521302 ps
CPU time 1.67 seconds
Started May 30 03:41:51 PM PDT 24
Finished May 30 03:41:57 PM PDT 24
Peak memory 207616 kb
Host smart-cee23831-3ece-4632-8ab6-6b316a3a7bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77347668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.77347668
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3091946118
Short name T317
Test name
Test status
Simulation time 303959883 ps
CPU time 1.63 seconds
Started May 30 03:42:04 PM PDT 24
Finished May 30 03:42:09 PM PDT 24
Peak memory 216092 kb
Host smart-5bc9a9cc-4ae6-4f32-926e-42b5bc603a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091946118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3091946118
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2901490361
Short name T854
Test name
Test status
Simulation time 37130760 ps
CPU time 0.84 seconds
Started May 30 03:41:59 PM PDT 24
Finished May 30 03:42:02 PM PDT 24
Peak memory 205612 kb
Host smart-b4303d56-a676-4cf4-8ac8-cc347ae85734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901490361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2901490361
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1471715113
Short name T950
Test name
Test status
Simulation time 167593697 ps
CPU time 2.55 seconds
Started May 30 03:41:58 PM PDT 24
Finished May 30 03:42:03 PM PDT 24
Peak memory 212728 kb
Host smart-c96aaa79-f24a-473f-8797-f35070d3f21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471715113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1471715113
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2941104099
Short name T72
Test name
Test status
Simulation time 16716802 ps
CPU time 0.73 seconds
Started May 30 03:42:00 PM PDT 24
Finished May 30 03:42:06 PM PDT 24
Peak memory 205736 kb
Host smart-908132dd-116b-4440-a7d4-11d57fe35e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941104099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2941104099
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3428387521
Short name T831
Test name
Test status
Simulation time 812530427 ps
CPU time 3.81 seconds
Started May 30 03:42:01 PM PDT 24
Finished May 30 03:42:10 PM PDT 24
Peak memory 219720 kb
Host smart-37c4824a-fe8a-4c8e-8695-b75fb29eda76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428387521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3428387521
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1761962282
Short name T310
Test name
Test status
Simulation time 44532535 ps
CPU time 0.79 seconds
Started May 30 03:42:04 PM PDT 24
Finished May 30 03:42:08 PM PDT 24
Peak memory 206680 kb
Host smart-6b081856-71a5-4d8d-9763-9afbb69c54b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761962282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1761962282
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1732875800
Short name T2
Test name
Test status
Simulation time 12062224 ps
CPU time 0.77 seconds
Started May 30 03:42:03 PM PDT 24
Finished May 30 03:42:08 PM PDT 24
Peak memory 215680 kb
Host smart-01aa322e-7471-4ad1-a5d0-56e75564be1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732875800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1732875800
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2142104916
Short name T214
Test name
Test status
Simulation time 10075913002 ps
CPU time 78.34 seconds
Started May 30 03:42:03 PM PDT 24
Finished May 30 03:43:25 PM PDT 24
Peak memory 222480 kb
Host smart-cf9bd28a-a861-4d93-a23b-51f90e8c80fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142104916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2142104916
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1894944584
Short name T764
Test name
Test status
Simulation time 102711709550 ps
CPU time 161.03 seconds
Started May 30 03:42:01 PM PDT 24
Finished May 30 03:44:46 PM PDT 24
Peak memory 253800 kb
Host smart-10c0f540-8f13-4bf2-8632-b111805f3ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894944584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1894944584
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.733006895
Short name T476
Test name
Test status
Simulation time 3292953390 ps
CPU time 14.9 seconds
Started May 30 03:41:58 PM PDT 24
Finished May 30 03:42:17 PM PDT 24
Peak memory 240612 kb
Host smart-09abea7f-c509-4506-8613-744f7f7582cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733006895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.733006895
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2495159659
Short name T198
Test name
Test status
Simulation time 243200702 ps
CPU time 4.05 seconds
Started May 30 03:42:03 PM PDT 24
Finished May 30 03:42:11 PM PDT 24
Peak memory 218672 kb
Host smart-a60e29cc-09d3-4d0b-a7fa-23294c0fc870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495159659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2495159659
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.489580229
Short name T856
Test name
Test status
Simulation time 10102756677 ps
CPU time 88 seconds
Started May 30 03:41:59 PM PDT 24
Finished May 30 03:43:31 PM PDT 24
Peak memory 234232 kb
Host smart-c3cc5219-a6ec-471b-b986-01336cd69215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489580229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.489580229
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3913417780
Short name T752
Test name
Test status
Simulation time 72342861 ps
CPU time 2.26 seconds
Started May 30 03:42:08 PM PDT 24
Finished May 30 03:42:13 PM PDT 24
Peak memory 232636 kb
Host smart-e883be8c-b82d-4aef-8390-387aba3886f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913417780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3913417780
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3702256752
Short name T226
Test name
Test status
Simulation time 51225276580 ps
CPU time 35.77 seconds
Started May 30 03:41:59 PM PDT 24
Finished May 30 03:42:38 PM PDT 24
Peak memory 237016 kb
Host smart-b7282b13-dcea-4adb-aedd-a25a63a18dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702256752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3702256752
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.513971479
Short name T545
Test name
Test status
Simulation time 1473468927 ps
CPU time 8.99 seconds
Started May 30 03:42:00 PM PDT 24
Finished May 30 03:42:13 PM PDT 24
Peak memory 222716 kb
Host smart-599eb9a5-c5aa-42bd-ae12-a38da960f2e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=513971479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.513971479
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2707045091
Short name T229
Test name
Test status
Simulation time 57639184675 ps
CPU time 290.29 seconds
Started May 30 03:41:59 PM PDT 24
Finished May 30 03:46:52 PM PDT 24
Peak memory 260984 kb
Host smart-e001b955-c2fb-4280-9b6c-46b95dd9f255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707045091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2707045091
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3355910300
Short name T866
Test name
Test status
Simulation time 28066160085 ps
CPU time 25.04 seconds
Started May 30 03:42:00 PM PDT 24
Finished May 30 03:42:30 PM PDT 24
Peak memory 216248 kb
Host smart-7e50026c-0426-4e51-a5c6-1a0039c2ff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355910300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3355910300
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.231701399
Short name T755
Test name
Test status
Simulation time 29029204222 ps
CPU time 17.7 seconds
Started May 30 03:42:07 PM PDT 24
Finished May 30 03:42:27 PM PDT 24
Peak memory 216136 kb
Host smart-9bdc4b37-7d4e-4183-a884-74d165de376d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231701399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.231701399
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.333242976
Short name T809
Test name
Test status
Simulation time 127134677 ps
CPU time 1.46 seconds
Started May 30 03:41:58 PM PDT 24
Finished May 30 03:42:03 PM PDT 24
Peak memory 216168 kb
Host smart-1f9ea4f0-9cab-4930-9bb6-0af34999e597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333242976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.333242976
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1862617563
Short name T617
Test name
Test status
Simulation time 105664155 ps
CPU time 0.99 seconds
Started May 30 03:41:59 PM PDT 24
Finished May 30 03:42:04 PM PDT 24
Peak memory 205652 kb
Host smart-ce6fc33f-0b5c-4a2e-9af0-10e130268915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862617563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1862617563
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2984505222
Short name T618
Test name
Test status
Simulation time 725298136 ps
CPU time 2.45 seconds
Started May 30 03:41:59 PM PDT 24
Finished May 30 03:42:06 PM PDT 24
Peak memory 207828 kb
Host smart-c72cd600-4bb8-4123-9162-d25cc23531c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984505222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2984505222
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1090114985
Short name T735
Test name
Test status
Simulation time 23893495 ps
CPU time 0.72 seconds
Started May 30 03:42:09 PM PDT 24
Finished May 30 03:42:12 PM PDT 24
Peak memory 205408 kb
Host smart-b6ca85b7-e9fb-41ab-b884-963ec31b06c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090114985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1090114985
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2148209334
Short name T562
Test name
Test status
Simulation time 154753928 ps
CPU time 2.31 seconds
Started May 30 03:42:02 PM PDT 24
Finished May 30 03:42:09 PM PDT 24
Peak memory 218724 kb
Host smart-020944b0-c789-45d4-9783-6a98234794f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148209334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2148209334
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2228186402
Short name T748
Test name
Test status
Simulation time 20624419 ps
CPU time 0.79 seconds
Started May 30 03:42:00 PM PDT 24
Finished May 30 03:42:05 PM PDT 24
Peak memory 206724 kb
Host smart-cf0a8fd2-afd1-4903-b4d1-361214f1861f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228186402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2228186402
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2948536589
Short name T925
Test name
Test status
Simulation time 30208167446 ps
CPU time 222.38 seconds
Started May 30 03:42:02 PM PDT 24
Finished May 30 03:45:49 PM PDT 24
Peak memory 249012 kb
Host smart-69138d36-6a8c-40ee-986c-626187f393cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948536589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2948536589
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.308986695
Short name T597
Test name
Test status
Simulation time 28314812696 ps
CPU time 157.04 seconds
Started May 30 03:42:00 PM PDT 24
Finished May 30 03:44:42 PM PDT 24
Peak memory 265460 kb
Host smart-d4484925-ad31-4955-b33a-83e93b861517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308986695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.308986695
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1984392202
Short name T814
Test name
Test status
Simulation time 64181109424 ps
CPU time 336.36 seconds
Started May 30 03:42:02 PM PDT 24
Finished May 30 03:47:43 PM PDT 24
Peak memory 249068 kb
Host smart-0d31c69e-02fc-49bb-87f0-4e99a51588e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984392202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1984392202
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2728621074
Short name T538
Test name
Test status
Simulation time 798153955 ps
CPU time 5.27 seconds
Started May 30 03:41:59 PM PDT 24
Finished May 30 03:42:09 PM PDT 24
Peak memory 224464 kb
Host smart-261580cf-558e-4f8d-9655-929068f5109d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728621074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2728621074
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3050055676
Short name T780
Test name
Test status
Simulation time 808805552 ps
CPU time 4.81 seconds
Started May 30 03:42:08 PM PDT 24
Finished May 30 03:42:15 PM PDT 24
Peak memory 218424 kb
Host smart-e31ef799-8b5a-4a5b-b3ed-2721026616f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050055676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3050055676
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3302524368
Short name T518
Test name
Test status
Simulation time 13766751453 ps
CPU time 23.68 seconds
Started May 30 03:42:00 PM PDT 24
Finished May 30 03:42:28 PM PDT 24
Peak memory 217848 kb
Host smart-070ced5a-3e1e-4b7d-91b1-18394696f616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302524368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3302524368
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3003538761
Short name T168
Test name
Test status
Simulation time 45370018324 ps
CPU time 31.94 seconds
Started May 30 03:42:03 PM PDT 24
Finished May 30 03:42:39 PM PDT 24
Peak memory 223788 kb
Host smart-7933cc17-91d9-447d-81c1-13a50b810bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003538761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3003538761
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1336643196
Short name T392
Test name
Test status
Simulation time 440685211 ps
CPU time 3.26 seconds
Started May 30 03:41:58 PM PDT 24
Finished May 30 03:42:05 PM PDT 24
Peak memory 232616 kb
Host smart-61d9570e-3fe1-41e4-819c-685bcf69b53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336643196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1336643196
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1468778020
Short name T763
Test name
Test status
Simulation time 176447304 ps
CPU time 4.92 seconds
Started May 30 03:42:02 PM PDT 24
Finished May 30 03:42:11 PM PDT 24
Peak memory 220248 kb
Host smart-132f645f-b90f-4511-a663-1d75101d4e9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1468778020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1468778020
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2548722361
Short name T149
Test name
Test status
Simulation time 143858264 ps
CPU time 1 seconds
Started May 30 03:42:01 PM PDT 24
Finished May 30 03:42:07 PM PDT 24
Peak memory 206824 kb
Host smart-f58c2f8e-dfac-4157-939a-38a8b9e821b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548722361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2548722361
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2947014402
Short name T784
Test name
Test status
Simulation time 12643663363 ps
CPU time 16.45 seconds
Started May 30 03:42:08 PM PDT 24
Finished May 30 03:42:27 PM PDT 24
Peak memory 216188 kb
Host smart-54c7b23f-432e-4add-ad7b-62b889a0ee4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947014402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2947014402
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2621728389
Short name T671
Test name
Test status
Simulation time 335251531 ps
CPU time 2.47 seconds
Started May 30 03:42:02 PM PDT 24
Finished May 30 03:42:09 PM PDT 24
Peak memory 216100 kb
Host smart-5f79710f-d4de-44cd-85db-ee7b03ff7181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621728389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2621728389
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.961655928
Short name T638
Test name
Test status
Simulation time 62970564 ps
CPU time 1.52 seconds
Started May 30 03:41:59 PM PDT 24
Finished May 30 03:42:05 PM PDT 24
Peak memory 216208 kb
Host smart-811beb1f-68eb-4b30-824b-6400c9e865e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961655928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.961655928
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.4257128680
Short name T411
Test name
Test status
Simulation time 87717191 ps
CPU time 0.73 seconds
Started May 30 03:42:01 PM PDT 24
Finished May 30 03:42:07 PM PDT 24
Peak memory 205684 kb
Host smart-f1028ed9-02ff-4472-ac1d-b637613ba793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257128680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.4257128680
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3590479085
Short name T678
Test name
Test status
Simulation time 285578339 ps
CPU time 3.41 seconds
Started May 30 03:42:01 PM PDT 24
Finished May 30 03:42:09 PM PDT 24
Peak memory 219784 kb
Host smart-a2b317c2-2667-41b9-9852-a2e96a0e9d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590479085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3590479085
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3013556784
Short name T835
Test name
Test status
Simulation time 107449446 ps
CPU time 0.71 seconds
Started May 30 03:39:32 PM PDT 24
Finished May 30 03:39:35 PM PDT 24
Peak memory 205444 kb
Host smart-9d0d69df-c380-4ee1-85d2-6694d9594bd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013556784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
013556784
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3376062313
Short name T73
Test name
Test status
Simulation time 4075248679 ps
CPU time 14.04 seconds
Started May 30 03:39:27 PM PDT 24
Finished May 30 03:39:43 PM PDT 24
Peak memory 218696 kb
Host smart-329713e8-7cec-4a1e-a7ea-a90e1315a119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376062313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3376062313
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.784881263
Short name T652
Test name
Test status
Simulation time 90332742 ps
CPU time 0.72 seconds
Started May 30 03:39:26 PM PDT 24
Finished May 30 03:39:28 PM PDT 24
Peak memory 205412 kb
Host smart-29079e6e-cf98-49e3-92f1-28b69f39308b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784881263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.784881263
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.604502654
Short name T237
Test name
Test status
Simulation time 8504155676 ps
CPU time 89.93 seconds
Started May 30 03:39:27 PM PDT 24
Finished May 30 03:40:58 PM PDT 24
Peak memory 251648 kb
Host smart-0a4ab687-1a22-4db1-b1a4-22903a34474d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604502654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.604502654
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3583062470
Short name T403
Test name
Test status
Simulation time 5693588574 ps
CPU time 42.69 seconds
Started May 30 03:39:30 PM PDT 24
Finished May 30 03:40:14 PM PDT 24
Peak memory 238772 kb
Host smart-21c94354-15d9-4326-b35b-01f33f0a27ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583062470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3583062470
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.151524803
Short name T732
Test name
Test status
Simulation time 135884342 ps
CPU time 5.11 seconds
Started May 30 03:39:27 PM PDT 24
Finished May 30 03:39:34 PM PDT 24
Peak memory 248404 kb
Host smart-8812e0cf-ee40-4024-a86b-74c3d7046439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151524803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.151524803
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2673431934
Short name T791
Test name
Test status
Simulation time 9117473609 ps
CPU time 20.85 seconds
Started May 30 03:39:33 PM PDT 24
Finished May 30 03:39:55 PM PDT 24
Peak memory 219480 kb
Host smart-9065891b-0396-41e5-9874-eec01f418ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673431934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2673431934
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.4081025787
Short name T756
Test name
Test status
Simulation time 71804126 ps
CPU time 2.26 seconds
Started May 30 03:39:22 PM PDT 24
Finished May 30 03:39:27 PM PDT 24
Peak memory 215996 kb
Host smart-a26e56ae-5c36-469b-b22b-69cfd78d5071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081025787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4081025787
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3875863015
Short name T609
Test name
Test status
Simulation time 240526755 ps
CPU time 5.34 seconds
Started May 30 03:39:24 PM PDT 24
Finished May 30 03:39:32 PM PDT 24
Peak memory 227864 kb
Host smart-7811cf5d-db3a-4d11-818d-fa8572e348b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875863015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3875863015
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3995646018
Short name T733
Test name
Test status
Simulation time 5110745796 ps
CPU time 13.59 seconds
Started May 30 03:39:27 PM PDT 24
Finished May 30 03:39:42 PM PDT 24
Peak memory 233292 kb
Host smart-a642772b-0441-48af-85b8-2789f8d1e028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995646018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3995646018
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3667330593
Short name T468
Test name
Test status
Simulation time 131471800 ps
CPU time 3.8 seconds
Started May 30 03:39:24 PM PDT 24
Finished May 30 03:39:30 PM PDT 24
Peak memory 222864 kb
Host smart-b1e78e63-3815-4194-bcad-2c8f3f874ffe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3667330593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3667330593
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1270171523
Short name T910
Test name
Test status
Simulation time 1573935393 ps
CPU time 24.93 seconds
Started May 30 03:39:26 PM PDT 24
Finished May 30 03:39:52 PM PDT 24
Peak memory 216408 kb
Host smart-7af3e35a-9c89-4524-88c0-f553e87d47e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270171523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1270171523
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3979177505
Short name T908
Test name
Test status
Simulation time 3109075156 ps
CPU time 12.39 seconds
Started May 30 03:39:27 PM PDT 24
Finished May 30 03:39:41 PM PDT 24
Peak memory 216148 kb
Host smart-f559f387-7068-48c4-83d6-1726bdba7eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979177505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3979177505
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.98422867
Short name T331
Test name
Test status
Simulation time 363687919 ps
CPU time 2.99 seconds
Started May 30 03:39:24 PM PDT 24
Finished May 30 03:39:29 PM PDT 24
Peak memory 216224 kb
Host smart-9acafaea-d410-4fe5-8ab0-ff8a57ea4236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98422867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.98422867
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2803145768
Short name T487
Test name
Test status
Simulation time 140295439 ps
CPU time 1.12 seconds
Started May 30 03:39:30 PM PDT 24
Finished May 30 03:39:32 PM PDT 24
Peak memory 205624 kb
Host smart-ec702391-c06f-489a-abe3-c5e67a9b25db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803145768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2803145768
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.565588778
Short name T881
Test name
Test status
Simulation time 970225600 ps
CPU time 4.97 seconds
Started May 30 03:39:30 PM PDT 24
Finished May 30 03:39:36 PM PDT 24
Peak memory 224372 kb
Host smart-91675cdf-3148-4930-9f98-ac2ce14040de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565588778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.565588778
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1460957747
Short name T459
Test name
Test status
Simulation time 31589502 ps
CPU time 0.71 seconds
Started May 30 03:39:34 PM PDT 24
Finished May 30 03:39:36 PM PDT 24
Peak memory 205704 kb
Host smart-803aa289-9299-437c-8909-15128f7cdd97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460957747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
460957747
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2030184018
Short name T353
Test name
Test status
Simulation time 356478558 ps
CPU time 2.99 seconds
Started May 30 03:39:32 PM PDT 24
Finished May 30 03:39:37 PM PDT 24
Peak memory 234436 kb
Host smart-d5490e3a-423c-4848-abc3-31ab1556b4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030184018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2030184018
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2236889441
Short name T737
Test name
Test status
Simulation time 85631643 ps
CPU time 0.83 seconds
Started May 30 03:39:34 PM PDT 24
Finished May 30 03:39:37 PM PDT 24
Peak memory 206464 kb
Host smart-167f139c-e08c-4b4f-85b6-ace6692e62cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236889441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2236889441
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1280087570
Short name T268
Test name
Test status
Simulation time 26143712078 ps
CPU time 66.02 seconds
Started May 30 03:39:33 PM PDT 24
Finished May 30 03:40:40 PM PDT 24
Peak memory 240856 kb
Host smart-d0f47673-df7d-48b8-b674-fba78785cc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280087570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1280087570
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3985605326
Short name T267
Test name
Test status
Simulation time 284819238871 ps
CPU time 234.17 seconds
Started May 30 03:39:34 PM PDT 24
Finished May 30 03:43:30 PM PDT 24
Peak memory 253500 kb
Host smart-49c25bfe-2205-4555-a1a9-b43943eeb908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985605326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3985605326
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3235037443
Short name T575
Test name
Test status
Simulation time 15407922638 ps
CPU time 146 seconds
Started May 30 03:39:39 PM PDT 24
Finished May 30 03:42:07 PM PDT 24
Peak memory 253564 kb
Host smart-8fb49470-dd6c-4639-963c-1eff1e1f5196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235037443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3235037443
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2286012019
Short name T283
Test name
Test status
Simulation time 4060501861 ps
CPU time 15.45 seconds
Started May 30 03:39:32 PM PDT 24
Finished May 30 03:39:50 PM PDT 24
Peak memory 240892 kb
Host smart-8e8badd6-92e1-4a09-87d3-77dd22af1c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286012019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2286012019
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2445641419
Short name T723
Test name
Test status
Simulation time 209098985 ps
CPU time 4.2 seconds
Started May 30 03:39:39 PM PDT 24
Finished May 30 03:39:45 PM PDT 24
Peak memory 218244 kb
Host smart-eb1ece8e-d8d6-4a45-96e9-812ff2b802f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445641419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2445641419
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.4259287227
Short name T200
Test name
Test status
Simulation time 40358883216 ps
CPU time 80.38 seconds
Started May 30 03:39:33 PM PDT 24
Finished May 30 03:40:56 PM PDT 24
Peak memory 237904 kb
Host smart-00508e65-96f8-4905-af2b-b64a3c437b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259287227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.4259287227
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3537052217
Short name T577
Test name
Test status
Simulation time 861125459 ps
CPU time 4.84 seconds
Started May 30 03:39:34 PM PDT 24
Finished May 30 03:39:41 PM PDT 24
Peak memory 233612 kb
Host smart-a0191826-8762-47c1-8573-e99199a3ab6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537052217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3537052217
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1972875765
Short name T604
Test name
Test status
Simulation time 3787662598 ps
CPU time 12.84 seconds
Started May 30 03:39:37 PM PDT 24
Finished May 30 03:39:51 PM PDT 24
Peak memory 218416 kb
Host smart-4a962ecd-929d-4532-a058-5963dff88d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972875765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1972875765
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.4023151027
Short name T385
Test name
Test status
Simulation time 183932154 ps
CPU time 4.13 seconds
Started May 30 03:39:40 PM PDT 24
Finished May 30 03:39:46 PM PDT 24
Peak memory 219816 kb
Host smart-24619ac4-cc43-4e50-a37b-741f70584212
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4023151027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.4023151027
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3905535478
Short name T841
Test name
Test status
Simulation time 80639780621 ps
CPU time 176.52 seconds
Started May 30 03:39:42 PM PDT 24
Finished May 30 03:42:40 PM PDT 24
Peak memory 265480 kb
Host smart-bcccd79a-a662-4856-b89a-65c9c138854b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905535478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3905535478
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3580670740
Short name T729
Test name
Test status
Simulation time 13353402069 ps
CPU time 35.76 seconds
Started May 30 03:39:41 PM PDT 24
Finished May 30 03:40:19 PM PDT 24
Peak memory 219992 kb
Host smart-4e7fb545-c14c-4d52-9ce1-7add65c85f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580670740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3580670740
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3255006625
Short name T390
Test name
Test status
Simulation time 216290123 ps
CPU time 1.13 seconds
Started May 30 03:39:32 PM PDT 24
Finished May 30 03:39:35 PM PDT 24
Peak memory 207552 kb
Host smart-701de599-b177-4900-9693-e4d3728af6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255006625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3255006625
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1807172756
Short name T710
Test name
Test status
Simulation time 79993717 ps
CPU time 1.29 seconds
Started May 30 03:39:33 PM PDT 24
Finished May 30 03:39:36 PM PDT 24
Peak memory 216008 kb
Host smart-7df3d608-9a8a-458e-83e3-2825e757a67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807172756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1807172756
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3490559657
Short name T375
Test name
Test status
Simulation time 70134467 ps
CPU time 0.88 seconds
Started May 30 03:39:39 PM PDT 24
Finished May 30 03:39:41 PM PDT 24
Peak memory 205596 kb
Host smart-4c183303-c9d0-4f55-9f1c-b84857d83df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490559657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3490559657
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.38216230
Short name T70
Test name
Test status
Simulation time 159726339 ps
CPU time 2.92 seconds
Started May 30 03:39:34 PM PDT 24
Finished May 30 03:39:39 PM PDT 24
Peak memory 234568 kb
Host smart-c39033c9-edd6-4b8c-b341-c32f0fd1e6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38216230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.38216230
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2892451072
Short name T358
Test name
Test status
Simulation time 42416318 ps
CPU time 0.71 seconds
Started May 30 03:39:40 PM PDT 24
Finished May 30 03:39:42 PM PDT 24
Peak memory 205356 kb
Host smart-52a5b0e8-864d-4a30-bd28-627f83ecd991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892451072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
892451072
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1013782174
Short name T905
Test name
Test status
Simulation time 924375888 ps
CPU time 6.83 seconds
Started May 30 03:39:34 PM PDT 24
Finished May 30 03:39:43 PM PDT 24
Peak memory 219160 kb
Host smart-d2208b7b-4be3-43d0-8392-dafc9c89084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013782174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1013782174
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2768308644
Short name T461
Test name
Test status
Simulation time 13282316 ps
CPU time 0.79 seconds
Started May 30 03:39:33 PM PDT 24
Finished May 30 03:39:35 PM PDT 24
Peak memory 206456 kb
Host smart-9276a46b-2578-413a-80db-a4cae6a5aa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768308644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2768308644
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2437756129
Short name T766
Test name
Test status
Simulation time 6964915857 ps
CPU time 13.48 seconds
Started May 30 03:39:35 PM PDT 24
Finished May 30 03:39:51 PM PDT 24
Peak memory 240816 kb
Host smart-5c91e4a8-3b69-4e29-a538-1ec4d9dab9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437756129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2437756129
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.627667458
Short name T258
Test name
Test status
Simulation time 2690080443 ps
CPU time 21.99 seconds
Started May 30 03:39:42 PM PDT 24
Finished May 30 03:40:05 PM PDT 24
Peak memory 237388 kb
Host smart-0ec65cee-f608-4d68-97a2-47a7396fbac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627667458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.627667458
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3219632332
Short name T810
Test name
Test status
Simulation time 1390082733 ps
CPU time 17.92 seconds
Started May 30 03:39:33 PM PDT 24
Finished May 30 03:39:53 PM PDT 24
Peak memory 232596 kb
Host smart-3596bbbb-efc3-49dd-a26b-422d1689de00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219632332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3219632332
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3313565785
Short name T565
Test name
Test status
Simulation time 34486807 ps
CPU time 2.53 seconds
Started May 30 03:39:35 PM PDT 24
Finished May 30 03:39:40 PM PDT 24
Peak memory 221292 kb
Host smart-8707945a-b66a-4cf8-ac68-5271437c1c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313565785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3313565785
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.4284257741
Short name T685
Test name
Test status
Simulation time 3162761647 ps
CPU time 22.77 seconds
Started May 30 03:39:42 PM PDT 24
Finished May 30 03:40:07 PM PDT 24
Peak memory 229052 kb
Host smart-fcb625c0-f70e-4f2a-9e37-6f83902971e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284257741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.4284257741
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.39433604
Short name T567
Test name
Test status
Simulation time 3663067090 ps
CPU time 7.65 seconds
Started May 30 03:39:34 PM PDT 24
Finished May 30 03:39:44 PM PDT 24
Peak memory 238072 kb
Host smart-ce5df40e-50da-4937-8851-5dab05810e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39433604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.39433604
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1709669858
Short name T114
Test name
Test status
Simulation time 507708024 ps
CPU time 6.58 seconds
Started May 30 03:39:34 PM PDT 24
Finished May 30 03:39:43 PM PDT 24
Peak memory 226112 kb
Host smart-f126f15e-13c5-49b6-ae5e-0a3eed4c1e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709669858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1709669858
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1844946333
Short name T606
Test name
Test status
Simulation time 823391393 ps
CPU time 10.54 seconds
Started May 30 03:39:33 PM PDT 24
Finished May 30 03:39:45 PM PDT 24
Peak memory 222000 kb
Host smart-6b2c0283-e7ee-4f07-a463-d04f74318746
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1844946333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1844946333
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.979270302
Short name T410
Test name
Test status
Simulation time 43855422 ps
CPU time 1.03 seconds
Started May 30 03:39:34 PM PDT 24
Finished May 30 03:39:38 PM PDT 24
Peak memory 206788 kb
Host smart-9e1ed70b-3ea1-409b-8003-abf745516dc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979270302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.979270302
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4252283608
Short name T819
Test name
Test status
Simulation time 733395562 ps
CPU time 6 seconds
Started May 30 03:39:37 PM PDT 24
Finished May 30 03:39:44 PM PDT 24
Peak memory 217892 kb
Host smart-fcf5b3d8-629a-43e4-ba1b-fb58338ca0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252283608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4252283608
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4193093018
Short name T860
Test name
Test status
Simulation time 10775695 ps
CPU time 0.71 seconds
Started May 30 03:39:34 PM PDT 24
Finished May 30 03:39:37 PM PDT 24
Peak memory 205488 kb
Host smart-ebe0327d-1974-4ce8-ba04-bdc3284f58b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193093018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4193093018
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.308861880
Short name T801
Test name
Test status
Simulation time 1193262514 ps
CPU time 3.77 seconds
Started May 30 03:39:36 PM PDT 24
Finished May 30 03:39:41 PM PDT 24
Peak memory 216200 kb
Host smart-ba25ffd0-7f67-4214-bf15-6dc47f5e1735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308861880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.308861880
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1930289820
Short name T720
Test name
Test status
Simulation time 89066515 ps
CPU time 0.81 seconds
Started May 30 03:39:35 PM PDT 24
Finished May 30 03:39:38 PM PDT 24
Peak memory 205660 kb
Host smart-f96a9db3-43af-4711-b8cd-d35d39606a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930289820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1930289820
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2945710105
Short name T539
Test name
Test status
Simulation time 6849090865 ps
CPU time 16.65 seconds
Started May 30 03:39:40 PM PDT 24
Finished May 30 03:39:59 PM PDT 24
Peak memory 237320 kb
Host smart-3c3e288a-1295-496f-a120-8b50ad84c25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945710105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2945710105
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3788559426
Short name T344
Test name
Test status
Simulation time 35695358 ps
CPU time 0.73 seconds
Started May 30 03:39:42 PM PDT 24
Finished May 30 03:39:45 PM PDT 24
Peak memory 204868 kb
Host smart-f19c97ae-87f2-47fa-b388-d3a34a5cc1a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788559426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
788559426
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3293526372
Short name T800
Test name
Test status
Simulation time 746683621 ps
CPU time 4.28 seconds
Started May 30 03:39:43 PM PDT 24
Finished May 30 03:39:50 PM PDT 24
Peak memory 219656 kb
Host smart-c2c64fca-f298-4ac3-803a-d3ac19a1bf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293526372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3293526372
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3122603412
Short name T862
Test name
Test status
Simulation time 174346329 ps
CPU time 0.84 seconds
Started May 30 03:39:41 PM PDT 24
Finished May 30 03:39:44 PM PDT 24
Peak memory 206400 kb
Host smart-51ee6011-8fc9-4ed7-929a-599f23f88c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122603412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3122603412
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2277787094
Short name T178
Test name
Test status
Simulation time 1525324279 ps
CPU time 6.84 seconds
Started May 30 03:39:45 PM PDT 24
Finished May 30 03:39:54 PM PDT 24
Peak memory 232580 kb
Host smart-6e5cd683-3708-4cec-b25e-ec6a0b629fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277787094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2277787094
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.458088281
Short name T199
Test name
Test status
Simulation time 287672483510 ps
CPU time 810 seconds
Started May 30 03:39:42 PM PDT 24
Finished May 30 03:53:15 PM PDT 24
Peak memory 255548 kb
Host smart-78dcbcf6-c4ee-4e8e-96ed-3907a0f337eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458088281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.458088281
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3965699730
Short name T303
Test name
Test status
Simulation time 1455505417 ps
CPU time 17.08 seconds
Started May 30 03:39:46 PM PDT 24
Finished May 30 03:40:05 PM PDT 24
Peak memory 217344 kb
Host smart-d287e919-3318-42d5-8db8-0fb07e874da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965699730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3965699730
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2876365228
Short name T397
Test name
Test status
Simulation time 958670079 ps
CPU time 5.65 seconds
Started May 30 03:39:41 PM PDT 24
Finished May 30 03:39:48 PM PDT 24
Peak memory 224384 kb
Host smart-07e0cf7e-3579-40c4-8153-611af347e831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876365228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2876365228
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1516074738
Short name T773
Test name
Test status
Simulation time 499039859 ps
CPU time 7.65 seconds
Started May 30 03:39:45 PM PDT 24
Finished May 30 03:39:54 PM PDT 24
Peak memory 220184 kb
Host smart-1c1ca089-df13-4149-9253-0f1675209d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516074738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1516074738
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3424219263
Short name T620
Test name
Test status
Simulation time 851258460 ps
CPU time 11.41 seconds
Started May 30 03:39:45 PM PDT 24
Finished May 30 03:39:59 PM PDT 24
Peak memory 232580 kb
Host smart-504a5bd1-8add-44a9-bf7c-0bc1243ce951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424219263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3424219263
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1781664878
Short name T275
Test name
Test status
Simulation time 188401503 ps
CPU time 4.6 seconds
Started May 30 03:39:46 PM PDT 24
Finished May 30 03:39:52 PM PDT 24
Peak memory 234500 kb
Host smart-cfe6b210-90d6-479b-b42a-3a59a1ec49fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781664878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1781664878
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3180606983
Short name T352
Test name
Test status
Simulation time 4903552169 ps
CPU time 10.99 seconds
Started May 30 03:39:40 PM PDT 24
Finished May 30 03:39:53 PM PDT 24
Peak memory 227708 kb
Host smart-e244ec69-adee-43b1-a07e-26a927d40b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180606983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3180606983
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1598085461
Short name T511
Test name
Test status
Simulation time 1521471993 ps
CPU time 5 seconds
Started May 30 03:39:43 PM PDT 24
Finished May 30 03:39:50 PM PDT 24
Peak memory 222588 kb
Host smart-27188696-4faa-4a3e-a024-87865c6d0822
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1598085461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1598085461
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3047887671
Short name T279
Test name
Test status
Simulation time 99129293891 ps
CPU time 192.02 seconds
Started May 30 03:39:47 PM PDT 24
Finished May 30 03:43:01 PM PDT 24
Peak memory 257220 kb
Host smart-5139ab78-d785-449b-b3a0-42b8149a464f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047887671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3047887671
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.4107172647
Short name T813
Test name
Test status
Simulation time 1678750984 ps
CPU time 18.6 seconds
Started May 30 03:39:43 PM PDT 24
Finished May 30 03:40:04 PM PDT 24
Peak memory 216212 kb
Host smart-bf92d8d6-4001-4283-a705-3230a80ed9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107172647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.4107172647
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.56023292
Short name T680
Test name
Test status
Simulation time 5392488906 ps
CPU time 14.86 seconds
Started May 30 03:39:41 PM PDT 24
Finished May 30 03:39:58 PM PDT 24
Peak memory 216240 kb
Host smart-cebf4c8d-679e-44b4-9693-3a78856e4119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56023292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.56023292
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3585722482
Short name T931
Test name
Test status
Simulation time 22171120 ps
CPU time 0.73 seconds
Started May 30 03:39:42 PM PDT 24
Finished May 30 03:39:45 PM PDT 24
Peak memory 205680 kb
Host smart-4c4174a4-d734-4514-a209-05ee83ca32fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585722482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3585722482
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2010649094
Short name T646
Test name
Test status
Simulation time 81455436 ps
CPU time 0.8 seconds
Started May 30 03:39:42 PM PDT 24
Finished May 30 03:39:45 PM PDT 24
Peak memory 205668 kb
Host smart-f8f3a4d8-866d-4881-a4f5-bbdf846c1acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010649094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2010649094
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1205661601
Short name T663
Test name
Test status
Simulation time 10432471549 ps
CPU time 12.38 seconds
Started May 30 03:39:41 PM PDT 24
Finished May 30 03:39:55 PM PDT 24
Peak memory 218612 kb
Host smart-469cfd56-3432-420a-a6b6-96096b4fcc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205661601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1205661601
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2850589885
Short name T850
Test name
Test status
Simulation time 15011151 ps
CPU time 0.73 seconds
Started May 30 03:39:41 PM PDT 24
Finished May 30 03:39:43 PM PDT 24
Peak memory 205392 kb
Host smart-b59ed9e6-ebc6-4041-8e38-04a55a33ceb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850589885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
850589885
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1386920799
Short name T768
Test name
Test status
Simulation time 218745203 ps
CPU time 2.87 seconds
Started May 30 03:39:44 PM PDT 24
Finished May 30 03:39:49 PM PDT 24
Peak memory 233616 kb
Host smart-49da24c8-2a99-4d49-8baf-3687696517c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386920799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1386920799
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3141426911
Short name T304
Test name
Test status
Simulation time 16944326 ps
CPU time 0.78 seconds
Started May 30 03:39:41 PM PDT 24
Finished May 30 03:39:44 PM PDT 24
Peak memory 206432 kb
Host smart-5cfeb313-baa8-4f74-b434-0198d4472e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141426911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3141426911
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.144748687
Short name T204
Test name
Test status
Simulation time 6467379515 ps
CPU time 76.17 seconds
Started May 30 03:39:42 PM PDT 24
Finished May 30 03:41:00 PM PDT 24
Peak memory 252524 kb
Host smart-d77bebfc-fcc0-45e8-8c5d-f10f5e788d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144748687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.144748687
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.120564325
Short name T44
Test name
Test status
Simulation time 26265638862 ps
CPU time 152.53 seconds
Started May 30 03:39:43 PM PDT 24
Finished May 30 03:42:17 PM PDT 24
Peak memory 249220 kb
Host smart-becb8332-f071-4cde-9a54-aaadda6a460f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120564325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.120564325
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.207337974
Short name T830
Test name
Test status
Simulation time 125887167028 ps
CPU time 299.5 seconds
Started May 30 03:39:43 PM PDT 24
Finished May 30 03:44:44 PM PDT 24
Peak memory 252876 kb
Host smart-f3399d88-259b-407d-aa82-fbd35ba50e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207337974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
207337974
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2926139632
Short name T759
Test name
Test status
Simulation time 578490691 ps
CPU time 7.61 seconds
Started May 30 03:39:46 PM PDT 24
Finished May 30 03:39:56 PM PDT 24
Peak memory 224344 kb
Host smart-94470f4a-b269-4851-9c3f-c4f1263ad568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926139632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2926139632
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.896269693
Short name T172
Test name
Test status
Simulation time 123418492 ps
CPU time 4.06 seconds
Started May 30 03:39:41 PM PDT 24
Finished May 30 03:39:47 PM PDT 24
Peak memory 233432 kb
Host smart-bf6268de-73ce-4906-bb2b-8c46d18bb9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896269693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.896269693
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3004254210
Short name T688
Test name
Test status
Simulation time 748771352 ps
CPU time 13.08 seconds
Started May 30 03:39:46 PM PDT 24
Finished May 30 03:40:01 PM PDT 24
Peak memory 238128 kb
Host smart-d3cb4295-4ac2-4159-84f1-c7b83d2e916f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004254210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3004254210
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.23873105
Short name T906
Test name
Test status
Simulation time 4437140133 ps
CPU time 11.13 seconds
Started May 30 03:39:42 PM PDT 24
Finished May 30 03:39:56 PM PDT 24
Peak memory 219372 kb
Host smart-b8053af0-5c1e-4608-bb40-e43a51b46029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23873105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.23873105
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.514065158
Short name T405
Test name
Test status
Simulation time 3276358492 ps
CPU time 6.04 seconds
Started May 30 03:39:41 PM PDT 24
Finished May 30 03:39:49 PM PDT 24
Peak memory 219612 kb
Host smart-7d5330cd-22ca-4870-9930-8f2a2d48df27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514065158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.514065158
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.170585800
Short name T131
Test name
Test status
Simulation time 5295700718 ps
CPU time 14.39 seconds
Started May 30 03:39:43 PM PDT 24
Finished May 30 03:39:59 PM PDT 24
Peak memory 222844 kb
Host smart-15117745-77b3-49da-9bcc-91c6df23471d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=170585800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.170585800
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2594333383
Short name T360
Test name
Test status
Simulation time 197385657 ps
CPU time 1.2 seconds
Started May 30 03:39:46 PM PDT 24
Finished May 30 03:39:49 PM PDT 24
Peak memory 206904 kb
Host smart-89502097-4479-484f-afcd-1f4c379e3d01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594333383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2594333383
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2830436205
Short name T924
Test name
Test status
Simulation time 3500814489 ps
CPU time 24.69 seconds
Started May 30 03:39:43 PM PDT 24
Finished May 30 03:40:10 PM PDT 24
Peak memory 216340 kb
Host smart-897bacbb-3189-4960-adaf-cc39589c6c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830436205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2830436205
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1144062783
Short name T452
Test name
Test status
Simulation time 2957376271 ps
CPU time 6.82 seconds
Started May 30 03:39:44 PM PDT 24
Finished May 30 03:39:52 PM PDT 24
Peak memory 216164 kb
Host smart-e23890d1-3440-4a21-b028-60cda8585f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144062783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1144062783
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3809501682
Short name T580
Test name
Test status
Simulation time 22354779 ps
CPU time 0.84 seconds
Started May 30 03:39:43 PM PDT 24
Finished May 30 03:39:46 PM PDT 24
Peak memory 205732 kb
Host smart-af908fad-4cb9-4a87-8c7a-bcbe49777113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809501682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3809501682
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3010134505
Short name T456
Test name
Test status
Simulation time 148244462 ps
CPU time 0.86 seconds
Started May 30 03:39:43 PM PDT 24
Finished May 30 03:39:46 PM PDT 24
Peak memory 205964 kb
Host smart-3019eb1e-254c-4d76-8811-47bc41000852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010134505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3010134505
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1455491150
Short name T547
Test name
Test status
Simulation time 933567809 ps
CPU time 5.91 seconds
Started May 30 03:39:46 PM PDT 24
Finished May 30 03:39:54 PM PDT 24
Peak memory 233836 kb
Host smart-7d65b676-42a8-4c1d-aba4-4594342ef1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455491150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1455491150
Directory /workspace/9.spi_device_upload/latest
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