Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3615334	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4016400

1

T1

7

T2

1608

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4157491	1			T1	19		T2	1391		T3	1
values[0x0]	1737212	1			T1	3		T2	450		T3	7
values[0x1]	1737031	1			T1	7		T2	449		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2549864	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5081870

1

T1

10

T2

1738

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29075	1			T6	34		T8	16		T10	15
valid_sources[0x01]	28624	1			T6	30		T8	14		T10	7
valid_sources[0x02]	32048	1			T6	17		T10	6		T12	98
valid_sources[0x03]	29272	1			T6	57		T8	3		T10	16
valid_sources[0x04]	33142	1			T2	1		T6	44		T7	22
valid_sources[0x05]	28341	1			T6	39		T8	7		T10	6
valid_sources[0x06]	28901	1			T6	19		T8	19		T10	11
valid_sources[0x07]	29945	1			T6	31		T10	13		T12	62
valid_sources[0x08]	28293	1			T6	29		T8	10		T10	4
valid_sources[0x09]	33103	1			T2	1448		T6	24		T10	8
valid_sources[0x0a]	27429	1			T6	34		T12	57		T14	17
valid_sources[0x0b]	35924	1			T6	50		T8	1		T10	8
valid_sources[0x0c]	30111	1			T6	22		T10	8		T12	60
valid_sources[0x0d]	28008	1			T6	31		T8	3		T10	8
valid_sources[0x0e]	30242	1			T6	9		T8	1		T10	8
valid_sources[0x0f]	28041	1			T6	22		T8	6		T10	1
valid_sources[0x10]	27930	1			T3	1		T6	33		T10	18
valid_sources[0x11]	30235	1			T2	1		T4	8		T6	34
valid_sources[0x12]	32191	1			T4	5		T6	33		T10	5
valid_sources[0x13]	27956	1			T6	35		T8	3		T10	9
valid_sources[0x14]	30437	1			T6	24		T8	4		T10	10
valid_sources[0x15]	30316	1			T3	1		T4	7		T6	35
valid_sources[0x16]	31434	1			T3	1		T4	2		T6	16
valid_sources[0x17]	27385	1			T6	30		T7	40		T8	6
valid_sources[0x18]	28225	1			T6	30		T7	30		T8	2
valid_sources[0x19]	27296	1			T6	23		T8	5		T10	14
valid_sources[0x1a]	37385	1			T6	18		T8	5		T10	7
valid_sources[0x1b]	27637	1			T4	5		T6	7		T8	4
valid_sources[0x1c]	30062	1			T4	15		T6	41		T10	18
valid_sources[0x1d]	27441	1			T4	2		T6	65		T8	2
valid_sources[0x1e]	28935	1			T6	18		T8	4		T10	13
valid_sources[0x1f]	27825	1			T4	1		T6	7		T8	16
valid_sources[0x20]	28267	1			T6	27		T8	2		T10	14
valid_sources[0x21]	29360	1			T2	11		T4	5		T6	21
valid_sources[0x22]	30212	1			T4	5		T6	39		T10	17
valid_sources[0x23]	28510	1			T6	62		T8	4		T10	12
valid_sources[0x24]	27444	1			T6	40		T7	47		T8	5
valid_sources[0x25]	30285	1			T2	1		T4	19		T6	17
valid_sources[0x26]	33814	1			T4	3		T6	3		T8	7
valid_sources[0x27]	30308	1			T6	9		T8	10		T10	10
valid_sources[0x28]	30290	1			T6	29		T7	28		T8	4
valid_sources[0x29]	28916	1			T6	17		T8	1		T10	7
valid_sources[0x2a]	30152	1			T4	3		T6	20		T7	27
valid_sources[0x2b]	33303	1			T4	11		T6	14		T8	12
valid_sources[0x2c]	29148	1			T6	30		T8	3		T10	15
valid_sources[0x2d]	35159	1			T6	16		T8	12		T10	2
valid_sources[0x2e]	27782	1			T6	25		T10	14		T12	64
valid_sources[0x2f]	27467	1			T6	25		T8	12		T10	15
valid_sources[0x30]	27211	1			T6	34		T8	5		T10	7
valid_sources[0x31]	28588	1			T6	25		T7	14		T8	3
valid_sources[0x32]	29779	1			T4	10		T6	78		T10	11
valid_sources[0x33]	28961	1			T6	10		T8	2		T10	12
valid_sources[0x34]	29164	1			T4	50		T6	15		T8	6
valid_sources[0x35]	29291	1			T6	43		T8	6		T10	19
valid_sources[0x36]	32068	1			T6	53		T8	9		T10	15
valid_sources[0x37]	28342	1			T4	2		T6	37		T10	13
valid_sources[0x38]	27889	1			T6	35		T8	7		T10	11
valid_sources[0x39]	27462	1			T6	45		T8	5		T10	17
valid_sources[0x3a]	30885	1			T4	1		T6	12		T8	13
valid_sources[0x3b]	28856	1			T6	40		T8	9		T10	12
valid_sources[0x3c]	28949	1			T4	8		T6	27		T8	9
valid_sources[0x3d]	28195	1			T6	30		T10	11		T12	85
valid_sources[0x3e]	31851	1			T4	13		T6	42		T8	1
valid_sources[0x3f]	28948	1			T2	2		T6	33		T8	7
valid_sources[0x40]	28247	1			T2	399		T6	20		T8	1
valid_sources[0x41]	28443	1			T4	4		T6	51		T10	18
valid_sources[0x42]	29296	1			T4	4		T6	45		T8	1
valid_sources[0x43]	31233	1			T4	2		T6	86		T10	12
valid_sources[0x44]	28701	1			T6	28		T8	5		T10	5
valid_sources[0x45]	28736	1			T6	19		T10	15		T12	42
valid_sources[0x46]	56990	1			T4	11		T6	11		T7	26
valid_sources[0x47]	27338	1			T3	1		T4	6		T6	23
valid_sources[0x48]	28829	1			T6	35		T8	1		T10	10
valid_sources[0x49]	31094	1			T4	5		T6	64		T8	1
valid_sources[0x4a]	30035	1			T4	1		T6	29		T10	5
valid_sources[0x4b]	27861	1			T6	28		T8	3		T10	6
valid_sources[0x4c]	36883	1			T6	24		T10	15		T12	72
valid_sources[0x4d]	29881	1			T4	1		T6	64		T10	14
valid_sources[0x4e]	30499	1			T6	36		T8	3		T10	3
valid_sources[0x4f]	28259	1			T6	21		T8	1		T10	11
valid_sources[0x50]	27783	1			T6	49		T10	14		T12	56
valid_sources[0x51]	29566	1			T2	1		T6	29		T10	14
valid_sources[0x52]	30127	1			T6	30		T8	7		T10	13
valid_sources[0x53]	30624	1			T4	3		T6	29		T8	1
valid_sources[0x54]	28328	1			T4	9		T6	4		T8	3
valid_sources[0x55]	29315	1			T4	16		T6	20		T8	2
valid_sources[0x56]	29366	1			T6	27		T10	19		T12	67
valid_sources[0x57]	29954	1			T4	8		T6	23		T8	3
valid_sources[0x58]	32555	1			T6	23		T10	9		T12	86
valid_sources[0x59]	28417	1			T2	1		T3	2		T4	14
valid_sources[0x5a]	29143	1			T4	22		T6	30		T10	14
valid_sources[0x5b]	29651	1			T3	1		T4	22		T6	20
valid_sources[0x5c]	27767	1			T3	1		T6	37		T10	6
valid_sources[0x5d]	35885	1			T6	21		T10	12		T12	37
valid_sources[0x5e]	28757	1			T6	36		T8	2		T10	13
valid_sources[0x5f]	31745	1			T6	48		T8	1		T10	10
valid_sources[0x60]	28623	1			T4	1		T6	11		T8	12
valid_sources[0x61]	30369	1			T3	1		T6	5		T8	2
valid_sources[0x62]	31171	1			T4	28		T6	8		T8	5
valid_sources[0x63]	30475	1			T6	15		T7	8		T8	13
valid_sources[0x64]	33290	1			T6	51		T10	24		T12	76
valid_sources[0x65]	30793	1			T2	1		T4	5		T6	63
valid_sources[0x66]	27899	1			T2	1		T4	9		T6	30
valid_sources[0x67]	31034	1			T6	33		T10	11		T12	52
valid_sources[0x68]	32115	1			T4	25		T6	29		T10	25
valid_sources[0x69]	28357	1			T6	12		T7	72		T10	9
valid_sources[0x6a]	31364	1			T4	9		T6	10		T8	6
valid_sources[0x6b]	30210	1			T4	26		T6	24		T8	1
valid_sources[0x6c]	28919	1			T4	1		T6	54		T8	1
valid_sources[0x6d]	29975	1			T6	76		T8	1		T10	17
valid_sources[0x6e]	31155	1			T4	8		T6	16		T8	5
valid_sources[0x6f]	27861	1			T4	6		T6	17		T10	13
valid_sources[0x70]	30179	1			T4	4		T6	18		T10	17
valid_sources[0x71]	29254	1			T6	33		T10	17		T12	35
valid_sources[0x72]	29629	1			T4	56		T6	54		T7	2
valid_sources[0x73]	28532	1			T6	25		T10	14		T12	62
valid_sources[0x74]	27874	1			T2	188		T6	46		T10	17
valid_sources[0x75]	28249	1			T6	38		T8	2		T10	8
valid_sources[0x76]	28501	1			T2	2		T6	28		T10	15
valid_sources[0x77]	28475	1			T6	56		T8	1		T10	7
valid_sources[0x78]	29541	1			T6	76		T8	6		T10	21
valid_sources[0x79]	29770	1			T6	48		T7	142		T10	5
valid_sources[0x7a]	29300	1			T4	7		T6	54		T7	8
valid_sources[0x7b]	28049	1			T6	26		T8	2		T10	26
valid_sources[0x7c]	29340	1			T4	3		T6	21		T10	21
valid_sources[0x7d]	33394	1			T5	9		T6	9		T8	16
valid_sources[0x7e]	27848	1			T6	46		T8	3		T10	9
valid_sources[0x7f]	30164	1			T2	1		T6	26		T10	6
valid_sources[0x80]	28471	1			T6	9		T8	10		T10	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

891645

1

T1

4

T2

712

T3

1

values[0x0]

all_enables

biggest_size

1575043

1

T1

1

T2

448

T3

3

values[0x1]

all_enables

biggest_size

1549712

1

T1

2

T2

448

T3

2