Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3633785

1

T1

22

T2

682

T3

9

full_word

4017410

1

T1

7

T2

1608

T3

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7650745	1			T1	29		T2	2290		T3	15
auto[TlIntgErrCmd]	140	1			T94	4		T95	8		T96	9
auto[TlIntgErrData]	147	1			T94	4		T95	10		T96	6
auto[TlIntgErrBoth]	163	1			T94	2		T95	12		T96	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4160510

1

T1

19

T2

1391

T3

1

auto[1]

3490685

1

T1

10

T2

899

T3

14

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3268431	1			T1	15		T2	679		T4	2
auto[TlIntgErrNone]	partial	auto[1]	364948	1			T1	7		T2	3		T3	9
auto[TlIntgErrNone]	full_word	auto[0]	891885	1			T1	4		T2	712		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3125481	1			T1	3		T2	896		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T94	3		T95	3		T153	3
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T94	1		T95	5		T96	6
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T182	1		T183	1		T184	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T96	3		T154	1		T178	2
auto[TlIntgErrData]	partial	auto[0]	68	1			T94	3		T95	2		T96	4
auto[TlIntgErrData]	partial	auto[1]	63	1			T94	1		T95	6		T96	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T95	2		T153	1		T183	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T154	2		T180	1		T178	1
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T95	2		T96	1		T153	2
auto[TlIntgErrBoth]	partial	auto[1]	94	1			T94	1		T95	9		T96	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T94	1		T95	1		T156	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T154	1		T177	1		T185	1