Unified Coverage Report :: Module :: spid_status

Module : spid_status

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.31	100.00	100.00			97.22	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_status	99.31	100.00	100.00			97.22	100.00

---

Module Instance : tb.dut.u_spid_status

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.31	100.00	100.00			97.22	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	97.83			98.63	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.62	93.89	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sck2csb_status	100.00	100.00				100.00
u_stage_to_commit	100.00	100.00				100.00
u_sw_status_update_sync	99.00	100.00	96.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_status

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
ALWAYS	159	6	6	100.00
ALWAYS	170	8	8	100.00
ALWAYS	183	4	4	100.00
ALWAYS	195	7	7	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
ALWAYS	256	3	3	100.00
CONT_ASSIGN	262	1	1	100.00
ALWAYS	293	4	4	100.00
ALWAYS	306	5	5	100.00
ALWAYS	320	3	3	100.00
ALWAYS	328	6	6	100.00
CONT_ASSIGN	342	1	1	100.00
ALWAYS	349	3	3	100.00
ALWAYS	354	9	9	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
91	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
170	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
186	1	1
			MISSING_ELSE
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
			MISSING_ELSE
201	1	1
202	1	1
			MISSING_ELSE
217	1	1
218	1	1
233	1	1
256	1	1
257	1	1
259	1	1
262	1	1
293	1	1
294	1	1
295	1	1
296	1	1
			MISSING_ELSE
306	1	1
307	1	1
308	1	1
310	1	1
311	1	1
320	1	1
321	1	1
323	1	1
328	1	1
330	1	1
332	1	1
334	1	1
335	1	1
336	1	1
			MISSING_ELSE
			MISSING_ELSE
342	1	1
349	2	2
350	1	1
354	1	1
356	1	1
358	1	1
360	1	1
362	1	1
363	1	1
365	1	1
366	1	1
			MISSING_ELSE
371	1	1

---

Cond Coverage for Module : spid_status

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       163
 EXPRESSION (sck_sw_we && (sck_sw_status[BitBusy] == 1'b0))
             ----1----    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T7,T10,T12
1	1	Covered	T10,T12,T15

 LINE       163
 SUB-EXPRESSION (sck_sw_status[BitBusy] == 1'b0)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T7,T10,T12
1	Covered	T1,T2,T4

 LINE       176
 EXPRESSION (sck_sw_we && (sck_sw_status[BitWe] == 1'b0))
             ----1----    ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T7,T10,T12
1	1	Covered	T7,T10,T12

 LINE       176
 SUB-EXPRESSION (sck_sw_status[BitWe] == 1'b0)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T7,T10,T12
1	Covered	T1,T2,T4

 LINE       262
 EXPRESSION (sys_rst_ni & status_fifo_clr_n)
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T13,T23,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION (cmd_info_idx_i == 5'(StatusCmdIdx[i]))
            -------------------1-------------------

-1-	Status	Tests
0	Covered	T2,T12,T15
1	Covered	T2,T12,T15

 LINE       342
 EXPRESSION ((st_q == StIdle) ? sck_status_committed[(8 * byte_sel_d)+:8] : sck_status_committed[(8 * byte_sel_q)+:8])
             --------1-------

-1-	Status	Tests
0	Covered	T2,T12,T15
1	Covered	T1,T2,T3

 LINE       342
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       362
 EXPRESSION (sel_dp_i == DpReadStatus)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T12,T15

---

Branch Coverage for Module : spid_status

	Line No.	Total	Covered	Percent
Branches		36	35	97.22
TERNARY	342	2	2	100.00
IF	159	4	4	100.00
IF	170	5	5	100.00
IF	183	3	3	100.00
IF	196	3	3	100.00
IF	201	2	2	100.00
IF	256	2	2	100.00
IF	293	3	3	100.00
IF	306	2	2	100.00
IF	320	2	2	100.00
IF	330	2	2	100.00
IF	349	2	2	100.00
CASE	360	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	342	((st_q == StIdle)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T12,T15

	LineNo.	Expression
-1-:	159	if ((!sys_rst_ni))
-2-:	161	if (inclk_busy_set_i)
-3-:	163	if ((sck_sw_we && (sck_sw_status[BitBusy] == 1'b0)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T12,T15,T17
0	0	1	Covered	T10,T12,T15
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	170	if ((!sys_rst_ni))
-2-:	172	if (inclk_we_set_i)
-3-:	174	if (inclk_we_clr_i)
-4-:	176	if ((sck_sw_we && (sck_sw_status[BitWe] == 1'b0)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T12,T17,T18
0	0	1	-	Covered	T12,T17,T18
0	0	0	1	Covered	T7,T10,T12
0	0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	183	if ((!sys_rst_ni))
-2-:	185	if (sck_sw_we)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T7,T10,T12
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	196	if (inclk_we_set_i)
-2-:	198	if (inclk_we_clr_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T17,T18
0	1	Covered	T12,T17,T18
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	201	if (inclk_busy_set_i)

Branches:

-1-	Status	Tests
1	Covered	T12,T15,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	256	if ((!sys_rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	if ((!sys_rst_ni))
-2-:	295	if (sys_csb_deasserted_pulse_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T4,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	306	if ((!rst_out_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	320	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	330	if (byte_sel_update)

Branches:

-1-	Status	Tests
1	Covered	T2,T12,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	360	case (st_q)
-2-:	362	if ((sel_dp_i == DpReadStatus))

Branches:

-1-	-2-	Status	Tests
StIdle	1	Covered	T2,T12,T15
StIdle	0	Covered	T1,T2,T3
StActive	-	Covered	T2,T12,T15
default	-	Not Covered

---

Assert Coverage for Module : spid_status

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusyBitZero_A	906	906	0	0

BusyBitZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0