Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T12
1	0	Covered	T1,T6,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T9
1	0	Unreachable
1	1	Covered	T1,T6,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T15,T17

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T15,T17
1	0	Covered	T12,T15,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Unreachable
1	1	Covered	T12,T15,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T12
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	678585063	535563267	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	678585063	3300318	0	0
GntImpliesValid_A	678585063	3300318	0	0
GrantKnown_A	678585063	535563267	0	0
IdxKnown_A	678585063	535563267	0	0
IndexIsCorrect_A	678585063	3300318	0	0
LockArbDecision_A	678585063	0	0	0
NoReadyValidNoGrant_A	678585063	0	0	0
ReadyAndValidImplyGrant_A	678585063	3300318	0	0
ReqAndReadyImplyGrant_A	678585063	3300318	0	0
ReqImpliesValid_A	678585063	3300318	0	0
ReqStaysHighUntilGranted0_M	678585063	0	0	0
RoundRobin_A	678585063	3	0	906
ValidKnown_A	678585063	535563267	0	0
gen_data_port_assertion.DataFlow_A	678585063	3300318	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678585063	535563267	0	0
T1	1945	1895	0	0
T2	1237296	1114103	0	0
T3	840	754	0	0
T4	1085275	965605	0	0
T5	814	724	0	0
T6	743656	505532	0	0
T7	23075	18868	0	0
T8	364805	220196	0	0
T9	65162	57620	0	0
T10	69225	52157	0	0
T11	432	216	0	0
T12	1855898	919533	0	0
T14	25492	25492	0	0
T15	0	95888	0	0
T16	0	105720	0	0
T17	0	785398	0	0
T18	0	137776	0	0
T19	0	2176	0	0
T20	0	19808	0	0
T21	0	64222	0	0
T23	0	96048	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678585063	3300318	0	0
T1	1945	13	0	0
T2	1114522	832	0	0
T3	840	0	0	0
T4	965703	832	0	0
T5	814	0	0	0
T6	509312	8418	0	0
T7	18963	832	0	0
T8	220263	832	0	0
T9	58375	0	0	0
T10	52683	832	0	0
T11	216	0	0	0
T12	1855898	12556	0	0
T14	25492	832	0	0
T15	96650	866	0	0
T16	112086	0	0	0
T17	785952	5020	0	0
T18	302179	11420	0	0
T19	0	76	0	0
T21	64222	0	0	0
T23	0	4245	0	0
T24	0	2746	0	0
T25	0	166	0	0
T26	0	9097	0	0
T27	0	3335	0	0
T28	0	404	0	0
T36	4112	0	0	0
T37	47948	0	0	0
T38	46884	0	0	0
T44	0	1156	0	0
T45	0	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678585063	3300318	0	0
T1	1945	13	0	0
T2	1114522	832	0	0
T3	840	0	0	0
T4	965703	832	0	0
T5	814	0	0	0
T6	509312	8418	0	0
T7	18963	832	0	0
T8	220263	832	0	0
T9	58375	0	0	0
T10	52683	832	0	0
T11	216	0	0	0
T12	1855898	12556	0	0
T14	25492	832	0	0
T15	96650	866	0	0
T16	112086	0	0	0
T17	785952	5020	0	0
T18	302179	11420	0	0
T19	0	76	0	0
T21	64222	0	0	0
T23	0	4245	0	0
T24	0	2746	0	0
T25	0	166	0	0
T26	0	9097	0	0
T27	0	3335	0	0
T28	0	404	0	0
T36	4112	0	0	0
T37	47948	0	0	0
T38	46884	0	0	0
T44	0	1156	0	0
T45	0	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678585063	535563267	0	0
T1	1945	1895	0	0
T2	1237296	1114103	0	0
T3	840	754	0	0
T4	1085275	965605	0	0
T5	814	724	0	0
T6	743656	505532	0	0
T7	23075	18868	0	0
T8	364805	220196	0	0
T9	65162	57620	0	0
T10	69225	52157	0	0
T11	432	216	0	0
T12	1855898	919533	0	0
T14	25492	25492	0	0
T15	0	95888	0	0
T16	0	105720	0	0
T17	0	785398	0	0
T18	0	137776	0	0
T19	0	2176	0	0
T20	0	19808	0	0
T21	0	64222	0	0
T23	0	96048	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678585063	535563267	0	0
T1	1945	1895	0	0
T2	1237296	1114103	0	0
T3	840	754	0	0
T4	1085275	965605	0	0
T5	814	724	0	0
T6	743656	505532	0	0
T7	23075	18868	0	0
T8	364805	220196	0	0
T9	65162	57620	0	0
T10	69225	52157	0	0
T11	432	216	0	0
T12	1855898	919533	0	0
T14	25492	25492	0	0
T15	0	95888	0	0
T16	0	105720	0	0
T17	0	785398	0	0
T18	0	137776	0	0
T19	0	2176	0	0
T20	0	19808	0	0
T21	0	64222	0	0
T23	0	96048	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678585063	3300318	0	0
T1	1945	13	0	0
T2	1114522	832	0	0
T3	840	0	0	0
T4	965703	832	0	0
T5	814	0	0	0
T6	509312	8418	0	0
T7	18963	832	0	0
T8	220263	832	0	0
T9	58375	0	0	0
T10	52683	832	0	0
T11	216	0	0	0
T12	1855898	12556	0	0
T14	25492	832	0	0
T15	96650	866	0	0
T16	112086	0	0	0
T17	785952	5020	0	0
T18	302179	11420	0	0
T19	0	76	0	0
T21	64222	0	0	0
T23	0	4245	0	0
T24	0	2746	0	0
T25	0	166	0	0
T26	0	9097	0	0
T27	0	3335	0	0
T28	0	404	0	0
T36	4112	0	0	0
T37	47948	0	0	0
T38	46884	0	0	0
T44	0	1156	0	0
T45	0	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678585063	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678585063	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678585063	3300318	0	0
T1	1945	13	0	0
T2	1114522	832	0	0
T3	840	0	0	0
T4	965703	832	0	0
T5	814	0	0	0
T6	509312	8418	0	0
T7	18963	832	0	0
T8	220263	832	0	0
T9	58375	0	0	0
T10	52683	832	0	0
T11	216	0	0	0
T12	1855898	12556	0	0
T14	25492	832	0	0
T15	96650	866	0	0
T16	112086	0	0	0
T17	785952	5020	0	0
T18	302179	11420	0	0
T19	0	76	0	0
T21	64222	0	0	0
T23	0	4245	0	0
T24	0	2746	0	0
T25	0	166	0	0
T26	0	9097	0	0
T27	0	3335	0	0
T28	0	404	0	0
T36	4112	0	0	0
T37	47948	0	0	0
T38	46884	0	0	0
T44	0	1156	0	0
T45	0	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678585063	3300318	0	0
T1	1945	13	0	0
T2	1114522	832	0	0
T3	840	0	0	0
T4	965703	832	0	0
T5	814	0	0	0
T6	509312	8418	0	0
T7	18963	832	0	0
T8	220263	832	0	0
T9	58375	0	0	0
T10	52683	832	0	0
T11	216	0	0	0
T12	1855898	12556	0	0
T14	25492	832	0	0
T15	96650	866	0	0
T16	112086	0	0	0
T17	785952	5020	0	0
T18	302179	11420	0	0
T19	0	76	0	0
T21	64222	0	0	0
T23	0	4245	0	0
T24	0	2746	0	0
T25	0	166	0	0
T26	0	9097	0	0
T27	0	3335	0	0
T28	0	404	0	0
T36	4112	0	0	0
T37	47948	0	0	0
T38	46884	0	0	0
T44	0	1156	0	0
T45	0	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678585063	3300318	0	0
T1	1945	13	0	0
T2	1114522	832	0	0
T3	840	0	0	0
T4	965703	832	0	0
T5	814	0	0	0
T6	509312	8418	0	0
T7	18963	832	0	0
T8	220263	832	0	0
T9	58375	0	0	0
T10	52683	832	0	0
T11	216	0	0	0
T12	1855898	12556	0	0
T14	25492	832	0	0
T15	96650	866	0	0
T16	112086	0	0	0
T17	785952	5020	0	0
T18	302179	11420	0	0
T19	0	76	0	0
T21	64222	0	0	0
T23	0	4245	0	0
T24	0	2746	0	0
T25	0	166	0	0
T26	0	9097	0	0
T27	0	3335	0	0
T28	0	404	0	0
T36	4112	0	0	0
T37	47948	0	0	0
T38	46884	0	0	0
T44	0	1156	0	0
T45	0	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	678585063	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678585063	3	0	906
T33	384037	1	0	1
T34	988604	0	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	27935	0	0	1
T49	35321	0	0	1
T50	3045	0	0	1
T51	1747	0	0	1
T52	4573	0	0	1
T53	364413	0	0	1
T54	1680	0	0	1
T55	155655	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678585063	535563267	0	0
T1	1945	1895	0	0
T2	1237296	1114103	0	0
T3	840	754	0	0
T4	1085275	965605	0	0
T5	814	724	0	0
T6	743656	505532	0	0
T7	23075	18868	0	0
T8	364805	220196	0	0
T9	65162	57620	0	0
T10	69225	52157	0	0
T11	432	216	0	0
T12	1855898	919533	0	0
T14	25492	25492	0	0
T15	0	95888	0	0
T16	0	105720	0	0
T17	0	785398	0	0
T18	0	137776	0	0
T19	0	2176	0	0
T20	0	19808	0	0
T21	0	64222	0	0
T23	0	96048	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	678585063	3300318	0	0
T1	1945	13	0	0
T2	1114522	832	0	0
T3	840	0	0	0
T4	965703	832	0	0
T5	814	0	0	0
T6	509312	8418	0	0
T7	18963	832	0	0
T8	220263	832	0	0
T9	58375	0	0	0
T10	52683	832	0	0
T11	216	0	0	0
T12	1855898	12556	0	0
T14	25492	832	0	0
T15	96650	866	0	0
T16	112086	0	0	0
T17	785952	5020	0	0
T18	302179	11420	0	0
T19	0	76	0	0
T21	64222	0	0	0
T23	0	4245	0	0
T24	0	2746	0	0
T25	0	166	0	0
T26	0	9097	0	0
T27	0	3335	0	0
T28	0	404	0	0
T36	4112	0	0	0
T37	47948	0	0	0
T38	46884	0	0	0
T44	0	1156	0	0
T45	0	2	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T12
1	0	Covered	T1,T6,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T9
1	0	Unreachable
1	1	Covered	T1,T6,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T6,T12
0	0	1	Unreachable
0	0	0	Covered	T1,T6,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	141591902	30750811	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	141591902	643660	0	0
GntImpliesValid_A	141591902	643660	0	0
GrantKnown_A	141591902	30750811	0	0
IdxKnown_A	141591902	30750811	0	0
IndexIsCorrect_A	141591902	643660	0	0
LockArbDecision_A	141591902	0	0	0
NoReadyValidNoGrant_A	141591902	0	0	0
ReadyAndValidImplyGrant_A	141591902	643660	0	0
ReqAndReadyImplyGrant_A	141591902	643660	0	0
ReqImpliesValid_A	141591902	643660	0	0
ReqStaysHighUntilGranted0_M	141591902	0	0	0
RoundRobin_A	141591902	0	0	0
ValidKnown_A	141591902	30750811	0	0
gen_data_port_assertion.DataFlow_A	141591902	643660	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	30750811	0	0
T1	552	552	0	0
T2	122774	0	0	0
T4	119572	0	0	0
T6	234344	230664	0	0
T7	4112	0	0	0
T8	144542	0	0	0
T9	6787	6112	0	0
T10	16542	0	0	0
T11	216	216	0	0
T12	927949	330416	0	0
T16	0	105720	0	0
T18	0	137776	0	0
T19	0	2176	0	0
T20	0	19808	0	0
T23	0	96048	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	643660	0	0
T1	552	9	0	0
T2	122774	0	0	0
T4	119572	0	0	0
T6	234344	5715	0	0
T7	4112	0	0	0
T8	144542	0	0	0
T9	6787	0	0	0
T10	16542	0	0	0
T11	216	0	0	0
T12	927949	3578	0	0
T18	0	5920	0	0
T19	0	76	0	0
T23	0	4245	0	0
T24	0	2746	0	0
T25	0	166	0	0
T26	0	6880	0	0
T44	0	505	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	643660	0	0
T1	552	9	0	0
T2	122774	0	0	0
T4	119572	0	0	0
T6	234344	5715	0	0
T7	4112	0	0	0
T8	144542	0	0	0
T9	6787	0	0	0
T10	16542	0	0	0
T11	216	0	0	0
T12	927949	3578	0	0
T18	0	5920	0	0
T19	0	76	0	0
T23	0	4245	0	0
T24	0	2746	0	0
T25	0	166	0	0
T26	0	6880	0	0
T44	0	505	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	30750811	0	0
T1	552	552	0	0
T2	122774	0	0	0
T4	119572	0	0	0
T6	234344	230664	0	0
T7	4112	0	0	0
T8	144542	0	0	0
T9	6787	6112	0	0
T10	16542	0	0	0
T11	216	216	0	0
T12	927949	330416	0	0
T16	0	105720	0	0
T18	0	137776	0	0
T19	0	2176	0	0
T20	0	19808	0	0
T23	0	96048	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	30750811	0	0
T1	552	552	0	0
T2	122774	0	0	0
T4	119572	0	0	0
T6	234344	230664	0	0
T7	4112	0	0	0
T8	144542	0	0	0
T9	6787	6112	0	0
T10	16542	0	0	0
T11	216	216	0	0
T12	927949	330416	0	0
T16	0	105720	0	0
T18	0	137776	0	0
T19	0	2176	0	0
T20	0	19808	0	0
T23	0	96048	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	643660	0	0
T1	552	9	0	0
T2	122774	0	0	0
T4	119572	0	0	0
T6	234344	5715	0	0
T7	4112	0	0	0
T8	144542	0	0	0
T9	6787	0	0	0
T10	16542	0	0	0
T11	216	0	0	0
T12	927949	3578	0	0
T18	0	5920	0	0
T19	0	76	0	0
T23	0	4245	0	0
T24	0	2746	0	0
T25	0	166	0	0
T26	0	6880	0	0
T44	0	505	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	643660	0	0
T1	552	9	0	0
T2	122774	0	0	0
T4	119572	0	0	0
T6	234344	5715	0	0
T7	4112	0	0	0
T8	144542	0	0	0
T9	6787	0	0	0
T10	16542	0	0	0
T11	216	0	0	0
T12	927949	3578	0	0
T18	0	5920	0	0
T19	0	76	0	0
T23	0	4245	0	0
T24	0	2746	0	0
T25	0	166	0	0
T26	0	6880	0	0
T44	0	505	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	643660	0	0
T1	552	9	0	0
T2	122774	0	0	0
T4	119572	0	0	0
T6	234344	5715	0	0
T7	4112	0	0	0
T8	144542	0	0	0
T9	6787	0	0	0
T10	16542	0	0	0
T11	216	0	0	0
T12	927949	3578	0	0
T18	0	5920	0	0
T19	0	76	0	0
T23	0	4245	0	0
T24	0	2746	0	0
T25	0	166	0	0
T26	0	6880	0	0
T44	0	505	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	643660	0	0
T1	552	9	0	0
T2	122774	0	0	0
T4	119572	0	0	0
T6	234344	5715	0	0
T7	4112	0	0	0
T8	144542	0	0	0
T9	6787	0	0	0
T10	16542	0	0	0
T11	216	0	0	0
T12	927949	3578	0	0
T18	0	5920	0	0
T19	0	76	0	0
T23	0	4245	0	0
T24	0	2746	0	0
T25	0	166	0	0
T26	0	6880	0	0
T44	0	505	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	30750811	0	0
T1	552	552	0	0
T2	122774	0	0	0
T4	119572	0	0	0
T6	234344	230664	0	0
T7	4112	0	0	0
T8	144542	0	0	0
T9	6787	6112	0	0
T10	16542	0	0	0
T11	216	216	0	0
T12	927949	330416	0	0
T16	0	105720	0	0
T18	0	137776	0	0
T19	0	2176	0	0
T20	0	19808	0	0
T23	0	96048	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	643660	0	0
T1	552	9	0	0
T2	122774	0	0	0
T4	119572	0	0	0
T6	234344	5715	0	0
T7	4112	0	0	0
T8	144542	0	0	0
T9	6787	0	0	0
T10	16542	0	0	0
T11	216	0	0	0
T12	927949	3578	0	0
T18	0	5920	0	0
T19	0	76	0	0
T23	0	4245	0	0
T24	0	2746	0	0
T25	0	166	0	0
T26	0	6880	0	0
T44	0	505	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T15,T17

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T15,T17
1	0	Covered	T12,T15,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Unreachable
1	1	Covered	T12,T15,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T15,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T12,T15,T17
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T12,T15,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T12,T15,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	141591902	109491670	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	141591902	546877	0	0
GntImpliesValid_A	141591902	546877	0	0
GrantKnown_A	141591902	109491670	0	0
IdxKnown_A	141591902	109491670	0	0
IndexIsCorrect_A	141591902	546877	0	0
LockArbDecision_A	141591902	0	0	0
NoReadyValidNoGrant_A	141591902	0	0	0
ReadyAndValidImplyGrant_A	141591902	546877	0	0
ReqAndReadyImplyGrant_A	141591902	546877	0	0
ReqImpliesValid_A	141591902	546877	0	0
ReqStaysHighUntilGranted0_M	141591902	0	0	0
RoundRobin_A	141591902	0	0	0
ValidKnown_A	141591902	109491670	0	0
gen_data_port_assertion.DataFlow_A	141591902	546877	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	109491670	0	0
T2	122774	122444	0	0
T4	119572	119572	0	0
T6	234344	0	0	0
T7	4112	4112	0	0
T8	144542	144542	0	0
T9	6787	0	0	0
T10	16542	16089	0	0
T11	216	0	0	0
T12	927949	589117	0	0
T14	25492	25492	0	0
T15	0	95888	0	0
T17	0	785398	0	0
T21	0	64222	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	546877	0	0
T12	927949	398	0	0
T14	25492	0	0	0
T15	96650	20	0	0
T16	112086	0	0	0
T17	785952	5020	0	0
T18	302179	5500	0	0
T21	64222	0	0	0
T26	0	2217	0	0
T27	0	3335	0	0
T28	0	404	0	0
T36	4112	0	0	0
T37	47948	0	0	0
T38	46884	0	0	0
T44	0	651	0	0
T45	0	2	0	0
T56	0	6088	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	546877	0	0
T12	927949	398	0	0
T14	25492	0	0	0
T15	96650	20	0	0
T16	112086	0	0	0
T17	785952	5020	0	0
T18	302179	5500	0	0
T21	64222	0	0	0
T26	0	2217	0	0
T27	0	3335	0	0
T28	0	404	0	0
T36	4112	0	0	0
T37	47948	0	0	0
T38	46884	0	0	0
T44	0	651	0	0
T45	0	2	0	0
T56	0	6088	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	109491670	0	0
T2	122774	122444	0	0
T4	119572	119572	0	0
T6	234344	0	0	0
T7	4112	4112	0	0
T8	144542	144542	0	0
T9	6787	0	0	0
T10	16542	16089	0	0
T11	216	0	0	0
T12	927949	589117	0	0
T14	25492	25492	0	0
T15	0	95888	0	0
T17	0	785398	0	0
T21	0	64222	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	109491670	0	0
T2	122774	122444	0	0
T4	119572	119572	0	0
T6	234344	0	0	0
T7	4112	4112	0	0
T8	144542	144542	0	0
T9	6787	0	0	0
T10	16542	16089	0	0
T11	216	0	0	0
T12	927949	589117	0	0
T14	25492	25492	0	0
T15	0	95888	0	0
T17	0	785398	0	0
T21	0	64222	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	546877	0	0
T12	927949	398	0	0
T14	25492	0	0	0
T15	96650	20	0	0
T16	112086	0	0	0
T17	785952	5020	0	0
T18	302179	5500	0	0
T21	64222	0	0	0
T26	0	2217	0	0
T27	0	3335	0	0
T28	0	404	0	0
T36	4112	0	0	0
T37	47948	0	0	0
T38	46884	0	0	0
T44	0	651	0	0
T45	0	2	0	0
T56	0	6088	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	546877	0	0
T12	927949	398	0	0
T14	25492	0	0	0
T15	96650	20	0	0
T16	112086	0	0	0
T17	785952	5020	0	0
T18	302179	5500	0	0
T21	64222	0	0	0
T26	0	2217	0	0
T27	0	3335	0	0
T28	0	404	0	0
T36	4112	0	0	0
T37	47948	0	0	0
T38	46884	0	0	0
T44	0	651	0	0
T45	0	2	0	0
T56	0	6088	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	546877	0	0
T12	927949	398	0	0
T14	25492	0	0	0
T15	96650	20	0	0
T16	112086	0	0	0
T17	785952	5020	0	0
T18	302179	5500	0	0
T21	64222	0	0	0
T26	0	2217	0	0
T27	0	3335	0	0
T28	0	404	0	0
T36	4112	0	0	0
T37	47948	0	0	0
T38	46884	0	0	0
T44	0	651	0	0
T45	0	2	0	0
T56	0	6088	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	546877	0	0
T12	927949	398	0	0
T14	25492	0	0	0
T15	96650	20	0	0
T16	112086	0	0	0
T17	785952	5020	0	0
T18	302179	5500	0	0
T21	64222	0	0	0
T26	0	2217	0	0
T27	0	3335	0	0
T28	0	404	0	0
T36	4112	0	0	0
T37	47948	0	0	0
T38	46884	0	0	0
T44	0	651	0	0
T45	0	2	0	0
T56	0	6088	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	109491670	0	0
T2	122774	122444	0	0
T4	119572	119572	0	0
T6	234344	0	0	0
T7	4112	4112	0	0
T8	144542	144542	0	0
T9	6787	0	0	0
T10	16542	16089	0	0
T11	216	0	0	0
T12	927949	589117	0	0
T14	25492	25492	0	0
T15	0	95888	0	0
T17	0	785398	0	0
T21	0	64222	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141591902	546877	0	0
T12	927949	398	0	0
T14	25492	0	0	0
T15	96650	20	0	0
T16	112086	0	0	0
T17	785952	5020	0	0
T18	302179	5500	0	0
T21	64222	0	0	0
T26	0	2217	0	0
T27	0	3335	0	0
T28	0	404	0	0
T36	4112	0	0	0
T37	47948	0	0	0
T38	46884	0	0	0
T44	0	651	0	0
T45	0	2	0	0
T56	0	6088	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T12
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395401259	395320786	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	395401259	2109781	0	0
GntImpliesValid_A	395401259	2109781	0	0
GrantKnown_A	395401259	395320786	0	0
IdxKnown_A	395401259	395320786	0	0
IndexIsCorrect_A	395401259	2109781	0	0
LockArbDecision_A	395401259	0	0	0
NoReadyValidNoGrant_A	395401259	0	0	0
ReadyAndValidImplyGrant_A	395401259	2109781	0	0
ReqAndReadyImplyGrant_A	395401259	2109781	0	0
ReqImpliesValid_A	395401259	2109781	0	0
ReqStaysHighUntilGranted0_M	395401259	0	0	0
RoundRobin_A	395401259	3	0	906
ValidKnown_A	395401259	395320786	0	0
gen_data_port_assertion.DataFlow_A	395401259	2109781	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395401259	395320786	0	0
T1	1393	1343	0	0
T2	991748	991659	0	0
T3	840	754	0	0
T4	846131	846033	0	0
T5	814	724	0	0
T6	274968	274868	0	0
T7	14851	14756	0	0
T8	75721	75654	0	0
T9	51588	51508	0	0
T10	36141	36068	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395401259	2109781	0	0
T1	1393	4	0	0
T2	991748	832	0	0
T3	840	0	0	0
T4	846131	832	0	0
T5	814	0	0	0
T6	274968	2703	0	0
T7	14851	832	0	0
T8	75721	832	0	0
T9	51588	0	0	0
T10	36141	832	0	0
T12	0	8580	0	0
T14	0	832	0	0
T15	0	846	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395401259	2109781	0	0
T1	1393	4	0	0
T2	991748	832	0	0
T3	840	0	0	0
T4	846131	832	0	0
T5	814	0	0	0
T6	274968	2703	0	0
T7	14851	832	0	0
T8	75721	832	0	0
T9	51588	0	0	0
T10	36141	832	0	0
T12	0	8580	0	0
T14	0	832	0	0
T15	0	846	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395401259	395320786	0	0
T1	1393	1343	0	0
T2	991748	991659	0	0
T3	840	754	0	0
T4	846131	846033	0	0
T5	814	724	0	0
T6	274968	274868	0	0
T7	14851	14756	0	0
T8	75721	75654	0	0
T9	51588	51508	0	0
T10	36141	36068	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395401259	395320786	0	0
T1	1393	1343	0	0
T2	991748	991659	0	0
T3	840	754	0	0
T4	846131	846033	0	0
T5	814	724	0	0
T6	274968	274868	0	0
T7	14851	14756	0	0
T8	75721	75654	0	0
T9	51588	51508	0	0
T10	36141	36068	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395401259	2109781	0	0
T1	1393	4	0	0
T2	991748	832	0	0
T3	840	0	0	0
T4	846131	832	0	0
T5	814	0	0	0
T6	274968	2703	0	0
T7	14851	832	0	0
T8	75721	832	0	0
T9	51588	0	0	0
T10	36141	832	0	0
T12	0	8580	0	0
T14	0	832	0	0
T15	0	846	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395401259	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395401259	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395401259	2109781	0	0
T1	1393	4	0	0
T2	991748	832	0	0
T3	840	0	0	0
T4	846131	832	0	0
T5	814	0	0	0
T6	274968	2703	0	0
T7	14851	832	0	0
T8	75721	832	0	0
T9	51588	0	0	0
T10	36141	832	0	0
T12	0	8580	0	0
T14	0	832	0	0
T15	0	846	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395401259	2109781	0	0
T1	1393	4	0	0
T2	991748	832	0	0
T3	840	0	0	0
T4	846131	832	0	0
T5	814	0	0	0
T6	274968	2703	0	0
T7	14851	832	0	0
T8	75721	832	0	0
T9	51588	0	0	0
T10	36141	832	0	0
T12	0	8580	0	0
T14	0	832	0	0
T15	0	846	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395401259	2109781	0	0
T1	1393	4	0	0
T2	991748	832	0	0
T3	840	0	0	0
T4	846131	832	0	0
T5	814	0	0	0
T6	274968	2703	0	0
T7	14851	832	0	0
T8	75721	832	0	0
T9	51588	0	0	0
T10	36141	832	0	0
T12	0	8580	0	0
T14	0	832	0	0
T15	0	846	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395401259	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395401259	3	0	906
T33	384037	1	0	1
T34	988604	0	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	27935	0	0	1
T49	35321	0	0	1
T50	3045	0	0	1
T51	1747	0	0	1
T52	4573	0	0	1
T53	364413	0	0	1
T54	1680	0	0	1
T55	155655	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395401259	395320786	0	0
T1	1393	1343	0	0
T2	991748	991659	0	0
T3	840	754	0	0
T4	846131	846033	0	0
T5	814	724	0	0
T6	274968	274868	0	0
T7	14851	14756	0	0
T8	75721	75654	0	0
T9	51588	51508	0	0
T10	36141	36068	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395401259	2109781	0	0
T1	1393	4	0	0
T2	991748	832	0	0
T3	840	0	0	0
T4	846131	832	0	0
T5	814	0	0	0
T6	274968	2703	0	0
T7	14851	832	0	0
T8	75721	832	0	0
T9	51588	0	0	0
T10	36141	832	0	0
T12	0	8580	0	0
T14	0	832	0	0
T15	0	846	0	0