Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
3192 |
0 |
0 |
T60 |
10621 |
169 |
0 |
0 |
T61 |
7308 |
86 |
0 |
0 |
T62 |
6318 |
69 |
0 |
0 |
T94 |
10249 |
1 |
0 |
0 |
T95 |
78624 |
3 |
0 |
0 |
T97 |
11852 |
168 |
0 |
0 |
T108 |
3370 |
6 |
0 |
0 |
T110 |
2629 |
3 |
0 |
0 |
T111 |
3491 |
12 |
0 |
0 |
T112 |
2742 |
16 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
2933 |
0 |
0 |
T81 |
4364 |
8 |
0 |
0 |
T82 |
3101 |
2 |
0 |
0 |
T113 |
74082 |
447 |
0 |
0 |
T114 |
11075 |
17 |
0 |
0 |
T115 |
10024 |
7 |
0 |
0 |
T144 |
14176 |
60 |
0 |
0 |
T152 |
155466 |
243 |
0 |
0 |
T153 |
63187 |
56 |
0 |
0 |
T154 |
99047 |
93 |
0 |
0 |
T155 |
6500 |
10 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
2821 |
0 |
0 |
T81 |
4364 |
4 |
0 |
0 |
T101 |
20611 |
2 |
0 |
0 |
T113 |
74082 |
501 |
0 |
0 |
T114 |
11075 |
11 |
0 |
0 |
T115 |
10024 |
2 |
0 |
0 |
T144 |
14176 |
10 |
0 |
0 |
T152 |
155466 |
256 |
0 |
0 |
T153 |
63187 |
51 |
0 |
0 |
T154 |
99047 |
77 |
0 |
0 |
T155 |
6500 |
11 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
3291 |
0 |
0 |
T81 |
4364 |
20 |
0 |
0 |
T82 |
3101 |
2 |
0 |
0 |
T113 |
74082 |
444 |
0 |
0 |
T114 |
11075 |
12 |
0 |
0 |
T115 |
10024 |
16 |
0 |
0 |
T144 |
14176 |
34 |
0 |
0 |
T152 |
155466 |
292 |
0 |
0 |
T153 |
63187 |
123 |
0 |
0 |
T154 |
99047 |
88 |
0 |
0 |
T155 |
6500 |
1 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
9794 |
0 |
0 |
T81 |
4364 |
16 |
0 |
0 |
T82 |
3101 |
2 |
0 |
0 |
T113 |
74082 |
468 |
0 |
0 |
T114 |
11075 |
166 |
0 |
0 |
T115 |
10024 |
237 |
0 |
0 |
T144 |
14176 |
29 |
0 |
0 |
T152 |
155466 |
235 |
0 |
0 |
T153 |
63187 |
674 |
0 |
0 |
T154 |
99047 |
1101 |
0 |
0 |
T155 |
6500 |
8 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
10391 |
0 |
0 |
T81 |
4364 |
7 |
0 |
0 |
T101 |
20611 |
5 |
0 |
0 |
T113 |
74082 |
488 |
0 |
0 |
T114 |
11075 |
244 |
0 |
0 |
T115 |
10024 |
362 |
0 |
0 |
T144 |
14176 |
65 |
0 |
0 |
T152 |
155466 |
230 |
0 |
0 |
T153 |
63187 |
751 |
0 |
0 |
T154 |
99047 |
927 |
0 |
0 |
T155 |
6500 |
126 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
9555 |
0 |
0 |
T81 |
4364 |
10 |
0 |
0 |
T82 |
3101 |
8 |
0 |
0 |
T113 |
74082 |
425 |
0 |
0 |
T114 |
11075 |
240 |
0 |
0 |
T115 |
10024 |
143 |
0 |
0 |
T144 |
14176 |
43 |
0 |
0 |
T152 |
155466 |
262 |
0 |
0 |
T153 |
63187 |
300 |
0 |
0 |
T154 |
99047 |
878 |
0 |
0 |
T155 |
6500 |
105 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
9753 |
0 |
0 |
T82 |
3101 |
5 |
0 |
0 |
T113 |
74082 |
527 |
0 |
0 |
T114 |
11075 |
213 |
0 |
0 |
T115 |
10024 |
118 |
0 |
0 |
T144 |
14176 |
68 |
0 |
0 |
T152 |
155466 |
230 |
0 |
0 |
T153 |
63187 |
712 |
0 |
0 |
T154 |
99047 |
1518 |
0 |
0 |
T155 |
6500 |
121 |
0 |
0 |
T156 |
30394 |
167 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
9851 |
0 |
0 |
T81 |
4364 |
10 |
0 |
0 |
T82 |
3101 |
2 |
0 |
0 |
T113 |
74082 |
477 |
0 |
0 |
T114 |
11075 |
273 |
0 |
0 |
T115 |
10024 |
210 |
0 |
0 |
T144 |
14176 |
47 |
0 |
0 |
T152 |
155466 |
235 |
0 |
0 |
T153 |
63187 |
667 |
0 |
0 |
T154 |
99047 |
1181 |
0 |
0 |
T155 |
6500 |
140 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
9682 |
0 |
0 |
T60 |
10621 |
3 |
0 |
0 |
T81 |
4364 |
6 |
0 |
0 |
T113 |
74082 |
534 |
0 |
0 |
T114 |
11075 |
389 |
0 |
0 |
T115 |
10024 |
18 |
0 |
0 |
T144 |
14176 |
46 |
0 |
0 |
T152 |
155466 |
314 |
0 |
0 |
T153 |
63187 |
651 |
0 |
0 |
T154 |
99047 |
889 |
0 |
0 |
T155 |
6500 |
4 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
8820 |
0 |
0 |
T81 |
4364 |
10 |
0 |
0 |
T82 |
3101 |
9 |
0 |
0 |
T113 |
74082 |
488 |
0 |
0 |
T114 |
11075 |
277 |
0 |
0 |
T115 |
10024 |
256 |
0 |
0 |
T144 |
14176 |
61 |
0 |
0 |
T152 |
155466 |
293 |
0 |
0 |
T153 |
63187 |
878 |
0 |
0 |
T154 |
99047 |
1026 |
0 |
0 |
T155 |
6500 |
127 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
10329 |
0 |
0 |
T81 |
4364 |
9 |
0 |
0 |
T82 |
3101 |
1 |
0 |
0 |
T113 |
74082 |
507 |
0 |
0 |
T114 |
11075 |
133 |
0 |
0 |
T115 |
10024 |
5 |
0 |
0 |
T144 |
14176 |
17 |
0 |
0 |
T152 |
155466 |
323 |
0 |
0 |
T153 |
63187 |
1021 |
0 |
0 |
T154 |
99047 |
935 |
0 |
0 |
T155 |
6500 |
1 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5658 |
0 |
0 |
T81 |
4364 |
11 |
0 |
0 |
T113 |
74082 |
505 |
0 |
0 |
T114 |
11075 |
96 |
0 |
0 |
T115 |
10024 |
97 |
0 |
0 |
T120 |
10564 |
153 |
0 |
0 |
T144 |
14176 |
53 |
0 |
0 |
T152 |
155466 |
340 |
0 |
0 |
T153 |
63187 |
300 |
0 |
0 |
T154 |
99047 |
502 |
0 |
0 |
T156 |
30394 |
133 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5431 |
0 |
0 |
T81 |
4364 |
6 |
0 |
0 |
T82 |
3101 |
2 |
0 |
0 |
T113 |
74082 |
508 |
0 |
0 |
T114 |
11075 |
61 |
0 |
0 |
T115 |
10024 |
35 |
0 |
0 |
T144 |
14176 |
54 |
0 |
0 |
T152 |
155466 |
321 |
0 |
0 |
T153 |
63187 |
349 |
0 |
0 |
T154 |
99047 |
457 |
0 |
0 |
T155 |
6500 |
52 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5542 |
0 |
0 |
T81 |
4364 |
6 |
0 |
0 |
T82 |
3101 |
5 |
0 |
0 |
T113 |
74082 |
517 |
0 |
0 |
T114 |
11075 |
106 |
0 |
0 |
T115 |
10024 |
107 |
0 |
0 |
T144 |
14176 |
53 |
0 |
0 |
T152 |
155466 |
284 |
0 |
0 |
T153 |
63187 |
246 |
0 |
0 |
T154 |
99047 |
499 |
0 |
0 |
T155 |
6500 |
7 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5065 |
0 |
0 |
T81 |
4364 |
12 |
0 |
0 |
T82 |
3101 |
10 |
0 |
0 |
T113 |
74082 |
487 |
0 |
0 |
T114 |
11075 |
113 |
0 |
0 |
T115 |
10024 |
54 |
0 |
0 |
T144 |
14176 |
56 |
0 |
0 |
T152 |
155466 |
239 |
0 |
0 |
T153 |
63187 |
430 |
0 |
0 |
T154 |
99047 |
305 |
0 |
0 |
T155 |
6500 |
17 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5930 |
0 |
0 |
T81 |
4364 |
10 |
0 |
0 |
T113 |
74082 |
548 |
0 |
0 |
T114 |
11075 |
63 |
0 |
0 |
T115 |
10024 |
34 |
0 |
0 |
T144 |
14176 |
48 |
0 |
0 |
T152 |
155466 |
303 |
0 |
0 |
T153 |
63187 |
233 |
0 |
0 |
T154 |
99047 |
499 |
0 |
0 |
T155 |
6500 |
61 |
0 |
0 |
T156 |
30394 |
182 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5373 |
0 |
0 |
T81 |
4364 |
5 |
0 |
0 |
T82 |
3101 |
7 |
0 |
0 |
T113 |
74082 |
515 |
0 |
0 |
T114 |
11075 |
56 |
0 |
0 |
T115 |
10024 |
141 |
0 |
0 |
T144 |
14176 |
16 |
0 |
0 |
T152 |
155466 |
261 |
0 |
0 |
T153 |
63187 |
316 |
0 |
0 |
T154 |
99047 |
265 |
0 |
0 |
T155 |
6500 |
70 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5629 |
0 |
0 |
T81 |
4364 |
4 |
0 |
0 |
T82 |
3101 |
5 |
0 |
0 |
T113 |
74082 |
481 |
0 |
0 |
T114 |
11075 |
70 |
0 |
0 |
T115 |
10024 |
34 |
0 |
0 |
T144 |
14176 |
29 |
0 |
0 |
T152 |
155466 |
282 |
0 |
0 |
T153 |
63187 |
216 |
0 |
0 |
T154 |
99047 |
490 |
0 |
0 |
T155 |
6500 |
53 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5387 |
0 |
0 |
T81 |
4364 |
13 |
0 |
0 |
T113 |
74082 |
508 |
0 |
0 |
T114 |
11075 |
77 |
0 |
0 |
T115 |
10024 |
11 |
0 |
0 |
T144 |
14176 |
62 |
0 |
0 |
T152 |
155466 |
229 |
0 |
0 |
T153 |
63187 |
259 |
0 |
0 |
T154 |
99047 |
365 |
0 |
0 |
T155 |
6500 |
34 |
0 |
0 |
T156 |
30394 |
167 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5770 |
0 |
0 |
T81 |
4364 |
21 |
0 |
0 |
T82 |
3101 |
15 |
0 |
0 |
T113 |
74082 |
483 |
0 |
0 |
T114 |
11075 |
3 |
0 |
0 |
T115 |
10024 |
121 |
0 |
0 |
T144 |
14176 |
88 |
0 |
0 |
T152 |
155466 |
261 |
0 |
0 |
T153 |
63187 |
330 |
0 |
0 |
T154 |
99047 |
411 |
0 |
0 |
T155 |
6500 |
53 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5347 |
0 |
0 |
T81 |
4364 |
6 |
0 |
0 |
T82 |
3101 |
1 |
0 |
0 |
T113 |
74082 |
418 |
0 |
0 |
T114 |
11075 |
4 |
0 |
0 |
T115 |
10024 |
8 |
0 |
0 |
T144 |
14176 |
44 |
0 |
0 |
T152 |
155466 |
265 |
0 |
0 |
T153 |
63187 |
358 |
0 |
0 |
T154 |
99047 |
551 |
0 |
0 |
T155 |
6500 |
15 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5451 |
0 |
0 |
T81 |
4364 |
5 |
0 |
0 |
T82 |
3101 |
5 |
0 |
0 |
T113 |
74082 |
482 |
0 |
0 |
T114 |
11075 |
92 |
0 |
0 |
T115 |
10024 |
7 |
0 |
0 |
T144 |
14176 |
19 |
0 |
0 |
T152 |
155466 |
282 |
0 |
0 |
T153 |
63187 |
210 |
0 |
0 |
T154 |
99047 |
460 |
0 |
0 |
T155 |
6500 |
31 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5739 |
0 |
0 |
T81 |
4364 |
22 |
0 |
0 |
T82 |
3101 |
3 |
0 |
0 |
T113 |
74082 |
474 |
0 |
0 |
T114 |
11075 |
86 |
0 |
0 |
T115 |
10024 |
7 |
0 |
0 |
T144 |
14176 |
45 |
0 |
0 |
T152 |
155466 |
297 |
0 |
0 |
T153 |
63187 |
324 |
0 |
0 |
T154 |
99047 |
555 |
0 |
0 |
T155 |
6500 |
45 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5694 |
0 |
0 |
T81 |
4364 |
18 |
0 |
0 |
T82 |
3101 |
4 |
0 |
0 |
T113 |
74082 |
591 |
0 |
0 |
T114 |
11075 |
98 |
0 |
0 |
T115 |
10024 |
144 |
0 |
0 |
T144 |
14176 |
43 |
0 |
0 |
T152 |
155466 |
250 |
0 |
0 |
T153 |
63187 |
304 |
0 |
0 |
T154 |
99047 |
461 |
0 |
0 |
T155 |
6500 |
36 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5439 |
0 |
0 |
T81 |
4364 |
7 |
0 |
0 |
T82 |
3101 |
4 |
0 |
0 |
T113 |
74082 |
504 |
0 |
0 |
T114 |
11075 |
7 |
0 |
0 |
T115 |
10024 |
53 |
0 |
0 |
T144 |
14176 |
10 |
0 |
0 |
T152 |
155466 |
195 |
0 |
0 |
T153 |
63187 |
360 |
0 |
0 |
T154 |
99047 |
422 |
0 |
0 |
T155 |
6500 |
52 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5772 |
0 |
0 |
T81 |
4364 |
9 |
0 |
0 |
T101 |
20611 |
5 |
0 |
0 |
T113 |
74082 |
438 |
0 |
0 |
T114 |
11075 |
116 |
0 |
0 |
T115 |
10024 |
55 |
0 |
0 |
T144 |
14176 |
42 |
0 |
0 |
T152 |
155466 |
265 |
0 |
0 |
T153 |
63187 |
265 |
0 |
0 |
T154 |
99047 |
542 |
0 |
0 |
T155 |
6500 |
68 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5212 |
0 |
0 |
T60 |
10621 |
5 |
0 |
0 |
T81 |
4364 |
5 |
0 |
0 |
T113 |
74082 |
468 |
0 |
0 |
T114 |
11075 |
124 |
0 |
0 |
T115 |
10024 |
133 |
0 |
0 |
T144 |
14176 |
35 |
0 |
0 |
T152 |
155466 |
272 |
0 |
0 |
T153 |
63187 |
270 |
0 |
0 |
T154 |
99047 |
317 |
0 |
0 |
T155 |
6500 |
51 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5621 |
0 |
0 |
T81 |
4364 |
16 |
0 |
0 |
T82 |
3101 |
3 |
0 |
0 |
T113 |
74082 |
517 |
0 |
0 |
T114 |
11075 |
95 |
0 |
0 |
T115 |
10024 |
59 |
0 |
0 |
T144 |
14176 |
32 |
0 |
0 |
T152 |
155466 |
325 |
0 |
0 |
T153 |
63187 |
245 |
0 |
0 |
T154 |
99047 |
443 |
0 |
0 |
T155 |
6500 |
9 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5817 |
0 |
0 |
T81 |
4364 |
7 |
0 |
0 |
T113 |
74082 |
502 |
0 |
0 |
T114 |
11075 |
85 |
0 |
0 |
T115 |
10024 |
78 |
0 |
0 |
T144 |
14176 |
27 |
0 |
0 |
T152 |
155466 |
217 |
0 |
0 |
T153 |
63187 |
338 |
0 |
0 |
T154 |
99047 |
596 |
0 |
0 |
T155 |
6500 |
45 |
0 |
0 |
T156 |
30394 |
135 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5344 |
0 |
0 |
T81 |
4364 |
7 |
0 |
0 |
T82 |
3101 |
2 |
0 |
0 |
T113 |
74082 |
466 |
0 |
0 |
T114 |
11075 |
9 |
0 |
0 |
T115 |
10024 |
60 |
0 |
0 |
T144 |
14176 |
49 |
0 |
0 |
T152 |
155466 |
250 |
0 |
0 |
T153 |
63187 |
337 |
0 |
0 |
T154 |
99047 |
387 |
0 |
0 |
T155 |
6500 |
50 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5363 |
0 |
0 |
T81 |
4364 |
7 |
0 |
0 |
T82 |
3101 |
2 |
0 |
0 |
T113 |
74082 |
473 |
0 |
0 |
T114 |
11075 |
45 |
0 |
0 |
T115 |
10024 |
78 |
0 |
0 |
T144 |
14176 |
54 |
0 |
0 |
T152 |
155466 |
283 |
0 |
0 |
T153 |
63187 |
231 |
0 |
0 |
T154 |
99047 |
323 |
0 |
0 |
T155 |
6500 |
7 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5527 |
0 |
0 |
T81 |
4364 |
4 |
0 |
0 |
T82 |
3101 |
7 |
0 |
0 |
T113 |
74082 |
529 |
0 |
0 |
T114 |
11075 |
124 |
0 |
0 |
T115 |
10024 |
90 |
0 |
0 |
T144 |
14176 |
63 |
0 |
0 |
T152 |
155466 |
259 |
0 |
0 |
T153 |
63187 |
215 |
0 |
0 |
T154 |
99047 |
585 |
0 |
0 |
T155 |
6500 |
58 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5519 |
0 |
0 |
T81 |
4364 |
21 |
0 |
0 |
T113 |
74082 |
528 |
0 |
0 |
T114 |
11075 |
58 |
0 |
0 |
T115 |
10024 |
78 |
0 |
0 |
T144 |
14176 |
44 |
0 |
0 |
T152 |
155466 |
314 |
0 |
0 |
T153 |
63187 |
360 |
0 |
0 |
T154 |
99047 |
425 |
0 |
0 |
T155 |
6500 |
69 |
0 |
0 |
T156 |
30394 |
134 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5504 |
0 |
0 |
T81 |
4364 |
5 |
0 |
0 |
T82 |
3101 |
1 |
0 |
0 |
T113 |
74082 |
549 |
0 |
0 |
T114 |
11075 |
50 |
0 |
0 |
T115 |
10024 |
50 |
0 |
0 |
T144 |
14176 |
47 |
0 |
0 |
T152 |
155466 |
288 |
0 |
0 |
T153 |
63187 |
291 |
0 |
0 |
T154 |
99047 |
496 |
0 |
0 |
T156 |
30394 |
125 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
5522 |
0 |
0 |
T81 |
4364 |
8 |
0 |
0 |
T113 |
74082 |
460 |
0 |
0 |
T114 |
11075 |
13 |
0 |
0 |
T115 |
10024 |
161 |
0 |
0 |
T144 |
14176 |
68 |
0 |
0 |
T152 |
155466 |
275 |
0 |
0 |
T153 |
63187 |
350 |
0 |
0 |
T154 |
99047 |
417 |
0 |
0 |
T155 |
6500 |
48 |
0 |
0 |
T156 |
30394 |
94 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
3102 |
0 |
0 |
T81 |
4364 |
11 |
0 |
0 |
T101 |
20611 |
7 |
0 |
0 |
T113 |
74082 |
527 |
0 |
0 |
T114 |
11075 |
13 |
0 |
0 |
T115 |
10024 |
11 |
0 |
0 |
T144 |
14176 |
52 |
0 |
0 |
T152 |
155466 |
252 |
0 |
0 |
T153 |
63187 |
57 |
0 |
0 |
T154 |
99047 |
88 |
0 |
0 |
T155 |
6500 |
10 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
3061 |
0 |
0 |
T81 |
4364 |
14 |
0 |
0 |
T82 |
3101 |
9 |
0 |
0 |
T113 |
74082 |
532 |
0 |
0 |
T114 |
11075 |
12 |
0 |
0 |
T115 |
10024 |
22 |
0 |
0 |
T144 |
14176 |
32 |
0 |
0 |
T152 |
155466 |
244 |
0 |
0 |
T153 |
63187 |
55 |
0 |
0 |
T154 |
99047 |
112 |
0 |
0 |
T155 |
6500 |
11 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
3032 |
0 |
0 |
T81 |
4364 |
11 |
0 |
0 |
T82 |
3101 |
5 |
0 |
0 |
T113 |
74082 |
520 |
0 |
0 |
T114 |
11075 |
15 |
0 |
0 |
T115 |
10024 |
20 |
0 |
0 |
T144 |
14176 |
31 |
0 |
0 |
T152 |
155466 |
214 |
0 |
0 |
T153 |
63187 |
52 |
0 |
0 |
T154 |
99047 |
97 |
0 |
0 |
T155 |
6500 |
9 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
2925 |
0 |
0 |
T81 |
4364 |
10 |
0 |
0 |
T82 |
3101 |
3 |
0 |
0 |
T113 |
74082 |
474 |
0 |
0 |
T114 |
11075 |
12 |
0 |
0 |
T115 |
10024 |
17 |
0 |
0 |
T144 |
14176 |
50 |
0 |
0 |
T152 |
155466 |
303 |
0 |
0 |
T153 |
63187 |
91 |
0 |
0 |
T154 |
99047 |
51 |
0 |
0 |
T155 |
6500 |
9 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
3624 |
0 |
0 |
T81 |
4364 |
7 |
0 |
0 |
T82 |
3101 |
4 |
0 |
0 |
T113 |
74082 |
457 |
0 |
0 |
T114 |
11075 |
19 |
0 |
0 |
T115 |
10024 |
5 |
0 |
0 |
T144 |
14176 |
53 |
0 |
0 |
T152 |
155466 |
267 |
0 |
0 |
T153 |
63187 |
116 |
0 |
0 |
T154 |
99047 |
158 |
0 |
0 |
T155 |
6500 |
19 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
4941 |
0 |
0 |
T31 |
459828 |
28 |
0 |
0 |
T32 |
347963 |
0 |
0 |
0 |
T43 |
25706 |
0 |
0 |
0 |
T47 |
0 |
5 |
0 |
0 |
T78 |
0 |
24 |
0 |
0 |
T133 |
0 |
17 |
0 |
0 |
T146 |
18972 |
0 |
0 |
0 |
T157 |
0 |
33 |
0 |
0 |
T158 |
0 |
15 |
0 |
0 |
T159 |
0 |
4 |
0 |
0 |
T160 |
0 |
39 |
0 |
0 |
T161 |
0 |
19 |
0 |
0 |
T162 |
0 |
10 |
0 |
0 |
T163 |
9621 |
0 |
0 |
0 |
T164 |
1125 |
0 |
0 |
0 |
T165 |
278736 |
0 |
0 |
0 |
T166 |
158330 |
0 |
0 |
0 |
T167 |
279090 |
0 |
0 |
0 |
T168 |
4763 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
3278 |
0 |
0 |
T81 |
4364 |
13 |
0 |
0 |
T82 |
3101 |
6 |
0 |
0 |
T113 |
74082 |
582 |
0 |
0 |
T114 |
11075 |
12 |
0 |
0 |
T115 |
10024 |
12 |
0 |
0 |
T144 |
14176 |
64 |
0 |
0 |
T152 |
155466 |
296 |
0 |
0 |
T153 |
63187 |
99 |
0 |
0 |
T154 |
99047 |
88 |
0 |
0 |
T155 |
6500 |
18 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
3396 |
0 |
0 |
T81 |
4364 |
10 |
0 |
0 |
T82 |
3101 |
5 |
0 |
0 |
T113 |
74082 |
526 |
0 |
0 |
T114 |
11075 |
18 |
0 |
0 |
T115 |
10024 |
18 |
0 |
0 |
T144 |
14176 |
53 |
0 |
0 |
T152 |
155466 |
337 |
0 |
0 |
T153 |
63187 |
64 |
0 |
0 |
T154 |
99047 |
111 |
0 |
0 |
T155 |
6500 |
4 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
2844 |
0 |
0 |
T81 |
4364 |
14 |
0 |
0 |
T101 |
20611 |
5 |
0 |
0 |
T113 |
74082 |
434 |
0 |
0 |
T114 |
11075 |
17 |
0 |
0 |
T115 |
10024 |
10 |
0 |
0 |
T144 |
14176 |
43 |
0 |
0 |
T152 |
155466 |
266 |
0 |
0 |
T153 |
63187 |
46 |
0 |
0 |
T154 |
99047 |
20 |
0 |
0 |
T155 |
6500 |
11 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
2902 |
0 |
0 |
T81 |
4364 |
5 |
0 |
0 |
T82 |
3101 |
7 |
0 |
0 |
T113 |
74082 |
557 |
0 |
0 |
T114 |
11075 |
3 |
0 |
0 |
T115 |
10024 |
7 |
0 |
0 |
T144 |
14176 |
62 |
0 |
0 |
T152 |
155466 |
254 |
0 |
0 |
T153 |
63187 |
69 |
0 |
0 |
T154 |
99047 |
50 |
0 |
0 |
T155 |
6500 |
7 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
2994 |
0 |
0 |
T81 |
4364 |
23 |
0 |
0 |
T113 |
74082 |
522 |
0 |
0 |
T114 |
11075 |
6 |
0 |
0 |
T115 |
10024 |
18 |
0 |
0 |
T144 |
14176 |
12 |
0 |
0 |
T152 |
155466 |
234 |
0 |
0 |
T153 |
63187 |
64 |
0 |
0 |
T154 |
99047 |
75 |
0 |
0 |
T155 |
6500 |
11 |
0 |
0 |
T156 |
30394 |
10 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
2798 |
0 |
0 |
T81 |
4364 |
18 |
0 |
0 |
T82 |
3101 |
2 |
0 |
0 |
T113 |
74082 |
491 |
0 |
0 |
T114 |
11075 |
10 |
0 |
0 |
T115 |
10024 |
13 |
0 |
0 |
T144 |
14176 |
46 |
0 |
0 |
T152 |
155466 |
278 |
0 |
0 |
T153 |
63187 |
54 |
0 |
0 |
T154 |
99047 |
51 |
0 |
0 |
T155 |
6500 |
11 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
3387 |
0 |
0 |
T81 |
4364 |
12 |
0 |
0 |
T113 |
74082 |
490 |
0 |
0 |
T114 |
11075 |
39 |
0 |
0 |
T115 |
10024 |
25 |
0 |
0 |
T144 |
14176 |
57 |
0 |
0 |
T152 |
155466 |
217 |
0 |
0 |
T153 |
63187 |
105 |
0 |
0 |
T154 |
99047 |
190 |
0 |
0 |
T155 |
6500 |
19 |
0 |
0 |
T156 |
30394 |
80 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
3073 |
0 |
0 |
T81 |
4364 |
19 |
0 |
0 |
T82 |
3101 |
6 |
0 |
0 |
T113 |
74082 |
468 |
0 |
0 |
T114 |
11075 |
11 |
0 |
0 |
T115 |
10024 |
11 |
0 |
0 |
T144 |
14176 |
63 |
0 |
0 |
T152 |
155466 |
293 |
0 |
0 |
T153 |
63187 |
38 |
0 |
0 |
T154 |
99047 |
61 |
0 |
0 |
T155 |
6500 |
7 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
4001 |
0 |
0 |
T81 |
4364 |
10 |
0 |
0 |
T113 |
74082 |
499 |
0 |
0 |
T114 |
11075 |
28 |
0 |
0 |
T115 |
10024 |
54 |
0 |
0 |
T144 |
14176 |
34 |
0 |
0 |
T152 |
155466 |
259 |
0 |
0 |
T153 |
63187 |
152 |
0 |
0 |
T154 |
99047 |
143 |
0 |
0 |
T155 |
6500 |
28 |
0 |
0 |
T156 |
30394 |
49 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
3106 |
0 |
0 |
T81 |
4364 |
3 |
0 |
0 |
T113 |
74082 |
510 |
0 |
0 |
T114 |
11075 |
7 |
0 |
0 |
T115 |
10024 |
19 |
0 |
0 |
T144 |
14176 |
59 |
0 |
0 |
T152 |
155466 |
324 |
0 |
0 |
T153 |
63187 |
43 |
0 |
0 |
T154 |
99047 |
56 |
0 |
0 |
T155 |
6500 |
14 |
0 |
0 |
T156 |
30394 |
25 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
3030 |
0 |
0 |
T81 |
4364 |
13 |
0 |
0 |
T82 |
3101 |
2 |
0 |
0 |
T113 |
74082 |
511 |
0 |
0 |
T114 |
11075 |
9 |
0 |
0 |
T115 |
10024 |
10 |
0 |
0 |
T144 |
14176 |
112 |
0 |
0 |
T152 |
155466 |
311 |
0 |
0 |
T153 |
63187 |
28 |
0 |
0 |
T154 |
99047 |
68 |
0 |
0 |
T155 |
6500 |
6 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
2835 |
0 |
0 |
T81 |
4364 |
2 |
0 |
0 |
T113 |
74082 |
555 |
0 |
0 |
T114 |
11075 |
9 |
0 |
0 |
T115 |
10024 |
10 |
0 |
0 |
T144 |
14176 |
74 |
0 |
0 |
T152 |
155466 |
229 |
0 |
0 |
T153 |
63187 |
48 |
0 |
0 |
T154 |
99047 |
70 |
0 |
0 |
T155 |
6500 |
7 |
0 |
0 |
T156 |
30394 |
29 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
3041 |
0 |
0 |
T81 |
4364 |
5 |
0 |
0 |
T82 |
3101 |
15 |
0 |
0 |
T113 |
74082 |
484 |
0 |
0 |
T114 |
11075 |
15 |
0 |
0 |
T115 |
10024 |
13 |
0 |
0 |
T144 |
14176 |
43 |
0 |
0 |
T152 |
155466 |
297 |
0 |
0 |
T153 |
63187 |
48 |
0 |
0 |
T154 |
99047 |
57 |
0 |
0 |
T155 |
6500 |
1 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
2799 |
0 |
0 |
T81 |
4364 |
17 |
0 |
0 |
T82 |
3101 |
9 |
0 |
0 |
T113 |
74082 |
411 |
0 |
0 |
T114 |
11075 |
13 |
0 |
0 |
T115 |
10024 |
8 |
0 |
0 |
T144 |
14176 |
66 |
0 |
0 |
T152 |
155466 |
215 |
0 |
0 |
T153 |
63187 |
24 |
0 |
0 |
T154 |
99047 |
54 |
0 |
0 |
T155 |
6500 |
5 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
2709 |
0 |
0 |
T81 |
4364 |
11 |
0 |
0 |
T82 |
3101 |
4 |
0 |
0 |
T113 |
74082 |
480 |
0 |
0 |
T114 |
11075 |
11 |
0 |
0 |
T115 |
10024 |
15 |
0 |
0 |
T144 |
14176 |
24 |
0 |
0 |
T152 |
155466 |
241 |
0 |
0 |
T153 |
63187 |
49 |
0 |
0 |
T154 |
99047 |
68 |
0 |
0 |
T155 |
6500 |
10 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
398024405 |
2929 |
0 |
0 |
T81 |
4364 |
2 |
0 |
0 |
T101 |
20611 |
6 |
0 |
0 |
T113 |
74082 |
520 |
0 |
0 |
T114 |
11075 |
13 |
0 |
0 |
T115 |
10024 |
14 |
0 |
0 |
T144 |
14176 |
65 |
0 |
0 |
T152 |
155466 |
256 |
0 |
0 |
T153 |
63187 |
27 |
0 |
0 |
T154 |
99047 |
54 |
0 |
0 |
T155 |
6500 |
12 |
0 |
0 |