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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.08 98.31 94.11 98.61 89.36 97.16 95.84 99.20


Total test records in report: 1081
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T1011 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1851373277 Jun 02 03:06:38 PM PDT 24 Jun 02 03:06:39 PM PDT 24 17467121 ps
T125 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.894045920 Jun 02 03:06:29 PM PDT 24 Jun 02 03:06:31 PM PDT 24 157457367 ps
T1012 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3184865066 Jun 02 03:06:27 PM PDT 24 Jun 02 03:06:29 PM PDT 24 27757996 ps
T1013 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1497622443 Jun 02 03:06:41 PM PDT 24 Jun 02 03:06:43 PM PDT 24 29657872 ps
T1014 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2612059666 Jun 02 03:06:23 PM PDT 24 Jun 02 03:06:24 PM PDT 24 42386611 ps
T1015 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3378250220 Jun 02 03:06:43 PM PDT 24 Jun 02 03:06:45 PM PDT 24 10999229 ps
T1016 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.459563218 Jun 02 03:06:31 PM PDT 24 Jun 02 03:06:33 PM PDT 24 126148223 ps
T1017 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1354148812 Jun 02 03:06:41 PM PDT 24 Jun 02 03:06:43 PM PDT 24 25823687 ps
T107 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1089362487 Jun 02 03:06:16 PM PDT 24 Jun 02 03:06:21 PM PDT 24 694852039 ps
T1018 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2859196390 Jun 02 03:06:14 PM PDT 24 Jun 02 03:06:15 PM PDT 24 31005197 ps
T182 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1325604250 Jun 02 03:06:17 PM PDT 24 Jun 02 03:06:32 PM PDT 24 3503985798 ps
T1019 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3375286612 Jun 02 03:06:38 PM PDT 24 Jun 02 03:06:39 PM PDT 24 13273034 ps
T1020 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2143489355 Jun 02 03:06:22 PM PDT 24 Jun 02 03:06:25 PM PDT 24 240764636 ps
T1021 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2276491789 Jun 02 03:06:45 PM PDT 24 Jun 02 03:06:46 PM PDT 24 61627384 ps
T1022 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2485444141 Jun 02 03:06:11 PM PDT 24 Jun 02 03:06:13 PM PDT 24 69189508 ps
T1023 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3956971959 Jun 02 03:06:18 PM PDT 24 Jun 02 03:06:21 PM PDT 24 69140984 ps
T126 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3208876924 Jun 02 03:06:12 PM PDT 24 Jun 02 03:06:13 PM PDT 24 33735164 ps
T1024 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3231411077 Jun 02 03:06:19 PM PDT 24 Jun 02 03:06:55 PM PDT 24 7210630630 ps
T179 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3446428285 Jun 02 03:06:31 PM PDT 24 Jun 02 03:06:53 PM PDT 24 572266846 ps
T1025 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3582493554 Jun 02 03:06:07 PM PDT 24 Jun 02 03:06:12 PM PDT 24 393558056 ps
T1026 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.194718246 Jun 02 03:06:28 PM PDT 24 Jun 02 03:06:29 PM PDT 24 30411655 ps
T183 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2686849385 Jun 02 03:06:29 PM PDT 24 Jun 02 03:06:44 PM PDT 24 1452905673 ps
T1027 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.817958984 Jun 02 03:06:43 PM PDT 24 Jun 02 03:06:45 PM PDT 24 45377980 ps
T127 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1588256537 Jun 02 03:06:19 PM PDT 24 Jun 02 03:06:21 PM PDT 24 64555176 ps
T1028 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3022591171 Jun 02 03:06:35 PM PDT 24 Jun 02 03:06:36 PM PDT 24 44125365 ps
T1029 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2289145572 Jun 02 03:06:14 PM PDT 24 Jun 02 03:06:41 PM PDT 24 13837502388 ps
T1030 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2019481044 Jun 02 03:06:38 PM PDT 24 Jun 02 03:06:39 PM PDT 24 17191542 ps
T1031 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2993971403 Jun 02 03:06:37 PM PDT 24 Jun 02 03:06:57 PM PDT 24 1115668096 ps
T1032 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1172003494 Jun 02 03:06:19 PM PDT 24 Jun 02 03:06:21 PM PDT 24 70597509 ps
T1033 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3534556071 Jun 02 03:06:27 PM PDT 24 Jun 02 03:06:31 PM PDT 24 140926470 ps
T1034 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4090105727 Jun 02 03:06:33 PM PDT 24 Jun 02 03:06:37 PM PDT 24 116790248 ps
T1035 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2833267378 Jun 02 03:06:06 PM PDT 24 Jun 02 03:06:10 PM PDT 24 245894740 ps
T184 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.747338545 Jun 02 03:06:12 PM PDT 24 Jun 02 03:06:33 PM PDT 24 311025292 ps
T1036 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1106969068 Jun 02 03:06:17 PM PDT 24 Jun 02 03:06:19 PM PDT 24 26673152 ps
T1037 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.243155704 Jun 02 03:06:19 PM PDT 24 Jun 02 03:06:21 PM PDT 24 25556809 ps
T1038 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.438331024 Jun 02 03:06:21 PM PDT 24 Jun 02 03:06:36 PM PDT 24 222243555 ps
T1039 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3395329921 Jun 02 03:06:33 PM PDT 24 Jun 02 03:06:34 PM PDT 24 16398092 ps
T1040 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2808136828 Jun 02 03:06:07 PM PDT 24 Jun 02 03:06:09 PM PDT 24 56736277 ps
T1041 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2880588365 Jun 02 03:06:35 PM PDT 24 Jun 02 03:06:36 PM PDT 24 22033909 ps
T1042 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1461384321 Jun 02 03:06:41 PM PDT 24 Jun 02 03:06:43 PM PDT 24 44384887 ps
T1043 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.669557080 Jun 02 03:06:34 PM PDT 24 Jun 02 03:06:37 PM PDT 24 73895022 ps
T1044 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2083026776 Jun 02 03:06:35 PM PDT 24 Jun 02 03:06:36 PM PDT 24 18966471 ps
T1045 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1318121544 Jun 02 03:06:40 PM PDT 24 Jun 02 03:06:43 PM PDT 24 44949365 ps
T1046 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3011295678 Jun 02 03:06:06 PM PDT 24 Jun 02 03:06:14 PM PDT 24 212897561 ps
T84 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3858308148 Jun 02 03:06:16 PM PDT 24 Jun 02 03:06:17 PM PDT 24 140976568 ps
T1047 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3461652529 Jun 02 03:06:27 PM PDT 24 Jun 02 03:06:43 PM PDT 24 1415810033 ps
T1048 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4291712751 Jun 02 03:06:18 PM PDT 24 Jun 02 03:06:20 PM PDT 24 24722634 ps
T1049 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2557332011 Jun 02 03:06:18 PM PDT 24 Jun 02 03:06:21 PM PDT 24 104220311 ps
T1050 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1998073917 Jun 02 03:06:16 PM PDT 24 Jun 02 03:06:19 PM PDT 24 228897804 ps
T1051 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2521695457 Jun 02 03:06:42 PM PDT 24 Jun 02 03:06:45 PM PDT 24 113171844 ps
T1052 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.534973244 Jun 02 03:06:17 PM PDT 24 Jun 02 03:06:21 PM PDT 24 1579010953 ps
T1053 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2558669070 Jun 02 03:06:13 PM PDT 24 Jun 02 03:06:38 PM PDT 24 16391696218 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4263369816 Jun 02 03:06:18 PM PDT 24 Jun 02 03:06:22 PM PDT 24 524314910 ps
T1055 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1642663255 Jun 02 03:06:49 PM PDT 24 Jun 02 03:06:50 PM PDT 24 41212637 ps
T1056 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2749370008 Jun 02 03:06:37 PM PDT 24 Jun 02 03:06:42 PM PDT 24 323156738 ps
T1057 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1388806688 Jun 02 03:06:18 PM PDT 24 Jun 02 03:06:19 PM PDT 24 14721060 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3498559142 Jun 02 03:06:13 PM PDT 24 Jun 02 03:06:14 PM PDT 24 55691199 ps
T1059 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2386875690 Jun 02 03:06:25 PM PDT 24 Jun 02 03:06:29 PM PDT 24 2762179950 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.420142822 Jun 02 03:06:14 PM PDT 24 Jun 02 03:06:15 PM PDT 24 13523850 ps
T1061 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2203900748 Jun 02 03:06:34 PM PDT 24 Jun 02 03:06:37 PM PDT 24 68736262 ps
T1062 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.945362609 Jun 02 03:06:13 PM PDT 24 Jun 02 03:06:14 PM PDT 24 29166174 ps
T1063 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1171129423 Jun 02 03:06:29 PM PDT 24 Jun 02 03:06:34 PM PDT 24 205585582 ps
T1064 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.52799852 Jun 02 03:06:25 PM PDT 24 Jun 02 03:06:40 PM PDT 24 9023705045 ps
T1065 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1623739277 Jun 02 03:06:09 PM PDT 24 Jun 02 03:06:10 PM PDT 24 31648497 ps
T1066 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3603871517 Jun 02 03:06:32 PM PDT 24 Jun 02 03:06:33 PM PDT 24 46839313 ps
T176 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.923998867 Jun 02 03:06:32 PM PDT 24 Jun 02 03:06:36 PM PDT 24 515935309 ps
T1067 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3940601813 Jun 02 03:06:25 PM PDT 24 Jun 02 03:06:27 PM PDT 24 179620240 ps
T1068 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.276714622 Jun 02 03:06:37 PM PDT 24 Jun 02 03:06:54 PM PDT 24 1577284938 ps
T1069 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2775658189 Jun 02 03:06:18 PM PDT 24 Jun 02 03:06:21 PM PDT 24 157984197 ps
T1070 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2033155246 Jun 02 03:06:23 PM PDT 24 Jun 02 03:06:25 PM PDT 24 451792982 ps
T1071 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3595157961 Jun 02 03:06:35 PM PDT 24 Jun 02 03:06:37 PM PDT 24 13273464 ps
T1072 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.664807724 Jun 02 03:06:05 PM PDT 24 Jun 02 03:06:20 PM PDT 24 3226106549 ps
T1073 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.511796962 Jun 02 03:06:27 PM PDT 24 Jun 02 03:06:49 PM PDT 24 976429151 ps
T1074 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2806074965 Jun 02 03:06:14 PM PDT 24 Jun 02 03:06:18 PM PDT 24 85168060 ps
T1075 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3905826925 Jun 02 03:06:18 PM PDT 24 Jun 02 03:06:23 PM PDT 24 636687628 ps
T1076 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.892324300 Jun 02 03:06:05 PM PDT 24 Jun 02 03:06:07 PM PDT 24 125542186 ps
T1077 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3915605655 Jun 02 03:06:37 PM PDT 24 Jun 02 03:06:38 PM PDT 24 77568475 ps
T1078 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1005243471 Jun 02 03:06:24 PM PDT 24 Jun 02 03:06:26 PM PDT 24 81444016 ps
T1079 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2221309500 Jun 02 03:06:24 PM PDT 24 Jun 02 03:06:28 PM PDT 24 221373976 ps
T1080 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2967926371 Jun 02 03:06:44 PM PDT 24 Jun 02 03:06:45 PM PDT 24 35249738 ps
T1081 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1987241277 Jun 02 03:06:24 PM PDT 24 Jun 02 03:06:26 PM PDT 24 23540217 ps

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1708221773
Short name T4
Test name
Test status
Simulation time 94014547582 ps
CPU time 26.72 seconds
Started Jun 02 03:15:47 PM PDT 24
Finished Jun 02 03:16:14 PM PDT 24
Peak memory 229776 kb
Host smart-77ec0a6a-de70-481c-95e7-761f410867a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708221773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1708221773
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1244141527
Short name T12
Test name
Test status
Simulation time 4011244048 ps
CPU time 87.9 seconds
Started Jun 02 03:17:38 PM PDT 24
Finished Jun 02 03:19:07 PM PDT 24
Peak memory 255356 kb
Host smart-991c7490-909d-46a0-9c15-25e0703b4b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244141527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1244141527
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.690350725
Short name T30
Test name
Test status
Simulation time 610274568506 ps
CPU time 756.92 seconds
Started Jun 02 03:18:17 PM PDT 24
Finished Jun 02 03:30:55 PM PDT 24
Peak memory 273400 kb
Host smart-3831e4ad-f3cf-4c1d-805c-5984e1acbead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690350725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.690350725
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2683299637
Short name T26
Test name
Test status
Simulation time 23514499831 ps
CPU time 166.29 seconds
Started Jun 02 03:15:52 PM PDT 24
Finished Jun 02 03:18:39 PM PDT 24
Peak memory 253832 kb
Host smart-4dfe5a51-9a0a-49d2-b0f5-4d13236708df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683299637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2683299637
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3648510098
Short name T154
Test name
Test status
Simulation time 5502769687 ps
CPU time 23.89 seconds
Started Jun 02 03:06:14 PM PDT 24
Finished Jun 02 03:06:39 PM PDT 24
Peak memory 215368 kb
Host smart-a801336e-1f5d-4281-8f17-2790b6d089d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648510098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3648510098
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3682870364
Short name T170
Test name
Test status
Simulation time 409656103244 ps
CPU time 596.75 seconds
Started Jun 02 03:16:25 PM PDT 24
Finished Jun 02 03:26:23 PM PDT 24
Peak memory 281852 kb
Host smart-302468d3-fbf1-4a64-a552-cabd867a31d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682870364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3682870364
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.485784370
Short name T47
Test name
Test status
Simulation time 117152193415 ps
CPU time 606.1 seconds
Started Jun 02 03:17:51 PM PDT 24
Finished Jun 02 03:27:58 PM PDT 24
Peak memory 285972 kb
Host smart-931ce413-3803-44bf-b07b-4c7ede7f5285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485784370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.485784370
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2230862957
Short name T97
Test name
Test status
Simulation time 538784721 ps
CPU time 3.46 seconds
Started Jun 02 03:06:34 PM PDT 24
Finished Jun 02 03:06:38 PM PDT 24
Peak memory 215716 kb
Host smart-c2537790-d627-447c-822a-c169dfa57832
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230862957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2230862957
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.146080450
Short name T63
Test name
Test status
Simulation time 55621892 ps
CPU time 0.81 seconds
Started Jun 02 03:15:10 PM PDT 24
Finished Jun 02 03:15:12 PM PDT 24
Peak memory 216068 kb
Host smart-f1021e89-0700-4e83-9de0-5a7ca3850924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146080450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.146080450
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4000044213
Short name T214
Test name
Test status
Simulation time 72411110746 ps
CPU time 694.17 seconds
Started Jun 02 03:16:14 PM PDT 24
Finished Jun 02 03:27:48 PM PDT 24
Peak memory 269848 kb
Host smart-c0824b4d-855b-49e0-806e-f8fdff48c8cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000044213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4000044213
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2399083092
Short name T64
Test name
Test status
Simulation time 241370752 ps
CPU time 1.07 seconds
Started Jun 02 03:15:15 PM PDT 24
Finished Jun 02 03:15:16 PM PDT 24
Peak memory 235164 kb
Host smart-22e1f648-00fb-450b-9512-1b32fc4c207e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399083092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2399083092
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1669815802
Short name T150
Test name
Test status
Simulation time 682808434 ps
CPU time 7.64 seconds
Started Jun 02 03:15:22 PM PDT 24
Finished Jun 02 03:15:31 PM PDT 24
Peak memory 240736 kb
Host smart-6224801f-bc4e-4973-a3b5-6d6ebb66be6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669815802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1669815802
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1986006396
Short name T211
Test name
Test status
Simulation time 10346125911 ps
CPU time 176.44 seconds
Started Jun 02 03:15:55 PM PDT 24
Finished Jun 02 03:18:52 PM PDT 24
Peak memory 273476 kb
Host smart-6de80de7-3b28-40ec-8274-1f0ce00f240c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986006396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1986006396
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.4137878619
Short name T207
Test name
Test status
Simulation time 244314360931 ps
CPU time 675.64 seconds
Started Jun 02 03:17:33 PM PDT 24
Finished Jun 02 03:28:49 PM PDT 24
Peak memory 265704 kb
Host smart-300a042f-7a21-45f1-803c-83800c0a8073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137878619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.4137878619
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.118179916
Short name T114
Test name
Test status
Simulation time 230752398 ps
CPU time 2.93 seconds
Started Jun 02 03:06:24 PM PDT 24
Finished Jun 02 03:06:28 PM PDT 24
Peak memory 215220 kb
Host smart-c87262a9-1dc0-4be7-8e8c-231640a9cbc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118179916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.118179916
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1150679279
Short name T46
Test name
Test status
Simulation time 632784781860 ps
CPU time 1149.52 seconds
Started Jun 02 03:16:50 PM PDT 24
Finished Jun 02 03:36:01 PM PDT 24
Peak memory 265580 kb
Host smart-ee31bb34-cde6-4dfc-abda-232a2d63aba1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150679279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1150679279
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1808281622
Short name T23
Test name
Test status
Simulation time 16659115908 ps
CPU time 43.55 seconds
Started Jun 02 03:16:01 PM PDT 24
Finished Jun 02 03:16:45 PM PDT 24
Peak memory 218792 kb
Host smart-95d552ce-c2d1-48fa-8913-35a5c0521b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808281622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1808281622
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1897066672
Short name T187
Test name
Test status
Simulation time 47412172723 ps
CPU time 524.39 seconds
Started Jun 02 03:17:24 PM PDT 24
Finished Jun 02 03:26:09 PM PDT 24
Peak memory 267916 kb
Host smart-2ed71d16-7639-4530-98fa-243580774f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897066672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1897066672
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2771033538
Short name T188
Test name
Test status
Simulation time 49703661365 ps
CPU time 186.4 seconds
Started Jun 02 03:18:21 PM PDT 24
Finished Jun 02 03:21:28 PM PDT 24
Peak memory 256144 kb
Host smart-6910f059-0e62-4f63-b8d7-755c27fb7249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771033538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2771033538
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.589773821
Short name T171
Test name
Test status
Simulation time 118354472174 ps
CPU time 415.78 seconds
Started Jun 02 03:16:14 PM PDT 24
Finished Jun 02 03:23:10 PM PDT 24
Peak memory 255936 kb
Host smart-12f52c78-bc25-48f1-b2e3-ab6976fb79d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589773821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.589773821
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.186538566
Short name T22
Test name
Test status
Simulation time 10677860232 ps
CPU time 194.24 seconds
Started Jun 02 03:15:40 PM PDT 24
Finished Jun 02 03:18:55 PM PDT 24
Peak memory 265412 kb
Host smart-584f14bf-0ffa-4a5e-bb27-85088b0f8efd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186538566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.186538566
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1176764861
Short name T17
Test name
Test status
Simulation time 21589621721 ps
CPU time 73.35 seconds
Started Jun 02 03:16:06 PM PDT 24
Finished Jun 02 03:17:20 PM PDT 24
Peak memory 253872 kb
Host smart-269f62b1-3c93-4b83-81db-4a43ef142b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176764861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1176764861
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1906620436
Short name T128
Test name
Test status
Simulation time 32615850300 ps
CPU time 117.21 seconds
Started Jun 02 03:18:29 PM PDT 24
Finished Jun 02 03:20:27 PM PDT 24
Peak memory 256648 kb
Host smart-f05c43db-1745-4e0e-a103-407ee1bb3bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906620436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1906620436
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1876667326
Short name T5
Test name
Test status
Simulation time 34016045 ps
CPU time 0.71 seconds
Started Jun 02 03:17:24 PM PDT 24
Finished Jun 02 03:17:26 PM PDT 24
Peak memory 204816 kb
Host smart-a044b4e8-a856-475d-bb8d-43ea5d193a13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876667326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1876667326
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1089362487
Short name T107
Test name
Test status
Simulation time 694852039 ps
CPU time 4.93 seconds
Started Jun 02 03:06:16 PM PDT 24
Finished Jun 02 03:06:21 PM PDT 24
Peak memory 216420 kb
Host smart-ed856880-3f14-445f-bbe2-13e67b0ce937
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089362487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
089362487
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.963803223
Short name T289
Test name
Test status
Simulation time 13509291196 ps
CPU time 117.53 seconds
Started Jun 02 03:18:29 PM PDT 24
Finished Jun 02 03:20:27 PM PDT 24
Peak memory 264260 kb
Host smart-6908f511-5e0e-4fd5-b80c-0bcf3bce1b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963803223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.963803223
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.511796962
Short name T1073
Test name
Test status
Simulation time 976429151 ps
CPU time 21.82 seconds
Started Jun 02 03:06:27 PM PDT 24
Finished Jun 02 03:06:49 PM PDT 24
Peak memory 215224 kb
Host smart-b0a46aaf-e2cd-4d2d-998b-81f3c4687a3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511796962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.511796962
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2675751166
Short name T212
Test name
Test status
Simulation time 7170709053 ps
CPU time 151.69 seconds
Started Jun 02 03:17:05 PM PDT 24
Finished Jun 02 03:19:38 PM PDT 24
Peak memory 273284 kb
Host smart-28f6942d-0833-4b7e-8372-4f38e684e114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675751166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2675751166
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1310982739
Short name T776
Test name
Test status
Simulation time 410314805305 ps
CPU time 1029.7 seconds
Started Jun 02 03:17:22 PM PDT 24
Finished Jun 02 03:34:32 PM PDT 24
Peak memory 268324 kb
Host smart-aa88815b-a974-4702-9933-8f7e3d1e09da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310982739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1310982739
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.4042952151
Short name T283
Test name
Test status
Simulation time 6238281525 ps
CPU time 57.46 seconds
Started Jun 02 03:16:54 PM PDT 24
Finished Jun 02 03:17:52 PM PDT 24
Peak memory 255336 kb
Host smart-0401f867-de61-4b56-856c-2f2e4e46a017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042952151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.4042952151
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3865775511
Short name T173
Test name
Test status
Simulation time 87975444526 ps
CPU time 186 seconds
Started Jun 02 03:17:23 PM PDT 24
Finished Jun 02 03:20:29 PM PDT 24
Peak memory 255032 kb
Host smart-04541e2f-189f-424c-8df7-25892b02c34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865775511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3865775511
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1592522506
Short name T48
Test name
Test status
Simulation time 317488644 ps
CPU time 11.53 seconds
Started Jun 02 03:17:27 PM PDT 24
Finished Jun 02 03:17:40 PM PDT 24
Peak memory 248980 kb
Host smart-7fc23e41-5fb4-471e-be47-9d72531244fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592522506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1592522506
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3719263456
Short name T719
Test name
Test status
Simulation time 2634014982 ps
CPU time 63.45 seconds
Started Jun 02 03:17:48 PM PDT 24
Finished Jun 02 03:18:51 PM PDT 24
Peak memory 249084 kb
Host smart-e82000b3-ea42-44a7-98c9-a813605f62cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719263456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3719263456
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2290390689
Short name T91
Test name
Test status
Simulation time 798000925 ps
CPU time 6.58 seconds
Started Jun 02 03:16:44 PM PDT 24
Finished Jun 02 03:16:51 PM PDT 24
Peak memory 224364 kb
Host smart-d157bef8-d5d4-4504-93d5-0dde9a625370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290390689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2290390689
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2259973320
Short name T31
Test name
Test status
Simulation time 47900340663 ps
CPU time 487.62 seconds
Started Jun 02 03:16:51 PM PDT 24
Finished Jun 02 03:25:00 PM PDT 24
Peak memory 252752 kb
Host smart-9869872a-db2f-4f30-aa8d-adf7f7476504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259973320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2259973320
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3888155095
Short name T260
Test name
Test status
Simulation time 107624155422 ps
CPU time 624.08 seconds
Started Jun 02 03:16:02 PM PDT 24
Finished Jun 02 03:26:27 PM PDT 24
Peak memory 298300 kb
Host smart-7b8df6f5-67b7-48a9-a104-746b4cde9eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888155095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3888155095
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1260443889
Short name T228
Test name
Test status
Simulation time 15789411371 ps
CPU time 129.66 seconds
Started Jun 02 03:16:07 PM PDT 24
Finished Jun 02 03:18:17 PM PDT 24
Peak memory 255876 kb
Host smart-e01683f3-b0f1-4c76-a750-33e399096420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260443889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1260443889
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3760767227
Short name T21
Test name
Test status
Simulation time 12483902850 ps
CPU time 7 seconds
Started Jun 02 03:16:06 PM PDT 24
Finished Jun 02 03:16:14 PM PDT 24
Peak memory 218472 kb
Host smart-aab81983-dee2-445c-9838-fdf8516850ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760767227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3760767227
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2686849385
Short name T183
Test name
Test status
Simulation time 1452905673 ps
CPU time 15 seconds
Started Jun 02 03:06:29 PM PDT 24
Finished Jun 02 03:06:44 PM PDT 24
Peak memory 215524 kb
Host smart-b1285a8f-4cf9-413f-a91c-fc2b372448d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686849385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2686849385
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.282229615
Short name T273
Test name
Test status
Simulation time 18950216113 ps
CPU time 108.36 seconds
Started Jun 02 03:16:12 PM PDT 24
Finished Jun 02 03:18:01 PM PDT 24
Peak memory 249048 kb
Host smart-2e4fd3dd-2ec7-4acc-8311-03ebf93f43f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282229615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.282229615
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.4192688996
Short name T280
Test name
Test status
Simulation time 41713515745 ps
CPU time 147.41 seconds
Started Jun 02 03:16:16 PM PDT 24
Finished Jun 02 03:18:44 PM PDT 24
Peak memory 249048 kb
Host smart-c4b1dd9d-31fb-4519-811e-7edf86538546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192688996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.4192688996
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.265141455
Short name T301
Test name
Test status
Simulation time 5137122520 ps
CPU time 18.97 seconds
Started Jun 02 03:16:38 PM PDT 24
Finished Jun 02 03:16:58 PM PDT 24
Peak memory 232924 kb
Host smart-947b2e2c-6b22-48c4-94ee-4094a821dcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265141455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.265141455
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2581899329
Short name T157
Test name
Test status
Simulation time 331636273817 ps
CPU time 789.58 seconds
Started Jun 02 03:16:41 PM PDT 24
Finished Jun 02 03:29:51 PM PDT 24
Peak memory 270596 kb
Host smart-a435e8c0-9a0e-49b5-b132-74bfeafe2818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581899329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2581899329
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2728079083
Short name T61
Test name
Test status
Simulation time 73108524 ps
CPU time 2.1 seconds
Started Jun 02 03:06:08 PM PDT 24
Finished Jun 02 03:06:10 PM PDT 24
Peak memory 215412 kb
Host smart-a02e3c07-6096-449f-8934-4db514cb4db3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728079083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
728079083
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3563722973
Short name T85
Test name
Test status
Simulation time 7264780180 ps
CPU time 12.83 seconds
Started Jun 02 03:15:30 PM PDT 24
Finished Jun 02 03:15:44 PM PDT 24
Peak memory 218976 kb
Host smart-fc99c3c5-97ca-44b1-b8bb-0c4f83d830f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563722973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3563722973
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1493907706
Short name T82
Test name
Test status
Simulation time 67436381 ps
CPU time 1.2 seconds
Started Jun 02 03:06:08 PM PDT 24
Finished Jun 02 03:06:10 PM PDT 24
Peak memory 206976 kb
Host smart-1aba2f7c-9965-4561-89bd-04c5bbff6595
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493907706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1493907706
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/1.spi_device_upload.1466909945
Short name T15
Test name
Test status
Simulation time 14239571391 ps
CPU time 24.63 seconds
Started Jun 02 03:15:18 PM PDT 24
Finished Jun 02 03:15:43 PM PDT 24
Peak memory 240524 kb
Host smart-e529947c-f09e-41ec-b891-5fbdc18868dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466909945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1466909945
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2558669070
Short name T1053
Test name
Test status
Simulation time 16391696218 ps
CPU time 25.07 seconds
Started Jun 02 03:06:13 PM PDT 24
Finished Jun 02 03:06:38 PM PDT 24
Peak memory 215236 kb
Host smart-b5e24391-283e-48b1-9e31-13ee2fec363f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558669070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2558669070
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.664807724
Short name T1072
Test name
Test status
Simulation time 3226106549 ps
CPU time 14.09 seconds
Started Jun 02 03:06:05 PM PDT 24
Finished Jun 02 03:06:20 PM PDT 24
Peak memory 215268 kb
Host smart-0dd50ff7-7dac-487d-b50a-bb5a8d8efa72
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664807724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.664807724
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2833267378
Short name T1035
Test name
Test status
Simulation time 245894740 ps
CPU time 3.57 seconds
Started Jun 02 03:06:06 PM PDT 24
Finished Jun 02 03:06:10 PM PDT 24
Peak memory 217040 kb
Host smart-8e8c693a-ffa5-40d0-9ce5-562f01bb5cf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833267378 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2833267378
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2808136828
Short name T1040
Test name
Test status
Simulation time 56736277 ps
CPU time 1.9 seconds
Started Jun 02 03:06:07 PM PDT 24
Finished Jun 02 03:06:09 PM PDT 24
Peak memory 207004 kb
Host smart-d3008420-37f0-46b8-ae95-facc7ff10070
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808136828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
808136828
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1097600993
Short name T998
Test name
Test status
Simulation time 33237472 ps
CPU time 0.76 seconds
Started Jun 02 03:06:12 PM PDT 24
Finished Jun 02 03:06:13 PM PDT 24
Peak memory 203644 kb
Host smart-12b512e3-bffb-43fd-841f-bd08d2e9e673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097600993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
097600993
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1623739277
Short name T1065
Test name
Test status
Simulation time 31648497 ps
CPU time 1.33 seconds
Started Jun 02 03:06:09 PM PDT 24
Finished Jun 02 03:06:10 PM PDT 24
Peak memory 215268 kb
Host smart-73fa90aa-a82f-4396-9699-63d5e59acb7f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623739277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1623739277
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2362262257
Short name T978
Test name
Test status
Simulation time 42416882 ps
CPU time 0.66 seconds
Started Jun 02 03:06:06 PM PDT 24
Finished Jun 02 03:06:07 PM PDT 24
Peak memory 203568 kb
Host smart-f7e1338d-2ee8-421e-9214-1e20061a3dba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362262257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2362262257
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.148119831
Short name T142
Test name
Test status
Simulation time 214461013 ps
CPU time 1.94 seconds
Started Jun 02 03:06:14 PM PDT 24
Finished Jun 02 03:06:16 PM PDT 24
Peak memory 215120 kb
Host smart-b26a6a17-e526-4493-9b27-99e0101fb293
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148119831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.148119831
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1188178777
Short name T96
Test name
Test status
Simulation time 1635815614 ps
CPU time 15.24 seconds
Started Jun 02 03:06:06 PM PDT 24
Finished Jun 02 03:06:22 PM PDT 24
Peak memory 215236 kb
Host smart-06daf49c-4989-4f3a-82ef-d7e4f9c9c261
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188178777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1188178777
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3011295678
Short name T1046
Test name
Test status
Simulation time 212897561 ps
CPU time 7.99 seconds
Started Jun 02 03:06:06 PM PDT 24
Finished Jun 02 03:06:14 PM PDT 24
Peak memory 207000 kb
Host smart-c7e276ac-21c0-4b9a-be13-860584e3d56a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011295678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3011295678
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1948613060
Short name T1009
Test name
Test status
Simulation time 1114571903 ps
CPU time 13.5 seconds
Started Jun 02 03:06:08 PM PDT 24
Finished Jun 02 03:06:22 PM PDT 24
Peak memory 206964 kb
Host smart-056d7a64-7110-40fb-944c-a4430f2b0a0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948613060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1948613060
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1865151040
Short name T81
Test name
Test status
Simulation time 198432163 ps
CPU time 1.45 seconds
Started Jun 02 03:06:07 PM PDT 24
Finished Jun 02 03:06:09 PM PDT 24
Peak memory 216256 kb
Host smart-0d3efc01-6c5c-47b8-b008-48c79b6eca65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865151040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1865151040
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1650980958
Short name T1003
Test name
Test status
Simulation time 46187018 ps
CPU time 1.63 seconds
Started Jun 02 03:06:08 PM PDT 24
Finished Jun 02 03:06:10 PM PDT 24
Peak memory 215448 kb
Host smart-5c87a631-534e-46e0-aef4-4d3158ebcde4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650980958 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1650980958
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.892324300
Short name T1076
Test name
Test status
Simulation time 125542186 ps
CPU time 2.02 seconds
Started Jun 02 03:06:05 PM PDT 24
Finished Jun 02 03:06:07 PM PDT 24
Peak memory 215240 kb
Host smart-f10693fd-1e6f-45cd-865d-a6512bea5064
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892324300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.892324300
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1311494382
Short name T979
Test name
Test status
Simulation time 34543446 ps
CPU time 0.75 seconds
Started Jun 02 03:06:07 PM PDT 24
Finished Jun 02 03:06:09 PM PDT 24
Peak memory 204016 kb
Host smart-ead8c662-cc75-49ae-b93a-c8c6aec0fba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311494382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
311494382
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4066184586
Short name T117
Test name
Test status
Simulation time 19973855 ps
CPU time 1.09 seconds
Started Jun 02 03:06:09 PM PDT 24
Finished Jun 02 03:06:10 PM PDT 24
Peak memory 215180 kb
Host smart-0c44c803-cdfc-47da-9683-47ca32c28363
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066184586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4066184586
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.837774592
Short name T993
Test name
Test status
Simulation time 32916407 ps
CPU time 0.7 seconds
Started Jun 02 03:06:09 PM PDT 24
Finished Jun 02 03:06:11 PM PDT 24
Peak memory 203900 kb
Host smart-48e48b58-9863-4745-b746-d795908c227d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837774592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.837774592
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3582493554
Short name T1025
Test name
Test status
Simulation time 393558056 ps
CPU time 4.23 seconds
Started Jun 02 03:06:07 PM PDT 24
Finished Jun 02 03:06:12 PM PDT 24
Peak memory 215244 kb
Host smart-925953f2-f3c2-48cb-883c-c0660a0e284d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582493554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3582493554
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1192562222
Short name T106
Test name
Test status
Simulation time 64159548 ps
CPU time 2.43 seconds
Started Jun 02 03:06:13 PM PDT 24
Finished Jun 02 03:06:17 PM PDT 24
Peak memory 215384 kb
Host smart-07b11a39-2442-49ec-ae1e-2d1752b96ab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192562222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
192562222
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.913250062
Short name T185
Test name
Test status
Simulation time 682085127 ps
CPU time 15.7 seconds
Started Jun 02 03:06:10 PM PDT 24
Finished Jun 02 03:06:26 PM PDT 24
Peak memory 215116 kb
Host smart-aef46b6f-a38b-40cf-9a79-014e1e897951
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913250062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.913250062
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2221309500
Short name T1079
Test name
Test status
Simulation time 221373976 ps
CPU time 3.87 seconds
Started Jun 02 03:06:24 PM PDT 24
Finished Jun 02 03:06:28 PM PDT 24
Peak memory 217052 kb
Host smart-517ab2db-be8d-41e2-9759-45211c0bf60d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221309500 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2221309500
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1005243471
Short name T1078
Test name
Test status
Simulation time 81444016 ps
CPU time 2.02 seconds
Started Jun 02 03:06:24 PM PDT 24
Finished Jun 02 03:06:26 PM PDT 24
Peak memory 215232 kb
Host smart-e03cb12e-1f6d-414d-9db3-dac163a596fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005243471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1005243471
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.194718246
Short name T1026
Test name
Test status
Simulation time 30411655 ps
CPU time 0.78 seconds
Started Jun 02 03:06:28 PM PDT 24
Finished Jun 02 03:06:29 PM PDT 24
Peak memory 203680 kb
Host smart-8d70a6b9-7b65-45e7-8a8c-4ba08c0acfea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194718246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.194718246
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3848436406
Short name T990
Test name
Test status
Simulation time 42051378 ps
CPU time 2.77 seconds
Started Jun 02 03:06:23 PM PDT 24
Finished Jun 02 03:06:26 PM PDT 24
Peak memory 215196 kb
Host smart-015c314f-0a55-44e0-920c-4493b76d4adf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848436406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3848436406
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3534556071
Short name T1033
Test name
Test status
Simulation time 140926470 ps
CPU time 3.36 seconds
Started Jun 02 03:06:27 PM PDT 24
Finished Jun 02 03:06:31 PM PDT 24
Peak memory 215304 kb
Host smart-bab8f077-eda6-4658-a39d-f87a35c73c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534556071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3534556071
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.52799852
Short name T1064
Test name
Test status
Simulation time 9023705045 ps
CPU time 14.04 seconds
Started Jun 02 03:06:25 PM PDT 24
Finished Jun 02 03:06:40 PM PDT 24
Peak memory 215324 kb
Host smart-e9f4be4e-749b-4137-b983-617b5c39ff52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52799852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_
tl_intg_err.52799852
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2386875690
Short name T1059
Test name
Test status
Simulation time 2762179950 ps
CPU time 3.78 seconds
Started Jun 02 03:06:25 PM PDT 24
Finished Jun 02 03:06:29 PM PDT 24
Peak memory 217020 kb
Host smart-299673db-49c4-4ccc-9215-17754cf141ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386875690 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2386875690
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2371456390
Short name T975
Test name
Test status
Simulation time 62602523 ps
CPU time 2.02 seconds
Started Jun 02 03:06:24 PM PDT 24
Finished Jun 02 03:06:27 PM PDT 24
Peak memory 215168 kb
Host smart-e844f654-5f8c-4db8-9b5c-0f3c79b22135
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371456390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2371456390
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3171130484
Short name T971
Test name
Test status
Simulation time 13874688 ps
CPU time 0.75 seconds
Started Jun 02 03:06:22 PM PDT 24
Finished Jun 02 03:06:23 PM PDT 24
Peak memory 204036 kb
Host smart-a89971df-7d32-4028-b343-5e73c9dad29e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171130484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3171130484
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2232678833
Short name T143
Test name
Test status
Simulation time 482649380 ps
CPU time 2.92 seconds
Started Jun 02 03:06:25 PM PDT 24
Finished Jun 02 03:06:29 PM PDT 24
Peak memory 215184 kb
Host smart-20331215-f27e-45b1-81ff-e6d225df090b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232678833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2232678833
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2660680518
Short name T105
Test name
Test status
Simulation time 93490032 ps
CPU time 1.66 seconds
Started Jun 02 03:06:24 PM PDT 24
Finished Jun 02 03:06:26 PM PDT 24
Peak memory 215372 kb
Host smart-c9911a8a-4a46-456f-ab63-17891e374797
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660680518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2660680518
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3544010819
Short name T108
Test name
Test status
Simulation time 140541112 ps
CPU time 2.45 seconds
Started Jun 02 03:06:33 PM PDT 24
Finished Jun 02 03:06:36 PM PDT 24
Peak memory 216576 kb
Host smart-66cdcafc-7e90-4061-9d60-deea5289bdd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544010819 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3544010819
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.894045920
Short name T125
Test name
Test status
Simulation time 157457367 ps
CPU time 1.96 seconds
Started Jun 02 03:06:29 PM PDT 24
Finished Jun 02 03:06:31 PM PDT 24
Peak memory 215180 kb
Host smart-5afd8552-eb98-457e-ba2a-faed3969202a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894045920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.894045920
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1019540964
Short name T969
Test name
Test status
Simulation time 27470345 ps
CPU time 0.77 seconds
Started Jun 02 03:06:23 PM PDT 24
Finished Jun 02 03:06:24 PM PDT 24
Peak memory 203964 kb
Host smart-06313ca1-c4ba-4f35-98f6-b45b0fa95779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019540964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1019540964
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1349599337
Short name T145
Test name
Test status
Simulation time 292027292 ps
CPU time 2.91 seconds
Started Jun 02 03:06:29 PM PDT 24
Finished Jun 02 03:06:32 PM PDT 24
Peak memory 215256 kb
Host smart-97517f74-ab77-4af1-b3e2-af8414011732
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349599337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1349599337
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3940601813
Short name T1067
Test name
Test status
Simulation time 179620240 ps
CPU time 1.56 seconds
Started Jun 02 03:06:25 PM PDT 24
Finished Jun 02 03:06:27 PM PDT 24
Peak memory 215300 kb
Host smart-88e44b74-4527-4b5d-ab1e-1733c8a1e44a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940601813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3940601813
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3026797403
Short name T180
Test name
Test status
Simulation time 2308873265 ps
CPU time 15.11 seconds
Started Jun 02 03:06:24 PM PDT 24
Finished Jun 02 03:06:39 PM PDT 24
Peak memory 215500 kb
Host smart-3509a704-1cd0-405d-af6e-d56d8da935f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026797403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3026797403
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2799323204
Short name T109
Test name
Test status
Simulation time 55805340 ps
CPU time 4.05 seconds
Started Jun 02 03:06:31 PM PDT 24
Finished Jun 02 03:06:35 PM PDT 24
Peak memory 217472 kb
Host smart-3284d791-d51b-43d1-a1de-d056777d1db4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799323204 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2799323204
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.276028490
Short name T116
Test name
Test status
Simulation time 140628144 ps
CPU time 2.41 seconds
Started Jun 02 03:06:29 PM PDT 24
Finished Jun 02 03:06:32 PM PDT 24
Peak memory 206964 kb
Host smart-0fd72bb0-a12e-4a7c-abd8-7a2634e541e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276028490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.276028490
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3603871517
Short name T1066
Test name
Test status
Simulation time 46839313 ps
CPU time 0.75 seconds
Started Jun 02 03:06:32 PM PDT 24
Finished Jun 02 03:06:33 PM PDT 24
Peak memory 203660 kb
Host smart-3b463c9f-571e-4001-af19-c66db0ba3805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603871517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3603871517
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3160045539
Short name T1007
Test name
Test status
Simulation time 234447538 ps
CPU time 1.98 seconds
Started Jun 02 03:06:32 PM PDT 24
Finished Jun 02 03:06:34 PM PDT 24
Peak memory 216424 kb
Host smart-060ceffe-0d05-4567-b4c1-30a868d51cd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160045539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3160045539
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1716797853
Short name T95
Test name
Test status
Simulation time 3931264497 ps
CPU time 21.06 seconds
Started Jun 02 03:06:29 PM PDT 24
Finished Jun 02 03:06:50 PM PDT 24
Peak memory 215600 kb
Host smart-86192ac7-080c-4d45-9969-1ee722706d0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716797853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1716797853
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2249495061
Short name T155
Test name
Test status
Simulation time 295528315 ps
CPU time 1.99 seconds
Started Jun 02 03:06:30 PM PDT 24
Finished Jun 02 03:06:32 PM PDT 24
Peak memory 215276 kb
Host smart-d5e48d0b-5a79-44be-8606-79c08bd306a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249495061 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2249495061
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3837567622
Short name T122
Test name
Test status
Simulation time 97855851 ps
CPU time 2.59 seconds
Started Jun 02 03:06:30 PM PDT 24
Finished Jun 02 03:06:33 PM PDT 24
Peak memory 206896 kb
Host smart-5000c543-244c-48ba-a308-7f91b76eac07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837567622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3837567622
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2766716317
Short name T968
Test name
Test status
Simulation time 18653618 ps
CPU time 0.77 seconds
Started Jun 02 03:06:30 PM PDT 24
Finished Jun 02 03:06:32 PM PDT 24
Peak memory 203644 kb
Host smart-16cca6ee-63e5-49c2-b98f-71cf4acb6c86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766716317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2766716317
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1171129423
Short name T1063
Test name
Test status
Simulation time 205585582 ps
CPU time 4.09 seconds
Started Jun 02 03:06:29 PM PDT 24
Finished Jun 02 03:06:34 PM PDT 24
Peak memory 215192 kb
Host smart-968fe0ac-9891-4504-89af-c09104f27454
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171129423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1171129423
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.669557080
Short name T1043
Test name
Test status
Simulation time 73895022 ps
CPU time 2.38 seconds
Started Jun 02 03:06:34 PM PDT 24
Finished Jun 02 03:06:37 PM PDT 24
Peak memory 215344 kb
Host smart-0510a574-a215-4654-b54b-24178d2875ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669557080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.669557080
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2674298639
Short name T997
Test name
Test status
Simulation time 202607014 ps
CPU time 1.67 seconds
Started Jun 02 03:06:34 PM PDT 24
Finished Jun 02 03:06:36 PM PDT 24
Peak memory 215252 kb
Host smart-804dfef1-ade9-43cf-a1f8-6e38baec3a04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674298639 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2674298639
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3945554471
Short name T1008
Test name
Test status
Simulation time 382270068 ps
CPU time 1.93 seconds
Started Jun 02 03:06:31 PM PDT 24
Finished Jun 02 03:06:33 PM PDT 24
Peak memory 215212 kb
Host smart-1ca23684-64fe-4400-9c25-eaad73da8d39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945554471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3945554471
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.478242379
Short name T994
Test name
Test status
Simulation time 95718997 ps
CPU time 0.76 seconds
Started Jun 02 03:06:31 PM PDT 24
Finished Jun 02 03:06:33 PM PDT 24
Peak memory 204028 kb
Host smart-8b8144f2-67ea-4d60-91fe-2cae7bf1fa2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478242379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.478242379
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4090105727
Short name T1034
Test name
Test status
Simulation time 116790248 ps
CPU time 3.22 seconds
Started Jun 02 03:06:33 PM PDT 24
Finished Jun 02 03:06:37 PM PDT 24
Peak memory 215168 kb
Host smart-03a85127-27bd-4c80-8481-cef3dc88f1a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090105727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4090105727
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.459563218
Short name T1016
Test name
Test status
Simulation time 126148223 ps
CPU time 1.95 seconds
Started Jun 02 03:06:31 PM PDT 24
Finished Jun 02 03:06:33 PM PDT 24
Peak memory 216412 kb
Host smart-611743e1-c85e-4f78-a8b5-e86214edbd33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459563218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.459563218
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3446428285
Short name T179
Test name
Test status
Simulation time 572266846 ps
CPU time 20.6 seconds
Started Jun 02 03:06:31 PM PDT 24
Finished Jun 02 03:06:53 PM PDT 24
Peak memory 215484 kb
Host smart-d30f8a06-4842-4a53-bd00-daac9cabfe31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446428285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3446428285
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1030493189
Short name T972
Test name
Test status
Simulation time 56220462 ps
CPU time 3.74 seconds
Started Jun 02 03:06:34 PM PDT 24
Finished Jun 02 03:06:38 PM PDT 24
Peak memory 217688 kb
Host smart-e5cd8991-626b-48e0-a76e-8f953a6bb3c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030493189 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1030493189
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.155931127
Short name T115
Test name
Test status
Simulation time 401009716 ps
CPU time 2.55 seconds
Started Jun 02 03:06:30 PM PDT 24
Finished Jun 02 03:06:33 PM PDT 24
Peak memory 215148 kb
Host smart-19375e00-aa95-4e39-9fdd-3e2906fb7f08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155931127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.155931127
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3395329921
Short name T1039
Test name
Test status
Simulation time 16398092 ps
CPU time 0.76 seconds
Started Jun 02 03:06:33 PM PDT 24
Finished Jun 02 03:06:34 PM PDT 24
Peak memory 203692 kb
Host smart-1c2afb11-8a12-457b-99fe-87fcac46c9c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395329921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3395329921
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2928003837
Short name T141
Test name
Test status
Simulation time 147299043 ps
CPU time 1.66 seconds
Started Jun 02 03:06:32 PM PDT 24
Finished Jun 02 03:06:34 PM PDT 24
Peak memory 207012 kb
Host smart-bdd08d63-c4ad-4c45-bc94-56eea03b3321
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928003837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2928003837
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.923998867
Short name T176
Test name
Test status
Simulation time 515935309 ps
CPU time 3.23 seconds
Started Jun 02 03:06:32 PM PDT 24
Finished Jun 02 03:06:36 PM PDT 24
Peak memory 215476 kb
Host smart-56212810-5af0-4b84-abd9-c378e1ce163a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923998867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.923998867
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1471204110
Short name T153
Test name
Test status
Simulation time 631898346 ps
CPU time 14.53 seconds
Started Jun 02 03:06:31 PM PDT 24
Finished Jun 02 03:06:46 PM PDT 24
Peak memory 215256 kb
Host smart-1f77448d-4fb6-4592-a67a-04deedc5bdae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471204110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1471204110
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4048956281
Short name T111
Test name
Test status
Simulation time 139743804 ps
CPU time 3.01 seconds
Started Jun 02 03:06:42 PM PDT 24
Finished Jun 02 03:06:47 PM PDT 24
Peak memory 216636 kb
Host smart-7ca0fbd9-95a9-4605-b50c-68c9cebcd8d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048956281 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4048956281
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2521695457
Short name T1051
Test name
Test status
Simulation time 113171844 ps
CPU time 2.15 seconds
Started Jun 02 03:06:42 PM PDT 24
Finished Jun 02 03:06:45 PM PDT 24
Peak memory 207036 kb
Host smart-d7b42e00-b1fc-4c35-b2da-b208b117a8f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521695457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2521695457
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3451375075
Short name T1001
Test name
Test status
Simulation time 18073359 ps
CPU time 0.76 seconds
Started Jun 02 03:06:36 PM PDT 24
Finished Jun 02 03:06:37 PM PDT 24
Peak memory 203644 kb
Host smart-ec5159c7-3224-4864-b465-ae96e92fcf5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451375075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3451375075
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.635116886
Short name T985
Test name
Test status
Simulation time 41305208 ps
CPU time 2.74 seconds
Started Jun 02 03:06:35 PM PDT 24
Finished Jun 02 03:06:39 PM PDT 24
Peak memory 215156 kb
Host smart-90837268-a723-4c6e-97dc-18b82289d2a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635116886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.635116886
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2749370008
Short name T1056
Test name
Test status
Simulation time 323156738 ps
CPU time 4.4 seconds
Started Jun 02 03:06:37 PM PDT 24
Finished Jun 02 03:06:42 PM PDT 24
Peak memory 215344 kb
Host smart-807b10f4-a15a-4ea1-96c2-45c7fcfe23d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749370008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2749370008
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.276714622
Short name T1068
Test name
Test status
Simulation time 1577284938 ps
CPU time 17.11 seconds
Started Jun 02 03:06:37 PM PDT 24
Finished Jun 02 03:06:54 PM PDT 24
Peak memory 215820 kb
Host smart-ffeceb10-19b2-4f58-8396-423c7d0c1c58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276714622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.276714622
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2249708817
Short name T981
Test name
Test status
Simulation time 36754013 ps
CPU time 2.65 seconds
Started Jun 02 03:06:35 PM PDT 24
Finished Jun 02 03:06:38 PM PDT 24
Peak memory 216904 kb
Host smart-f5f8da33-4f30-47d7-856d-0742332fbc66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249708817 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2249708817
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.711325004
Short name T120
Test name
Test status
Simulation time 105668574 ps
CPU time 2.59 seconds
Started Jun 02 03:06:35 PM PDT 24
Finished Jun 02 03:06:38 PM PDT 24
Peak memory 215228 kb
Host smart-5c169486-26d9-4336-8b1b-fe5aa04504d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711325004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.711325004
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2083026776
Short name T1044
Test name
Test status
Simulation time 18966471 ps
CPU time 0.72 seconds
Started Jun 02 03:06:35 PM PDT 24
Finished Jun 02 03:06:36 PM PDT 24
Peak memory 203680 kb
Host smart-281fa3b1-6125-426a-882d-c365f5c87c18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083026776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2083026776
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.87825225
Short name T991
Test name
Test status
Simulation time 66409000 ps
CPU time 4.21 seconds
Started Jun 02 03:06:42 PM PDT 24
Finished Jun 02 03:06:47 PM PDT 24
Peak memory 215152 kb
Host smart-8a8ecb10-477a-46c5-994d-18e4cb95b03d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87825225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sp
i_device_same_csr_outstanding.87825225
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.340169577
Short name T62
Test name
Test status
Simulation time 252794482 ps
CPU time 1.95 seconds
Started Jun 02 03:06:35 PM PDT 24
Finished Jun 02 03:06:37 PM PDT 24
Peak memory 215552 kb
Host smart-49e24b38-c3f7-4152-9762-71475d2fbb46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340169577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.340169577
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2993971403
Short name T1031
Test name
Test status
Simulation time 1115668096 ps
CPU time 18.63 seconds
Started Jun 02 03:06:37 PM PDT 24
Finished Jun 02 03:06:57 PM PDT 24
Peak memory 215368 kb
Host smart-8fe8d916-27d3-44c4-b7d1-949675419798
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993971403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2993971403
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1318121544
Short name T1045
Test name
Test status
Simulation time 44949365 ps
CPU time 2.98 seconds
Started Jun 02 03:06:40 PM PDT 24
Finished Jun 02 03:06:43 PM PDT 24
Peak memory 216912 kb
Host smart-589f98dd-65b2-40fa-8b86-51b1e89151e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318121544 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1318121544
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2203900748
Short name T1061
Test name
Test status
Simulation time 68736262 ps
CPU time 2.46 seconds
Started Jun 02 03:06:34 PM PDT 24
Finished Jun 02 03:06:37 PM PDT 24
Peak memory 207064 kb
Host smart-b7201f9f-9f7f-4f84-9a8d-e6a8bf4e9836
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203900748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2203900748
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3015632999
Short name T1004
Test name
Test status
Simulation time 56003151 ps
CPU time 0.8 seconds
Started Jun 02 03:06:35 PM PDT 24
Finished Jun 02 03:06:37 PM PDT 24
Peak memory 203696 kb
Host smart-41427504-760e-44bf-b14d-664f259ec454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015632999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3015632999
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2878868220
Short name T140
Test name
Test status
Simulation time 1157722418 ps
CPU time 3.15 seconds
Started Jun 02 03:06:42 PM PDT 24
Finished Jun 02 03:06:47 PM PDT 24
Peak memory 216412 kb
Host smart-e244ed55-eb6d-4cfe-9c1c-68186f022166
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878868220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2878868220
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2937754690
Short name T104
Test name
Test status
Simulation time 133205719 ps
CPU time 3.53 seconds
Started Jun 02 03:06:41 PM PDT 24
Finished Jun 02 03:06:46 PM PDT 24
Peak memory 215416 kb
Host smart-c2c9364c-1d61-47e7-bc79-bd0d56351519
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937754690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2937754690
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2831840705
Short name T181
Test name
Test status
Simulation time 287064662 ps
CPU time 7.8 seconds
Started Jun 02 03:06:36 PM PDT 24
Finished Jun 02 03:06:44 PM PDT 24
Peak memory 215232 kb
Host smart-ebee7b4b-85a4-4886-b410-c4e8543b8fcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831840705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2831840705
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2085994729
Short name T113
Test name
Test status
Simulation time 2963359433 ps
CPU time 15.99 seconds
Started Jun 02 03:06:12 PM PDT 24
Finished Jun 02 03:06:28 PM PDT 24
Peak memory 215344 kb
Host smart-c6edb2bc-4624-4ef6-95f1-8fd44d21bcdd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085994729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2085994729
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2289145572
Short name T1029
Test name
Test status
Simulation time 13837502388 ps
CPU time 26.61 seconds
Started Jun 02 03:06:14 PM PDT 24
Finished Jun 02 03:06:41 PM PDT 24
Peak memory 207268 kb
Host smart-85a13a63-8c37-4265-8086-295f4a11d475
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289145572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2289145572
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3858308148
Short name T84
Test name
Test status
Simulation time 140976568 ps
CPU time 0.93 seconds
Started Jun 02 03:06:16 PM PDT 24
Finished Jun 02 03:06:17 PM PDT 24
Peak memory 206868 kb
Host smart-e409b0ed-3e0d-45f4-910d-622b6d42838f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858308148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3858308148
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1426122325
Short name T992
Test name
Test status
Simulation time 90075622 ps
CPU time 2.02 seconds
Started Jun 02 03:06:16 PM PDT 24
Finished Jun 02 03:06:19 PM PDT 24
Peak memory 216640 kb
Host smart-de7870ee-9940-49fb-8897-e03a77337c9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426122325 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1426122325
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3208876924
Short name T126
Test name
Test status
Simulation time 33735164 ps
CPU time 1.28 seconds
Started Jun 02 03:06:12 PM PDT 24
Finished Jun 02 03:06:13 PM PDT 24
Peak memory 207004 kb
Host smart-69b47b78-5021-4164-991c-1c77299f87bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208876924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
208876924
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1751612368
Short name T977
Test name
Test status
Simulation time 23176039 ps
CPU time 0.72 seconds
Started Jun 02 03:06:12 PM PDT 24
Finished Jun 02 03:06:13 PM PDT 24
Peak memory 204020 kb
Host smart-1cb3bca8-c799-4cd9-9d74-8b7682514824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751612368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
751612368
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3650534417
Short name T119
Test name
Test status
Simulation time 32471941 ps
CPU time 1.16 seconds
Started Jun 02 03:06:14 PM PDT 24
Finished Jun 02 03:06:15 PM PDT 24
Peak memory 215180 kb
Host smart-23c6f8ee-0666-472b-bb9d-e0c1b44b6f7b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650534417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3650534417
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3498559142
Short name T1058
Test name
Test status
Simulation time 55691199 ps
CPU time 0.67 seconds
Started Jun 02 03:06:13 PM PDT 24
Finished Jun 02 03:06:14 PM PDT 24
Peak memory 203568 kb
Host smart-9139c949-3563-48f2-bc07-da48913dbde4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498559142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3498559142
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2806074965
Short name T1074
Test name
Test status
Simulation time 85168060 ps
CPU time 2.85 seconds
Started Jun 02 03:06:14 PM PDT 24
Finished Jun 02 03:06:18 PM PDT 24
Peak memory 215256 kb
Host smart-74524657-4cd6-4d2a-964b-1bea807b47c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806074965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2806074965
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.463420802
Short name T999
Test name
Test status
Simulation time 52853494 ps
CPU time 1.69 seconds
Started Jun 02 03:06:08 PM PDT 24
Finished Jun 02 03:06:10 PM PDT 24
Peak memory 216396 kb
Host smart-47f537f9-fa62-423b-b72a-66497a8f4f02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463420802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.463420802
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3318702514
Short name T156
Test name
Test status
Simulation time 607917493 ps
CPU time 7.13 seconds
Started Jun 02 03:06:07 PM PDT 24
Finished Jun 02 03:06:15 PM PDT 24
Peak memory 215284 kb
Host smart-3951d5b9-02b8-4f7a-822e-5348a02c78cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318702514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3318702514
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2047344388
Short name T1006
Test name
Test status
Simulation time 14486254 ps
CPU time 0.75 seconds
Started Jun 02 03:06:35 PM PDT 24
Finished Jun 02 03:06:37 PM PDT 24
Peak memory 203972 kb
Host smart-9990e41b-907d-4c07-a771-41bd71ea6ac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047344388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2047344388
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2880588365
Short name T1041
Test name
Test status
Simulation time 22033909 ps
CPU time 0.67 seconds
Started Jun 02 03:06:35 PM PDT 24
Finished Jun 02 03:06:36 PM PDT 24
Peak memory 203720 kb
Host smart-33a30884-bfb5-4624-8da2-397298ad2d34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880588365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2880588365
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3022591171
Short name T1028
Test name
Test status
Simulation time 44125365 ps
CPU time 0.72 seconds
Started Jun 02 03:06:35 PM PDT 24
Finished Jun 02 03:06:36 PM PDT 24
Peak memory 203672 kb
Host smart-67924169-5e24-4611-b730-888992ff0f16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022591171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3022591171
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1851373277
Short name T1011
Test name
Test status
Simulation time 17467121 ps
CPU time 0.78 seconds
Started Jun 02 03:06:38 PM PDT 24
Finished Jun 02 03:06:39 PM PDT 24
Peak memory 203544 kb
Host smart-95fdfdc6-5d66-40cd-ae82-7a59706057b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851373277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1851373277
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1113542144
Short name T967
Test name
Test status
Simulation time 17232853 ps
CPU time 0.72 seconds
Started Jun 02 03:06:35 PM PDT 24
Finished Jun 02 03:06:36 PM PDT 24
Peak memory 204020 kb
Host smart-8981b051-56da-4dce-a12c-ae2786fa0c0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113542144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1113542144
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.269604665
Short name T976
Test name
Test status
Simulation time 15750702 ps
CPU time 0.73 seconds
Started Jun 02 03:06:36 PM PDT 24
Finished Jun 02 03:06:37 PM PDT 24
Peak memory 203640 kb
Host smart-a6689032-632e-4b84-8346-3e6caa9360b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269604665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.269604665
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1497622443
Short name T1013
Test name
Test status
Simulation time 29657872 ps
CPU time 0.71 seconds
Started Jun 02 03:06:41 PM PDT 24
Finished Jun 02 03:06:43 PM PDT 24
Peak memory 203704 kb
Host smart-f03231c8-bfd5-400b-bc55-3f90da775eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497622443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1497622443
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3595157961
Short name T1071
Test name
Test status
Simulation time 13273464 ps
CPU time 0.74 seconds
Started Jun 02 03:06:35 PM PDT 24
Finished Jun 02 03:06:37 PM PDT 24
Peak memory 204016 kb
Host smart-2ba03c9e-bb42-4ca0-9149-d3398522f9e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595157961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3595157961
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1354148812
Short name T1017
Test name
Test status
Simulation time 25823687 ps
CPU time 0.74 seconds
Started Jun 02 03:06:41 PM PDT 24
Finished Jun 02 03:06:43 PM PDT 24
Peak memory 203704 kb
Host smart-5402b695-9037-46a9-93d7-fba281f612da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354148812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1354148812
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3606083469
Short name T989
Test name
Test status
Simulation time 12010173 ps
CPU time 0.75 seconds
Started Jun 02 03:06:36 PM PDT 24
Finished Jun 02 03:06:38 PM PDT 24
Peak memory 204008 kb
Host smart-8983223c-3b9a-4f35-b194-0c97febff23a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606083469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3606083469
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.699051645
Short name T123
Test name
Test status
Simulation time 2256792988 ps
CPU time 13.69 seconds
Started Jun 02 03:06:16 PM PDT 24
Finished Jun 02 03:06:30 PM PDT 24
Peak memory 215328 kb
Host smart-e4134ba7-37c0-4326-a421-4411e3b53131
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699051645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.699051645
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1449595614
Short name T152
Test name
Test status
Simulation time 3109359365 ps
CPU time 24.94 seconds
Started Jun 02 03:06:13 PM PDT 24
Finished Jun 02 03:06:39 PM PDT 24
Peak memory 207084 kb
Host smart-48452bd7-386b-4cc9-87f1-8ac2a0a3f775
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449595614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1449595614
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2716064702
Short name T83
Test name
Test status
Simulation time 25233745 ps
CPU time 0.94 seconds
Started Jun 02 03:06:11 PM PDT 24
Finished Jun 02 03:06:12 PM PDT 24
Peak memory 206836 kb
Host smart-827967cd-a680-422a-8aca-2c7ee2d89b08
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716064702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2716064702
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4139780666
Short name T995
Test name
Test status
Simulation time 107711279 ps
CPU time 2.75 seconds
Started Jun 02 03:06:17 PM PDT 24
Finished Jun 02 03:06:20 PM PDT 24
Peak memory 217228 kb
Host smart-919403ee-479c-483c-b820-eddb73ce2f3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139780666 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.4139780666
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.326553924
Short name T121
Test name
Test status
Simulation time 28800664 ps
CPU time 1.93 seconds
Started Jun 02 03:06:11 PM PDT 24
Finished Jun 02 03:06:14 PM PDT 24
Peak memory 215224 kb
Host smart-83d76a1d-d3ee-45e7-8da8-54f2a05256d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326553924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.326553924
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2859196390
Short name T1018
Test name
Test status
Simulation time 31005197 ps
CPU time 0.71 seconds
Started Jun 02 03:06:14 PM PDT 24
Finished Jun 02 03:06:15 PM PDT 24
Peak memory 203708 kb
Host smart-57bf9d91-b577-46bb-9117-e14bbad68b6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859196390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
859196390
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1973301216
Short name T124
Test name
Test status
Simulation time 337971532 ps
CPU time 2.44 seconds
Started Jun 02 03:06:13 PM PDT 24
Finished Jun 02 03:06:16 PM PDT 24
Peak memory 215300 kb
Host smart-f63d76c3-464d-4851-a011-7753beb41b93
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973301216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1973301216
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.420142822
Short name T1060
Test name
Test status
Simulation time 13523850 ps
CPU time 0.69 seconds
Started Jun 02 03:06:14 PM PDT 24
Finished Jun 02 03:06:15 PM PDT 24
Peak memory 203544 kb
Host smart-9a338c0c-25c8-4c67-b781-2340ced423d9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420142822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.420142822
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3034482862
Short name T980
Test name
Test status
Simulation time 77889758 ps
CPU time 1.89 seconds
Started Jun 02 03:06:12 PM PDT 24
Finished Jun 02 03:06:15 PM PDT 24
Peak memory 215144 kb
Host smart-54d56c38-f599-4c94-a9d1-b5ec262a4a89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034482862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3034482862
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.747338545
Short name T184
Test name
Test status
Simulation time 311025292 ps
CPU time 20.75 seconds
Started Jun 02 03:06:12 PM PDT 24
Finished Jun 02 03:06:33 PM PDT 24
Peak memory 215376 kb
Host smart-c7c9f31f-eae5-4123-a0e1-0cda01bf1584
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747338545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.747338545
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3362833949
Short name T988
Test name
Test status
Simulation time 15560630 ps
CPU time 0.74 seconds
Started Jun 02 03:06:36 PM PDT 24
Finished Jun 02 03:06:38 PM PDT 24
Peak memory 203696 kb
Host smart-0d19adb3-726c-4144-b8cb-f2737be3b966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362833949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3362833949
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3375286612
Short name T1019
Test name
Test status
Simulation time 13273034 ps
CPU time 0.78 seconds
Started Jun 02 03:06:38 PM PDT 24
Finished Jun 02 03:06:39 PM PDT 24
Peak memory 203940 kb
Host smart-75a8861c-fa36-4c9c-8040-3eab046476c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375286612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3375286612
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3598143380
Short name T1010
Test name
Test status
Simulation time 29724474 ps
CPU time 0.69 seconds
Started Jun 02 03:06:36 PM PDT 24
Finished Jun 02 03:06:38 PM PDT 24
Peak memory 203708 kb
Host smart-3e316a57-8654-45a1-aecd-e31f3579ba94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598143380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3598143380
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3378720986
Short name T983
Test name
Test status
Simulation time 14678513 ps
CPU time 0.7 seconds
Started Jun 02 03:06:36 PM PDT 24
Finished Jun 02 03:06:37 PM PDT 24
Peak memory 203676 kb
Host smart-3d86bc74-64c2-4e1b-bf1f-4fddc5285005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378720986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3378720986
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1839399412
Short name T987
Test name
Test status
Simulation time 11933004 ps
CPU time 0.79 seconds
Started Jun 02 03:06:42 PM PDT 24
Finished Jun 02 03:06:43 PM PDT 24
Peak memory 203700 kb
Host smart-dd58c533-7d16-4f89-a459-fc5bb261c17c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839399412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1839399412
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2033677042
Short name T982
Test name
Test status
Simulation time 18523150 ps
CPU time 0.76 seconds
Started Jun 02 03:06:36 PM PDT 24
Finished Jun 02 03:06:37 PM PDT 24
Peak memory 204016 kb
Host smart-8be909d7-3274-4117-96e5-2603be798bc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033677042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2033677042
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2359703954
Short name T970
Test name
Test status
Simulation time 14131720 ps
CPU time 0.72 seconds
Started Jun 02 03:06:40 PM PDT 24
Finished Jun 02 03:06:41 PM PDT 24
Peak memory 203708 kb
Host smart-6cdeb946-987f-4992-8519-03af08ceb097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359703954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2359703954
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.549549137
Short name T973
Test name
Test status
Simulation time 13089100 ps
CPU time 0.72 seconds
Started Jun 02 03:06:35 PM PDT 24
Finished Jun 02 03:06:36 PM PDT 24
Peak memory 203684 kb
Host smart-5cd1135b-5a69-4fd8-ab6a-ebf44933dcee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549549137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.549549137
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3915605655
Short name T1077
Test name
Test status
Simulation time 77568475 ps
CPU time 0.78 seconds
Started Jun 02 03:06:37 PM PDT 24
Finished Jun 02 03:06:38 PM PDT 24
Peak memory 203736 kb
Host smart-b127f95c-32bf-4bde-988c-52c0141777a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915605655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3915605655
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.608043029
Short name T974
Test name
Test status
Simulation time 18347643 ps
CPU time 0.79 seconds
Started Jun 02 03:06:40 PM PDT 24
Finished Jun 02 03:06:41 PM PDT 24
Peak memory 203688 kb
Host smart-507ead20-c960-4955-be19-9d9eb496af27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608043029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.608043029
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.438331024
Short name T1038
Test name
Test status
Simulation time 222243555 ps
CPU time 14.33 seconds
Started Jun 02 03:06:21 PM PDT 24
Finished Jun 02 03:06:36 PM PDT 24
Peak memory 207036 kb
Host smart-0361f831-3132-4146-9cb2-f17228f0352c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438331024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.438331024
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3231411077
Short name T1024
Test name
Test status
Simulation time 7210630630 ps
CPU time 35.28 seconds
Started Jun 02 03:06:19 PM PDT 24
Finished Jun 02 03:06:55 PM PDT 24
Peak memory 215332 kb
Host smart-0cba7d86-6d3f-414a-a6ab-ffb82e8a3f23
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231411077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3231411077
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1106969068
Short name T1036
Test name
Test status
Simulation time 26673152 ps
CPU time 1.4 seconds
Started Jun 02 03:06:17 PM PDT 24
Finished Jun 02 03:06:19 PM PDT 24
Peak memory 216244 kb
Host smart-9c4a46b7-6c27-4a96-af07-10091e18b84b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106969068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1106969068
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4263369816
Short name T1054
Test name
Test status
Simulation time 524314910 ps
CPU time 3.87 seconds
Started Jun 02 03:06:18 PM PDT 24
Finished Jun 02 03:06:22 PM PDT 24
Peak memory 217152 kb
Host smart-c305fd07-c118-41b6-a23d-b6aae4fc5f46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263369816 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4263369816
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1588256537
Short name T127
Test name
Test status
Simulation time 64555176 ps
CPU time 1.83 seconds
Started Jun 02 03:06:19 PM PDT 24
Finished Jun 02 03:06:21 PM PDT 24
Peak memory 215280 kb
Host smart-e7dbeba2-7852-4d08-8d8d-08d091438558
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588256537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
588256537
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2485444141
Short name T1022
Test name
Test status
Simulation time 69189508 ps
CPU time 0.76 seconds
Started Jun 02 03:06:11 PM PDT 24
Finished Jun 02 03:06:13 PM PDT 24
Peak memory 203688 kb
Host smart-390acc7c-a41f-484d-b15c-0423df0a5be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485444141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
485444141
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.243155704
Short name T1037
Test name
Test status
Simulation time 25556809 ps
CPU time 1.56 seconds
Started Jun 02 03:06:19 PM PDT 24
Finished Jun 02 03:06:21 PM PDT 24
Peak memory 215244 kb
Host smart-14e5183d-05f4-4639-a2d4-a7f7b0f4dd27
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243155704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.243155704
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.945362609
Short name T1062
Test name
Test status
Simulation time 29166174 ps
CPU time 0.66 seconds
Started Jun 02 03:06:13 PM PDT 24
Finished Jun 02 03:06:14 PM PDT 24
Peak memory 203484 kb
Host smart-cbd19aa5-6c43-4858-9dc5-fc5f46dea7f9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945362609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.945362609
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2638351625
Short name T144
Test name
Test status
Simulation time 567159476 ps
CPU time 3.24 seconds
Started Jun 02 03:06:18 PM PDT 24
Finished Jun 02 03:06:21 PM PDT 24
Peak memory 215208 kb
Host smart-bddff4d4-13aa-484a-9c2f-b093fa71a154
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638351625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2638351625
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1601847936
Short name T101
Test name
Test status
Simulation time 824553937 ps
CPU time 5.35 seconds
Started Jun 02 03:06:13 PM PDT 24
Finished Jun 02 03:06:19 PM PDT 24
Peak memory 215580 kb
Host smart-d05d1231-d63d-4d1e-9d75-b0a616df4807
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601847936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
601847936
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2019481044
Short name T1030
Test name
Test status
Simulation time 17191542 ps
CPU time 0.75 seconds
Started Jun 02 03:06:38 PM PDT 24
Finished Jun 02 03:06:39 PM PDT 24
Peak memory 203612 kb
Host smart-fa50aac3-0081-419a-ade7-7082f7499b3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019481044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2019481044
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.817958984
Short name T1027
Test name
Test status
Simulation time 45377980 ps
CPU time 0.73 seconds
Started Jun 02 03:06:43 PM PDT 24
Finished Jun 02 03:06:45 PM PDT 24
Peak memory 204020 kb
Host smart-787a496a-0eda-40de-a274-8d71f167b79b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817958984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.817958984
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2276491789
Short name T1021
Test name
Test status
Simulation time 61627384 ps
CPU time 0.68 seconds
Started Jun 02 03:06:45 PM PDT 24
Finished Jun 02 03:06:46 PM PDT 24
Peak memory 203704 kb
Host smart-e35ab9d9-f6ea-4113-ba10-890cc32da147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276491789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2276491789
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3378250220
Short name T1015
Test name
Test status
Simulation time 10999229 ps
CPU time 0.72 seconds
Started Jun 02 03:06:43 PM PDT 24
Finished Jun 02 03:06:45 PM PDT 24
Peak memory 203704 kb
Host smart-e80ad767-6c52-4503-ba2a-555036211c51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378250220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3378250220
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2505822864
Short name T986
Test name
Test status
Simulation time 39039078 ps
CPU time 0.73 seconds
Started Jun 02 03:06:41 PM PDT 24
Finished Jun 02 03:06:43 PM PDT 24
Peak memory 203960 kb
Host smart-3edeb092-4f5e-464a-bcaa-b46392302014
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505822864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2505822864
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1642663255
Short name T1055
Test name
Test status
Simulation time 41212637 ps
CPU time 0.71 seconds
Started Jun 02 03:06:49 PM PDT 24
Finished Jun 02 03:06:50 PM PDT 24
Peak memory 204020 kb
Host smart-a03fdc49-9e00-42dc-9084-fe0a1aeb7427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642663255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1642663255
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2967926371
Short name T1080
Test name
Test status
Simulation time 35249738 ps
CPU time 0.73 seconds
Started Jun 02 03:06:44 PM PDT 24
Finished Jun 02 03:06:45 PM PDT 24
Peak memory 204008 kb
Host smart-fdb0df29-5dc3-47cd-b60a-d7af242dd5ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967926371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2967926371
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3632999979
Short name T966
Test name
Test status
Simulation time 30050432 ps
CPU time 0.78 seconds
Started Jun 02 03:06:43 PM PDT 24
Finished Jun 02 03:06:45 PM PDT 24
Peak memory 203964 kb
Host smart-2a0d4245-3096-4626-874b-325fc4b7e44d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632999979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3632999979
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3368166030
Short name T1005
Test name
Test status
Simulation time 28533878 ps
CPU time 0.72 seconds
Started Jun 02 03:06:40 PM PDT 24
Finished Jun 02 03:06:42 PM PDT 24
Peak memory 203696 kb
Host smart-a4c95e5d-c5b5-43d8-937d-cfb95ba6dba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368166030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3368166030
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1461384321
Short name T1042
Test name
Test status
Simulation time 44384887 ps
CPU time 0.73 seconds
Started Jun 02 03:06:41 PM PDT 24
Finished Jun 02 03:06:43 PM PDT 24
Peak memory 203720 kb
Host smart-150c531e-40b3-4b36-8322-379b4d58b561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461384321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1461384321
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1545951639
Short name T112
Test name
Test status
Simulation time 28589163 ps
CPU time 2.06 seconds
Started Jun 02 03:06:19 PM PDT 24
Finished Jun 02 03:06:22 PM PDT 24
Peak memory 215368 kb
Host smart-2b0b57e5-c9e4-4bd9-a6b3-8a56a0b4f804
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545951639 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1545951639
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.619936919
Short name T118
Test name
Test status
Simulation time 36602207 ps
CPU time 2.34 seconds
Started Jun 02 03:06:18 PM PDT 24
Finished Jun 02 03:06:21 PM PDT 24
Peak memory 215228 kb
Host smart-a5c4d1d6-902a-4e2f-b3d6-f472dc469d3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619936919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.619936919
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1172003494
Short name T1032
Test name
Test status
Simulation time 70597509 ps
CPU time 0.72 seconds
Started Jun 02 03:06:19 PM PDT 24
Finished Jun 02 03:06:21 PM PDT 24
Peak memory 203652 kb
Host smart-82b9be6e-c485-44c9-9495-e19e45cb3ce5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172003494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
172003494
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1998073917
Short name T1050
Test name
Test status
Simulation time 228897804 ps
CPU time 1.83 seconds
Started Jun 02 03:06:16 PM PDT 24
Finished Jun 02 03:06:19 PM PDT 24
Peak memory 215236 kb
Host smart-bdc58632-c469-4de1-a19b-650a8c09034e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998073917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1998073917
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3905826925
Short name T1075
Test name
Test status
Simulation time 636687628 ps
CPU time 4.15 seconds
Started Jun 02 03:06:18 PM PDT 24
Finished Jun 02 03:06:23 PM PDT 24
Peak memory 216432 kb
Host smart-e934fbd8-619a-49bf-be52-f465a5173672
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905826925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
905826925
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3348312841
Short name T94
Test name
Test status
Simulation time 102516944 ps
CPU time 6.88 seconds
Started Jun 02 03:06:21 PM PDT 24
Finished Jun 02 03:06:29 PM PDT 24
Peak memory 215156 kb
Host smart-c0aa37a8-b8f5-441b-8ec4-484b60b49fec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348312841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3348312841
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3956971959
Short name T1023
Test name
Test status
Simulation time 69140984 ps
CPU time 2.37 seconds
Started Jun 02 03:06:18 PM PDT 24
Finished Jun 02 03:06:21 PM PDT 24
Peak memory 216420 kb
Host smart-55cfe7fa-da95-4391-a83a-382f64587327
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956971959 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3956971959
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2557332011
Short name T1049
Test name
Test status
Simulation time 104220311 ps
CPU time 1.84 seconds
Started Jun 02 03:06:18 PM PDT 24
Finished Jun 02 03:06:21 PM PDT 24
Peak memory 219812 kb
Host smart-c8c8729e-c881-4b78-8595-d8772f8e9223
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557332011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
557332011
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4291712751
Short name T1048
Test name
Test status
Simulation time 24722634 ps
CPU time 0.72 seconds
Started Jun 02 03:06:18 PM PDT 24
Finished Jun 02 03:06:20 PM PDT 24
Peak memory 203700 kb
Host smart-c7840784-637e-462d-9b37-ab12a121f1e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291712751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
291712751
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3050432410
Short name T1000
Test name
Test status
Simulation time 57181383 ps
CPU time 1.98 seconds
Started Jun 02 03:06:19 PM PDT 24
Finished Jun 02 03:06:21 PM PDT 24
Peak memory 215628 kb
Host smart-ca245a08-1771-47a0-872f-c5150b4d53c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050432410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3050432410
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2843454448
Short name T60
Test name
Test status
Simulation time 106236099 ps
CPU time 2.81 seconds
Started Jun 02 03:06:20 PM PDT 24
Finished Jun 02 03:06:23 PM PDT 24
Peak memory 215392 kb
Host smart-33dd9c88-1560-47f6-b3fc-bacdda86957f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843454448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
843454448
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2617777287
Short name T178
Test name
Test status
Simulation time 204566181 ps
CPU time 13.31 seconds
Started Jun 02 03:06:19 PM PDT 24
Finished Jun 02 03:06:33 PM PDT 24
Peak memory 215196 kb
Host smart-a345e43b-143e-4830-8a8f-c27a347dcade
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617777287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2617777287
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3318339271
Short name T996
Test name
Test status
Simulation time 151912371 ps
CPU time 3.79 seconds
Started Jun 02 03:06:25 PM PDT 24
Finished Jun 02 03:06:29 PM PDT 24
Peak memory 217696 kb
Host smart-c5025369-a91e-4f64-b7ef-2b75f74ba91b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318339271 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3318339271
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2775658189
Short name T1069
Test name
Test status
Simulation time 157984197 ps
CPU time 2.55 seconds
Started Jun 02 03:06:18 PM PDT 24
Finished Jun 02 03:06:21 PM PDT 24
Peak memory 215244 kb
Host smart-5d5a9ecd-f07e-434e-ba5c-0d74eecbdc64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775658189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
775658189
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1388806688
Short name T1057
Test name
Test status
Simulation time 14721060 ps
CPU time 0.78 seconds
Started Jun 02 03:06:18 PM PDT 24
Finished Jun 02 03:06:19 PM PDT 24
Peak memory 203696 kb
Host smart-f23b6905-d5ea-45be-9cab-25bf01aba1f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388806688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
388806688
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.534973244
Short name T1052
Test name
Test status
Simulation time 1579010953 ps
CPU time 3.29 seconds
Started Jun 02 03:06:17 PM PDT 24
Finished Jun 02 03:06:21 PM PDT 24
Peak memory 215256 kb
Host smart-c5ca3214-f0ec-44ff-a2f9-a6b5cdbc0603
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534973244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.534973244
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1060905637
Short name T102
Test name
Test status
Simulation time 177707581 ps
CPU time 3.04 seconds
Started Jun 02 03:06:19 PM PDT 24
Finished Jun 02 03:06:23 PM PDT 24
Peak memory 215356 kb
Host smart-88a1eec6-db93-4433-a235-dd7065491440
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060905637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
060905637
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1325604250
Short name T182
Test name
Test status
Simulation time 3503985798 ps
CPU time 14.39 seconds
Started Jun 02 03:06:17 PM PDT 24
Finished Jun 02 03:06:32 PM PDT 24
Peak memory 215376 kb
Host smart-4a545fd3-1146-49fd-81e5-2428b935a903
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325604250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1325604250
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2143489355
Short name T1020
Test name
Test status
Simulation time 240764636 ps
CPU time 1.89 seconds
Started Jun 02 03:06:22 PM PDT 24
Finished Jun 02 03:06:25 PM PDT 24
Peak memory 215232 kb
Host smart-f3c58c92-82c8-4096-96ae-9df3e67891d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143489355 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2143489355
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1987241277
Short name T1081
Test name
Test status
Simulation time 23540217 ps
CPU time 0.78 seconds
Started Jun 02 03:06:24 PM PDT 24
Finished Jun 02 03:06:26 PM PDT 24
Peak memory 204032 kb
Host smart-5d142e62-012f-4df1-84c5-1f49aea8433e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987241277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
987241277
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1000303369
Short name T984
Test name
Test status
Simulation time 44903867 ps
CPU time 1.77 seconds
Started Jun 02 03:06:22 PM PDT 24
Finished Jun 02 03:06:24 PM PDT 24
Peak memory 207044 kb
Host smart-d3a9d50a-9faf-427b-9370-3a80acf813dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000303369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1000303369
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2780723383
Short name T103
Test name
Test status
Simulation time 384336293 ps
CPU time 2.76 seconds
Started Jun 02 03:06:23 PM PDT 24
Finished Jun 02 03:06:27 PM PDT 24
Peak memory 215464 kb
Host smart-cc3b201d-aa1d-4d3b-9ae6-97709798b890
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780723383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
780723383
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3461652529
Short name T1047
Test name
Test status
Simulation time 1415810033 ps
CPU time 15.42 seconds
Started Jun 02 03:06:27 PM PDT 24
Finished Jun 02 03:06:43 PM PDT 24
Peak memory 215220 kb
Host smart-c91887c3-7f45-4e2e-8e31-2da2ff020e16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461652529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3461652529
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.387030432
Short name T110
Test name
Test status
Simulation time 90742716 ps
CPU time 2 seconds
Started Jun 02 03:06:22 PM PDT 24
Finished Jun 02 03:06:25 PM PDT 24
Peak memory 215156 kb
Host smart-1c33df9a-2997-4625-b16d-ad68bba66f6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387030432 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.387030432
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2033155246
Short name T1070
Test name
Test status
Simulation time 451792982 ps
CPU time 2.08 seconds
Started Jun 02 03:06:23 PM PDT 24
Finished Jun 02 03:06:25 PM PDT 24
Peak memory 215088 kb
Host smart-4f5da802-40ab-415c-a4dd-0ee2489e7639
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033155246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
033155246
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2612059666
Short name T1014
Test name
Test status
Simulation time 42386611 ps
CPU time 0.74 seconds
Started Jun 02 03:06:23 PM PDT 24
Finished Jun 02 03:06:24 PM PDT 24
Peak memory 203652 kb
Host smart-5caac0f9-85eb-49ac-8c28-35353ef3ae0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612059666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
612059666
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3016261251
Short name T1002
Test name
Test status
Simulation time 208315397 ps
CPU time 4.42 seconds
Started Jun 02 03:06:22 PM PDT 24
Finished Jun 02 03:06:27 PM PDT 24
Peak memory 215188 kb
Host smart-9d38676f-befd-463a-89d5-ef71e495009f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016261251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3016261251
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3184865066
Short name T1012
Test name
Test status
Simulation time 27757996 ps
CPU time 1.78 seconds
Started Jun 02 03:06:27 PM PDT 24
Finished Jun 02 03:06:29 PM PDT 24
Peak memory 218756 kb
Host smart-c9ed01a5-5a3d-412f-90f8-9691d0736957
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184865066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
184865066
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.76758202
Short name T177
Test name
Test status
Simulation time 3467207330 ps
CPU time 20.29 seconds
Started Jun 02 03:06:24 PM PDT 24
Finished Jun 02 03:06:45 PM PDT 24
Peak memory 215596 kb
Host smart-de1d041c-997a-41a7-8fa8-f2add550b638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76758202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_t
l_intg_err.76758202
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3664132657
Short name T667
Test name
Test status
Simulation time 33461739 ps
CPU time 0.72 seconds
Started Jun 02 03:15:17 PM PDT 24
Finished Jun 02 03:15:18 PM PDT 24
Peak memory 205428 kb
Host smart-b03880b3-6c13-4534-85fe-47ed5ed6e7ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664132657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
664132657
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2600956049
Short name T245
Test name
Test status
Simulation time 82198011 ps
CPU time 2.16 seconds
Started Jun 02 03:15:14 PM PDT 24
Finished Jun 02 03:15:17 PM PDT 24
Peak memory 218592 kb
Host smart-2fd405ca-c58a-4c35-beae-4eb5e1a0655a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600956049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2600956049
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.996728807
Short name T54
Test name
Test status
Simulation time 67304277 ps
CPU time 0.79 seconds
Started Jun 02 03:15:10 PM PDT 24
Finished Jun 02 03:15:11 PM PDT 24
Peak memory 206428 kb
Host smart-c336b817-9ef4-447a-84e6-6315a899e2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996728807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.996728807
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1890167270
Short name T532
Test name
Test status
Simulation time 12099398372 ps
CPU time 41.99 seconds
Started Jun 02 03:15:16 PM PDT 24
Finished Jun 02 03:15:58 PM PDT 24
Peak memory 250332 kb
Host smart-a3138681-2a32-4cbd-beed-aa7b41c6c34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890167270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1890167270
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1642273108
Short name T395
Test name
Test status
Simulation time 67355971909 ps
CPU time 114.95 seconds
Started Jun 02 03:15:14 PM PDT 24
Finished Jun 02 03:17:10 PM PDT 24
Peak memory 249968 kb
Host smart-5c8a846f-66ff-4722-a852-15c7cd5f6c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642273108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1642273108
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3956563048
Short name T860
Test name
Test status
Simulation time 8142255071 ps
CPU time 31.39 seconds
Started Jun 02 03:15:15 PM PDT 24
Finished Jun 02 03:15:47 PM PDT 24
Peak memory 224496 kb
Host smart-622699cc-9d88-4b70-926a-24ffdd84c603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956563048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3956563048
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1050365948
Short name T725
Test name
Test status
Simulation time 365566125 ps
CPU time 8.11 seconds
Started Jun 02 03:15:16 PM PDT 24
Finished Jun 02 03:15:25 PM PDT 24
Peak memory 232584 kb
Host smart-1a91e287-9ed1-449c-8e3e-4cc8f111a27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050365948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1050365948
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2690500700
Short name T681
Test name
Test status
Simulation time 145596902 ps
CPU time 2.22 seconds
Started Jun 02 03:15:15 PM PDT 24
Finished Jun 02 03:15:18 PM PDT 24
Peak memory 215948 kb
Host smart-bdab346c-a9ae-4f7e-b418-559f78170f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690500700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2690500700
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1117415896
Short name T527
Test name
Test status
Simulation time 51948010529 ps
CPU time 67.62 seconds
Started Jun 02 03:15:16 PM PDT 24
Finished Jun 02 03:16:24 PM PDT 24
Peak memory 226708 kb
Host smart-b6c5edcd-7fe6-4fce-a31c-f6b946a03cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117415896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1117415896
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.342250601
Short name T818
Test name
Test status
Simulation time 678282319 ps
CPU time 3.78 seconds
Started Jun 02 03:15:18 PM PDT 24
Finished Jun 02 03:15:22 PM PDT 24
Peak memory 233484 kb
Host smart-3c487fc7-f44c-4323-8e84-9ca34bd324cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342250601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
342250601
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.520436159
Short name T908
Test name
Test status
Simulation time 6428850902 ps
CPU time 6.1 seconds
Started Jun 02 03:15:14 PM PDT 24
Finished Jun 02 03:15:20 PM PDT 24
Peak memory 233712 kb
Host smart-fb9d1a47-f461-4092-9bb6-dccd2201e83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520436159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.520436159
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.598627606
Short name T836
Test name
Test status
Simulation time 353725311 ps
CPU time 5.85 seconds
Started Jun 02 03:15:15 PM PDT 24
Finished Jun 02 03:15:22 PM PDT 24
Peak memory 219144 kb
Host smart-7e55fb22-75ae-486f-92ef-773dde40ea0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=598627606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.598627606
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1381622376
Short name T78
Test name
Test status
Simulation time 141656832120 ps
CPU time 321.29 seconds
Started Jun 02 03:15:14 PM PDT 24
Finished Jun 02 03:20:37 PM PDT 24
Peak memory 268864 kb
Host smart-0aeb1af0-37ca-4505-9157-722ea2c1c63b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381622376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1381622376
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3904285685
Short name T309
Test name
Test status
Simulation time 15834077773 ps
CPU time 45.08 seconds
Started Jun 02 03:15:10 PM PDT 24
Finished Jun 02 03:15:56 PM PDT 24
Peak memory 216292 kb
Host smart-9ca50f9a-e302-4b23-b066-09228420b019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904285685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3904285685
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3092472017
Short name T53
Test name
Test status
Simulation time 7591845442 ps
CPU time 11.39 seconds
Started Jun 02 03:15:10 PM PDT 24
Finished Jun 02 03:15:22 PM PDT 24
Peak memory 216180 kb
Host smart-24f80767-f6a1-4769-819e-0f6095fcd67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092472017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3092472017
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1165433246
Short name T671
Test name
Test status
Simulation time 37178357 ps
CPU time 0.72 seconds
Started Jun 02 03:15:16 PM PDT 24
Finished Jun 02 03:15:18 PM PDT 24
Peak memory 205428 kb
Host smart-c499d752-316b-4710-ac51-0bccc3305767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165433246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1165433246
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3658351130
Short name T332
Test name
Test status
Simulation time 414031084 ps
CPU time 0.88 seconds
Started Jun 02 03:15:10 PM PDT 24
Finished Jun 02 03:15:11 PM PDT 24
Peak memory 205620 kb
Host smart-5467687a-7dd5-479e-8cf0-45ced354a9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658351130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3658351130
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3500328174
Short name T559
Test name
Test status
Simulation time 137320478 ps
CPU time 2.62 seconds
Started Jun 02 03:15:13 PM PDT 24
Finished Jun 02 03:15:17 PM PDT 24
Peak memory 224504 kb
Host smart-4e28c74b-722b-4758-b29a-67e62388370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500328174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3500328174
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.699876784
Short name T341
Test name
Test status
Simulation time 47950915 ps
CPU time 0.73 seconds
Started Jun 02 03:15:22 PM PDT 24
Finished Jun 02 03:15:24 PM PDT 24
Peak memory 205772 kb
Host smart-999c66bf-0b4e-42ad-b4ec-3651997a0e30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699876784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.699876784
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1340729380
Short name T749
Test name
Test status
Simulation time 101261007 ps
CPU time 4.11 seconds
Started Jun 02 03:15:14 PM PDT 24
Finished Jun 02 03:15:19 PM PDT 24
Peak memory 233672 kb
Host smart-495ccdcb-48d7-42c6-b897-1b9fbc436ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340729380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1340729380
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3052522499
Short name T523
Test name
Test status
Simulation time 14540398 ps
CPU time 0.77 seconds
Started Jun 02 03:15:13 PM PDT 24
Finished Jun 02 03:15:15 PM PDT 24
Peak memory 206428 kb
Host smart-ef925b47-a604-4c82-9fe7-9cfb5eca5930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052522499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3052522499
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1301118771
Short name T932
Test name
Test status
Simulation time 5590053738 ps
CPU time 71.39 seconds
Started Jun 02 03:15:16 PM PDT 24
Finished Jun 02 03:16:28 PM PDT 24
Peak memory 254800 kb
Host smart-24b56338-2235-4b5c-b710-7c480b2d8da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301118771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1301118771
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1057301681
Short name T840
Test name
Test status
Simulation time 8990352870 ps
CPU time 117.75 seconds
Started Jun 02 03:15:16 PM PDT 24
Finished Jun 02 03:17:14 PM PDT 24
Peak memory 257340 kb
Host smart-63234fad-03cf-4d5d-829d-51dc42d92cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057301681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1057301681
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.848401127
Short name T717
Test name
Test status
Simulation time 19837789 ps
CPU time 0.82 seconds
Started Jun 02 03:15:22 PM PDT 24
Finished Jun 02 03:15:24 PM PDT 24
Peak memory 216768 kb
Host smart-ef2a9dcb-00c6-4dce-ac48-5425a123ac02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848401127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
848401127
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1314484397
Short name T938
Test name
Test status
Simulation time 459217399 ps
CPU time 3.08 seconds
Started Jun 02 03:15:18 PM PDT 24
Finished Jun 02 03:15:22 PM PDT 24
Peak memory 224396 kb
Host smart-fa789a6e-a559-47c7-943b-3b6353a2bfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314484397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1314484397
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3286281475
Short name T503
Test name
Test status
Simulation time 277833292 ps
CPU time 2.28 seconds
Started Jun 02 03:15:16 PM PDT 24
Finished Jun 02 03:15:19 PM PDT 24
Peak memory 221564 kb
Host smart-01fe6631-f4af-4807-8d25-f74e2481509c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286281475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3286281475
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1270533812
Short name T525
Test name
Test status
Simulation time 1568458541 ps
CPU time 24.92 seconds
Started Jun 02 03:15:20 PM PDT 24
Finished Jun 02 03:15:45 PM PDT 24
Peak memory 218444 kb
Host smart-163bac3b-36f4-4801-8b7d-6c6ef6ecd898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270533812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1270533812
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2047801492
Short name T540
Test name
Test status
Simulation time 2077785584 ps
CPU time 5.53 seconds
Started Jun 02 03:15:17 PM PDT 24
Finished Jun 02 03:15:23 PM PDT 24
Peak memory 233624 kb
Host smart-003c8be0-0774-4d76-a425-6ca67440f9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047801492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2047801492
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1919874110
Short name T248
Test name
Test status
Simulation time 3025921168 ps
CPU time 6.5 seconds
Started Jun 02 03:15:16 PM PDT 24
Finished Jun 02 03:15:24 PM PDT 24
Peak memory 233800 kb
Host smart-0eafe760-5eb1-4d2e-bea7-a977eabb4005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919874110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1919874110
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2636192628
Short name T809
Test name
Test status
Simulation time 526008672 ps
CPU time 4.9 seconds
Started Jun 02 03:15:15 PM PDT 24
Finished Jun 02 03:15:20 PM PDT 24
Peak memory 218632 kb
Host smart-90841dde-bacb-422b-9c86-93bfde7d79fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2636192628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2636192628
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3856174113
Short name T65
Test name
Test status
Simulation time 38197416 ps
CPU time 1.04 seconds
Started Jun 02 03:15:21 PM PDT 24
Finished Jun 02 03:15:22 PM PDT 24
Peak memory 235136 kb
Host smart-5740dfaf-5fae-4c85-8100-4944c072f0b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856174113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3856174113
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2007343146
Short name T139
Test name
Test status
Simulation time 89317659705 ps
CPU time 567.04 seconds
Started Jun 02 03:15:22 PM PDT 24
Finished Jun 02 03:24:50 PM PDT 24
Peak memory 273652 kb
Host smart-c38bb4b1-16e5-4347-83e5-9552cb06a3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007343146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2007343146
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2549774237
Short name T24
Test name
Test status
Simulation time 4750893309 ps
CPU time 24.25 seconds
Started Jun 02 03:15:16 PM PDT 24
Finished Jun 02 03:15:41 PM PDT 24
Peak memory 216260 kb
Host smart-264e8396-9141-4340-9747-d192f7b8234e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549774237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2549774237
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.114768711
Short name T489
Test name
Test status
Simulation time 9586978922 ps
CPU time 14.7 seconds
Started Jun 02 03:15:14 PM PDT 24
Finished Jun 02 03:15:29 PM PDT 24
Peak memory 216156 kb
Host smart-7b93d8cd-c8c6-44c8-9c19-b1573181f728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114768711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.114768711
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1226757411
Short name T821
Test name
Test status
Simulation time 56336392 ps
CPU time 1.19 seconds
Started Jun 02 03:15:16 PM PDT 24
Finished Jun 02 03:15:18 PM PDT 24
Peak memory 216224 kb
Host smart-b6e64e86-02ea-48fc-9ed5-7168b964bdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226757411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1226757411
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2055588388
Short name T377
Test name
Test status
Simulation time 92959954 ps
CPU time 0.8 seconds
Started Jun 02 03:15:16 PM PDT 24
Finished Jun 02 03:15:18 PM PDT 24
Peak memory 205632 kb
Host smart-7c3c0466-d86c-4b47-a58c-42c7c26b87eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055588388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2055588388
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1740727010
Short name T597
Test name
Test status
Simulation time 31226051 ps
CPU time 0.72 seconds
Started Jun 02 03:16:00 PM PDT 24
Finished Jun 02 03:16:02 PM PDT 24
Peak memory 205716 kb
Host smart-ba6a0a55-7288-4bc9-b0f2-1d165a354440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740727010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1740727010
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1981658398
Short name T957
Test name
Test status
Simulation time 3005926372 ps
CPU time 7.14 seconds
Started Jun 02 03:15:56 PM PDT 24
Finished Jun 02 03:16:04 PM PDT 24
Peak memory 234488 kb
Host smart-ade442e8-6603-466c-a8fb-4a5030f9f004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981658398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1981658398
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2643198284
Short name T520
Test name
Test status
Simulation time 50549598 ps
CPU time 0.77 seconds
Started Jun 02 03:15:55 PM PDT 24
Finished Jun 02 03:15:56 PM PDT 24
Peak memory 206424 kb
Host smart-6a7faca3-9994-466a-a7ed-8ad8d9c2fa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643198284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2643198284
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3843831308
Short name T510
Test name
Test status
Simulation time 14444005122 ps
CPU time 126.96 seconds
Started Jun 02 03:16:00 PM PDT 24
Finished Jun 02 03:18:08 PM PDT 24
Peak memory 249004 kb
Host smart-4b3caba9-7715-4bb3-b035-85a022b6886e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843831308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3843831308
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3273988735
Short name T594
Test name
Test status
Simulation time 46372377172 ps
CPU time 202.79 seconds
Started Jun 02 03:16:02 PM PDT 24
Finished Jun 02 03:19:25 PM PDT 24
Peak memory 239064 kb
Host smart-a596a7bc-b957-4a5b-a14c-57d2505a3499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273988735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3273988735
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3600757812
Short name T192
Test name
Test status
Simulation time 3315401573 ps
CPU time 87.82 seconds
Started Jun 02 03:16:03 PM PDT 24
Finished Jun 02 03:17:32 PM PDT 24
Peak memory 257040 kb
Host smart-b950b86b-5e6b-4a18-a9b5-656bc749a830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600757812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3600757812
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1682513983
Short name T393
Test name
Test status
Simulation time 747256975 ps
CPU time 18.98 seconds
Started Jun 02 03:15:55 PM PDT 24
Finished Jun 02 03:16:14 PM PDT 24
Peak memory 245508 kb
Host smart-f621a5cf-4895-4a63-8197-c293e99033b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682513983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1682513983
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2010458957
Short name T244
Test name
Test status
Simulation time 85025640 ps
CPU time 3.34 seconds
Started Jun 02 03:15:55 PM PDT 24
Finished Jun 02 03:15:59 PM PDT 24
Peak memory 219560 kb
Host smart-d96a87f7-5248-4f3c-b1fd-5780b693fef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010458957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2010458957
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1776871724
Short name T524
Test name
Test status
Simulation time 642295243 ps
CPU time 7.36 seconds
Started Jun 02 03:15:54 PM PDT 24
Finished Jun 02 03:16:02 PM PDT 24
Peak memory 218364 kb
Host smart-09841560-a61b-4db7-a3d7-567f94a261b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776871724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1776871724
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1167846291
Short name T259
Test name
Test status
Simulation time 423084417 ps
CPU time 3.55 seconds
Started Jun 02 03:15:54 PM PDT 24
Finished Jun 02 03:15:58 PM PDT 24
Peak memory 233668 kb
Host smart-c6372cd6-ddf8-4a0f-99e0-d2d14502e45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167846291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1167846291
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.262492194
Short name T249
Test name
Test status
Simulation time 4805525270 ps
CPU time 17.95 seconds
Started Jun 02 03:15:55 PM PDT 24
Finished Jun 02 03:16:13 PM PDT 24
Peak memory 240400 kb
Host smart-1b76fcdd-f623-4fb3-93d9-8b53907ed4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262492194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.262492194
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.42559386
Short name T854
Test name
Test status
Simulation time 2774096022 ps
CPU time 9.13 seconds
Started Jun 02 03:15:54 PM PDT 24
Finished Jun 02 03:16:04 PM PDT 24
Peak memory 218860 kb
Host smart-be723de7-1c3a-46b6-a93e-4b5ee16773ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=42559386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direc
t.42559386
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.39142360
Short name T308
Test name
Test status
Simulation time 4036380013 ps
CPU time 11.12 seconds
Started Jun 02 03:15:56 PM PDT 24
Finished Jun 02 03:16:07 PM PDT 24
Peak memory 216268 kb
Host smart-a33fd08b-13e2-40df-ad4a-435c9249077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39142360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.39142360
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.759369879
Short name T9
Test name
Test status
Simulation time 2456593765 ps
CPU time 2.34 seconds
Started Jun 02 03:15:57 PM PDT 24
Finished Jun 02 03:16:00 PM PDT 24
Peak memory 207740 kb
Host smart-090829d2-5d7d-49fd-ad9b-919e08a913dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759369879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.759369879
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2599360918
Short name T349
Test name
Test status
Simulation time 29481807 ps
CPU time 1.51 seconds
Started Jun 02 03:15:55 PM PDT 24
Finished Jun 02 03:15:57 PM PDT 24
Peak memory 216152 kb
Host smart-9ddb0c06-ed0c-4cfc-b593-8640f11196c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599360918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2599360918
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1285752424
Short name T436
Test name
Test status
Simulation time 265267057 ps
CPU time 0.89 seconds
Started Jun 02 03:15:54 PM PDT 24
Finished Jun 02 03:15:55 PM PDT 24
Peak memory 205856 kb
Host smart-b51fe8fa-8a7e-4e3b-aec5-1d5e56140525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285752424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1285752424
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.960112805
Short name T771
Test name
Test status
Simulation time 6312568588 ps
CPU time 7.52 seconds
Started Jun 02 03:15:55 PM PDT 24
Finished Jun 02 03:16:03 PM PDT 24
Peak memory 218752 kb
Host smart-4d33862c-faca-49a9-97b5-dbcf1cbfde0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960112805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.960112805
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1117836424
Short name T414
Test name
Test status
Simulation time 13970159 ps
CPU time 0.71 seconds
Started Jun 02 03:15:58 PM PDT 24
Finished Jun 02 03:16:00 PM PDT 24
Peak memory 205472 kb
Host smart-463db07f-71ce-44ca-b504-79d262f9809d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117836424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1117836424
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.638203330
Short name T99
Test name
Test status
Simulation time 76180995 ps
CPU time 3.02 seconds
Started Jun 02 03:15:59 PM PDT 24
Finished Jun 02 03:16:03 PM PDT 24
Peak memory 218544 kb
Host smart-24122e8a-4fc8-4da0-8eea-a096b618a6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638203330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.638203330
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3579578318
Short name T423
Test name
Test status
Simulation time 16494503 ps
CPU time 0.75 seconds
Started Jun 02 03:16:01 PM PDT 24
Finished Jun 02 03:16:02 PM PDT 24
Peak memory 205384 kb
Host smart-a1f1554f-e655-487e-b993-972fb17318bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579578318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3579578318
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1081793704
Short name T293
Test name
Test status
Simulation time 198562086981 ps
CPU time 490.48 seconds
Started Jun 02 03:15:59 PM PDT 24
Finished Jun 02 03:24:10 PM PDT 24
Peak memory 265396 kb
Host smart-2bce4327-35d6-4c7e-a787-354584752048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081793704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1081793704
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1854354309
Short name T292
Test name
Test status
Simulation time 23270503925 ps
CPU time 62.23 seconds
Started Jun 02 03:16:03 PM PDT 24
Finished Jun 02 03:17:06 PM PDT 24
Peak memory 255028 kb
Host smart-875db013-2d34-4e40-8478-604253089385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854354309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1854354309
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.392423971
Short name T415
Test name
Test status
Simulation time 219904789 ps
CPU time 5.61 seconds
Started Jun 02 03:16:00 PM PDT 24
Finished Jun 02 03:16:06 PM PDT 24
Peak memory 232552 kb
Host smart-400148e1-7422-4d1c-8319-a4e7209ae139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392423971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.392423971
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3013857898
Short name T583
Test name
Test status
Simulation time 713954493 ps
CPU time 8.82 seconds
Started Jun 02 03:16:02 PM PDT 24
Finished Jun 02 03:16:11 PM PDT 24
Peak memory 234416 kb
Host smart-8ce9f476-5a8b-423c-85dd-3d80c1a61b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013857898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3013857898
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3101411122
Short name T813
Test name
Test status
Simulation time 2041135439 ps
CPU time 29.46 seconds
Started Jun 02 03:15:59 PM PDT 24
Finished Jun 02 03:16:29 PM PDT 24
Peak memory 231972 kb
Host smart-a5814770-c667-45fe-8c19-7e6c504640d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101411122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3101411122
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2540828449
Short name T319
Test name
Test status
Simulation time 235702921 ps
CPU time 2.98 seconds
Started Jun 02 03:15:59 PM PDT 24
Finished Jun 02 03:16:03 PM PDT 24
Peak memory 232540 kb
Host smart-5b960c72-066f-4562-8b62-26db5e5fae8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540828449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2540828449
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3756213398
Short name T564
Test name
Test status
Simulation time 1337153113 ps
CPU time 3.3 seconds
Started Jun 02 03:16:04 PM PDT 24
Finished Jun 02 03:16:08 PM PDT 24
Peak memory 218536 kb
Host smart-a6fa5d9d-5742-4343-a6a2-35854e564f39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3756213398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3756213398
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3043343091
Short name T808
Test name
Test status
Simulation time 2611486041 ps
CPU time 7.86 seconds
Started Jun 02 03:16:00 PM PDT 24
Finished Jun 02 03:16:09 PM PDT 24
Peak memory 216308 kb
Host smart-01de9da2-3a07-4991-830e-1f0c42d1d71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043343091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3043343091
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3430609058
Short name T869
Test name
Test status
Simulation time 1344230715 ps
CPU time 2.41 seconds
Started Jun 02 03:15:58 PM PDT 24
Finished Jun 02 03:16:01 PM PDT 24
Peak memory 216080 kb
Host smart-14c78932-fb3e-48f0-a4be-bf756055fb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430609058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3430609058
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.589099219
Short name T529
Test name
Test status
Simulation time 56717434 ps
CPU time 1.57 seconds
Started Jun 02 03:16:02 PM PDT 24
Finished Jun 02 03:16:04 PM PDT 24
Peak memory 216152 kb
Host smart-bfeeb16e-aed6-4b12-9f71-6f6f5f050822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589099219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.589099219
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1469064774
Short name T87
Test name
Test status
Simulation time 58928478 ps
CPU time 0.74 seconds
Started Jun 02 03:16:01 PM PDT 24
Finished Jun 02 03:16:02 PM PDT 24
Peak memory 205632 kb
Host smart-8fd40a4e-95ba-4a7c-b76f-387f0f4bafde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469064774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1469064774
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2549015452
Short name T768
Test name
Test status
Simulation time 93402415 ps
CPU time 2.09 seconds
Started Jun 02 03:16:00 PM PDT 24
Finished Jun 02 03:16:03 PM PDT 24
Peak memory 215916 kb
Host smart-32b24b88-ac45-4635-a9d1-59ee8bd075b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549015452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2549015452
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4084443371
Short name T75
Test name
Test status
Simulation time 29744547 ps
CPU time 0.68 seconds
Started Jun 02 03:16:00 PM PDT 24
Finished Jun 02 03:16:02 PM PDT 24
Peak memory 204756 kb
Host smart-464f0b61-fc6c-4b9a-af8a-334dcc91f6c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084443371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4084443371
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1973572478
Short name T403
Test name
Test status
Simulation time 225598988 ps
CPU time 3.63 seconds
Started Jun 02 03:16:06 PM PDT 24
Finished Jun 02 03:16:11 PM PDT 24
Peak memory 218704 kb
Host smart-8847e5dc-d1f6-423b-a31f-d72df39e79b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973572478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1973572478
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.50958726
Short name T57
Test name
Test status
Simulation time 21619008 ps
CPU time 0.74 seconds
Started Jun 02 03:16:00 PM PDT 24
Finished Jun 02 03:16:02 PM PDT 24
Peak memory 205400 kb
Host smart-53f88180-4312-41b2-bc05-d9b0cb7acc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50958726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.50958726
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3256897319
Short name T835
Test name
Test status
Simulation time 47369641415 ps
CPU time 129.67 seconds
Started Jun 02 03:16:04 PM PDT 24
Finished Jun 02 03:18:14 PM PDT 24
Peak memory 240860 kb
Host smart-5b4616db-0e70-40a0-a995-4ac3ea7e38c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256897319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3256897319
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2759624965
Short name T783
Test name
Test status
Simulation time 11442091270 ps
CPU time 45.5 seconds
Started Jun 02 03:16:03 PM PDT 24
Finished Jun 02 03:16:49 PM PDT 24
Peak memory 224276 kb
Host smart-bb3c5dba-be5a-4c79-9501-362d3a75a7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759624965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2759624965
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3545503647
Short name T934
Test name
Test status
Simulation time 69475524211 ps
CPU time 74.99 seconds
Started Jun 02 03:16:00 PM PDT 24
Finished Jun 02 03:17:16 PM PDT 24
Peak memory 232724 kb
Host smart-d873058c-f3e6-4062-af00-e2c184f0457b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545503647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3545503647
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3112485449
Short name T151
Test name
Test status
Simulation time 1352663136 ps
CPU time 10.97 seconds
Started Jun 02 03:16:00 PM PDT 24
Finished Jun 02 03:16:12 PM PDT 24
Peak memory 232572 kb
Host smart-bb50b320-1488-480c-b9c1-2e8577a63825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112485449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3112485449
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3164392008
Short name T626
Test name
Test status
Simulation time 801841145 ps
CPU time 8.58 seconds
Started Jun 02 03:16:03 PM PDT 24
Finished Jun 02 03:16:13 PM PDT 24
Peak memory 221116 kb
Host smart-ca4e03d2-58f3-4baf-803d-5fadd13059c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164392008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3164392008
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.983806825
Short name T394
Test name
Test status
Simulation time 417215837 ps
CPU time 5.97 seconds
Started Jun 02 03:16:02 PM PDT 24
Finished Jun 02 03:16:09 PM PDT 24
Peak memory 227656 kb
Host smart-ab5541a6-dac8-4001-9a34-007f7fc2b132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983806825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.983806825
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1788763826
Short name T296
Test name
Test status
Simulation time 11396304254 ps
CPU time 18.01 seconds
Started Jun 02 03:16:00 PM PDT 24
Finished Jun 02 03:16:19 PM PDT 24
Peak memory 226764 kb
Host smart-edf0d363-43a7-4616-b934-c42e43ce54f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788763826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1788763826
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1770030030
Short name T649
Test name
Test status
Simulation time 222581298 ps
CPU time 2.56 seconds
Started Jun 02 03:16:00 PM PDT 24
Finished Jun 02 03:16:04 PM PDT 24
Peak memory 218704 kb
Host smart-f8b9c9a8-540f-413f-906f-af6fb802697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770030030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1770030030
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3785953500
Short name T500
Test name
Test status
Simulation time 342160252 ps
CPU time 3.47 seconds
Started Jun 02 03:16:02 PM PDT 24
Finished Jun 02 03:16:07 PM PDT 24
Peak memory 222812 kb
Host smart-c82c082a-06d6-4235-b4a0-cc0dea07ebac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3785953500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3785953500
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.4285972378
Short name T162
Test name
Test status
Simulation time 2838872240 ps
CPU time 12.61 seconds
Started Jun 02 03:16:01 PM PDT 24
Finished Jun 02 03:16:14 PM PDT 24
Peak memory 224416 kb
Host smart-54537d07-f3a3-4fd3-a975-63fe5760096d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285972378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.4285972378
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.73051712
Short name T342
Test name
Test status
Simulation time 17080452 ps
CPU time 0.73 seconds
Started Jun 02 03:16:03 PM PDT 24
Finished Jun 02 03:16:04 PM PDT 24
Peak memory 205520 kb
Host smart-fae93e06-6818-43ac-bcab-a5db9dd23919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73051712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.73051712
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1798720097
Short name T327
Test name
Test status
Simulation time 133570869 ps
CPU time 1.21 seconds
Started Jun 02 03:16:00 PM PDT 24
Finished Jun 02 03:16:02 PM PDT 24
Peak memory 206820 kb
Host smart-2c37079b-9b0f-47f2-9353-c8e1f921d508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798720097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1798720097
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2781847528
Short name T688
Test name
Test status
Simulation time 22736652 ps
CPU time 0.69 seconds
Started Jun 02 03:16:00 PM PDT 24
Finished Jun 02 03:16:02 PM PDT 24
Peak memory 205448 kb
Host smart-6e4503b8-ed1e-4c0b-b5b0-bfa846855344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781847528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2781847528
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.4101623343
Short name T356
Test name
Test status
Simulation time 21277732 ps
CPU time 0.74 seconds
Started Jun 02 03:15:59 PM PDT 24
Finished Jun 02 03:16:00 PM PDT 24
Peak memory 205656 kb
Host smart-dec00b42-7e8c-42bf-9a3e-9dc646f7acef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101623343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.4101623343
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2863702524
Short name T910
Test name
Test status
Simulation time 1204048911 ps
CPU time 9.86 seconds
Started Jun 02 03:16:01 PM PDT 24
Finished Jun 02 03:16:12 PM PDT 24
Peak memory 234776 kb
Host smart-9c5443f0-7889-4e03-a7c4-2712dc0b468b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863702524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2863702524
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2098471641
Short name T729
Test name
Test status
Simulation time 13164983 ps
CPU time 0.74 seconds
Started Jun 02 03:16:10 PM PDT 24
Finished Jun 02 03:16:12 PM PDT 24
Peak memory 205412 kb
Host smart-6eac5c8e-5a75-47a3-b71b-9929fc7562b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098471641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2098471641
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2962767791
Short name T607
Test name
Test status
Simulation time 671182816 ps
CPU time 3.93 seconds
Started Jun 02 03:16:08 PM PDT 24
Finished Jun 02 03:16:13 PM PDT 24
Peak memory 219732 kb
Host smart-2590541e-2967-4f76-af45-e09d9c9957ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962767791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2962767791
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2748584933
Short name T713
Test name
Test status
Simulation time 22279628 ps
CPU time 0.82 seconds
Started Jun 02 03:16:01 PM PDT 24
Finished Jun 02 03:16:02 PM PDT 24
Peak memory 206500 kb
Host smart-0129f379-21a6-4e64-8c92-1c379191bc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748584933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2748584933
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2421208376
Short name T617
Test name
Test status
Simulation time 4930073551 ps
CPU time 46.79 seconds
Started Jun 02 03:16:16 PM PDT 24
Finished Jun 02 03:17:03 PM PDT 24
Peak memory 240016 kb
Host smart-87d7d6ab-d9bf-4780-a8fe-06546654fa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421208376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2421208376
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1987793086
Short name T958
Test name
Test status
Simulation time 3901171416 ps
CPU time 81.86 seconds
Started Jun 02 03:16:07 PM PDT 24
Finished Jun 02 03:17:29 PM PDT 24
Peak memory 249108 kb
Host smart-510e49a1-eb52-45a3-8d35-b86cd626b546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987793086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1987793086
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2797515161
Short name T658
Test name
Test status
Simulation time 282464055 ps
CPU time 7.25 seconds
Started Jun 02 03:16:09 PM PDT 24
Finished Jun 02 03:16:16 PM PDT 24
Peak memory 224340 kb
Host smart-6e9d4e4c-43b3-45b6-b9e0-105543fc9475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797515161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2797515161
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1667681102
Short name T387
Test name
Test status
Simulation time 615536256 ps
CPU time 4.76 seconds
Started Jun 02 03:16:04 PM PDT 24
Finished Jun 02 03:16:09 PM PDT 24
Peak memory 224336 kb
Host smart-19292a29-07ab-4571-ab2f-04b43e5f4530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667681102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1667681102
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3099939536
Short name T265
Test name
Test status
Simulation time 180741682 ps
CPU time 4.66 seconds
Started Jun 02 03:16:08 PM PDT 24
Finished Jun 02 03:16:13 PM PDT 24
Peak memory 234184 kb
Host smart-e87494e6-5e5d-45fb-8386-dc10eb12e4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099939536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3099939536
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3701709274
Short name T337
Test name
Test status
Simulation time 4565787342 ps
CPU time 7.98 seconds
Started Jun 02 03:16:07 PM PDT 24
Finished Jun 02 03:16:15 PM PDT 24
Peak memory 218336 kb
Host smart-5a3ed908-813b-4efd-aa24-db18f7eefd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701709274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3701709274
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1229226796
Short name T8
Test name
Test status
Simulation time 757239474 ps
CPU time 10.04 seconds
Started Jun 02 03:16:06 PM PDT 24
Finished Jun 02 03:16:17 PM PDT 24
Peak memory 250920 kb
Host smart-8417160b-9291-4c39-9929-5527b2fb7a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229226796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1229226796
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1383738599
Short name T629
Test name
Test status
Simulation time 260366766 ps
CPU time 3.82 seconds
Started Jun 02 03:16:06 PM PDT 24
Finished Jun 02 03:16:10 PM PDT 24
Peak memory 219868 kb
Host smart-43e272fd-82a3-4fdb-8efd-c966ff1bbea4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1383738599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1383738599
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1056189207
Short name T286
Test name
Test status
Simulation time 50318404627 ps
CPU time 466.59 seconds
Started Jun 02 03:16:06 PM PDT 24
Finished Jun 02 03:23:54 PM PDT 24
Peak memory 288952 kb
Host smart-17d664cb-e73e-430f-89df-0687846b6a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056189207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1056189207
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3950225344
Short name T789
Test name
Test status
Simulation time 2121970081 ps
CPU time 30.84 seconds
Started Jun 02 03:16:06 PM PDT 24
Finished Jun 02 03:16:37 PM PDT 24
Peak memory 216188 kb
Host smart-22befcb6-73db-4753-bd97-4ccb84d1b011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950225344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3950225344
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1365055637
Short name T465
Test name
Test status
Simulation time 8101394198 ps
CPU time 3.4 seconds
Started Jun 02 03:16:10 PM PDT 24
Finished Jun 02 03:16:13 PM PDT 24
Peak memory 216164 kb
Host smart-63b92ec6-0370-4724-b475-99b13ec4b279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365055637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1365055637
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4188850546
Short name T324
Test name
Test status
Simulation time 99940242 ps
CPU time 1.1 seconds
Started Jun 02 03:16:07 PM PDT 24
Finished Jun 02 03:16:08 PM PDT 24
Peak memory 207224 kb
Host smart-d0e800b9-d3e3-4745-8d1a-72285586b528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188850546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4188850546
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1707043722
Short name T340
Test name
Test status
Simulation time 83910555 ps
CPU time 0.78 seconds
Started Jun 02 03:16:06 PM PDT 24
Finished Jun 02 03:16:07 PM PDT 24
Peak memory 205600 kb
Host smart-4faf9ed5-1419-46cb-bda3-c264473e6db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707043722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1707043722
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.127753664
Short name T785
Test name
Test status
Simulation time 126449106 ps
CPU time 2.59 seconds
Started Jun 02 03:16:05 PM PDT 24
Finished Jun 02 03:16:08 PM PDT 24
Peak memory 224508 kb
Host smart-672c0f7a-dd4a-4786-b2a8-008db3e4a0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127753664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.127753664
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1546326067
Short name T316
Test name
Test status
Simulation time 47820378 ps
CPU time 0.7 seconds
Started Jun 02 03:16:14 PM PDT 24
Finished Jun 02 03:16:15 PM PDT 24
Peak memory 205348 kb
Host smart-ea7d8a57-3b0b-4418-bc10-7fc35a021532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546326067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1546326067
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1201640307
Short name T409
Test name
Test status
Simulation time 2858371896 ps
CPU time 6.52 seconds
Started Jun 02 03:16:05 PM PDT 24
Finished Jun 02 03:16:12 PM PDT 24
Peak memory 218896 kb
Host smart-20aa76cf-8cac-49b6-a3a7-0fb69f942ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201640307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1201640307
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1724686081
Short name T870
Test name
Test status
Simulation time 66848554 ps
CPU time 0.77 seconds
Started Jun 02 03:16:10 PM PDT 24
Finished Jun 02 03:16:11 PM PDT 24
Peak memory 206396 kb
Host smart-eaa4f1d2-3a42-4ed5-b261-245bfa18e24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724686081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1724686081
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3382955730
Short name T656
Test name
Test status
Simulation time 114142089 ps
CPU time 0.95 seconds
Started Jun 02 03:16:13 PM PDT 24
Finished Jun 02 03:16:14 PM PDT 24
Peak memory 215968 kb
Host smart-e0934d22-b044-4bdd-b822-9201171cdb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382955730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3382955730
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3945110194
Short name T312
Test name
Test status
Simulation time 72042087958 ps
CPU time 33.19 seconds
Started Jun 02 03:16:13 PM PDT 24
Finished Jun 02 03:16:46 PM PDT 24
Peak memory 217172 kb
Host smart-5cd27f26-44c2-4c7f-a868-98606e6149b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945110194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3945110194
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1305693140
Short name T558
Test name
Test status
Simulation time 1351756960 ps
CPU time 14.46 seconds
Started Jun 02 03:16:11 PM PDT 24
Finished Jun 02 03:16:25 PM PDT 24
Peak memory 232660 kb
Host smart-d4e6047f-c2b0-45b9-a25e-6b478ac329dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305693140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1305693140
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3210509143
Short name T246
Test name
Test status
Simulation time 1188598281 ps
CPU time 7.73 seconds
Started Jun 02 03:16:04 PM PDT 24
Finished Jun 02 03:16:12 PM PDT 24
Peak memory 233460 kb
Host smart-6ff0f6a3-25ef-4a82-b2e1-8d70a6534c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210509143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3210509143
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2736395103
Short name T563
Test name
Test status
Simulation time 25198359610 ps
CPU time 71.48 seconds
Started Jun 02 03:16:09 PM PDT 24
Finished Jun 02 03:17:21 PM PDT 24
Peak memory 231576 kb
Host smart-022012de-9dfe-4e3e-946e-d01565c3f02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736395103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2736395103
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1066750390
Short name T543
Test name
Test status
Simulation time 9104843843 ps
CPU time 24.2 seconds
Started Jun 02 03:16:05 PM PDT 24
Finished Jun 02 03:16:30 PM PDT 24
Peak memory 218404 kb
Host smart-95cbde7f-1d7e-4f15-bd16-2a894bb3620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066750390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1066750390
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.387633822
Short name T801
Test name
Test status
Simulation time 4946071562 ps
CPU time 8.58 seconds
Started Jun 02 03:16:06 PM PDT 24
Finished Jun 02 03:16:15 PM PDT 24
Peak memory 233784 kb
Host smart-b52be222-57c8-4e62-8a43-bd091125ef39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387633822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.387633822
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4116244222
Short name T690
Test name
Test status
Simulation time 414210257 ps
CPU time 6.99 seconds
Started Jun 02 03:16:11 PM PDT 24
Finished Jun 02 03:16:19 PM PDT 24
Peak memory 218876 kb
Host smart-7d48e77a-bc02-4b7e-8d46-06325a8b923f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4116244222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4116244222
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1553609791
Short name T764
Test name
Test status
Simulation time 159062300 ps
CPU time 1.26 seconds
Started Jun 02 03:16:13 PM PDT 24
Finished Jun 02 03:16:15 PM PDT 24
Peak memory 207080 kb
Host smart-09c4b7ed-745e-4a73-ae2e-c0a3c3e79b73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553609791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1553609791
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3540814090
Short name T6
Test name
Test status
Simulation time 2805792564 ps
CPU time 29.5 seconds
Started Jun 02 03:16:05 PM PDT 24
Finished Jun 02 03:16:35 PM PDT 24
Peak memory 216404 kb
Host smart-ee0c2173-6e4b-4f0b-a2a5-76a9b9fbdd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540814090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3540814090
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.959766347
Short name T708
Test name
Test status
Simulation time 6798740255 ps
CPU time 21.1 seconds
Started Jun 02 03:16:08 PM PDT 24
Finished Jun 02 03:16:29 PM PDT 24
Peak memory 216220 kb
Host smart-5f707921-b375-4e95-bdaf-8916f405ea18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959766347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.959766347
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.318717830
Short name T440
Test name
Test status
Simulation time 392382041 ps
CPU time 3.45 seconds
Started Jun 02 03:16:06 PM PDT 24
Finished Jun 02 03:16:10 PM PDT 24
Peak memory 216380 kb
Host smart-39304c5a-c2f4-44cd-8cba-978155b4a2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318717830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.318717830
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3026025263
Short name T679
Test name
Test status
Simulation time 97442203 ps
CPU time 0.93 seconds
Started Jun 02 03:16:06 PM PDT 24
Finished Jun 02 03:16:08 PM PDT 24
Peak memory 205640 kb
Host smart-ac907b1e-6dea-4cb9-9749-273806664d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026025263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3026025263
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.140697245
Short name T805
Test name
Test status
Simulation time 3029410205 ps
CPU time 12.18 seconds
Started Jun 02 03:16:09 PM PDT 24
Finished Jun 02 03:16:21 PM PDT 24
Peak memory 233940 kb
Host smart-d6ffadff-5357-46c1-8e7c-263f0c3e5776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140697245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.140697245
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2359009140
Short name T696
Test name
Test status
Simulation time 28599945 ps
CPU time 0.8 seconds
Started Jun 02 03:16:12 PM PDT 24
Finished Jun 02 03:16:13 PM PDT 24
Peak memory 205740 kb
Host smart-b5e16f35-3b28-417f-80f7-75b865bfbc13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359009140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2359009140
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1960715708
Short name T401
Test name
Test status
Simulation time 299518023 ps
CPU time 5.89 seconds
Started Jun 02 03:16:15 PM PDT 24
Finished Jun 02 03:16:21 PM PDT 24
Peak memory 218548 kb
Host smart-bec949f7-1288-4025-8eb3-2d533fcccaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960715708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1960715708
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.361551592
Short name T722
Test name
Test status
Simulation time 25360943 ps
CPU time 0.81 seconds
Started Jun 02 03:16:14 PM PDT 24
Finished Jun 02 03:16:15 PM PDT 24
Peak memory 206696 kb
Host smart-86b1dd5b-d19d-4670-9777-355d9780604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361551592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.361551592
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.866227050
Short name T915
Test name
Test status
Simulation time 11194675161 ps
CPU time 97.36 seconds
Started Jun 02 03:16:15 PM PDT 24
Finished Jun 02 03:17:53 PM PDT 24
Peak memory 239256 kb
Host smart-d82c202f-2320-49fb-9002-7a623176d7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866227050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.866227050
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1770526268
Short name T477
Test name
Test status
Simulation time 251641348 ps
CPU time 4.09 seconds
Started Jun 02 03:16:12 PM PDT 24
Finished Jun 02 03:16:17 PM PDT 24
Peak memory 231268 kb
Host smart-af54f6b8-1355-4f45-b66e-ac8fa252c9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770526268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1770526268
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.381252088
Short name T530
Test name
Test status
Simulation time 152105512 ps
CPU time 5.09 seconds
Started Jun 02 03:16:11 PM PDT 24
Finished Jun 02 03:16:17 PM PDT 24
Peak memory 233416 kb
Host smart-a469af02-d339-4a4e-8e58-f4de3f155e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381252088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.381252088
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3042057916
Short name T691
Test name
Test status
Simulation time 177710865 ps
CPU time 2.16 seconds
Started Jun 02 03:16:11 PM PDT 24
Finished Jun 02 03:16:14 PM PDT 24
Peak memory 215992 kb
Host smart-47de393d-6760-4e9b-b93d-5e9ed58397b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042057916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3042057916
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.397172544
Short name T194
Test name
Test status
Simulation time 14630699934 ps
CPU time 12.97 seconds
Started Jun 02 03:16:13 PM PDT 24
Finished Jun 02 03:16:26 PM PDT 24
Peak memory 233756 kb
Host smart-64492fbe-32ee-4df8-89c3-3be595642d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397172544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.397172544
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1572707506
Short name T605
Test name
Test status
Simulation time 367895159 ps
CPU time 3.55 seconds
Started Jun 02 03:16:16 PM PDT 24
Finished Jun 02 03:16:20 PM PDT 24
Peak memory 218608 kb
Host smart-015f91a7-350f-49d4-a691-18f33e4ce287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572707506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1572707506
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3535235503
Short name T599
Test name
Test status
Simulation time 2469419787 ps
CPU time 11.1 seconds
Started Jun 02 03:16:15 PM PDT 24
Finished Jun 02 03:16:27 PM PDT 24
Peak memory 221996 kb
Host smart-529ecc8e-0766-4bea-be01-3f42bdfbf674
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3535235503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3535235503
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.573625539
Short name T504
Test name
Test status
Simulation time 7961674134 ps
CPU time 22.01 seconds
Started Jun 02 03:16:12 PM PDT 24
Finished Jun 02 03:16:35 PM PDT 24
Peak memory 219860 kb
Host smart-77f29238-ddc0-40c6-8830-713e78a397ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573625539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.573625539
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3159126883
Short name T552
Test name
Test status
Simulation time 3002835957 ps
CPU time 2.46 seconds
Started Jun 02 03:16:14 PM PDT 24
Finished Jun 02 03:16:17 PM PDT 24
Peak memory 207728 kb
Host smart-e96a45d4-dd99-4a89-9f3c-360e48d89a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159126883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3159126883
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3822831459
Short name T528
Test name
Test status
Simulation time 12648543 ps
CPU time 0.68 seconds
Started Jun 02 03:16:15 PM PDT 24
Finished Jun 02 03:16:16 PM PDT 24
Peak memory 205472 kb
Host smart-182caa48-93e0-4790-8b95-c43cc277bebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822831459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3822831459
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3420686733
Short name T168
Test name
Test status
Simulation time 680647162 ps
CPU time 0.88 seconds
Started Jun 02 03:16:15 PM PDT 24
Finished Jun 02 03:16:17 PM PDT 24
Peak memory 205660 kb
Host smart-cc085841-53ad-4d0f-a166-8ff7ab61c8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420686733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3420686733
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2833885444
Short name T834
Test name
Test status
Simulation time 4743271707 ps
CPU time 8.84 seconds
Started Jun 02 03:16:14 PM PDT 24
Finished Jun 02 03:16:23 PM PDT 24
Peak memory 219744 kb
Host smart-46d04dd7-2a9e-4ca9-aed1-7b0501bee4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833885444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2833885444
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2006883533
Short name T950
Test name
Test status
Simulation time 21797168 ps
CPU time 0.7 seconds
Started Jun 02 03:16:18 PM PDT 24
Finished Jun 02 03:16:19 PM PDT 24
Peak memory 204832 kb
Host smart-d387dc6f-040a-4bf4-9632-d9360477a730
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006883533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2006883533
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3455417722
Short name T363
Test name
Test status
Simulation time 64037922 ps
CPU time 2.23 seconds
Started Jun 02 03:16:24 PM PDT 24
Finished Jun 02 03:16:26 PM PDT 24
Peak memory 218528 kb
Host smart-1a04aa1c-4633-4095-a414-e8bc75be0359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455417722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3455417722
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2495675776
Short name T514
Test name
Test status
Simulation time 72997771 ps
CPU time 0.81 seconds
Started Jun 02 03:16:12 PM PDT 24
Finished Jun 02 03:16:13 PM PDT 24
Peak memory 206388 kb
Host smart-5c80a6c8-d7e1-41ef-beda-91548e1a9e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495675776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2495675776
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.4193403857
Short name T285
Test name
Test status
Simulation time 533126783 ps
CPU time 13.04 seconds
Started Jun 02 03:16:19 PM PDT 24
Finished Jun 02 03:16:32 PM PDT 24
Peak memory 235236 kb
Host smart-da12b8ed-fae0-45f0-939e-095ad121002a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193403857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.4193403857
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3782071890
Short name T817
Test name
Test status
Simulation time 1212094704 ps
CPU time 13.33 seconds
Started Jun 02 03:16:18 PM PDT 24
Finished Jun 02 03:16:32 PM PDT 24
Peak memory 217148 kb
Host smart-7987a0a9-f809-4774-ac6c-ebe4b3885d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782071890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3782071890
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2133916418
Short name T174
Test name
Test status
Simulation time 3845739522 ps
CPU time 96.62 seconds
Started Jun 02 03:16:25 PM PDT 24
Finished Jun 02 03:18:03 PM PDT 24
Peak memory 261804 kb
Host smart-02443e12-60d1-4d17-8d77-b6e9075f1c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133916418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2133916418
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2996382961
Short name T828
Test name
Test status
Simulation time 106673033 ps
CPU time 4.41 seconds
Started Jun 02 03:16:19 PM PDT 24
Finished Jun 02 03:16:24 PM PDT 24
Peak memory 232572 kb
Host smart-a5410d57-6217-4bef-9e5b-7dabaf430012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996382961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2996382961
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.640935339
Short name T909
Test name
Test status
Simulation time 1428123963 ps
CPU time 11.63 seconds
Started Jun 02 03:16:19 PM PDT 24
Finished Jun 02 03:16:31 PM PDT 24
Peak memory 224284 kb
Host smart-aa9b91c7-a95b-43a1-a655-584e63de0bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640935339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.640935339
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.192406562
Short name T213
Test name
Test status
Simulation time 3496408709 ps
CPU time 20.06 seconds
Started Jun 02 03:16:20 PM PDT 24
Finished Jun 02 03:16:40 PM PDT 24
Peak memory 234260 kb
Host smart-aecffcad-b8f9-4c82-beb5-9719801c68cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192406562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.192406562
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3746462414
Short name T888
Test name
Test status
Simulation time 48483055732 ps
CPU time 27.69 seconds
Started Jun 02 03:16:19 PM PDT 24
Finished Jun 02 03:16:47 PM PDT 24
Peak memory 240084 kb
Host smart-a400294b-00db-475c-b099-7a3d3dbce39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746462414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3746462414
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.557442450
Short name T499
Test name
Test status
Simulation time 3805794656 ps
CPU time 7.77 seconds
Started Jun 02 03:16:20 PM PDT 24
Finished Jun 02 03:16:28 PM PDT 24
Peak memory 218960 kb
Host smart-c54b63f9-d776-49ec-a444-b63262e98e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557442450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.557442450
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2481540690
Short name T874
Test name
Test status
Simulation time 324385551 ps
CPU time 3.96 seconds
Started Jun 02 03:16:27 PM PDT 24
Finished Jun 02 03:16:31 PM PDT 24
Peak memory 220552 kb
Host smart-e0c3e9b7-7046-4aa9-bd37-1a8e5648af73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2481540690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2481540690
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.717093377
Short name T485
Test name
Test status
Simulation time 7049161104 ps
CPU time 111.12 seconds
Started Jun 02 03:16:18 PM PDT 24
Finished Jun 02 03:18:09 PM PDT 24
Peak memory 251668 kb
Host smart-7b06dcc1-159a-44f8-b055-59a9fd8dd8a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717093377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.717093377
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.4100839666
Short name T550
Test name
Test status
Simulation time 1140175622 ps
CPU time 2.48 seconds
Started Jun 02 03:16:25 PM PDT 24
Finished Jun 02 03:16:28 PM PDT 24
Peak memory 216320 kb
Host smart-df69aff7-58fc-4c62-bc6f-657296c51f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100839666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4100839666
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.147580563
Short name T830
Test name
Test status
Simulation time 1289338499 ps
CPU time 4.92 seconds
Started Jun 02 03:16:19 PM PDT 24
Finished Jun 02 03:16:24 PM PDT 24
Peak memory 216068 kb
Host smart-c2729bef-b4c8-4ec9-810b-44050629b714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147580563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.147580563
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2585498689
Short name T878
Test name
Test status
Simulation time 17161146 ps
CPU time 0.91 seconds
Started Jun 02 03:16:23 PM PDT 24
Finished Jun 02 03:16:24 PM PDT 24
Peak memory 206472 kb
Host smart-ca9e4f08-f901-4192-99b2-11417903c738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585498689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2585498689
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3089521417
Short name T936
Test name
Test status
Simulation time 122388440 ps
CPU time 0.97 seconds
Started Jun 02 03:16:25 PM PDT 24
Finished Jun 02 03:16:26 PM PDT 24
Peak memory 206568 kb
Host smart-af7fc3fa-329b-4026-ad6f-57c16737e121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089521417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3089521417
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.4276589203
Short name T645
Test name
Test status
Simulation time 2715568805 ps
CPU time 9.21 seconds
Started Jun 02 03:16:21 PM PDT 24
Finished Jun 02 03:16:30 PM PDT 24
Peak memory 218680 kb
Host smart-1cbed72c-3fc1-4123-b240-b4e712dbcfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276589203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4276589203
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2164942416
Short name T345
Test name
Test status
Simulation time 38649827 ps
CPU time 0.76 seconds
Started Jun 02 03:16:27 PM PDT 24
Finished Jun 02 03:16:28 PM PDT 24
Peak memory 204812 kb
Host smart-96cedbf0-0da3-40bc-8518-e0f0697bff76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164942416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2164942416
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.997630277
Short name T743
Test name
Test status
Simulation time 132492388 ps
CPU time 2.36 seconds
Started Jun 02 03:16:27 PM PDT 24
Finished Jun 02 03:16:30 PM PDT 24
Peak memory 221528 kb
Host smart-7f28e56f-accc-41c0-aaf4-93c1d22cc6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997630277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.997630277
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.555029554
Short name T700
Test name
Test status
Simulation time 37783440 ps
CPU time 0.79 seconds
Started Jun 02 03:16:18 PM PDT 24
Finished Jun 02 03:16:20 PM PDT 24
Peak memory 206348 kb
Host smart-10635ddb-9934-4b05-a379-eb51da3f37c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555029554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.555029554
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3963823685
Short name T657
Test name
Test status
Simulation time 7965571797 ps
CPU time 21.16 seconds
Started Jun 02 03:16:24 PM PDT 24
Finished Jun 02 03:16:46 PM PDT 24
Peak memory 234792 kb
Host smart-1edf1547-1473-40be-ad30-320bf80c47d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963823685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3963823685
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2377930505
Short name T755
Test name
Test status
Simulation time 14818794456 ps
CPU time 86.13 seconds
Started Jun 02 03:16:24 PM PDT 24
Finished Jun 02 03:17:51 PM PDT 24
Peak memory 265508 kb
Host smart-45585173-a477-401c-bd4a-41c7fc21a548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377930505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2377930505
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2670655532
Short name T727
Test name
Test status
Simulation time 8766626008 ps
CPU time 24.53 seconds
Started Jun 02 03:16:32 PM PDT 24
Finished Jun 02 03:16:57 PM PDT 24
Peak memory 248924 kb
Host smart-d7a518ab-9f32-4a8c-8b6e-ed50945a7a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670655532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2670655532
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3350567484
Short name T788
Test name
Test status
Simulation time 69421899 ps
CPU time 4.42 seconds
Started Jun 02 03:16:26 PM PDT 24
Finished Jun 02 03:16:31 PM PDT 24
Peak memory 232592 kb
Host smart-0e550072-a5d7-4a79-bcd7-8a3d01ba2880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350567484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3350567484
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.304160221
Short name T793
Test name
Test status
Simulation time 145516380 ps
CPU time 2.3 seconds
Started Jun 02 03:16:25 PM PDT 24
Finished Jun 02 03:16:28 PM PDT 24
Peak memory 218628 kb
Host smart-cfabd606-3a19-453d-b35f-e1fc46ea5c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304160221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.304160221
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.4108165015
Short name T237
Test name
Test status
Simulation time 254611944 ps
CPU time 7.06 seconds
Started Jun 02 03:16:31 PM PDT 24
Finished Jun 02 03:16:39 PM PDT 24
Peak memory 239344 kb
Host smart-333fcd57-7342-4b89-8091-7814cd22514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108165015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.4108165015
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1242126200
Short name T880
Test name
Test status
Simulation time 1306834658 ps
CPU time 4.39 seconds
Started Jun 02 03:16:26 PM PDT 24
Finished Jun 02 03:16:31 PM PDT 24
Peak memory 233656 kb
Host smart-809aba69-236a-4d9b-90af-72ea069b731b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242126200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1242126200
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3354606618
Short name T919
Test name
Test status
Simulation time 2615883334 ps
CPU time 11.69 seconds
Started Jun 02 03:16:25 PM PDT 24
Finished Jun 02 03:16:38 PM PDT 24
Peak memory 226888 kb
Host smart-794958cc-f04d-402a-9aa3-39848eb2714d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354606618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3354606618
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4093147625
Short name T541
Test name
Test status
Simulation time 253744375 ps
CPU time 5.03 seconds
Started Jun 02 03:16:24 PM PDT 24
Finished Jun 02 03:16:30 PM PDT 24
Peak memory 218980 kb
Host smart-f4ee59a3-647f-453d-b60c-e706436e720a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4093147625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4093147625
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3975472381
Short name T483
Test name
Test status
Simulation time 916590380 ps
CPU time 10.5 seconds
Started Jun 02 03:16:24 PM PDT 24
Finished Jun 02 03:16:35 PM PDT 24
Peak memory 216288 kb
Host smart-5756f454-c0ba-4bd5-bb3e-4c475a2ccbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975472381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3975472381
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3345527978
Short name T669
Test name
Test status
Simulation time 1177065051 ps
CPU time 6.82 seconds
Started Jun 02 03:16:25 PM PDT 24
Finished Jun 02 03:16:32 PM PDT 24
Peak memory 216080 kb
Host smart-f7082cb8-1a9d-4ef3-8b5e-2f3d1db82e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345527978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3345527978
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1420922451
Short name T663
Test name
Test status
Simulation time 271514960 ps
CPU time 1.54 seconds
Started Jun 02 03:16:27 PM PDT 24
Finished Jun 02 03:16:29 PM PDT 24
Peak memory 216080 kb
Host smart-f636aa46-837f-49e3-bcfe-f0d46eed7f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420922451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1420922451
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.115810290
Short name T315
Test name
Test status
Simulation time 158810253 ps
CPU time 0.94 seconds
Started Jun 02 03:16:28 PM PDT 24
Finished Jun 02 03:16:29 PM PDT 24
Peak memory 205880 kb
Host smart-f990ec99-10ac-4f22-aab7-c0728ff0743a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115810290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.115810290
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.377637221
Short name T664
Test name
Test status
Simulation time 34774772 ps
CPU time 2.65 seconds
Started Jun 02 03:16:28 PM PDT 24
Finished Jun 02 03:16:31 PM PDT 24
Peak memory 212660 kb
Host smart-dc1677b0-692e-46ec-bd4e-1eb74f72c4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377637221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.377637221
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2274230077
Short name T795
Test name
Test status
Simulation time 11451514 ps
CPU time 0.72 seconds
Started Jun 02 03:16:30 PM PDT 24
Finished Jun 02 03:16:31 PM PDT 24
Peak memory 205404 kb
Host smart-5cfe3c42-1632-4aec-8c4a-1150685f0fc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274230077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2274230077
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3008525451
Short name T753
Test name
Test status
Simulation time 140752134 ps
CPU time 2.78 seconds
Started Jun 02 03:16:25 PM PDT 24
Finished Jun 02 03:16:29 PM PDT 24
Peak memory 233520 kb
Host smart-a837d3f0-00ba-43d7-8887-c499557694e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008525451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3008525451
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.4186955493
Short name T318
Test name
Test status
Simulation time 20575759 ps
CPU time 0.73 seconds
Started Jun 02 03:16:25 PM PDT 24
Finished Jun 02 03:16:27 PM PDT 24
Peak memory 205416 kb
Host smart-51030c36-00b8-467a-89d1-ee96d778e1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186955493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.4186955493
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1553735887
Short name T201
Test name
Test status
Simulation time 6610358134 ps
CPU time 63.86 seconds
Started Jun 02 03:16:28 PM PDT 24
Finished Jun 02 03:17:32 PM PDT 24
Peak memory 239292 kb
Host smart-e36a1730-59ed-402c-9862-8137e337b32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553735887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1553735887
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4014735784
Short name T205
Test name
Test status
Simulation time 2333604018 ps
CPU time 55.7 seconds
Started Jun 02 03:16:28 PM PDT 24
Finished Jun 02 03:17:24 PM PDT 24
Peak memory 262828 kb
Host smart-bc15465f-bca1-4ff5-8293-ee478eadfdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014735784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4014735784
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1724786492
Short name T659
Test name
Test status
Simulation time 233708967547 ps
CPU time 290.83 seconds
Started Jun 02 03:16:33 PM PDT 24
Finished Jun 02 03:21:24 PM PDT 24
Peak memory 250156 kb
Host smart-04ae6c96-aa08-49b5-a1d0-125d8f551564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724786492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1724786492
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1340968914
Short name T569
Test name
Test status
Simulation time 1824110945 ps
CPU time 26.28 seconds
Started Jun 02 03:16:25 PM PDT 24
Finished Jun 02 03:16:52 PM PDT 24
Peak memory 248972 kb
Host smart-52a7a53b-8f31-4753-b18b-e600be4c6a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340968914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1340968914
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.608729597
Short name T705
Test name
Test status
Simulation time 427216501 ps
CPU time 4.68 seconds
Started Jun 02 03:16:26 PM PDT 24
Finished Jun 02 03:16:31 PM PDT 24
Peak memory 233340 kb
Host smart-18a72180-5d20-4fb2-a894-d2bc6b004906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608729597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.608729597
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2660659611
Short name T929
Test name
Test status
Simulation time 917374505 ps
CPU time 7.13 seconds
Started Jun 02 03:16:26 PM PDT 24
Finished Jun 02 03:16:34 PM PDT 24
Peak memory 226660 kb
Host smart-d59673c0-bc1c-4738-8f6d-c621ad424488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660659611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2660659611
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2925361454
Short name T734
Test name
Test status
Simulation time 2734334604 ps
CPU time 9.05 seconds
Started Jun 02 03:16:33 PM PDT 24
Finished Jun 02 03:16:42 PM PDT 24
Peak memory 233056 kb
Host smart-8fb5cafb-b713-4a7a-9a43-a43706e2760e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925361454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2925361454
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.994295833
Short name T428
Test name
Test status
Simulation time 2849055742 ps
CPU time 11.06 seconds
Started Jun 02 03:16:26 PM PDT 24
Finished Jun 02 03:16:38 PM PDT 24
Peak memory 218576 kb
Host smart-c3d41630-cd84-4b89-973d-2bc325879b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994295833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.994295833
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3425391926
Short name T476
Test name
Test status
Simulation time 685928785 ps
CPU time 10.45 seconds
Started Jun 02 03:16:26 PM PDT 24
Finished Jun 02 03:16:37 PM PDT 24
Peak memory 222856 kb
Host smart-cfd34e70-55f4-43fa-9b84-1082dec26811
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3425391926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3425391926
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.17880079
Short name T160
Test name
Test status
Simulation time 105779773 ps
CPU time 1.16 seconds
Started Jun 02 03:16:26 PM PDT 24
Finished Jun 02 03:16:28 PM PDT 24
Peak memory 207112 kb
Host smart-83bf06d2-95c1-4bc1-b4d6-19dc0cd3c623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17880079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress
_all.17880079
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1077289603
Short name T925
Test name
Test status
Simulation time 15788614 ps
CPU time 0.72 seconds
Started Jun 02 03:16:32 PM PDT 24
Finished Jun 02 03:16:33 PM PDT 24
Peak memory 205844 kb
Host smart-6b18183d-f956-45ac-b2a9-da54e36ab578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077289603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1077289603
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.216840107
Short name T533
Test name
Test status
Simulation time 1829628740 ps
CPU time 4.92 seconds
Started Jun 02 03:16:23 PM PDT 24
Finished Jun 02 03:16:29 PM PDT 24
Peak memory 216080 kb
Host smart-03dddf2a-6333-472f-a529-6da404d8a17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216840107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.216840107
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.920417029
Short name T1
Test name
Test status
Simulation time 29672647 ps
CPU time 0.79 seconds
Started Jun 02 03:16:25 PM PDT 24
Finished Jun 02 03:16:26 PM PDT 24
Peak memory 205692 kb
Host smart-43f6a87c-2a2c-4c78-adf3-876bb16c2d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920417029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.920417029
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.389850429
Short name T506
Test name
Test status
Simulation time 75792628 ps
CPU time 0.73 seconds
Started Jun 02 03:16:25 PM PDT 24
Finished Jun 02 03:16:27 PM PDT 24
Peak memory 205652 kb
Host smart-ab8110f2-f97b-4e9d-833f-bd01529a76c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389850429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.389850429
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2182264406
Short name T457
Test name
Test status
Simulation time 26628372627 ps
CPU time 17.87 seconds
Started Jun 02 03:16:24 PM PDT 24
Finished Jun 02 03:16:43 PM PDT 24
Peak memory 234212 kb
Host smart-cf968fbd-c053-4664-97a0-a858a6197318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182264406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2182264406
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1748500469
Short name T74
Test name
Test status
Simulation time 46253409 ps
CPU time 0.75 seconds
Started Jun 02 03:16:33 PM PDT 24
Finished Jun 02 03:16:34 PM PDT 24
Peak memory 205396 kb
Host smart-c427d9e1-74a6-473f-91bd-ac58a425acbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748500469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1748500469
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.387635332
Short name T923
Test name
Test status
Simulation time 934040198 ps
CPU time 3.61 seconds
Started Jun 02 03:16:31 PM PDT 24
Finished Jun 02 03:16:35 PM PDT 24
Peak memory 236148 kb
Host smart-5597cf60-452b-48e2-953f-0bcc6c24368d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387635332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.387635332
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1139555701
Short name T756
Test name
Test status
Simulation time 42988380 ps
CPU time 0.73 seconds
Started Jun 02 03:16:33 PM PDT 24
Finished Jun 02 03:16:34 PM PDT 24
Peak memory 205400 kb
Host smart-d6a16feb-33d7-402e-b4dc-17e11bd3aa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139555701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1139555701
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.391507212
Short name T797
Test name
Test status
Simulation time 1136031316 ps
CPU time 20.62 seconds
Started Jun 02 03:16:34 PM PDT 24
Finished Jun 02 03:16:55 PM PDT 24
Peak memory 236540 kb
Host smart-e239d04b-c4b0-4c5e-83c8-00bd70f84987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391507212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.391507212
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.4167890164
Short name T943
Test name
Test status
Simulation time 5909223396 ps
CPU time 76.73 seconds
Started Jun 02 03:16:32 PM PDT 24
Finished Jun 02 03:17:49 PM PDT 24
Peak memory 251888 kb
Host smart-d4df9aaa-2db6-4c6a-886b-98fbb1d09c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167890164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4167890164
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.692509846
Short name T633
Test name
Test status
Simulation time 790848786 ps
CPU time 19.54 seconds
Started Jun 02 03:16:31 PM PDT 24
Finished Jun 02 03:16:51 PM PDT 24
Peak memory 237660 kb
Host smart-1458765b-5c24-4d5b-9108-10917e0dd8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692509846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.692509846
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3719000410
Short name T579
Test name
Test status
Simulation time 262849550 ps
CPU time 7.24 seconds
Started Jun 02 03:16:30 PM PDT 24
Finished Jun 02 03:16:38 PM PDT 24
Peak memory 232568 kb
Host smart-988438c1-494a-41c5-9438-17af54253e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719000410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3719000410
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3409444307
Short name T196
Test name
Test status
Simulation time 4985263532 ps
CPU time 16.67 seconds
Started Jun 02 03:16:32 PM PDT 24
Finished Jun 02 03:16:49 PM PDT 24
Peak memory 233100 kb
Host smart-3e20c22b-cc7d-46e7-8dea-e55f7a7be5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409444307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3409444307
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1089497513
Short name T431
Test name
Test status
Simulation time 6223539336 ps
CPU time 53.51 seconds
Started Jun 02 03:16:32 PM PDT 24
Finished Jun 02 03:17:26 PM PDT 24
Peak memory 234032 kb
Host smart-5338b2a1-f99e-4d04-9b3c-1274a7f8de71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089497513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1089497513
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.950450730
Short name T38
Test name
Test status
Simulation time 7774137880 ps
CPU time 7.58 seconds
Started Jun 02 03:16:33 PM PDT 24
Finished Jun 02 03:16:41 PM PDT 24
Peak memory 218380 kb
Host smart-9d8f6368-81fc-418f-8f93-63e32e051052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950450730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.950450730
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1918087977
Short name T203
Test name
Test status
Simulation time 6633404014 ps
CPU time 10.1 seconds
Started Jun 02 03:16:33 PM PDT 24
Finished Jun 02 03:16:44 PM PDT 24
Peak memory 218932 kb
Host smart-4c7d9d0d-53fc-4055-87a0-a6976df1c650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918087977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1918087977
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3654359752
Short name T926
Test name
Test status
Simulation time 2520773930 ps
CPU time 3.73 seconds
Started Jun 02 03:16:37 PM PDT 24
Finished Jun 02 03:16:41 PM PDT 24
Peak memory 219132 kb
Host smart-84ba9a7e-71b0-4ead-90a4-e1a700fa6da4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3654359752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3654359752
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3149210649
Short name T343
Test name
Test status
Simulation time 54017609 ps
CPU time 1.09 seconds
Started Jun 02 03:16:31 PM PDT 24
Finished Jun 02 03:16:33 PM PDT 24
Peak memory 206900 kb
Host smart-cef4ce36-ece8-4e6e-bd57-5ec09e94d7fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149210649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3149210649
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.847717451
Short name T710
Test name
Test status
Simulation time 734710885 ps
CPU time 5.1 seconds
Started Jun 02 03:16:33 PM PDT 24
Finished Jun 02 03:16:38 PM PDT 24
Peak memory 216168 kb
Host smart-b6457bc0-e1e6-403e-a450-edd58bd866ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847717451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.847717451
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1993279424
Short name T704
Test name
Test status
Simulation time 6430114625 ps
CPU time 21.08 seconds
Started Jun 02 03:16:37 PM PDT 24
Finished Jun 02 03:16:59 PM PDT 24
Peak memory 216120 kb
Host smart-c67ab97d-c0c6-46ec-98b5-d38bd1110be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993279424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1993279424
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2430705618
Short name T389
Test name
Test status
Simulation time 212600219 ps
CPU time 2.78 seconds
Started Jun 02 03:16:31 PM PDT 24
Finished Jun 02 03:16:34 PM PDT 24
Peak memory 216204 kb
Host smart-805ccd89-0946-4716-acc7-e3b69461add4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430705618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2430705618
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4174869012
Short name T482
Test name
Test status
Simulation time 40635461 ps
CPU time 0.8 seconds
Started Jun 02 03:16:33 PM PDT 24
Finished Jun 02 03:16:34 PM PDT 24
Peak memory 205632 kb
Host smart-36ddcdfd-edfc-4c1d-9d16-5a9cfc6a9c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174869012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4174869012
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1554576087
Short name T899
Test name
Test status
Simulation time 2370822642 ps
CPU time 10.73 seconds
Started Jun 02 03:16:33 PM PDT 24
Finished Jun 02 03:16:44 PM PDT 24
Peak memory 234272 kb
Host smart-8ac6edd5-f047-4764-88d5-ecc1e6527f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554576087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1554576087
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.863534051
Short name T562
Test name
Test status
Simulation time 19642687 ps
CPU time 0.73 seconds
Started Jun 02 03:15:22 PM PDT 24
Finished Jun 02 03:15:24 PM PDT 24
Peak memory 204820 kb
Host smart-37b00b29-112a-4fd3-9043-d3f678f69903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863534051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.863534051
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.955281865
Short name T130
Test name
Test status
Simulation time 492340899 ps
CPU time 4.47 seconds
Started Jun 02 03:15:23 PM PDT 24
Finished Jun 02 03:15:29 PM PDT 24
Peak memory 233428 kb
Host smart-050dea34-5470-45ea-8822-edf914710990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955281865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.955281865
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.741318076
Short name T907
Test name
Test status
Simulation time 215958255 ps
CPU time 0.77 seconds
Started Jun 02 03:15:23 PM PDT 24
Finished Jun 02 03:15:25 PM PDT 24
Peak memory 206620 kb
Host smart-4702444d-1dd2-4a9d-b920-1dbc937bfc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741318076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.741318076
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3043232563
Short name T295
Test name
Test status
Simulation time 9996210539 ps
CPU time 127.26 seconds
Started Jun 02 03:15:23 PM PDT 24
Finished Jun 02 03:17:31 PM PDT 24
Peak memory 255080 kb
Host smart-c791e474-5d3c-41d4-8743-57091feeb2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043232563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3043232563
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.51203665
Short name T291
Test name
Test status
Simulation time 6150689240 ps
CPU time 49.55 seconds
Started Jun 02 03:15:22 PM PDT 24
Finished Jun 02 03:16:13 PM PDT 24
Peak memory 239064 kb
Host smart-fc9ae4d2-1019-449e-886f-9630f0f3b594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51203665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.51203665
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.4204579901
Short name T44
Test name
Test status
Simulation time 3548257625 ps
CPU time 62.78 seconds
Started Jun 02 03:15:23 PM PDT 24
Finished Jun 02 03:16:27 PM PDT 24
Peak memory 250240 kb
Host smart-67543e23-a06e-4e12-8ef9-e71ad16d9883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204579901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.4204579901
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1970401280
Short name T586
Test name
Test status
Simulation time 543750786 ps
CPU time 5.83 seconds
Started Jun 02 03:15:22 PM PDT 24
Finished Jun 02 03:15:29 PM PDT 24
Peak memory 217880 kb
Host smart-44d9f914-60d4-4138-ba3b-d965031867a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970401280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1970401280
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2658894549
Short name T167
Test name
Test status
Simulation time 2907306227 ps
CPU time 27.06 seconds
Started Jun 02 03:15:22 PM PDT 24
Finished Jun 02 03:15:50 PM PDT 24
Peak memory 229616 kb
Host smart-5a49a97b-4bb0-4dcf-94a6-3c3eb19b9ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658894549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2658894549
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1422813423
Short name T73
Test name
Test status
Simulation time 14985686239 ps
CPU time 10.68 seconds
Started Jun 02 03:15:20 PM PDT 24
Finished Jun 02 03:15:31 PM PDT 24
Peak memory 218584 kb
Host smart-f7eb997a-f069-4a4a-9384-7039faa4d79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422813423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1422813423
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1079373523
Short name T534
Test name
Test status
Simulation time 1430728783 ps
CPU time 6.86 seconds
Started Jun 02 03:15:25 PM PDT 24
Finished Jun 02 03:15:32 PM PDT 24
Peak memory 237836 kb
Host smart-12ba69ba-7900-4e88-8288-d1c0ebea8cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079373523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1079373523
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.891391701
Short name T467
Test name
Test status
Simulation time 1184320776 ps
CPU time 10.96 seconds
Started Jun 02 03:15:24 PM PDT 24
Finished Jun 02 03:15:36 PM PDT 24
Peak memory 222840 kb
Host smart-db5027bc-a6dc-4664-83da-796cce8544f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=891391701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.891391701
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3046701766
Short name T67
Test name
Test status
Simulation time 213806335 ps
CPU time 0.98 seconds
Started Jun 02 03:15:22 PM PDT 24
Finished Jun 02 03:15:24 PM PDT 24
Peak memory 235044 kb
Host smart-2066f9a0-3b50-4a56-b2a1-2edefddf5788
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046701766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3046701766
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3906399518
Short name T531
Test name
Test status
Simulation time 12883538498 ps
CPU time 96.76 seconds
Started Jun 02 03:15:24 PM PDT 24
Finished Jun 02 03:17:02 PM PDT 24
Peak memory 236996 kb
Host smart-2179731b-7515-40b8-9115-b4245c0ac2a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906399518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3906399518
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.871822879
Short name T653
Test name
Test status
Simulation time 8943956854 ps
CPU time 25 seconds
Started Jun 02 03:15:22 PM PDT 24
Finished Jun 02 03:15:48 PM PDT 24
Peak memory 216236 kb
Host smart-01388ef2-5a9e-4fb3-8736-9b924284518d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871822879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.871822879
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3570618315
Short name T542
Test name
Test status
Simulation time 4393150137 ps
CPU time 11.07 seconds
Started Jun 02 03:15:23 PM PDT 24
Finished Jun 02 03:15:36 PM PDT 24
Peak memory 216220 kb
Host smart-298acc33-0268-4e84-9ede-9a0ac95053e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570618315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3570618315
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.421606495
Short name T587
Test name
Test status
Simulation time 20565411 ps
CPU time 1.22 seconds
Started Jun 02 03:15:20 PM PDT 24
Finished Jun 02 03:15:22 PM PDT 24
Peak memory 207832 kb
Host smart-648b67f0-cc4a-4c40-9cfb-12bdf09e57e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421606495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.421606495
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2364465690
Short name T553
Test name
Test status
Simulation time 101245886 ps
CPU time 1.04 seconds
Started Jun 02 03:15:24 PM PDT 24
Finished Jun 02 03:15:26 PM PDT 24
Peak memory 206668 kb
Host smart-4e09323f-c79e-43c1-8c58-6906b2cd411f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364465690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2364465690
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.801144623
Short name T596
Test name
Test status
Simulation time 1493726009 ps
CPU time 5.13 seconds
Started Jun 02 03:15:23 PM PDT 24
Finished Jun 02 03:15:29 PM PDT 24
Peak memory 235736 kb
Host smart-0406a4dc-bc23-496e-9fb8-c2d433365bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801144623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.801144623
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2972663685
Short name T765
Test name
Test status
Simulation time 28707227 ps
CPU time 0.71 seconds
Started Jun 02 03:16:44 PM PDT 24
Finished Jun 02 03:16:45 PM PDT 24
Peak memory 204784 kb
Host smart-208f915f-1c5f-4d6e-8408-d0814ed17501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972663685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2972663685
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3054180019
Short name T89
Test name
Test status
Simulation time 117406973 ps
CPU time 3.44 seconds
Started Jun 02 03:16:37 PM PDT 24
Finished Jun 02 03:16:41 PM PDT 24
Peak memory 234060 kb
Host smart-8d76882c-def3-446d-99c5-aaed8e41f7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054180019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3054180019
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3982850193
Short name T872
Test name
Test status
Simulation time 61432740 ps
CPU time 0.79 seconds
Started Jun 02 03:16:33 PM PDT 24
Finished Jun 02 03:16:34 PM PDT 24
Peak memory 206736 kb
Host smart-82698c6e-a7b9-45fc-9f24-ef5c57639904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982850193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3982850193
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1647338897
Short name T823
Test name
Test status
Simulation time 4961022587 ps
CPU time 12.2 seconds
Started Jun 02 03:16:46 PM PDT 24
Finished Jun 02 03:16:59 PM PDT 24
Peak memory 240816 kb
Host smart-f357ae76-b0fe-4d8e-a0cf-8cbf7416bdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647338897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1647338897
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.916034460
Short name T288
Test name
Test status
Simulation time 43611149791 ps
CPU time 413.63 seconds
Started Jun 02 03:16:37 PM PDT 24
Finished Jun 02 03:23:32 PM PDT 24
Peak memory 252368 kb
Host smart-f86ef070-8df4-41f4-9cf8-959849e0a66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916034460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.916034460
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.61296524
Short name T546
Test name
Test status
Simulation time 61926052413 ps
CPU time 163.54 seconds
Started Jun 02 03:16:40 PM PDT 24
Finished Jun 02 03:19:24 PM PDT 24
Peak memory 248992 kb
Host smart-2985b38f-9065-44c3-bdb2-80bfd5bf8b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61296524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.61296524
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3777692526
Short name T740
Test name
Test status
Simulation time 34041971 ps
CPU time 2.53 seconds
Started Jun 02 03:16:38 PM PDT 24
Finished Jun 02 03:16:41 PM PDT 24
Peak memory 224276 kb
Host smart-9b55d819-83b1-4902-a58f-2c846ccebc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777692526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3777692526
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2855667046
Short name T683
Test name
Test status
Simulation time 12964706059 ps
CPU time 62.83 seconds
Started Jun 02 03:16:38 PM PDT 24
Finished Jun 02 03:17:42 PM PDT 24
Peak memory 247824 kb
Host smart-f11498c7-3698-40b2-9fb5-0199e1836a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855667046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2855667046
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1005714029
Short name T843
Test name
Test status
Simulation time 1079115344 ps
CPU time 6.26 seconds
Started Jun 02 03:16:38 PM PDT 24
Finished Jun 02 03:16:45 PM PDT 24
Peak memory 226960 kb
Host smart-ee98faa8-50da-4930-91ea-a467e242d179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005714029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1005714029
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2572696412
Short name T251
Test name
Test status
Simulation time 26668666970 ps
CPU time 16.63 seconds
Started Jun 02 03:16:37 PM PDT 24
Finished Jun 02 03:16:55 PM PDT 24
Peak memory 216856 kb
Host smart-dff42e93-5f26-4f11-b93b-04e4939f7548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572696412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2572696412
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2522106158
Short name T905
Test name
Test status
Simulation time 1125760091 ps
CPU time 9.22 seconds
Started Jun 02 03:16:37 PM PDT 24
Finished Jun 02 03:16:47 PM PDT 24
Peak memory 221696 kb
Host smart-3b8ecc56-96be-41ee-9264-1ad104b3b2b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2522106158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2522106158
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3165931241
Short name T837
Test name
Test status
Simulation time 441553954 ps
CPU time 7.26 seconds
Started Jun 02 03:16:37 PM PDT 24
Finished Jun 02 03:16:44 PM PDT 24
Peak memory 218716 kb
Host smart-3b836813-1db1-41e7-bf6a-b1217709491a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165931241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3165931241
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.95969656
Short name T582
Test name
Test status
Simulation time 1963260615 ps
CPU time 7.85 seconds
Started Jun 02 03:16:38 PM PDT 24
Finished Jun 02 03:16:47 PM PDT 24
Peak memory 216144 kb
Host smart-93371264-a5c9-4391-ae4a-b75e3455b943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95969656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.95969656
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3522852530
Short name T733
Test name
Test status
Simulation time 244340958 ps
CPU time 1.27 seconds
Started Jun 02 03:16:38 PM PDT 24
Finished Jun 02 03:16:40 PM PDT 24
Peak memory 207788 kb
Host smart-26b84bb2-1d36-4372-9f80-9a4c764f6359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522852530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3522852530
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2566304840
Short name T803
Test name
Test status
Simulation time 223189064 ps
CPU time 1.09 seconds
Started Jun 02 03:16:38 PM PDT 24
Finished Jun 02 03:16:40 PM PDT 24
Peak memory 205568 kb
Host smart-c96770ec-22d6-4ede-b394-f5b724f5639b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566304840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2566304840
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2131661971
Short name T254
Test name
Test status
Simulation time 13881256876 ps
CPU time 24.03 seconds
Started Jun 02 03:16:38 PM PDT 24
Finished Jun 02 03:17:03 PM PDT 24
Peak memory 234648 kb
Host smart-a388652d-3d36-4711-a302-0979c7928686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131661971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2131661971
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1109066994
Short name T464
Test name
Test status
Simulation time 135684712 ps
CPU time 0.72 seconds
Started Jun 02 03:16:36 PM PDT 24
Finished Jun 02 03:16:37 PM PDT 24
Peak memory 205436 kb
Host smart-3025aa3d-0fa8-4cb6-9940-51b83ab67e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109066994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1109066994
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1344754076
Short name T786
Test name
Test status
Simulation time 2712082707 ps
CPU time 7.21 seconds
Started Jun 02 03:16:41 PM PDT 24
Finished Jun 02 03:16:49 PM PDT 24
Peak memory 238236 kb
Host smart-932654a1-4ccd-4dd6-97e9-e72d840b78ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344754076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1344754076
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3033815972
Short name T447
Test name
Test status
Simulation time 63430153 ps
CPU time 0.78 seconds
Started Jun 02 03:16:41 PM PDT 24
Finished Jun 02 03:16:42 PM PDT 24
Peak memory 205708 kb
Host smart-f51fb3dc-fa7f-48a8-b06a-1a68fe2a846d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033815972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3033815972
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.4027914803
Short name T644
Test name
Test status
Simulation time 536628054 ps
CPU time 10.46 seconds
Started Jun 02 03:16:39 PM PDT 24
Finished Jun 02 03:16:50 PM PDT 24
Peak memory 234928 kb
Host smart-2838eeb4-d95d-4086-85b2-e0de9b35ace5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027914803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4027914803
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3234221481
Short name T215
Test name
Test status
Simulation time 154360561781 ps
CPU time 425.04 seconds
Started Jun 02 03:16:38 PM PDT 24
Finished Jun 02 03:23:43 PM PDT 24
Peak memory 267548 kb
Host smart-e083afd2-4014-4446-9b05-02b36b5732e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234221481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3234221481
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.228525910
Short name T284
Test name
Test status
Simulation time 4875282669 ps
CPU time 131.93 seconds
Started Jun 02 03:16:40 PM PDT 24
Finished Jun 02 03:18:53 PM PDT 24
Peak memory 256208 kb
Host smart-83dc01a4-d404-4bcc-89b1-17932ba643f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228525910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.228525910
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.467672104
Short name T802
Test name
Test status
Simulation time 821098639 ps
CPU time 9.8 seconds
Started Jun 02 03:16:38 PM PDT 24
Finished Jun 02 03:16:49 PM PDT 24
Peak memory 232560 kb
Host smart-1e6c956a-c9e5-41ff-b427-bb5da01a3a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467672104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.467672104
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.83864302
Short name T392
Test name
Test status
Simulation time 60353494 ps
CPU time 2.3 seconds
Started Jun 02 03:16:41 PM PDT 24
Finished Jun 02 03:16:44 PM PDT 24
Peak memory 220980 kb
Host smart-549c3721-ffa4-4909-abcb-ef52d5dd5cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83864302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.83864302
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3260892811
Short name T7
Test name
Test status
Simulation time 781702828 ps
CPU time 3.18 seconds
Started Jun 02 03:16:46 PM PDT 24
Finished Jun 02 03:16:50 PM PDT 24
Peak memory 224192 kb
Host smart-fc34801e-f480-41a5-b570-e69bfc0feb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260892811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3260892811
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.41617248
Short name T578
Test name
Test status
Simulation time 1973290303 ps
CPU time 8.05 seconds
Started Jun 02 03:16:38 PM PDT 24
Finished Jun 02 03:16:47 PM PDT 24
Peak memory 248644 kb
Host smart-510fc01e-2c5f-4e14-835c-b774012ff032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41617248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.41617248
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2999319530
Short name T758
Test name
Test status
Simulation time 2131934406 ps
CPU time 4.92 seconds
Started Jun 02 03:16:38 PM PDT 24
Finished Jun 02 03:16:43 PM PDT 24
Peak memory 233460 kb
Host smart-1f116a73-76fa-44e6-b8cb-a271c2639fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999319530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2999319530
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.897662806
Short name T149
Test name
Test status
Simulation time 192883432 ps
CPU time 3.82 seconds
Started Jun 02 03:16:38 PM PDT 24
Finished Jun 02 03:16:43 PM PDT 24
Peak memory 218756 kb
Host smart-a3ec1200-f354-49f8-9887-c4f59656566d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=897662806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.897662806
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3475588983
Short name T379
Test name
Test status
Simulation time 13494932120 ps
CPU time 36.93 seconds
Started Jun 02 03:16:40 PM PDT 24
Finished Jun 02 03:17:18 PM PDT 24
Peak memory 216268 kb
Host smart-8291b518-9032-4eb7-933b-b2ca0e1b2a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475588983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3475588983
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.716726659
Short name T538
Test name
Test status
Simulation time 691678213 ps
CPU time 5.67 seconds
Started Jun 02 03:16:46 PM PDT 24
Finished Jun 02 03:16:52 PM PDT 24
Peak memory 216036 kb
Host smart-781cd2ba-580f-4454-ad6e-11c5395a2cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716726659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.716726659
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1286067113
Short name T19
Test name
Test status
Simulation time 431062015 ps
CPU time 2.08 seconds
Started Jun 02 03:16:40 PM PDT 24
Finished Jun 02 03:16:42 PM PDT 24
Peak memory 216248 kb
Host smart-d4da7b29-3805-420b-b771-4cd0a3ef7ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286067113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1286067113
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3055994219
Short name T347
Test name
Test status
Simulation time 76980598 ps
CPU time 0.89 seconds
Started Jun 02 03:16:36 PM PDT 24
Finished Jun 02 03:16:37 PM PDT 24
Peak memory 205664 kb
Host smart-bb683d2d-c894-467d-82ef-3a99e038ebcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055994219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3055994219
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3943497003
Short name T220
Test name
Test status
Simulation time 12779758719 ps
CPU time 42.19 seconds
Started Jun 02 03:16:37 PM PDT 24
Finished Jun 02 03:17:20 PM PDT 24
Peak memory 239120 kb
Host smart-3bd2f5cf-48d8-45ab-b471-0ee4f47de6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943497003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3943497003
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.959301565
Short name T509
Test name
Test status
Simulation time 22757284 ps
CPU time 0.74 seconds
Started Jun 02 03:16:44 PM PDT 24
Finished Jun 02 03:16:45 PM PDT 24
Peak memory 204804 kb
Host smart-dca4860f-2e56-4da8-8911-376c03cfd387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959301565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.959301565
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3403482075
Short name T751
Test name
Test status
Simulation time 62501672 ps
CPU time 2.21 seconds
Started Jun 02 03:16:45 PM PDT 24
Finished Jun 02 03:16:48 PM PDT 24
Peak memory 218644 kb
Host smart-95c6221f-7692-4ce1-801e-03b5e649b475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403482075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3403482075
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2500594628
Short name T461
Test name
Test status
Simulation time 40244341 ps
CPU time 0.77 seconds
Started Jun 02 03:16:46 PM PDT 24
Finished Jun 02 03:16:47 PM PDT 24
Peak memory 206688 kb
Host smart-6f197b8d-eda1-4781-be2b-fd7646ba74a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500594628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2500594628
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3714626212
Short name T535
Test name
Test status
Simulation time 4390295793 ps
CPU time 32.04 seconds
Started Jun 02 03:16:44 PM PDT 24
Finished Jun 02 03:17:17 PM PDT 24
Peak memory 239404 kb
Host smart-b2cc7be9-ca33-4c4a-8385-17006f5d4a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714626212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3714626212
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2835304146
Short name T590
Test name
Test status
Simulation time 20769850490 ps
CPU time 59.62 seconds
Started Jun 02 03:16:46 PM PDT 24
Finished Jun 02 03:17:46 PM PDT 24
Peak memory 249144 kb
Host smart-81bf29a0-ab1d-456e-89f0-c2c986a6af73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835304146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2835304146
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2551191431
Short name T677
Test name
Test status
Simulation time 5999112993 ps
CPU time 52.76 seconds
Started Jun 02 03:16:43 PM PDT 24
Finished Jun 02 03:17:37 PM PDT 24
Peak memory 249128 kb
Host smart-ed951f52-8305-4f23-99dd-9eba26852b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551191431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2551191431
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1749489187
Short name T70
Test name
Test status
Simulation time 3431766748 ps
CPU time 11.07 seconds
Started Jun 02 03:16:43 PM PDT 24
Finished Jun 02 03:16:54 PM PDT 24
Peak memory 233716 kb
Host smart-64382ea4-dbcc-47fe-b55c-8b78325aa5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749489187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1749489187
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1574390956
Short name T39
Test name
Test status
Simulation time 952744155 ps
CPU time 11.22 seconds
Started Jun 02 03:16:46 PM PDT 24
Finished Jun 02 03:16:58 PM PDT 24
Peak memory 236688 kb
Host smart-0a3f4179-f604-4fa2-b587-7d8f9b12b78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574390956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1574390956
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1961932337
Short name T799
Test name
Test status
Simulation time 1351602261 ps
CPU time 15.17 seconds
Started Jun 02 03:16:51 PM PDT 24
Finished Jun 02 03:17:07 PM PDT 24
Peak memory 240780 kb
Host smart-75da95c7-2175-491e-b446-30d50267717a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961932337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1961932337
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.618920965
Short name T271
Test name
Test status
Simulation time 481764360 ps
CPU time 8.04 seconds
Started Jun 02 03:16:44 PM PDT 24
Finished Jun 02 03:16:52 PM PDT 24
Peak memory 233480 kb
Host smart-5a366427-36e4-4438-9368-eba45f8ea017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618920965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.618920965
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2010227262
Short name T468
Test name
Test status
Simulation time 18536990326 ps
CPU time 8.26 seconds
Started Jun 02 03:16:38 PM PDT 24
Finished Jun 02 03:16:47 PM PDT 24
Peak memory 218468 kb
Host smart-17bc3dce-2ffe-4e11-9fea-5aa067fadc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010227262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2010227262
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2855731808
Short name T493
Test name
Test status
Simulation time 178720920 ps
CPU time 4.09 seconds
Started Jun 02 03:16:43 PM PDT 24
Finished Jun 02 03:16:48 PM PDT 24
Peak memory 219208 kb
Host smart-e34117cf-829f-4545-a076-0020ab16fa69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2855731808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2855731808
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2067169836
Short name T129
Test name
Test status
Simulation time 48591520657 ps
CPU time 211.41 seconds
Started Jun 02 03:16:42 PM PDT 24
Finished Jun 02 03:20:14 PM PDT 24
Peak memory 265472 kb
Host smart-10bc65b3-7075-42af-aa0f-01909a6e3afd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067169836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2067169836
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3770244742
Short name T404
Test name
Test status
Simulation time 22915353 ps
CPU time 0.75 seconds
Started Jun 02 03:16:46 PM PDT 24
Finished Jun 02 03:16:48 PM PDT 24
Peak memory 205540 kb
Host smart-a6b4ee2b-8fb4-4d92-be8c-b02feff0db2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770244742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3770244742
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3605124239
Short name T612
Test name
Test status
Simulation time 1794432011 ps
CPU time 5.84 seconds
Started Jun 02 03:16:37 PM PDT 24
Finished Jun 02 03:16:44 PM PDT 24
Peak memory 216084 kb
Host smart-898a583d-1b0b-44f2-bc87-4b7b13fcb8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605124239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3605124239
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1299124277
Short name T384
Test name
Test status
Simulation time 21730092 ps
CPU time 1.39 seconds
Started Jun 02 03:16:45 PM PDT 24
Finished Jun 02 03:16:47 PM PDT 24
Peak memory 216140 kb
Host smart-ea6143fc-d8da-4a54-b498-8fd61e048a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299124277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1299124277
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2984396184
Short name T86
Test name
Test status
Simulation time 56046462 ps
CPU time 0.84 seconds
Started Jun 02 03:16:41 PM PDT 24
Finished Jun 02 03:16:42 PM PDT 24
Peak memory 205720 kb
Host smart-b3797c20-7d32-4f89-9fea-b25e739039ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984396184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2984396184
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.453569778
Short name T714
Test name
Test status
Simulation time 176850954030 ps
CPU time 30.16 seconds
Started Jun 02 03:16:43 PM PDT 24
Finished Jun 02 03:17:14 PM PDT 24
Peak memory 229204 kb
Host smart-4e8fea2e-f1ed-4a17-b8bf-dcb716907444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453569778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.453569778
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2919595717
Short name T164
Test name
Test status
Simulation time 11745706 ps
CPU time 0.68 seconds
Started Jun 02 03:16:48 PM PDT 24
Finished Jun 02 03:16:50 PM PDT 24
Peak memory 204744 kb
Host smart-e2884450-a2d9-4abb-8d64-e382595f05bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919595717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2919595717
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3136120921
Short name T914
Test name
Test status
Simulation time 1054960120 ps
CPU time 5.89 seconds
Started Jun 02 03:16:43 PM PDT 24
Finished Jun 02 03:16:49 PM PDT 24
Peak memory 238276 kb
Host smart-ca5cc553-ecbf-43d1-95ec-7965c4201e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136120921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3136120921
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1711205227
Short name T614
Test name
Test status
Simulation time 66541521 ps
CPU time 0.8 seconds
Started Jun 02 03:16:44 PM PDT 24
Finished Jun 02 03:16:46 PM PDT 24
Peak memory 206404 kb
Host smart-c1b0b0d6-0b12-4acc-bf46-17726ab52601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711205227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1711205227
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.345775045
Short name T456
Test name
Test status
Simulation time 12111884382 ps
CPU time 59.66 seconds
Started Jun 02 03:16:51 PM PDT 24
Finished Jun 02 03:17:51 PM PDT 24
Peak memory 248996 kb
Host smart-d97021c2-d6da-4c70-8530-7fcc23ced5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345775045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.345775045
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3957960416
Short name T230
Test name
Test status
Simulation time 15173955781 ps
CPU time 86.54 seconds
Started Jun 02 03:16:49 PM PDT 24
Finished Jun 02 03:18:16 PM PDT 24
Peak memory 264280 kb
Host smart-ae5397cd-f6ba-4c48-823b-3fd0f6d58fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957960416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3957960416
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2903590039
Short name T956
Test name
Test status
Simulation time 3192421494 ps
CPU time 49.04 seconds
Started Jun 02 03:16:50 PM PDT 24
Finished Jun 02 03:17:40 PM PDT 24
Peak memory 250044 kb
Host smart-2b9949e4-4978-4329-8ab0-b6ad61589831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903590039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2903590039
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_intercept.452037508
Short name T429
Test name
Test status
Simulation time 2596857769 ps
CPU time 8.87 seconds
Started Jun 02 03:16:48 PM PDT 24
Finished Jun 02 03:16:57 PM PDT 24
Peak memory 234260 kb
Host smart-ac137698-3006-4939-82c8-b57bcbac9e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452037508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.452037508
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2564720736
Short name T954
Test name
Test status
Simulation time 1084270886 ps
CPU time 9.44 seconds
Started Jun 02 03:16:51 PM PDT 24
Finished Jun 02 03:17:01 PM PDT 24
Peak memory 235004 kb
Host smart-475cefd1-abb0-4aaf-897d-f31d6a225e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564720736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2564720736
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.4171942455
Short name T692
Test name
Test status
Simulation time 3298850569 ps
CPU time 10.99 seconds
Started Jun 02 03:16:45 PM PDT 24
Finished Jun 02 03:16:56 PM PDT 24
Peak memory 218584 kb
Host smart-44f4f998-4e28-4e57-8b6d-0ec269de04a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171942455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.4171942455
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3994920479
Short name T766
Test name
Test status
Simulation time 15978745333 ps
CPU time 21.35 seconds
Started Jun 02 03:16:43 PM PDT 24
Finished Jun 02 03:17:05 PM PDT 24
Peak memory 240444 kb
Host smart-6e8ea4bf-f0aa-40f6-ab1b-e3c2fa7a5ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994920479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3994920479
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.4250138101
Short name T148
Test name
Test status
Simulation time 451667934 ps
CPU time 3.22 seconds
Started Jun 02 03:16:42 PM PDT 24
Finished Jun 02 03:16:46 PM PDT 24
Peak memory 222272 kb
Host smart-a974c4bc-4da0-49ea-9d01-febf6c7e1b91
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4250138101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.4250138101
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3501399434
Short name T723
Test name
Test status
Simulation time 1417458238 ps
CPU time 13.42 seconds
Started Jun 02 03:16:45 PM PDT 24
Finished Jun 02 03:16:58 PM PDT 24
Peak memory 216168 kb
Host smart-e1ca39e5-26fc-4997-93b9-6105423fc182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501399434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3501399434
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3651721595
Short name T841
Test name
Test status
Simulation time 679632440 ps
CPU time 5.36 seconds
Started Jun 02 03:16:44 PM PDT 24
Finished Jun 02 03:16:50 PM PDT 24
Peak memory 216308 kb
Host smart-da81bd37-c979-4a7d-8af6-1e794fb9b294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651721595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3651721595
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1896974085
Short name T313
Test name
Test status
Simulation time 30776024 ps
CPU time 1.08 seconds
Started Jun 02 03:16:43 PM PDT 24
Finished Jun 02 03:16:44 PM PDT 24
Peak memory 207796 kb
Host smart-37a2028f-f176-4868-a121-0676e7d41710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896974085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1896974085
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1269366696
Short name T137
Test name
Test status
Simulation time 87843416 ps
CPU time 0.78 seconds
Started Jun 02 03:16:43 PM PDT 24
Finished Jun 02 03:16:45 PM PDT 24
Peak memory 205652 kb
Host smart-fb47912e-f322-4f43-a424-d10eb50842f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269366696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1269366696
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3126112487
Short name T398
Test name
Test status
Simulation time 26934982986 ps
CPU time 20.55 seconds
Started Jun 02 03:16:51 PM PDT 24
Finished Jun 02 03:17:12 PM PDT 24
Peak memory 217152 kb
Host smart-32b05abf-111c-4817-9da2-76f695b4b9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126112487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3126112487
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2660229214
Short name T641
Test name
Test status
Simulation time 109505266 ps
CPU time 0.72 seconds
Started Jun 02 03:16:50 PM PDT 24
Finished Jun 02 03:16:51 PM PDT 24
Peak memory 205424 kb
Host smart-ee9b03fc-b131-49e2-ad18-2ad976108d95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660229214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2660229214
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2910050439
Short name T247
Test name
Test status
Simulation time 1339536196 ps
CPU time 4.18 seconds
Started Jun 02 03:16:53 PM PDT 24
Finished Jun 02 03:16:58 PM PDT 24
Peak memory 220660 kb
Host smart-761e6119-e163-4b81-937d-b47a1b408207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910050439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2910050439
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1093719423
Short name T328
Test name
Test status
Simulation time 44180867 ps
CPU time 0.75 seconds
Started Jun 02 03:16:53 PM PDT 24
Finished Jun 02 03:16:54 PM PDT 24
Peak memory 206420 kb
Host smart-2f15ae2c-8815-41b0-9c53-9efdb126d2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093719423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1093719423
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2674552941
Short name T475
Test name
Test status
Simulation time 1005106549 ps
CPU time 6.74 seconds
Started Jun 02 03:16:49 PM PDT 24
Finished Jun 02 03:16:56 PM PDT 24
Peak memory 217116 kb
Host smart-91c0558b-8d41-4660-bdd3-496e2143825b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674552941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2674552941
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1809126473
Short name T928
Test name
Test status
Simulation time 8883187734 ps
CPU time 102.22 seconds
Started Jun 02 03:16:51 PM PDT 24
Finished Jun 02 03:18:34 PM PDT 24
Peak memory 257124 kb
Host smart-e1f2aa26-9cb4-470d-a95a-ee1b6415e2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809126473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1809126473
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1635340089
Short name T299
Test name
Test status
Simulation time 326475607 ps
CPU time 8.9 seconds
Started Jun 02 03:16:51 PM PDT 24
Finished Jun 02 03:17:01 PM PDT 24
Peak memory 236068 kb
Host smart-3ac1c364-b0aa-45d8-b6e9-ef16a86c050f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635340089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1635340089
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2771893397
Short name T225
Test name
Test status
Simulation time 620219229 ps
CPU time 3.5 seconds
Started Jun 02 03:16:49 PM PDT 24
Finished Jun 02 03:16:53 PM PDT 24
Peak memory 218356 kb
Host smart-b8721598-ea0c-4687-a4fc-303a7ef0a0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771893397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2771893397
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.656345810
Short name T632
Test name
Test status
Simulation time 1663928446 ps
CPU time 26.3 seconds
Started Jun 02 03:16:52 PM PDT 24
Finished Jun 02 03:17:19 PM PDT 24
Peak memory 249008 kb
Host smart-36d1e32f-2adf-4acc-a2c4-67d377461e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656345810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.656345810
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3688328198
Short name T487
Test name
Test status
Simulation time 6484901095 ps
CPU time 16.28 seconds
Started Jun 02 03:16:50 PM PDT 24
Finished Jun 02 03:17:07 PM PDT 24
Peak memory 231200 kb
Host smart-33ad9a14-6cc4-43e3-ad11-ff5da8d13a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688328198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3688328198
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.958495914
Short name T218
Test name
Test status
Simulation time 1689715756 ps
CPU time 4.74 seconds
Started Jun 02 03:17:00 PM PDT 24
Finished Jun 02 03:17:06 PM PDT 24
Peak memory 229356 kb
Host smart-994062d2-5d71-4091-bf97-a26e07824be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958495914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.958495914
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1345234781
Short name T369
Test name
Test status
Simulation time 320176070 ps
CPU time 5.42 seconds
Started Jun 02 03:16:53 PM PDT 24
Finished Jun 02 03:16:59 PM PDT 24
Peak memory 222596 kb
Host smart-181a2924-fe3f-4eaf-a79b-c20f6b62ac4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1345234781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1345234781
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2737797394
Short name T159
Test name
Test status
Simulation time 92039588368 ps
CPU time 407.52 seconds
Started Jun 02 03:16:52 PM PDT 24
Finished Jun 02 03:23:40 PM PDT 24
Peak memory 267404 kb
Host smart-d1dd5f55-f565-476c-948c-9c1301f0d716
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737797394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2737797394
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1549568698
Short name T873
Test name
Test status
Simulation time 1087800330 ps
CPU time 18.48 seconds
Started Jun 02 03:16:52 PM PDT 24
Finished Jun 02 03:17:11 PM PDT 24
Peak memory 216208 kb
Host smart-f314a98b-ba60-406f-88c9-535e2d0c9b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549568698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1549568698
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1478625266
Short name T474
Test name
Test status
Simulation time 3574865860 ps
CPU time 6.58 seconds
Started Jun 02 03:16:49 PM PDT 24
Finished Jun 02 03:16:56 PM PDT 24
Peak memory 216220 kb
Host smart-bde7dd6a-cc18-4946-9241-8c1cd4376ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478625266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1478625266
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1377543726
Short name T374
Test name
Test status
Simulation time 79719981 ps
CPU time 2.12 seconds
Started Jun 02 03:16:48 PM PDT 24
Finished Jun 02 03:16:51 PM PDT 24
Peak memory 216136 kb
Host smart-43e6f89b-fa9e-4398-932d-b7eb809babe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377543726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1377543726
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.372482738
Short name T650
Test name
Test status
Simulation time 40765464 ps
CPU time 0.91 seconds
Started Jun 02 03:16:51 PM PDT 24
Finished Jun 02 03:16:53 PM PDT 24
Peak memory 206280 kb
Host smart-43fc1eff-436f-464d-9b21-4a1b60194d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372482738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.372482738
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3394198582
Short name T812
Test name
Test status
Simulation time 6625560353 ps
CPU time 12.2 seconds
Started Jun 02 03:16:52 PM PDT 24
Finished Jun 02 03:17:05 PM PDT 24
Peak memory 239496 kb
Host smart-f64925d4-ffe0-4a78-8e8d-98d66ac5a45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394198582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3394198582
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3221985287
Short name T71
Test name
Test status
Simulation time 52602557 ps
CPU time 0.74 seconds
Started Jun 02 03:16:58 PM PDT 24
Finished Jun 02 03:17:00 PM PDT 24
Peak memory 205392 kb
Host smart-e84bbba8-246b-46f5-a107-cf5569f691c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221985287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3221985287
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.560225731
Short name T451
Test name
Test status
Simulation time 6079595540 ps
CPU time 8.89 seconds
Started Jun 02 03:16:52 PM PDT 24
Finished Jun 02 03:17:02 PM PDT 24
Peak memory 219600 kb
Host smart-6b656d55-ce90-4dbe-af6d-5cd58535d5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560225731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.560225731
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1629558922
Short name T348
Test name
Test status
Simulation time 19209195 ps
CPU time 0.79 seconds
Started Jun 02 03:16:52 PM PDT 24
Finished Jun 02 03:16:54 PM PDT 24
Peak memory 206420 kb
Host smart-a0dc9164-9141-4fd0-9502-9ed054be5488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629558922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1629558922
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2038919004
Short name T298
Test name
Test status
Simulation time 1389040817 ps
CPU time 35.32 seconds
Started Jun 02 03:16:57 PM PDT 24
Finished Jun 02 03:17:33 PM PDT 24
Peak memory 250952 kb
Host smart-29ff55f1-8d03-4f95-b40c-a9dd9b5c86c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038919004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2038919004
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1467513534
Short name T80
Test name
Test status
Simulation time 125346865185 ps
CPU time 611.15 seconds
Started Jun 02 03:17:00 PM PDT 24
Finished Jun 02 03:27:12 PM PDT 24
Peak memory 257312 kb
Host smart-ce0e02a9-d975-43c8-8bc2-561689f0e828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467513534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1467513534
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.595991351
Short name T745
Test name
Test status
Simulation time 1608913846 ps
CPU time 25.95 seconds
Started Jun 02 03:17:00 PM PDT 24
Finished Jun 02 03:17:27 PM PDT 24
Peak memory 219200 kb
Host smart-014b9012-a8cc-4860-94f2-725e64fe83fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595991351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.595991351
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3554217302
Short name T575
Test name
Test status
Simulation time 35056461 ps
CPU time 2.29 seconds
Started Jun 02 03:16:52 PM PDT 24
Finished Jun 02 03:16:55 PM PDT 24
Peak memory 224428 kb
Host smart-1709d9ce-c08c-4dd1-b619-2f23471434e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554217302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3554217302
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.4155627284
Short name T621
Test name
Test status
Simulation time 393927657 ps
CPU time 2.31 seconds
Started Jun 02 03:16:51 PM PDT 24
Finished Jun 02 03:16:54 PM PDT 24
Peak memory 215952 kb
Host smart-ad6f1fc3-ac02-4af7-8c37-186515e7cb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155627284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4155627284
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1819638731
Short name T775
Test name
Test status
Simulation time 1885474102 ps
CPU time 21.02 seconds
Started Jun 02 03:16:50 PM PDT 24
Finished Jun 02 03:17:11 PM PDT 24
Peak memory 240376 kb
Host smart-45711bd2-46a4-4f58-9e9e-01120f146473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819638731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1819638731
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4038034904
Short name T571
Test name
Test status
Simulation time 8221747628 ps
CPU time 13.73 seconds
Started Jun 02 03:16:50 PM PDT 24
Finished Jun 02 03:17:05 PM PDT 24
Peak memory 233824 kb
Host smart-8a41c118-db8a-43f1-9969-8a14fa1a7b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038034904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4038034904
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1080878971
Short name T471
Test name
Test status
Simulation time 9814317913 ps
CPU time 27.17 seconds
Started Jun 02 03:16:52 PM PDT 24
Finished Jun 02 03:17:20 PM PDT 24
Peak memory 252104 kb
Host smart-9852098d-7f65-43d2-bfe8-004aed0a11e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080878971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1080878971
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3343825214
Short name T496
Test name
Test status
Simulation time 256585313 ps
CPU time 3.71 seconds
Started Jun 02 03:16:51 PM PDT 24
Finished Jun 02 03:16:55 PM PDT 24
Peak memory 219684 kb
Host smart-97f0b6b6-104c-4229-9237-5cd2d65fdc5b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3343825214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3343825214
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2526697489
Short name T229
Test name
Test status
Simulation time 96797334513 ps
CPU time 162.98 seconds
Started Jun 02 03:16:59 PM PDT 24
Finished Jun 02 03:19:43 PM PDT 24
Peak memory 255548 kb
Host smart-c022e5de-1618-4c83-9741-5aefe669deb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526697489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2526697489
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3523545069
Short name T684
Test name
Test status
Simulation time 1713251745 ps
CPU time 9.26 seconds
Started Jun 02 03:16:50 PM PDT 24
Finished Jun 02 03:17:00 PM PDT 24
Peak memory 216204 kb
Host smart-215d2569-5c13-4532-a417-49cf5209b0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523545069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3523545069
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2621117839
Short name T674
Test name
Test status
Simulation time 1254620769 ps
CPU time 1.79 seconds
Started Jun 02 03:16:49 PM PDT 24
Finished Jun 02 03:16:52 PM PDT 24
Peak memory 207460 kb
Host smart-36f510c9-1889-4378-9ef5-7f7653c0480e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621117839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2621117839
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1817425631
Short name T598
Test name
Test status
Simulation time 123845317 ps
CPU time 1.32 seconds
Started Jun 02 03:16:52 PM PDT 24
Finished Jun 02 03:16:54 PM PDT 24
Peak memory 216244 kb
Host smart-8c684a59-69d6-4dd4-b42c-83138ec5cc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817425631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1817425631
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1271496231
Short name T11
Test name
Test status
Simulation time 28321123 ps
CPU time 0.75 seconds
Started Jun 02 03:16:53 PM PDT 24
Finished Jun 02 03:16:54 PM PDT 24
Peak memory 205428 kb
Host smart-2e1c8e8c-56ee-448e-ab7e-0b8b3592058a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271496231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1271496231
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.12211853
Short name T56
Test name
Test status
Simulation time 6490909861 ps
CPU time 9 seconds
Started Jun 02 03:16:51 PM PDT 24
Finished Jun 02 03:17:01 PM PDT 24
Peak memory 250932 kb
Host smart-7e7413d4-9787-4c16-92fd-171d723b4475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12211853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.12211853
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1772971768
Short name T581
Test name
Test status
Simulation time 214942635 ps
CPU time 0.73 seconds
Started Jun 02 03:17:05 PM PDT 24
Finished Jun 02 03:17:06 PM PDT 24
Peak memory 205376 kb
Host smart-c6cdf2e3-6876-4b2b-8555-c7022bd0f603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772971768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1772971768
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.153409746
Short name T555
Test name
Test status
Simulation time 966853485 ps
CPU time 5.35 seconds
Started Jun 02 03:17:00 PM PDT 24
Finished Jun 02 03:17:06 PM PDT 24
Peak memory 234432 kb
Host smart-28db9e7d-6b68-4bee-bb3d-381a38055ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153409746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.153409746
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.76383241
Short name T444
Test name
Test status
Simulation time 45961832 ps
CPU time 0.77 seconds
Started Jun 02 03:16:59 PM PDT 24
Finished Jun 02 03:17:00 PM PDT 24
Peak memory 206760 kb
Host smart-a4944aca-62d0-4f42-b0d4-8ef6ae6ab208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76383241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.76383241
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3152044480
Short name T216
Test name
Test status
Simulation time 13545556122 ps
CPU time 35.72 seconds
Started Jun 02 03:16:58 PM PDT 24
Finished Jun 02 03:17:35 PM PDT 24
Peak memory 239824 kb
Host smart-39e5fb37-ffe2-4f3e-b39d-041a073e6ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152044480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3152044480
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2140494934
Short name T791
Test name
Test status
Simulation time 4728936959 ps
CPU time 28.01 seconds
Started Jun 02 03:17:05 PM PDT 24
Finished Jun 02 03:17:34 PM PDT 24
Peak memory 216892 kb
Host smart-66972a38-41e5-41f4-b829-9437fd8b0206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140494934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2140494934
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3876365005
Short name T310
Test name
Test status
Simulation time 100169907641 ps
CPU time 477.97 seconds
Started Jun 02 03:17:06 PM PDT 24
Finished Jun 02 03:25:04 PM PDT 24
Peak memory 256308 kb
Host smart-d2cfc16b-8b7c-40da-b22b-440cc77dfd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876365005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3876365005
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2756382967
Short name T701
Test name
Test status
Simulation time 2921434387 ps
CPU time 15.62 seconds
Started Jun 02 03:16:58 PM PDT 24
Finished Jun 02 03:17:14 PM PDT 24
Peak memory 232652 kb
Host smart-c466b42f-b4e8-4cf7-8d17-0fd7dcb13977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756382967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2756382967
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4203799539
Short name T886
Test name
Test status
Simulation time 112908262 ps
CPU time 2.1 seconds
Started Jun 02 03:17:00 PM PDT 24
Finished Jun 02 03:17:03 PM PDT 24
Peak memory 215968 kb
Host smart-db857ed7-92f5-45e5-a306-185975f75b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203799539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4203799539
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.542931469
Short name T200
Test name
Test status
Simulation time 3734930421 ps
CPU time 25.61 seconds
Started Jun 02 03:16:59 PM PDT 24
Finished Jun 02 03:17:25 PM PDT 24
Peak memory 224004 kb
Host smart-09365692-a14c-42cc-bb9a-4a693b18423c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542931469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.542931469
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4141271149
Short name T258
Test name
Test status
Simulation time 554323052 ps
CPU time 3.25 seconds
Started Jun 02 03:16:59 PM PDT 24
Finished Jun 02 03:17:03 PM PDT 24
Peak memory 233540 kb
Host smart-3eda8d36-4cbd-43cb-baf1-a65c39aaf777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141271149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4141271149
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.189309574
Short name T675
Test name
Test status
Simulation time 4832678945 ps
CPU time 19.37 seconds
Started Jun 02 03:16:59 PM PDT 24
Finished Jun 02 03:17:19 PM PDT 24
Peak memory 234752 kb
Host smart-7ea9b825-859c-4e3c-9e2b-8b03be02333b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189309574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.189309574
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3669737435
Short name T589
Test name
Test status
Simulation time 216601208 ps
CPU time 4.76 seconds
Started Jun 02 03:16:58 PM PDT 24
Finished Jun 02 03:17:03 PM PDT 24
Peak memory 222880 kb
Host smart-849c5bf8-a1df-44b9-ad2d-7140c0b21fa7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3669737435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3669737435
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3369507503
Short name T787
Test name
Test status
Simulation time 549649743 ps
CPU time 5.72 seconds
Started Jun 02 03:16:59 PM PDT 24
Finished Jun 02 03:17:05 PM PDT 24
Peak memory 216244 kb
Host smart-499ac5b8-b62b-4422-bcf2-367d548adc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369507503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3369507503
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2629354815
Short name T339
Test name
Test status
Simulation time 1056155093 ps
CPU time 3.71 seconds
Started Jun 02 03:16:59 PM PDT 24
Finished Jun 02 03:17:03 PM PDT 24
Peak memory 216180 kb
Host smart-ab6cd5ea-844e-4a31-8e45-0230f65f1547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629354815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2629354815
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1854635738
Short name T875
Test name
Test status
Simulation time 227796214 ps
CPU time 1.4 seconds
Started Jun 02 03:17:00 PM PDT 24
Finished Jun 02 03:17:02 PM PDT 24
Peak memory 207780 kb
Host smart-742f9317-4451-4147-adfe-e82469a6054a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854635738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1854635738
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3505463981
Short name T941
Test name
Test status
Simulation time 135386036 ps
CPU time 0.79 seconds
Started Jun 02 03:16:58 PM PDT 24
Finished Jun 02 03:16:59 PM PDT 24
Peak memory 205640 kb
Host smart-c13b4660-d0b9-4998-bd4a-9b93f2f32891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505463981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3505463981
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.4171895729
Short name T391
Test name
Test status
Simulation time 81901936 ps
CPU time 2.28 seconds
Started Jun 02 03:16:58 PM PDT 24
Finished Jun 02 03:17:01 PM PDT 24
Peak memory 212864 kb
Host smart-75716f56-9152-4429-b90d-7f9cb052b541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171895729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4171895729
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2559837741
Short name T900
Test name
Test status
Simulation time 13433614 ps
CPU time 0.78 seconds
Started Jun 02 03:17:05 PM PDT 24
Finished Jun 02 03:17:07 PM PDT 24
Peak memory 204448 kb
Host smart-07b4fbc6-4b48-4905-a8f9-2747b963c54d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559837741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2559837741
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3208489938
Short name T946
Test name
Test status
Simulation time 148348775 ps
CPU time 2.49 seconds
Started Jun 02 03:17:08 PM PDT 24
Finished Jun 02 03:17:11 PM PDT 24
Peak memory 233860 kb
Host smart-efd5c458-97d0-4986-8f6f-94337f105d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208489938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3208489938
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1762725344
Short name T397
Test name
Test status
Simulation time 96988641 ps
CPU time 0.79 seconds
Started Jun 02 03:17:08 PM PDT 24
Finished Jun 02 03:17:10 PM PDT 24
Peak memory 206388 kb
Host smart-78c26e99-82c8-4431-9340-a0d1822f3afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762725344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1762725344
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3983925363
Short name T561
Test name
Test status
Simulation time 83491666952 ps
CPU time 105.06 seconds
Started Jun 02 03:17:08 PM PDT 24
Finished Jun 02 03:18:53 PM PDT 24
Peak memory 224424 kb
Host smart-243226ce-7ed5-4ae3-81b0-e87e443c0de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983925363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3983925363
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2635554284
Short name T920
Test name
Test status
Simulation time 62598794302 ps
CPU time 111.07 seconds
Started Jun 02 03:17:04 PM PDT 24
Finished Jun 02 03:18:56 PM PDT 24
Peak memory 257244 kb
Host smart-72544061-1876-49ea-ae14-ac8c77786781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635554284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2635554284
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.4001583578
Short name T697
Test name
Test status
Simulation time 6239426992 ps
CPU time 103.76 seconds
Started Jun 02 03:17:07 PM PDT 24
Finished Jun 02 03:18:51 PM PDT 24
Peak memory 249428 kb
Host smart-8296b8aa-82d8-4915-bf78-9767c78b328d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001583578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.4001583578
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2249927926
Short name T670
Test name
Test status
Simulation time 1279246549 ps
CPU time 23.05 seconds
Started Jun 02 03:17:03 PM PDT 24
Finished Jun 02 03:17:27 PM PDT 24
Peak memory 248964 kb
Host smart-252e1408-3eb7-4291-87fd-2e62031be905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249927926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2249927926
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3288495797
Short name T490
Test name
Test status
Simulation time 348925077 ps
CPU time 4.01 seconds
Started Jun 02 03:17:05 PM PDT 24
Finished Jun 02 03:17:09 PM PDT 24
Peak memory 234536 kb
Host smart-e5d0a463-4bd4-4170-b771-2311a3a026b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288495797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3288495797
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2480734577
Short name T206
Test name
Test status
Simulation time 10946790231 ps
CPU time 39.81 seconds
Started Jun 02 03:17:03 PM PDT 24
Finished Jun 02 03:17:44 PM PDT 24
Peak memory 240004 kb
Host smart-816dc1c9-0c32-483e-8b5c-77678f136ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480734577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2480734577
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2058567539
Short name T197
Test name
Test status
Simulation time 234523046 ps
CPU time 3.69 seconds
Started Jun 02 03:17:05 PM PDT 24
Finished Jun 02 03:17:09 PM PDT 24
Peak memory 233540 kb
Host smart-a5b842bd-5f91-4fec-8eb3-c673563ad0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058567539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2058567539
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1186510778
Short name T486
Test name
Test status
Simulation time 641507429 ps
CPU time 5.81 seconds
Started Jun 02 03:17:06 PM PDT 24
Finished Jun 02 03:17:13 PM PDT 24
Peak memory 219432 kb
Host smart-a8f8b5a3-0025-425b-b2be-aef274bba8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186510778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1186510778
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3093567915
Short name T439
Test name
Test status
Simulation time 3371650902 ps
CPU time 5.82 seconds
Started Jun 02 03:17:08 PM PDT 24
Finished Jun 02 03:17:14 PM PDT 24
Peak memory 219800 kb
Host smart-2758f364-b242-430d-a822-fed9b6c66782
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3093567915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3093567915
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1851620664
Short name T311
Test name
Test status
Simulation time 319770723947 ps
CPU time 551.24 seconds
Started Jun 02 03:17:08 PM PDT 24
Finished Jun 02 03:26:20 PM PDT 24
Peak memory 257252 kb
Host smart-1e8b22eb-1f17-4550-a0ef-367dfe90cba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851620664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1851620664
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4217402566
Short name T721
Test name
Test status
Simulation time 46718225 ps
CPU time 0.77 seconds
Started Jun 02 03:17:06 PM PDT 24
Finished Jun 02 03:17:08 PM PDT 24
Peak memory 206088 kb
Host smart-268acc54-77fe-4cb6-94b6-35e28f988c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217402566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4217402566
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3773130239
Short name T322
Test name
Test status
Simulation time 997757521 ps
CPU time 4.88 seconds
Started Jun 02 03:17:04 PM PDT 24
Finished Jun 02 03:17:09 PM PDT 24
Peak memory 216136 kb
Host smart-e2398977-adcd-42a9-b027-c16b0eacf1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773130239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3773130239
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3692959519
Short name T845
Test name
Test status
Simulation time 170681517 ps
CPU time 1.69 seconds
Started Jun 02 03:17:05 PM PDT 24
Finished Jun 02 03:17:07 PM PDT 24
Peak memory 216168 kb
Host smart-18e2d8c0-54fd-4dbc-8cb1-090fd2957938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692959519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3692959519
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3096762331
Short name T742
Test name
Test status
Simulation time 65507443 ps
CPU time 0.88 seconds
Started Jun 02 03:17:05 PM PDT 24
Finished Jun 02 03:17:06 PM PDT 24
Peak memory 205616 kb
Host smart-20696dd5-3382-4914-b8c5-3e2ea1942dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096762331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3096762331
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3305898403
Short name T2
Test name
Test status
Simulation time 38144702430 ps
CPU time 29.51 seconds
Started Jun 02 03:17:04 PM PDT 24
Finished Jun 02 03:17:34 PM PDT 24
Peak memory 218780 kb
Host smart-c5bfe59f-245b-4e57-a209-a595c12f604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305898403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3305898403
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2241176373
Short name T857
Test name
Test status
Simulation time 37487456 ps
CPU time 0.74 seconds
Started Jun 02 03:17:11 PM PDT 24
Finished Jun 02 03:17:12 PM PDT 24
Peak memory 205728 kb
Host smart-078b8bd9-83b4-4e9c-9ddb-c6665d9a7358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241176373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2241176373
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1892135959
Short name T668
Test name
Test status
Simulation time 1301641383 ps
CPU time 9.88 seconds
Started Jun 02 03:17:11 PM PDT 24
Finished Jun 02 03:17:22 PM PDT 24
Peak memory 233524 kb
Host smart-58ceaa7f-a7fa-4823-9025-42e4c93fba36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892135959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1892135959
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.585684376
Short name T357
Test name
Test status
Simulation time 38692099 ps
CPU time 0.77 seconds
Started Jun 02 03:17:06 PM PDT 24
Finished Jun 02 03:17:07 PM PDT 24
Peak memory 205668 kb
Host smart-dca30584-fb10-423a-b918-b7c91cc89dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585684376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.585684376
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2061376659
Short name T34
Test name
Test status
Simulation time 21034576500 ps
CPU time 105.11 seconds
Started Jun 02 03:17:11 PM PDT 24
Finished Jun 02 03:18:57 PM PDT 24
Peak memory 249032 kb
Host smart-ac2f6e36-b5ea-41df-b9eb-253689ec323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061376659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2061376659
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1863781020
Short name T862
Test name
Test status
Simulation time 3144772055 ps
CPU time 66.97 seconds
Started Jun 02 03:17:20 PM PDT 24
Finished Jun 02 03:18:27 PM PDT 24
Peak memory 249164 kb
Host smart-5d8e6956-134a-4085-a63d-02776057a90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863781020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1863781020
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1739923741
Short name T452
Test name
Test status
Simulation time 81532938166 ps
CPU time 366.32 seconds
Started Jun 02 03:17:14 PM PDT 24
Finished Jun 02 03:23:21 PM PDT 24
Peak memory 253316 kb
Host smart-0fe1ff04-fd23-4f9f-9894-4005a972f53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739923741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1739923741
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4077034511
Short name T666
Test name
Test status
Simulation time 74789873 ps
CPU time 2.63 seconds
Started Jun 02 03:17:11 PM PDT 24
Finished Jun 02 03:17:14 PM PDT 24
Peak memory 224300 kb
Host smart-91e676bf-0113-429a-a61f-8e1637fec5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077034511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4077034511
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3596737771
Short name T744
Test name
Test status
Simulation time 833746713 ps
CPU time 10.31 seconds
Started Jun 02 03:17:05 PM PDT 24
Finished Jun 02 03:17:15 PM PDT 24
Peak memory 234336 kb
Host smart-1fd075ba-70fc-4dd8-b6d6-35ea7f52141e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596737771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3596737771
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3793327954
Short name T517
Test name
Test status
Simulation time 9480264311 ps
CPU time 28.01 seconds
Started Jun 02 03:17:05 PM PDT 24
Finished Jun 02 03:17:33 PM PDT 24
Peak memory 222624 kb
Host smart-278f7c3e-35c9-49ec-82ab-0fb4a38b0249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793327954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3793327954
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.4006297199
Short name T459
Test name
Test status
Simulation time 342549193 ps
CPU time 4.75 seconds
Started Jun 02 03:17:07 PM PDT 24
Finished Jun 02 03:17:12 PM PDT 24
Peak memory 217844 kb
Host smart-31569fe0-b2fa-44b2-bb83-8e7968658ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006297199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.4006297199
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2514968527
Short name T222
Test name
Test status
Simulation time 153037640 ps
CPU time 2.77 seconds
Started Jun 02 03:17:05 PM PDT 24
Finished Jun 02 03:17:09 PM PDT 24
Peak memory 218708 kb
Host smart-11f4a5ad-f328-4bc4-a624-29eef560a99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514968527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2514968527
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2773500959
Short name T573
Test name
Test status
Simulation time 1402052743 ps
CPU time 16.05 seconds
Started Jun 02 03:17:10 PM PDT 24
Finished Jun 02 03:17:27 PM PDT 24
Peak memory 222916 kb
Host smart-8b6721bc-1c7a-467d-b9e8-e70436c281fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2773500959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2773500959
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.429459678
Short name T158
Test name
Test status
Simulation time 26585368712 ps
CPU time 279.76 seconds
Started Jun 02 03:17:21 PM PDT 24
Finished Jun 02 03:22:01 PM PDT 24
Peak memory 249076 kb
Host smart-5fcb519a-2ba9-4c71-bc91-2958acc0f565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429459678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.429459678
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1350988574
Short name T686
Test name
Test status
Simulation time 207233198 ps
CPU time 4.14 seconds
Started Jun 02 03:17:08 PM PDT 24
Finished Jun 02 03:17:13 PM PDT 24
Peak memory 216496 kb
Host smart-e05e6a0f-e8c2-42da-a7a2-8e7f0a3e137b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350988574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1350988574
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1745958210
Short name T325
Test name
Test status
Simulation time 20828009 ps
CPU time 0.73 seconds
Started Jun 02 03:17:03 PM PDT 24
Finished Jun 02 03:17:04 PM PDT 24
Peak memory 205524 kb
Host smart-f875e35a-9714-4f61-8a46-ae48e2997b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745958210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1745958210
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1579591818
Short name T25
Test name
Test status
Simulation time 117363469 ps
CPU time 3.26 seconds
Started Jun 02 03:17:08 PM PDT 24
Finished Jun 02 03:17:12 PM PDT 24
Peak memory 216212 kb
Host smart-2b88473f-2d94-4da4-9e49-56b5c1e642d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579591818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1579591818
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.463530343
Short name T336
Test name
Test status
Simulation time 40359510 ps
CPU time 0.8 seconds
Started Jun 02 03:17:06 PM PDT 24
Finished Jun 02 03:17:07 PM PDT 24
Peak memory 205644 kb
Host smart-4317272c-7198-4a4b-b484-80e745b00b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463530343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.463530343
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3086149573
Short name T469
Test name
Test status
Simulation time 7599366962 ps
CPU time 16.45 seconds
Started Jun 02 03:17:23 PM PDT 24
Finished Jun 02 03:17:40 PM PDT 24
Peak memory 242596 kb
Host smart-669f02dc-8a1e-46ae-847d-0f3a4cff4544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086149573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3086149573
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1098637016
Short name T355
Test name
Test status
Simulation time 43135511 ps
CPU time 0.71 seconds
Started Jun 02 03:17:11 PM PDT 24
Finished Jun 02 03:17:12 PM PDT 24
Peak memory 205400 kb
Host smart-cb1a9a3b-796a-4a21-b327-d07da11ce086
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098637016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1098637016
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1198953707
Short name T735
Test name
Test status
Simulation time 1883713812 ps
CPU time 5.08 seconds
Started Jun 02 03:17:20 PM PDT 24
Finished Jun 02 03:17:26 PM PDT 24
Peak memory 219536 kb
Host smart-6e6261b7-85a9-4c25-826c-faec089884db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198953707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1198953707
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3421453165
Short name T618
Test name
Test status
Simulation time 57868816 ps
CPU time 0.77 seconds
Started Jun 02 03:17:15 PM PDT 24
Finished Jun 02 03:17:16 PM PDT 24
Peak memory 206432 kb
Host smart-1c9a563a-eca1-4fe4-ae06-a83cc9040957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421453165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3421453165
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3960074770
Short name T462
Test name
Test status
Simulation time 18553147908 ps
CPU time 98.93 seconds
Started Jun 02 03:17:12 PM PDT 24
Finished Jun 02 03:18:52 PM PDT 24
Peak memory 251352 kb
Host smart-6b723898-1dcc-495f-b76a-0d80bcbea410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960074770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3960074770
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1285127368
Short name T294
Test name
Test status
Simulation time 4429660729 ps
CPU time 84 seconds
Started Jun 02 03:17:18 PM PDT 24
Finished Jun 02 03:18:42 PM PDT 24
Peak memory 257252 kb
Host smart-77f3ec4d-c88b-4ed8-a180-0fa223418d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285127368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1285127368
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.977068714
Short name T208
Test name
Test status
Simulation time 76557729539 ps
CPU time 652.11 seconds
Started Jun 02 03:17:12 PM PDT 24
Finished Jun 02 03:28:04 PM PDT 24
Peak memory 261444 kb
Host smart-f21865d1-7a11-48b6-b5e8-e3870f62461f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977068714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.977068714
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.564400359
Short name T931
Test name
Test status
Simulation time 298462048 ps
CPU time 4.32 seconds
Started Jun 02 03:17:13 PM PDT 24
Finished Jun 02 03:17:18 PM PDT 24
Peak memory 232548 kb
Host smart-ef2d19ae-8315-49f1-bd03-8f7f24972ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564400359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.564400359
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.781059799
Short name T100
Test name
Test status
Simulation time 24969906405 ps
CPU time 31.98 seconds
Started Jun 02 03:17:20 PM PDT 24
Finished Jun 02 03:17:53 PM PDT 24
Peak memory 220208 kb
Host smart-c12a9ffa-9204-4958-8215-a54bb7907360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781059799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.781059799
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3669401353
Short name T252
Test name
Test status
Simulation time 1878365107 ps
CPU time 8.87 seconds
Started Jun 02 03:17:19 PM PDT 24
Finished Jun 02 03:17:29 PM PDT 24
Peak memory 237012 kb
Host smart-8aca1954-543a-4183-8da1-d19e862cf6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669401353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3669401353
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1064461004
Short name T481
Test name
Test status
Simulation time 2461125130 ps
CPU time 8.38 seconds
Started Jun 02 03:17:13 PM PDT 24
Finished Jun 02 03:17:22 PM PDT 24
Peak memory 234356 kb
Host smart-8bc6c742-9b5b-4fe2-a217-1a9c3ca9b7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064461004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1064461004
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2465135313
Short name T432
Test name
Test status
Simulation time 2241223985 ps
CPU time 7.93 seconds
Started Jun 02 03:17:19 PM PDT 24
Finished Jun 02 03:17:27 PM PDT 24
Peak memory 235620 kb
Host smart-4c5fca32-e8a9-4164-85ac-9ef3d54a97f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465135313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2465135313
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1625522336
Short name T445
Test name
Test status
Simulation time 669762072 ps
CPU time 7.57 seconds
Started Jun 02 03:17:18 PM PDT 24
Finished Jun 02 03:17:26 PM PDT 24
Peak memory 222300 kb
Host smart-e2ee3ddb-368e-47f3-9fe9-cbac01d099f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1625522336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1625522336
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2217162964
Short name T479
Test name
Test status
Simulation time 37515991 ps
CPU time 1.13 seconds
Started Jun 02 03:17:20 PM PDT 24
Finished Jun 02 03:17:21 PM PDT 24
Peak memory 206688 kb
Host smart-f30285eb-b2ce-43b1-a3df-1597bcf2c0d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217162964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2217162964
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3352964000
Short name T131
Test name
Test status
Simulation time 842673072 ps
CPU time 7.52 seconds
Started Jun 02 03:17:19 PM PDT 24
Finished Jun 02 03:17:27 PM PDT 24
Peak memory 219260 kb
Host smart-a97d18f5-af9f-49c1-8924-ad7a2ed6a70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352964000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3352964000
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1424823680
Short name T827
Test name
Test status
Simulation time 5565710379 ps
CPU time 15.86 seconds
Started Jun 02 03:17:18 PM PDT 24
Finished Jun 02 03:17:34 PM PDT 24
Peak memory 215904 kb
Host smart-7a0d233d-3f35-4ed8-9e4a-ee74c1d5788c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424823680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1424823680
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2601029656
Short name T859
Test name
Test status
Simulation time 81703301 ps
CPU time 1.72 seconds
Started Jun 02 03:17:13 PM PDT 24
Finished Jun 02 03:17:16 PM PDT 24
Peak memory 216120 kb
Host smart-4b5bda9a-bd6c-447c-bae7-c7049cf7de48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601029656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2601029656
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1032859282
Short name T402
Test name
Test status
Simulation time 19758077 ps
CPU time 0.74 seconds
Started Jun 02 03:17:12 PM PDT 24
Finished Jun 02 03:17:13 PM PDT 24
Peak memory 205612 kb
Host smart-8a489b78-e3ef-4560-9009-b438dbd9b259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032859282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1032859282
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2382127223
Short name T604
Test name
Test status
Simulation time 145706607 ps
CPU time 3.46 seconds
Started Jun 02 03:17:13 PM PDT 24
Finished Jun 02 03:17:17 PM PDT 24
Peak memory 219164 kb
Host smart-ea501b1c-95ad-446f-934e-1ffd51ca5c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382127223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2382127223
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1792037210
Short name T613
Test name
Test status
Simulation time 139579574 ps
CPU time 0.68 seconds
Started Jun 02 03:15:28 PM PDT 24
Finished Jun 02 03:15:30 PM PDT 24
Peak memory 204756 kb
Host smart-8fb2c58e-36ea-4e70-a7cc-89672970edf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792037210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
792037210
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1890370297
Short name T88
Test name
Test status
Simulation time 140073550 ps
CPU time 3 seconds
Started Jun 02 03:15:32 PM PDT 24
Finished Jun 02 03:15:36 PM PDT 24
Peak memory 224380 kb
Host smart-23c59630-9c20-40ce-a11f-40a003f9e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890370297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1890370297
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.580447096
Short name T678
Test name
Test status
Simulation time 18979166 ps
CPU time 0.75 seconds
Started Jun 02 03:15:21 PM PDT 24
Finished Jun 02 03:15:22 PM PDT 24
Peak memory 205680 kb
Host smart-44f6647f-a6b7-4799-b19d-947617b34c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580447096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.580447096
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1145615317
Short name T831
Test name
Test status
Simulation time 5510573800 ps
CPU time 31.84 seconds
Started Jun 02 03:15:30 PM PDT 24
Finished Jun 02 03:16:03 PM PDT 24
Peak memory 249760 kb
Host smart-a98fa396-402f-4056-a564-a0133c37fdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145615317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1145615317
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1744342751
Short name T29
Test name
Test status
Simulation time 26026988885 ps
CPU time 46.7 seconds
Started Jun 02 03:15:30 PM PDT 24
Finished Jun 02 03:16:18 PM PDT 24
Peak memory 249104 kb
Host smart-7c14bb25-c489-4669-a335-2cbe7f52897c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744342751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1744342751
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3287799196
Short name T193
Test name
Test status
Simulation time 8032840873 ps
CPU time 84.25 seconds
Started Jun 02 03:15:28 PM PDT 24
Finished Jun 02 03:16:53 PM PDT 24
Peak memory 249112 kb
Host smart-1b8cebff-4908-47d7-839e-9729f55c795b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287799196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3287799196
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2758834763
Short name T850
Test name
Test status
Simulation time 209440225 ps
CPU time 5.16 seconds
Started Jun 02 03:15:27 PM PDT 24
Finished Jun 02 03:15:34 PM PDT 24
Peak memory 232600 kb
Host smart-02f570f3-db2c-4394-9fd2-e85a0b439cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758834763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2758834763
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2268330159
Short name T642
Test name
Test status
Simulation time 2516559612 ps
CPU time 17.57 seconds
Started Jun 02 03:15:27 PM PDT 24
Finished Jun 02 03:15:46 PM PDT 24
Peak memory 233888 kb
Host smart-0b9edf8a-8d2e-4e6d-9b30-ed5a0a659a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268330159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2268330159
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1185326250
Short name T660
Test name
Test status
Simulation time 7908435211 ps
CPU time 19.69 seconds
Started Jun 02 03:15:27 PM PDT 24
Finished Jun 02 03:15:48 PM PDT 24
Peak memory 228076 kb
Host smart-eae5526a-c908-4ed1-804c-5947c5dcfa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185326250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1185326250
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.14926017
Short name T560
Test name
Test status
Simulation time 12060869514 ps
CPU time 34.27 seconds
Started Jun 02 03:15:26 PM PDT 24
Finished Jun 02 03:16:02 PM PDT 24
Peak memory 228768 kb
Host smart-1df1f799-8c51-4aa2-ab3d-d978604a1c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14926017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.14926017
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1816528960
Short name T507
Test name
Test status
Simulation time 92170156 ps
CPU time 2.11 seconds
Started Jun 02 03:15:27 PM PDT 24
Finished Jun 02 03:15:31 PM PDT 24
Peak memory 215948 kb
Host smart-badd9770-6d02-4313-8b4a-a20d164da6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816528960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1816528960
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2477712312
Short name T346
Test name
Test status
Simulation time 555251875 ps
CPU time 3.29 seconds
Started Jun 02 03:15:31 PM PDT 24
Finished Jun 02 03:15:35 PM PDT 24
Peak memory 219908 kb
Host smart-88fbc645-3cc1-4b45-b2b4-59abb7a11949
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2477712312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2477712312
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2500394344
Short name T68
Test name
Test status
Simulation time 116525757 ps
CPU time 1.12 seconds
Started Jun 02 03:15:28 PM PDT 24
Finished Jun 02 03:15:30 PM PDT 24
Peak memory 235056 kb
Host smart-d420a738-ea95-4e29-99cb-03862fb46871
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500394344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2500394344
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3459532282
Short name T953
Test name
Test status
Simulation time 40054237467 ps
CPU time 97.25 seconds
Started Jun 02 03:15:25 PM PDT 24
Finished Jun 02 03:17:03 PM PDT 24
Peak memory 248804 kb
Host smart-78b2eb52-5a2f-491f-a901-099187948057
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459532282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3459532282
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2277274556
Short name T730
Test name
Test status
Simulation time 357541765 ps
CPU time 3.25 seconds
Started Jun 02 03:15:27 PM PDT 24
Finished Jun 02 03:15:32 PM PDT 24
Peak memory 216136 kb
Host smart-856e0a3b-8306-43dc-ac1f-b191561153b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277274556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2277274556
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2812394339
Short name T927
Test name
Test status
Simulation time 13352104229 ps
CPU time 18.6 seconds
Started Jun 02 03:15:33 PM PDT 24
Finished Jun 02 03:15:52 PM PDT 24
Peak memory 216232 kb
Host smart-f3074f9b-3220-46a0-ad65-a610755e74bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812394339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2812394339
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3613414650
Short name T51
Test name
Test status
Simulation time 18224963 ps
CPU time 0.99 seconds
Started Jun 02 03:15:26 PM PDT 24
Finished Jun 02 03:15:28 PM PDT 24
Peak memory 207088 kb
Host smart-1fc36eaf-43d1-42ef-92a4-b5ee153cfca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613414650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3613414650
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3695888513
Short name T825
Test name
Test status
Simulation time 183801646 ps
CPU time 0.84 seconds
Started Jun 02 03:15:26 PM PDT 24
Finished Jun 02 03:15:28 PM PDT 24
Peak memory 205604 kb
Host smart-90eeff69-16c1-4756-bb89-13668151dc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695888513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3695888513
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.4019134938
Short name T853
Test name
Test status
Simulation time 9535322037 ps
CPU time 10.29 seconds
Started Jun 02 03:15:26 PM PDT 24
Finished Jun 02 03:15:38 PM PDT 24
Peak memory 239712 kb
Host smart-b54b95cc-04d2-4424-a137-0e918a42a5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019134938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4019134938
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4269546487
Short name T901
Test name
Test status
Simulation time 28530361 ps
CPU time 0.74 seconds
Started Jun 02 03:17:23 PM PDT 24
Finished Jun 02 03:17:24 PM PDT 24
Peak memory 205648 kb
Host smart-2a79ab84-01ab-4c29-b665-1ce7493fa95b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269546487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4269546487
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.872070943
Short name T913
Test name
Test status
Simulation time 596831868 ps
CPU time 6.21 seconds
Started Jun 02 03:17:22 PM PDT 24
Finished Jun 02 03:17:28 PM PDT 24
Peak memory 219520 kb
Host smart-117b63a6-e001-43a7-9f8d-f44169bb7f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872070943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.872070943
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2118184761
Short name T839
Test name
Test status
Simulation time 36271576 ps
CPU time 0.77 seconds
Started Jun 02 03:17:17 PM PDT 24
Finished Jun 02 03:17:19 PM PDT 24
Peak memory 206460 kb
Host smart-01d4ee72-8555-4bdd-bade-48ef225c1a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118184761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2118184761
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3402129930
Short name T27
Test name
Test status
Simulation time 53516482974 ps
CPU time 87.16 seconds
Started Jun 02 03:17:20 PM PDT 24
Finished Jun 02 03:18:48 PM PDT 24
Peak memory 254308 kb
Host smart-2ab6f4ac-4380-42ac-982d-649541556680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402129930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3402129930
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.4219557146
Short name T712
Test name
Test status
Simulation time 8574699505 ps
CPU time 94.08 seconds
Started Jun 02 03:17:20 PM PDT 24
Finished Jun 02 03:18:54 PM PDT 24
Peak memory 249000 kb
Host smart-f4a84585-af5a-46c0-ac23-0bb04e72751c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219557146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.4219557146
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2071705869
Short name T303
Test name
Test status
Simulation time 767160981 ps
CPU time 6.59 seconds
Started Jun 02 03:17:23 PM PDT 24
Finished Jun 02 03:17:30 PM PDT 24
Peak memory 232520 kb
Host smart-f40fe3b8-0d96-418a-83e9-37352277e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071705869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2071705869
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3229595578
Short name T942
Test name
Test status
Simulation time 3545008429 ps
CPU time 29.67 seconds
Started Jun 02 03:17:19 PM PDT 24
Finished Jun 02 03:17:49 PM PDT 24
Peak memory 220524 kb
Host smart-4cc18133-25f6-438e-a318-c412cb3d895a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229595578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3229595578
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3083680728
Short name T202
Test name
Test status
Simulation time 7545728197 ps
CPU time 60.38 seconds
Started Jun 02 03:17:23 PM PDT 24
Finished Jun 02 03:18:24 PM PDT 24
Peak memory 235508 kb
Host smart-44cac04a-7f7d-4dbb-bd5f-015307fa0ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083680728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3083680728
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.752348049
Short name T317
Test name
Test status
Simulation time 285723834 ps
CPU time 2.3 seconds
Started Jun 02 03:17:23 PM PDT 24
Finished Jun 02 03:17:25 PM PDT 24
Peak memory 215972 kb
Host smart-c53374b3-5ab9-49b1-bb1d-f938cb07a035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752348049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.752348049
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2699576638
Short name T480
Test name
Test status
Simulation time 823258897 ps
CPU time 4.42 seconds
Started Jun 02 03:17:20 PM PDT 24
Finished Jun 02 03:17:25 PM PDT 24
Peak memory 216808 kb
Host smart-487232bb-45a8-411b-9150-fb4f99b0783d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699576638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2699576638
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1270538375
Short name T844
Test name
Test status
Simulation time 608123212 ps
CPU time 5.12 seconds
Started Jun 02 03:17:19 PM PDT 24
Finished Jun 02 03:17:25 PM PDT 24
Peak memory 222764 kb
Host smart-7b4b5400-92c7-40b3-9a6d-aae506162cf1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1270538375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1270538375
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1725807064
Short name T580
Test name
Test status
Simulation time 6534320124 ps
CPU time 20.09 seconds
Started Jun 02 03:17:11 PM PDT 24
Finished Jun 02 03:17:32 PM PDT 24
Peak memory 216356 kb
Host smart-d06b335d-208a-4575-a41f-8846199ee2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725807064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1725807064
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2045619446
Short name T434
Test name
Test status
Simulation time 424584077 ps
CPU time 1.73 seconds
Started Jun 02 03:17:11 PM PDT 24
Finished Jun 02 03:17:13 PM PDT 24
Peak memory 207732 kb
Host smart-871b8c02-3442-4b67-9d10-16fc08537032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045619446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2045619446
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.146275309
Short name T882
Test name
Test status
Simulation time 290199194 ps
CPU time 6.18 seconds
Started Jun 02 03:17:11 PM PDT 24
Finished Jun 02 03:17:18 PM PDT 24
Peak memory 216204 kb
Host smart-968fd012-e22f-4a9f-959a-bc3dd4360598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146275309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.146275309
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2110207632
Short name T52
Test name
Test status
Simulation time 47666041 ps
CPU time 0.85 seconds
Started Jun 02 03:17:13 PM PDT 24
Finished Jun 02 03:17:14 PM PDT 24
Peak memory 205636 kb
Host smart-ad0355e4-68cf-4f93-a439-4a9fcca8e5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110207632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2110207632
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.545355841
Short name T867
Test name
Test status
Simulation time 185592326 ps
CPU time 3.6 seconds
Started Jun 02 03:17:18 PM PDT 24
Finished Jun 02 03:17:22 PM PDT 24
Peak memory 218896 kb
Host smart-1473bb36-7f84-449a-8e9d-a6f23c0d1d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545355841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.545355841
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.616869697
Short name T947
Test name
Test status
Simulation time 578711529 ps
CPU time 9.52 seconds
Started Jun 02 03:17:19 PM PDT 24
Finished Jun 02 03:17:29 PM PDT 24
Peak memory 233808 kb
Host smart-e0a0e3d3-ea24-4535-ba0e-52a50e0f59a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616869697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.616869697
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.103428043
Short name T329
Test name
Test status
Simulation time 16428965 ps
CPU time 0.84 seconds
Started Jun 02 03:17:20 PM PDT 24
Finished Jun 02 03:17:21 PM PDT 24
Peak memory 206308 kb
Host smart-3b73716e-c7db-45f9-af8e-0798ac917e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103428043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.103428043
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1544934970
Short name T290
Test name
Test status
Simulation time 4909909102 ps
CPU time 50.43 seconds
Started Jun 02 03:17:25 PM PDT 24
Finished Jun 02 03:18:17 PM PDT 24
Peak memory 252856 kb
Host smart-61ba4a70-2969-41da-9055-f1c59ce91ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544934970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1544934970
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1232236693
Short name T695
Test name
Test status
Simulation time 3810359229 ps
CPU time 31.66 seconds
Started Jun 02 03:17:24 PM PDT 24
Finished Jun 02 03:17:57 PM PDT 24
Peak memory 217388 kb
Host smart-8949e379-794e-4cdf-acbc-bec61ae152fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232236693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1232236693
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3375010320
Short name T18
Test name
Test status
Simulation time 298199170844 ps
CPU time 167.33 seconds
Started Jun 02 03:17:26 PM PDT 24
Finished Jun 02 03:20:15 PM PDT 24
Peak memory 238980 kb
Host smart-d6e6ad61-db49-46d1-90a2-f4a453ba993e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375010320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3375010320
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2668445355
Short name T427
Test name
Test status
Simulation time 1710872548 ps
CPU time 15.77 seconds
Started Jun 02 03:17:21 PM PDT 24
Finished Jun 02 03:17:37 PM PDT 24
Peak memory 218528 kb
Host smart-b32a4b83-a867-4308-852d-018034daecf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668445355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2668445355
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3814604036
Short name T750
Test name
Test status
Simulation time 9568181683 ps
CPU time 12.01 seconds
Started Jun 02 03:17:20 PM PDT 24
Finished Jun 02 03:17:32 PM PDT 24
Peak memory 218760 kb
Host smart-88065b0a-4221-4075-80a9-65458bf9406a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814604036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3814604036
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.371102320
Short name T858
Test name
Test status
Simulation time 14357267658 ps
CPU time 11.71 seconds
Started Jun 02 03:17:18 PM PDT 24
Finished Jun 02 03:17:30 PM PDT 24
Peak memory 232624 kb
Host smart-0ee0aa33-5b6e-4a48-ab61-440a80e168ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371102320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.371102320
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1052368621
Short name T615
Test name
Test status
Simulation time 411387799 ps
CPU time 3.77 seconds
Started Jun 02 03:17:19 PM PDT 24
Finished Jun 02 03:17:23 PM PDT 24
Peak memory 233648 kb
Host smart-891c94fc-ca46-4a62-a4c4-5421f57dd3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052368621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1052368621
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3733325752
Short name T871
Test name
Test status
Simulation time 191543764 ps
CPU time 4 seconds
Started Jun 02 03:17:26 PM PDT 24
Finished Jun 02 03:17:31 PM PDT 24
Peak memory 220204 kb
Host smart-1a708b6b-d4f4-443d-b36a-b3d349db14d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3733325752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3733325752
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.78124331
Short name T133
Test name
Test status
Simulation time 8937051241 ps
CPU time 34.07 seconds
Started Jun 02 03:17:25 PM PDT 24
Finished Jun 02 03:18:00 PM PDT 24
Peak memory 238224 kb
Host smart-23ddb9e2-61fc-41c6-b759-07e14a3ac94d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78124331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress
_all.78124331
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3164440853
Short name T631
Test name
Test status
Simulation time 1546400483 ps
CPU time 19.07 seconds
Started Jun 02 03:17:20 PM PDT 24
Finished Jun 02 03:17:39 PM PDT 24
Peak memory 216084 kb
Host smart-5bccd3a7-a12a-4252-907b-b723169e5481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164440853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3164440853
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3020655603
Short name T386
Test name
Test status
Simulation time 10462780 ps
CPU time 0.72 seconds
Started Jun 02 03:17:19 PM PDT 24
Finished Jun 02 03:17:20 PM PDT 24
Peak memory 205500 kb
Host smart-458f677d-2c8e-453b-844a-4b068b580bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020655603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3020655603
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2211972944
Short name T488
Test name
Test status
Simulation time 16095654 ps
CPU time 1.07 seconds
Started Jun 02 03:17:22 PM PDT 24
Finished Jun 02 03:17:23 PM PDT 24
Peak memory 207912 kb
Host smart-c33de79c-d147-4c44-8f2b-d6b4713d53fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211972944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2211972944
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2267377579
Short name T371
Test name
Test status
Simulation time 71972047 ps
CPU time 0.95 seconds
Started Jun 02 03:17:20 PM PDT 24
Finished Jun 02 03:17:22 PM PDT 24
Peak memory 205668 kb
Host smart-b4f85f63-c1ee-455f-a803-1a33bd03c9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267377579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2267377579
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2871266018
Short name T894
Test name
Test status
Simulation time 841018059 ps
CPU time 2.42 seconds
Started Jun 02 03:17:19 PM PDT 24
Finished Jun 02 03:17:22 PM PDT 24
Peak memory 216260 kb
Host smart-a25af061-6dac-4dbc-89fc-8a6122175224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871266018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2871266018
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2652812921
Short name T545
Test name
Test status
Simulation time 11430635 ps
CPU time 0.77 seconds
Started Jun 02 03:17:25 PM PDT 24
Finished Jun 02 03:17:27 PM PDT 24
Peak memory 204820 kb
Host smart-11e5f1d5-8e93-44af-952a-226a566b1149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652812921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2652812921
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1842876595
Short name T944
Test name
Test status
Simulation time 583417993 ps
CPU time 5.1 seconds
Started Jun 02 03:17:23 PM PDT 24
Finished Jun 02 03:17:29 PM PDT 24
Peak memory 234760 kb
Host smart-16d6c67c-d9de-417f-95f4-f31e553fdc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842876595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1842876595
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2843899748
Short name T903
Test name
Test status
Simulation time 61120807 ps
CPU time 0.74 seconds
Started Jun 02 03:17:25 PM PDT 24
Finished Jun 02 03:17:27 PM PDT 24
Peak memory 205408 kb
Host smart-85c073bf-d51a-45c1-9c16-d07b55f1b247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843899748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2843899748
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3180114986
Short name T964
Test name
Test status
Simulation time 89012942991 ps
CPU time 149.09 seconds
Started Jun 02 03:17:27 PM PDT 24
Finished Jun 02 03:19:57 PM PDT 24
Peak memory 248992 kb
Host smart-e917cebb-a4e5-4509-9842-7c70e49ff37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180114986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3180114986
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.158278562
Short name T226
Test name
Test status
Simulation time 14774062428 ps
CPU time 160.96 seconds
Started Jun 02 03:17:24 PM PDT 24
Finished Jun 02 03:20:06 PM PDT 24
Peak memory 257228 kb
Host smart-511863e5-09fe-418e-bfa9-959f0e3dde5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158278562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.158278562
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3146442837
Short name T890
Test name
Test status
Simulation time 1493419265 ps
CPU time 18.92 seconds
Started Jun 02 03:17:27 PM PDT 24
Finished Jun 02 03:17:47 PM PDT 24
Peak memory 233404 kb
Host smart-1e2eb2b1-8714-4988-bc62-cfbd17099b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146442837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3146442837
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2583469870
Short name T450
Test name
Test status
Simulation time 2320503253 ps
CPU time 8.94 seconds
Started Jun 02 03:17:28 PM PDT 24
Finished Jun 02 03:17:38 PM PDT 24
Peak memory 224392 kb
Host smart-f144388b-b1c5-4b77-821f-2c1c1d41d9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583469870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2583469870
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3417970361
Short name T422
Test name
Test status
Simulation time 5760568558 ps
CPU time 16.86 seconds
Started Jun 02 03:17:23 PM PDT 24
Finished Jun 02 03:17:41 PM PDT 24
Peak memory 218436 kb
Host smart-a5c71e59-b1b5-491b-8a0f-4b8d3d53fc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417970361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3417970361
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1739200775
Short name T891
Test name
Test status
Simulation time 2285413025 ps
CPU time 3.72 seconds
Started Jun 02 03:17:23 PM PDT 24
Finished Jun 02 03:17:27 PM PDT 24
Peak memory 233488 kb
Host smart-9d4b49d4-7331-40f5-8e61-be79fde0d542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739200775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1739200775
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3662076151
Short name T263
Test name
Test status
Simulation time 1006186160 ps
CPU time 5.22 seconds
Started Jun 02 03:17:25 PM PDT 24
Finished Jun 02 03:17:32 PM PDT 24
Peak memory 238328 kb
Host smart-15c1aa12-aa8f-46fa-bbd0-f93f457c2892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662076151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3662076151
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1447757472
Short name T497
Test name
Test status
Simulation time 2663084525 ps
CPU time 8.7 seconds
Started Jun 02 03:17:25 PM PDT 24
Finished Jun 02 03:17:35 PM PDT 24
Peak memory 223136 kb
Host smart-87b59a71-5ad2-490d-aa7e-3c7d7c69b92b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1447757472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1447757472
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3280772318
Short name T961
Test name
Test status
Simulation time 2201452620 ps
CPU time 52.74 seconds
Started Jun 02 03:17:25 PM PDT 24
Finished Jun 02 03:18:19 PM PDT 24
Peak memory 238420 kb
Host smart-f1ca8af1-e1eb-48f5-a47e-ad8d8680cb94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280772318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3280772318
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3106268810
Short name T918
Test name
Test status
Simulation time 11985118724 ps
CPU time 37.72 seconds
Started Jun 02 03:17:29 PM PDT 24
Finished Jun 02 03:18:07 PM PDT 24
Peak memory 216236 kb
Host smart-140a0dab-4dc5-42de-bd0b-e0b3a2bbb7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106268810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3106268810
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.4088166887
Short name T774
Test name
Test status
Simulation time 2126830414 ps
CPU time 4.78 seconds
Started Jun 02 03:17:28 PM PDT 24
Finished Jun 02 03:17:33 PM PDT 24
Peak memory 215120 kb
Host smart-dc167c53-574b-4dda-8cd0-ac92ca08bcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088166887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.4088166887
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2837064690
Short name T383
Test name
Test status
Simulation time 294108525 ps
CPU time 5.88 seconds
Started Jun 02 03:17:24 PM PDT 24
Finished Jun 02 03:17:30 PM PDT 24
Peak memory 215984 kb
Host smart-9b8ca4c2-a795-4bda-bd36-71e62f069c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837064690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2837064690
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2567613575
Short name T314
Test name
Test status
Simulation time 256953941 ps
CPU time 0.9 seconds
Started Jun 02 03:17:28 PM PDT 24
Finished Jun 02 03:17:29 PM PDT 24
Peak memory 205024 kb
Host smart-9c3a3477-3db5-4d8b-aef2-ac4ab1791274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567613575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2567613575
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.667407906
Short name T682
Test name
Test status
Simulation time 99953332 ps
CPU time 2.72 seconds
Started Jun 02 03:17:24 PM PDT 24
Finished Jun 02 03:17:27 PM PDT 24
Peak memory 233708 kb
Host smart-df26edc7-1d2a-44c5-a97c-28910ad181aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667407906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.667407906
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.426401551
Short name T3
Test name
Test status
Simulation time 46716126 ps
CPU time 0.72 seconds
Started Jun 02 03:17:34 PM PDT 24
Finished Jun 02 03:17:36 PM PDT 24
Peak memory 205392 kb
Host smart-b87e7c88-8256-47dc-b6f1-ade405615807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426401551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.426401551
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3397751876
Short name T638
Test name
Test status
Simulation time 2566279409 ps
CPU time 8.98 seconds
Started Jun 02 03:17:25 PM PDT 24
Finished Jun 02 03:17:35 PM PDT 24
Peak memory 221728 kb
Host smart-5a1317dd-5310-4fa4-a151-83331adc69fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397751876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3397751876
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4080407826
Short name T592
Test name
Test status
Simulation time 36539020 ps
CPU time 0.79 seconds
Started Jun 02 03:17:25 PM PDT 24
Finished Jun 02 03:17:27 PM PDT 24
Peak memory 206748 kb
Host smart-4d0db3c9-1722-40c9-893d-5ba22eebec77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080407826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4080407826
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2546344170
Short name T726
Test name
Test status
Simulation time 2116951796 ps
CPU time 37.39 seconds
Started Jun 02 03:17:33 PM PDT 24
Finished Jun 02 03:18:11 PM PDT 24
Peak memory 248968 kb
Host smart-bda2dd95-94dc-4045-9edf-9c0295edbb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546344170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2546344170
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3817180778
Short name T272
Test name
Test status
Simulation time 554216179040 ps
CPU time 728.9 seconds
Started Jun 02 03:17:33 PM PDT 24
Finished Jun 02 03:29:43 PM PDT 24
Peak memory 263676 kb
Host smart-f7d8bdda-5b4a-4a0e-b767-535fa09cca24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817180778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3817180778
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2621941798
Short name T866
Test name
Test status
Simulation time 57094755547 ps
CPU time 281.42 seconds
Started Jun 02 03:17:34 PM PDT 24
Finished Jun 02 03:22:16 PM PDT 24
Peak memory 251132 kb
Host smart-2f923b40-23f8-4e41-842f-8f477c73ea05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621941798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2621941798
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3097825186
Short name T438
Test name
Test status
Simulation time 1960358611 ps
CPU time 24.82 seconds
Started Jun 02 03:17:27 PM PDT 24
Finished Jun 02 03:17:53 PM PDT 24
Peak memory 235536 kb
Host smart-5439c997-d3a3-468d-b312-68ca403c0f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097825186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3097825186
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2937947622
Short name T624
Test name
Test status
Simulation time 193580450 ps
CPU time 4.07 seconds
Started Jun 02 03:17:27 PM PDT 24
Finished Jun 02 03:17:32 PM PDT 24
Peak memory 218696 kb
Host smart-002f7d60-96ef-4991-bae5-727bf00e3665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937947622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2937947622
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1101736159
Short name T378
Test name
Test status
Simulation time 158425251 ps
CPU time 3.94 seconds
Started Jun 02 03:17:24 PM PDT 24
Finished Jun 02 03:17:28 PM PDT 24
Peak memory 234296 kb
Host smart-a02064ce-efc4-45cd-bbf5-e49bb6a1de99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101736159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1101736159
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3175039539
Short name T772
Test name
Test status
Simulation time 24354716965 ps
CPU time 37.56 seconds
Started Jun 02 03:17:27 PM PDT 24
Finished Jun 02 03:18:06 PM PDT 24
Peak memory 233236 kb
Host smart-d65e153d-6886-4937-bce8-cabbe4147742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175039539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3175039539
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.57253181
Short name T760
Test name
Test status
Simulation time 42250266 ps
CPU time 2.39 seconds
Started Jun 02 03:17:26 PM PDT 24
Finished Jun 02 03:17:29 PM PDT 24
Peak memory 232592 kb
Host smart-24869573-91f8-4684-81c2-2d85b7f97a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57253181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.57253181
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2797119616
Short name T381
Test name
Test status
Simulation time 501319424 ps
CPU time 3.33 seconds
Started Jun 02 03:17:31 PM PDT 24
Finished Jun 02 03:17:35 PM PDT 24
Peak memory 219848 kb
Host smart-94709dbf-497e-44ef-8b1d-cf411076c3cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2797119616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2797119616
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3403208156
Short name T963
Test name
Test status
Simulation time 3124105734 ps
CPU time 69.12 seconds
Started Jun 02 03:17:34 PM PDT 24
Finished Jun 02 03:18:43 PM PDT 24
Peak memory 255392 kb
Host smart-fa30e269-532b-4bb0-8e31-9ef9af7032cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403208156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3403208156
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1605174948
Short name T945
Test name
Test status
Simulation time 3100673182 ps
CPU time 28.77 seconds
Started Jun 02 03:17:24 PM PDT 24
Finished Jun 02 03:17:54 PM PDT 24
Peak memory 218768 kb
Host smart-48508cc7-1938-47d3-b6c9-27b85439c5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605174948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1605174948
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.4169578326
Short name T478
Test name
Test status
Simulation time 2922063024 ps
CPU time 1.98 seconds
Started Jun 02 03:17:24 PM PDT 24
Finished Jun 02 03:17:27 PM PDT 24
Peak memory 207696 kb
Host smart-06467ac9-de1c-4482-ba3e-6ea3adc11853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169578326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.4169578326
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.634856554
Short name T382
Test name
Test status
Simulation time 73736844 ps
CPU time 0.9 seconds
Started Jun 02 03:17:24 PM PDT 24
Finished Jun 02 03:17:26 PM PDT 24
Peak memory 206392 kb
Host smart-7ffe1720-f564-4b4c-94af-ef0b97a8e9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634856554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.634856554
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.400954669
Short name T893
Test name
Test status
Simulation time 32064217 ps
CPU time 0.69 seconds
Started Jun 02 03:17:25 PM PDT 24
Finished Jun 02 03:17:27 PM PDT 24
Peak memory 205408 kb
Host smart-23c8ca70-e90b-481e-a4cd-454b8d1dc11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400954669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.400954669
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3679720434
Short name T55
Test name
Test status
Simulation time 31131402019 ps
CPU time 7.61 seconds
Started Jun 02 03:17:26 PM PDT 24
Finished Jun 02 03:17:35 PM PDT 24
Peak memory 218916 kb
Host smart-f9409a36-5436-4a39-9545-bd5544e1c2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679720434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3679720434
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2898138079
Short name T902
Test name
Test status
Simulation time 17176096 ps
CPU time 0.73 seconds
Started Jun 02 03:17:31 PM PDT 24
Finished Jun 02 03:17:32 PM PDT 24
Peak memory 205732 kb
Host smart-a025ae71-5076-4af1-b902-77b2ee99f80d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898138079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2898138079
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2908993291
Short name T98
Test name
Test status
Simulation time 160818119 ps
CPU time 2.85 seconds
Started Jun 02 03:17:34 PM PDT 24
Finished Jun 02 03:17:38 PM PDT 24
Peak memory 233708 kb
Host smart-7f124232-4f81-43cc-8ca9-80d9644bea32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908993291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2908993291
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2236405039
Short name T433
Test name
Test status
Simulation time 13353791 ps
CPU time 0.78 seconds
Started Jun 02 03:17:31 PM PDT 24
Finished Jun 02 03:17:33 PM PDT 24
Peak memory 206748 kb
Host smart-7e88b0bf-9854-4ff7-b7f7-40f1be2cb9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236405039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2236405039
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1478469400
Short name T217
Test name
Test status
Simulation time 1991513577 ps
CPU time 9.41 seconds
Started Jun 02 03:17:32 PM PDT 24
Finished Jun 02 03:17:42 PM PDT 24
Peak memory 234556 kb
Host smart-0b260e44-25f3-4c8e-8083-b2bf8fd82df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478469400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1478469400
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4077204151
Short name T887
Test name
Test status
Simulation time 10819684815 ps
CPU time 64.28 seconds
Started Jun 02 03:17:29 PM PDT 24
Finished Jun 02 03:18:34 PM PDT 24
Peak memory 254956 kb
Host smart-867c7906-7677-4a0e-ae26-38515e9be882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077204151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4077204151
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3463424608
Short name T277
Test name
Test status
Simulation time 4420515688 ps
CPU time 114.49 seconds
Started Jun 02 03:18:02 PM PDT 24
Finished Jun 02 03:19:57 PM PDT 24
Peak memory 254536 kb
Host smart-e5b89228-3459-4c64-b183-c71d82beee84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463424608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3463424608
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1066045696
Short name T554
Test name
Test status
Simulation time 688438937 ps
CPU time 6.41 seconds
Started Jun 02 03:17:31 PM PDT 24
Finished Jun 02 03:17:38 PM PDT 24
Peak memory 240512 kb
Host smart-bb6318fe-c40b-4226-b80e-e099015db444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066045696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1066045696
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3492506401
Short name T572
Test name
Test status
Simulation time 518056058 ps
CPU time 5.98 seconds
Started Jun 02 03:17:31 PM PDT 24
Finished Jun 02 03:17:38 PM PDT 24
Peak memory 218792 kb
Host smart-bb29ebb8-f69e-4b7e-aee8-040a5a26454a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492506401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3492506401
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3452778098
Short name T261
Test name
Test status
Simulation time 27351780318 ps
CPU time 41.29 seconds
Started Jun 02 03:17:32 PM PDT 24
Finished Jun 02 03:18:14 PM PDT 24
Peak memory 227004 kb
Host smart-00254a9f-5072-4493-bb31-a56130e878b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452778098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3452778098
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.487647579
Short name T14
Test name
Test status
Simulation time 180903791 ps
CPU time 4.09 seconds
Started Jun 02 03:17:31 PM PDT 24
Finished Jun 02 03:17:36 PM PDT 24
Peak memory 233496 kb
Host smart-e4552a8b-e51d-4568-95af-1c517039a5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487647579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.487647579
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3869548849
Short name T810
Test name
Test status
Simulation time 360654353 ps
CPU time 3.11 seconds
Started Jun 02 03:17:30 PM PDT 24
Finished Jun 02 03:17:34 PM PDT 24
Peak memory 232580 kb
Host smart-73534837-f53f-4bd3-8e30-85c695247557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869548849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3869548849
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3147236798
Short name T855
Test name
Test status
Simulation time 4623143925 ps
CPU time 10.79 seconds
Started Jun 02 03:17:31 PM PDT 24
Finished Jun 02 03:17:43 PM PDT 24
Peak memory 221672 kb
Host smart-a27af544-fe40-4d0b-ab9b-9fa7c16aa811
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3147236798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3147236798
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1776595403
Short name T784
Test name
Test status
Simulation time 11060861032 ps
CPU time 33.6 seconds
Started Jun 02 03:17:29 PM PDT 24
Finished Jun 02 03:18:03 PM PDT 24
Peak memory 216260 kb
Host smart-cc29ce3e-60ad-4d05-aa2f-9d36f9177069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776595403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1776595403
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1015356080
Short name T16
Test name
Test status
Simulation time 25088588880 ps
CPU time 16.31 seconds
Started Jun 02 03:17:32 PM PDT 24
Finished Jun 02 03:17:49 PM PDT 24
Peak memory 216080 kb
Host smart-fb20c6e6-259f-476f-8e87-5c3e085d8dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015356080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1015356080
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2899908102
Short name T334
Test name
Test status
Simulation time 377840589 ps
CPU time 3.5 seconds
Started Jun 02 03:17:31 PM PDT 24
Finished Jun 02 03:17:35 PM PDT 24
Peak memory 216184 kb
Host smart-df807f87-251b-4825-8acb-9177b6873572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899908102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2899908102
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3083980853
Short name T424
Test name
Test status
Simulation time 64031836 ps
CPU time 0.83 seconds
Started Jun 02 03:17:32 PM PDT 24
Finished Jun 02 03:17:33 PM PDT 24
Peak memory 205648 kb
Host smart-ebf3f994-832d-4dda-bd99-9a40baee2378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083980853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3083980853
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3676408571
Short name T219
Test name
Test status
Simulation time 4652494749 ps
CPU time 3.9 seconds
Started Jun 02 03:17:35 PM PDT 24
Finished Jun 02 03:17:39 PM PDT 24
Peak memory 219640 kb
Host smart-abf53870-3a73-4d95-a197-0d898cbf93ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676408571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3676408571
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2263606708
Short name T330
Test name
Test status
Simulation time 50236557 ps
CPU time 0.75 seconds
Started Jun 02 03:17:38 PM PDT 24
Finished Jun 02 03:17:39 PM PDT 24
Peak memory 204808 kb
Host smart-2898f45b-01d5-4d67-a43c-edeb4cea2d1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263606708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2263606708
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1092335317
Short name T266
Test name
Test status
Simulation time 762130872 ps
CPU time 10.55 seconds
Started Jun 02 03:17:37 PM PDT 24
Finished Jun 02 03:17:48 PM PDT 24
Peak memory 218684 kb
Host smart-4c3c23f7-c676-4dbd-a06b-e46965075994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092335317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1092335317
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.872803175
Short name T443
Test name
Test status
Simulation time 33750433 ps
CPU time 0.79 seconds
Started Jun 02 03:17:32 PM PDT 24
Finished Jun 02 03:17:33 PM PDT 24
Peak memory 206720 kb
Host smart-6c3a720d-d583-4fab-8ea8-81fa18197fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872803175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.872803175
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2731709897
Short name T236
Test name
Test status
Simulation time 3178604767 ps
CPU time 75.9 seconds
Started Jun 02 03:17:36 PM PDT 24
Finished Jun 02 03:18:52 PM PDT 24
Peak memory 253332 kb
Host smart-38625de7-f693-4cc6-b838-a0da8bfb6964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731709897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2731709897
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2881860454
Short name T234
Test name
Test status
Simulation time 27213734204 ps
CPU time 196.39 seconds
Started Jun 02 03:17:37 PM PDT 24
Finished Jun 02 03:20:54 PM PDT 24
Peak memory 240832 kb
Host smart-882f1477-e2c5-43fb-bd5a-bb6c87f35b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881860454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2881860454
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.823933641
Short name T302
Test name
Test status
Simulation time 12771970161 ps
CPU time 81.29 seconds
Started Jun 02 03:17:37 PM PDT 24
Finished Jun 02 03:18:59 PM PDT 24
Peak memory 237952 kb
Host smart-524bd858-7d40-45ec-ac2b-d2a1a96d204a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823933641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.823933641
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.101215708
Short name T264
Test name
Test status
Simulation time 3410488587 ps
CPU time 8.83 seconds
Started Jun 02 03:17:38 PM PDT 24
Finished Jun 02 03:17:48 PM PDT 24
Peak memory 233664 kb
Host smart-d052733c-622e-46fa-99e0-240fcd16ae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101215708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.101215708
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3588837288
Short name T699
Test name
Test status
Simulation time 5314981798 ps
CPU time 12.74 seconds
Started Jun 02 03:17:40 PM PDT 24
Finished Jun 02 03:17:53 PM PDT 24
Peak memory 232632 kb
Host smart-95e91c9c-d1b6-4e4f-b386-a5619db5ef2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588837288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3588837288
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2402529005
Short name T227
Test name
Test status
Simulation time 941883329 ps
CPU time 7.07 seconds
Started Jun 02 03:17:31 PM PDT 24
Finished Jun 02 03:17:39 PM PDT 24
Peak memory 233008 kb
Host smart-f7fcfb17-1ce5-472b-95e5-7bf103127565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402529005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2402529005
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.23311902
Short name T807
Test name
Test status
Simulation time 4545615899 ps
CPU time 12.36 seconds
Started Jun 02 03:17:33 PM PDT 24
Finished Jun 02 03:17:46 PM PDT 24
Peak memory 218800 kb
Host smart-50756649-2c63-4d3b-a39f-936a1608975e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23311902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.23311902
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3561810740
Short name T146
Test name
Test status
Simulation time 189754521 ps
CPU time 4.31 seconds
Started Jun 02 03:17:37 PM PDT 24
Finished Jun 02 03:17:42 PM PDT 24
Peak memory 220008 kb
Host smart-def8499d-0eb9-4fae-9fae-cddd16a8a43c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3561810740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3561810740
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.805858622
Short name T134
Test name
Test status
Simulation time 9241778051 ps
CPU time 58.89 seconds
Started Jun 02 03:17:38 PM PDT 24
Finished Jun 02 03:18:37 PM PDT 24
Peak memory 254492 kb
Host smart-0b19b564-fbcb-423f-9195-5d56cae80671
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805858622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.805858622
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.377884475
Short name T625
Test name
Test status
Simulation time 2666194534 ps
CPU time 4.79 seconds
Started Jun 02 03:17:31 PM PDT 24
Finished Jun 02 03:17:36 PM PDT 24
Peak memory 219720 kb
Host smart-a30f240b-6b5b-43ab-8187-ffacc096b838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377884475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.377884475
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3669269332
Short name T838
Test name
Test status
Simulation time 2919789595 ps
CPU time 7.2 seconds
Started Jun 02 03:17:32 PM PDT 24
Finished Jun 02 03:17:40 PM PDT 24
Peak memory 216188 kb
Host smart-59087cde-6a9b-4e9a-8047-caf04114b926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669269332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3669269332
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1239236442
Short name T628
Test name
Test status
Simulation time 384638788 ps
CPU time 1.41 seconds
Started Jun 02 03:17:33 PM PDT 24
Finished Jun 02 03:17:35 PM PDT 24
Peak memory 216172 kb
Host smart-8ad83482-bf97-431e-a42b-86ba239bf9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239236442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1239236442
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2599892462
Short name T410
Test name
Test status
Simulation time 10765251 ps
CPU time 0.7 seconds
Started Jun 02 03:17:34 PM PDT 24
Finished Jun 02 03:17:36 PM PDT 24
Peak memory 205444 kb
Host smart-ed2b16cd-b7eb-45f4-9147-1405f7e4678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599892462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2599892462
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1422417240
Short name T940
Test name
Test status
Simulation time 397640814 ps
CPU time 3.52 seconds
Started Jun 02 03:17:38 PM PDT 24
Finished Jun 02 03:17:42 PM PDT 24
Peak memory 224328 kb
Host smart-3377fa4f-b00c-4c5f-a546-756574359d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422417240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1422417240
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2470136638
Short name T59
Test name
Test status
Simulation time 14741650 ps
CPU time 0.72 seconds
Started Jun 02 03:17:43 PM PDT 24
Finished Jun 02 03:17:45 PM PDT 24
Peak memory 204920 kb
Host smart-57585250-1a67-45f0-a970-6cfff2ba0004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470136638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2470136638
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1773649143
Short name T646
Test name
Test status
Simulation time 41202773 ps
CPU time 2.57 seconds
Started Jun 02 03:17:38 PM PDT 24
Finished Jun 02 03:17:41 PM PDT 24
Peak memory 233980 kb
Host smart-1c87cfae-8bec-402e-82ed-a1eec8ba3459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773649143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1773649143
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2345038497
Short name T460
Test name
Test status
Simulation time 19453326 ps
CPU time 0.74 seconds
Started Jun 02 03:17:40 PM PDT 24
Finished Jun 02 03:17:41 PM PDT 24
Peak memory 205712 kb
Host smart-e4e6c73a-0ecc-45b9-8571-21f415b90f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345038497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2345038497
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1702488550
Short name T643
Test name
Test status
Simulation time 411165081 ps
CPU time 11.13 seconds
Started Jun 02 03:17:39 PM PDT 24
Finished Jun 02 03:17:51 PM PDT 24
Peak memory 240764 kb
Host smart-175f7123-4f2c-42ce-878a-ce5ceb0ad6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702488550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1702488550
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2069748908
Short name T221
Test name
Test status
Simulation time 12023722809 ps
CPU time 125.81 seconds
Started Jun 02 03:17:41 PM PDT 24
Finished Jun 02 03:19:47 PM PDT 24
Peak memory 249188 kb
Host smart-d2f75bb7-43f7-4c5f-bba5-75bf8c7b170b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069748908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2069748908
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2163467645
Short name T42
Test name
Test status
Simulation time 484075501 ps
CPU time 4.9 seconds
Started Jun 02 03:17:36 PM PDT 24
Finished Jun 02 03:17:41 PM PDT 24
Peak memory 224308 kb
Host smart-433bdefc-0004-4ed3-a66d-db56951d4c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163467645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2163467645
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.345402992
Short name T375
Test name
Test status
Simulation time 1066543792 ps
CPU time 7.82 seconds
Started Jun 02 03:17:38 PM PDT 24
Finished Jun 02 03:17:46 PM PDT 24
Peak memory 233896 kb
Host smart-8e4ff9a2-4f53-4581-b718-0835cd78345f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345402992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.345402992
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1308270650
Short name T163
Test name
Test status
Simulation time 101292311 ps
CPU time 3.76 seconds
Started Jun 02 03:17:38 PM PDT 24
Finished Jun 02 03:17:42 PM PDT 24
Peak memory 234396 kb
Host smart-ec82ef54-56c7-4d50-a21a-e84a495045f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308270650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1308270650
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1868373992
Short name T737
Test name
Test status
Simulation time 4290621960 ps
CPU time 5.6 seconds
Started Jun 02 03:17:39 PM PDT 24
Finished Jun 02 03:17:45 PM PDT 24
Peak memory 235952 kb
Host smart-468aae0c-3f68-4d2e-b0e6-2277d9e6ac5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868373992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1868373992
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1864121226
Short name T437
Test name
Test status
Simulation time 11732608037 ps
CPU time 17.05 seconds
Started Jun 02 03:17:38 PM PDT 24
Finished Jun 02 03:17:55 PM PDT 24
Peak memory 233620 kb
Host smart-20cda9a2-5a3f-4625-a6b2-55ddedd43f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864121226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1864121226
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3136467775
Short name T948
Test name
Test status
Simulation time 143365247 ps
CPU time 4.37 seconds
Started Jun 02 03:17:39 PM PDT 24
Finished Jun 02 03:17:44 PM PDT 24
Peak memory 222940 kb
Host smart-87cceaf5-973b-4794-969f-e15a19b1b80c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3136467775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3136467775
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.4253386055
Short name T731
Test name
Test status
Simulation time 169002672 ps
CPU time 1 seconds
Started Jun 02 03:17:44 PM PDT 24
Finished Jun 02 03:17:45 PM PDT 24
Peak memory 207056 kb
Host smart-e170b672-3aa2-430d-a6a1-a6cbaa053118
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253386055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.4253386055
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1428922534
Short name T570
Test name
Test status
Simulation time 12857308581 ps
CPU time 33.15 seconds
Started Jun 02 03:17:38 PM PDT 24
Finished Jun 02 03:18:12 PM PDT 24
Peak memory 216288 kb
Host smart-e015e417-15d5-4121-a8b8-47d8aa6854e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428922534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1428922534
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3499947118
Short name T388
Test name
Test status
Simulation time 5039790327 ps
CPU time 15.16 seconds
Started Jun 02 03:17:38 PM PDT 24
Finished Jun 02 03:17:54 PM PDT 24
Peak memory 216184 kb
Host smart-dcef2837-317a-42df-afdb-5d30ab4debbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499947118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3499947118
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1064832026
Short name T636
Test name
Test status
Simulation time 343936118 ps
CPU time 2.64 seconds
Started Jun 02 03:17:37 PM PDT 24
Finished Jun 02 03:17:41 PM PDT 24
Peak memory 216184 kb
Host smart-f1fdc48f-1389-47ad-9a26-c130e2e6ab39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064832026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1064832026
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.4093793617
Short name T651
Test name
Test status
Simulation time 91807916 ps
CPU time 0.84 seconds
Started Jun 02 03:17:40 PM PDT 24
Finished Jun 02 03:17:41 PM PDT 24
Peak memory 205620 kb
Host smart-8ee87daf-98ca-43bf-9e38-40c7a1ee5925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093793617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4093793617
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2411445926
Short name T848
Test name
Test status
Simulation time 231905025 ps
CPU time 3.04 seconds
Started Jun 02 03:17:38 PM PDT 24
Finished Jun 02 03:17:42 PM PDT 24
Peak memory 224408 kb
Host smart-e0a98a50-5e04-4043-9c54-3a798b7aebfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411445926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2411445926
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.682375155
Short name T453
Test name
Test status
Simulation time 97237037 ps
CPU time 0.73 seconds
Started Jun 02 03:17:44 PM PDT 24
Finished Jun 02 03:17:45 PM PDT 24
Peak memory 205392 kb
Host smart-56041ed4-ce94-40ac-ae94-f106afc945d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682375155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.682375155
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2933101155
Short name T640
Test name
Test status
Simulation time 1927975840 ps
CPU time 16.95 seconds
Started Jun 02 03:17:43 PM PDT 24
Finished Jun 02 03:18:00 PM PDT 24
Peak memory 220132 kb
Host smart-82d8dd3d-e076-4caa-99c6-4a9a3137d852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933101155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2933101155
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4165809731
Short name T321
Test name
Test status
Simulation time 15912490 ps
CPU time 0.84 seconds
Started Jun 02 03:17:45 PM PDT 24
Finished Jun 02 03:17:46 PM PDT 24
Peak memory 205376 kb
Host smart-cb24b386-2204-446f-8ed5-d46a1149a20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165809731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4165809731
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3783943218
Short name T634
Test name
Test status
Simulation time 11196086080 ps
CPU time 81.56 seconds
Started Jun 02 03:17:47 PM PDT 24
Finished Jun 02 03:19:09 PM PDT 24
Peak memory 235364 kb
Host smart-90ae3933-4038-4e2f-a855-547b9fb7752d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783943218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3783943218
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1398243215
Short name T287
Test name
Test status
Simulation time 5980356067 ps
CPU time 75.8 seconds
Started Jun 02 03:17:43 PM PDT 24
Finished Jun 02 03:18:59 PM PDT 24
Peak memory 250496 kb
Host smart-70405f6c-5c6d-4e80-8e4a-d13d5468eb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398243215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1398243215
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2895393846
Short name T752
Test name
Test status
Simulation time 8343471317 ps
CPU time 102.58 seconds
Started Jun 02 03:17:43 PM PDT 24
Finished Jun 02 03:19:26 PM PDT 24
Peak memory 252104 kb
Host smart-81a5a5ab-1a22-40c6-b8f4-8b2ec7fdee65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895393846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2895393846
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.4191243121
Short name T513
Test name
Test status
Simulation time 237053517 ps
CPU time 10.81 seconds
Started Jun 02 03:17:44 PM PDT 24
Finished Jun 02 03:17:56 PM PDT 24
Peak memory 240816 kb
Host smart-1aab7cb8-5f45-4d5c-8c78-48f3e84f1c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191243121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.4191243121
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1574428978
Short name T611
Test name
Test status
Simulation time 651951915 ps
CPU time 9.78 seconds
Started Jun 02 03:17:44 PM PDT 24
Finished Jun 02 03:17:54 PM PDT 24
Peak memory 236032 kb
Host smart-982b931d-7d6c-4c70-accc-25793924cc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574428978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1574428978
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1295454555
Short name T921
Test name
Test status
Simulation time 4360205983 ps
CPU time 37.48 seconds
Started Jun 02 03:17:43 PM PDT 24
Finished Jun 02 03:18:20 PM PDT 24
Peak memory 222892 kb
Host smart-9281865b-e244-4529-9931-55b7421b88c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295454555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1295454555
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4062462143
Short name T408
Test name
Test status
Simulation time 1720027457 ps
CPU time 6 seconds
Started Jun 02 03:17:45 PM PDT 24
Finished Jun 02 03:17:51 PM PDT 24
Peak memory 233564 kb
Host smart-c46c78bd-0cb7-4c22-baa6-f57af984070d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062462143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4062462143
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3430561383
Short name T816
Test name
Test status
Simulation time 184735990 ps
CPU time 2.27 seconds
Started Jun 02 03:17:44 PM PDT 24
Finished Jun 02 03:17:47 PM PDT 24
Peak memory 220796 kb
Host smart-b4728994-9db1-4726-905e-e945bf8a09a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430561383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3430561383
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1574071892
Short name T769
Test name
Test status
Simulation time 1095342491 ps
CPU time 7.88 seconds
Started Jun 02 03:17:44 PM PDT 24
Finished Jun 02 03:17:52 PM PDT 24
Peak memory 218968 kb
Host smart-232385e9-879c-4107-b950-02ece798f5d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1574071892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1574071892
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.235139627
Short name T454
Test name
Test status
Simulation time 902567248 ps
CPU time 8.78 seconds
Started Jun 02 03:17:43 PM PDT 24
Finished Jun 02 03:17:52 PM PDT 24
Peak memory 237168 kb
Host smart-57e0e94f-80a9-4bf9-a596-4be9e4dbc20f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235139627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.235139627
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1443576038
Short name T852
Test name
Test status
Simulation time 2160771797 ps
CPU time 3.94 seconds
Started Jun 02 03:17:45 PM PDT 24
Finished Jun 02 03:17:50 PM PDT 24
Peak memory 216204 kb
Host smart-d037d581-950a-4729-96a3-b74c842d6263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443576038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1443576038
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.891615002
Short name T883
Test name
Test status
Simulation time 2519486961 ps
CPU time 6.97 seconds
Started Jun 02 03:17:44 PM PDT 24
Finished Jun 02 03:17:52 PM PDT 24
Peak memory 216176 kb
Host smart-822497e6-78a1-4fc4-9e22-073e1f6fbcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891615002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.891615002
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2071444589
Short name T906
Test name
Test status
Simulation time 33400596 ps
CPU time 0.82 seconds
Started Jun 02 03:17:43 PM PDT 24
Finished Jun 02 03:17:44 PM PDT 24
Peak memory 206776 kb
Host smart-91063971-d993-4e85-a148-527c59b3e3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071444589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2071444589
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3079121767
Short name T577
Test name
Test status
Simulation time 50232368 ps
CPU time 0.83 seconds
Started Jun 02 03:17:44 PM PDT 24
Finished Jun 02 03:17:45 PM PDT 24
Peak memory 205548 kb
Host smart-5b21d986-cc00-49b7-959b-f32b3b11d7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079121767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3079121767
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2463533241
Short name T199
Test name
Test status
Simulation time 28936409380 ps
CPU time 26.19 seconds
Started Jun 02 03:17:43 PM PDT 24
Finished Jun 02 03:18:10 PM PDT 24
Peak memory 229624 kb
Host smart-cc37b444-28ac-4bd0-8a0f-df0d8db6b946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463533241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2463533241
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2140448762
Short name T952
Test name
Test status
Simulation time 46789982 ps
CPU time 0.72 seconds
Started Jun 02 03:17:50 PM PDT 24
Finished Jun 02 03:17:51 PM PDT 24
Peak memory 205380 kb
Host smart-e0cd67d2-39e4-4ab6-bddd-8511f40eeb7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140448762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2140448762
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2850085800
Short name T895
Test name
Test status
Simulation time 30382631 ps
CPU time 2.49 seconds
Started Jun 02 03:17:48 PM PDT 24
Finished Jun 02 03:17:51 PM PDT 24
Peak memory 221472 kb
Host smart-83a8b2b7-c7bc-46bc-a14b-8dfa6468bbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850085800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2850085800
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3666395348
Short name T568
Test name
Test status
Simulation time 15297530 ps
CPU time 0.76 seconds
Started Jun 02 03:17:47 PM PDT 24
Finished Jun 02 03:17:48 PM PDT 24
Peak memory 205696 kb
Host smart-2887f8c8-ce50-4e84-9213-5730ee4e54c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666395348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3666395348
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1597607646
Short name T416
Test name
Test status
Simulation time 11582134999 ps
CPU time 86.24 seconds
Started Jun 02 03:17:50 PM PDT 24
Finished Jun 02 03:19:17 PM PDT 24
Peak memory 239848 kb
Host smart-5678b123-6b9a-41ff-a523-2a0f4f36af3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597607646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1597607646
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1882181467
Short name T639
Test name
Test status
Simulation time 1683254700 ps
CPU time 27.83 seconds
Started Jun 02 03:17:51 PM PDT 24
Finished Jun 02 03:18:20 PM PDT 24
Peak memory 239636 kb
Host smart-3a52e4ca-640f-40ed-8891-98f6cbfc4e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882181467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1882181467
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1545975165
Short name T269
Test name
Test status
Simulation time 13917506143 ps
CPU time 63 seconds
Started Jun 02 03:17:50 PM PDT 24
Finished Jun 02 03:18:54 PM PDT 24
Peak memory 248632 kb
Host smart-71bdd0dc-2a68-4271-b510-b673857fd275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545975165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1545975165
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3404872937
Short name T305
Test name
Test status
Simulation time 2295791703 ps
CPU time 38.57 seconds
Started Jun 02 03:17:52 PM PDT 24
Finished Jun 02 03:18:31 PM PDT 24
Peak memory 240844 kb
Host smart-91b366f9-fef5-4602-ab8f-6f0b4c539ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404872937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3404872937
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1379687811
Short name T204
Test name
Test status
Simulation time 9375409204 ps
CPU time 22.07 seconds
Started Jun 02 03:17:51 PM PDT 24
Finished Jun 02 03:18:14 PM PDT 24
Peak memory 218432 kb
Host smart-ec619242-c8d5-4961-b8ce-bce2425a7540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379687811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1379687811
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1521086143
Short name T911
Test name
Test status
Simulation time 77592856 ps
CPU time 2.27 seconds
Started Jun 02 03:17:49 PM PDT 24
Finished Jun 02 03:17:52 PM PDT 24
Peak memory 215964 kb
Host smart-3201151c-18b7-450f-9471-a5b805ad4cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521086143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1521086143
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3239760526
Short name T547
Test name
Test status
Simulation time 1327746270 ps
CPU time 4.04 seconds
Started Jun 02 03:17:49 PM PDT 24
Finished Jun 02 03:17:54 PM PDT 24
Peak memory 218776 kb
Host smart-d86dc42d-eacd-45b1-afcd-44cf3d3714fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239760526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3239760526
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.376477335
Short name T824
Test name
Test status
Simulation time 6529871517 ps
CPU time 20.72 seconds
Started Jun 02 03:17:45 PM PDT 24
Finished Jun 02 03:18:06 PM PDT 24
Peak memory 236356 kb
Host smart-c11ee0db-ebcb-4277-8636-617fad4bc409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376477335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.376477335
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4221745041
Short name T868
Test name
Test status
Simulation time 1988056424 ps
CPU time 8.65 seconds
Started Jun 02 03:17:51 PM PDT 24
Finished Jun 02 03:18:01 PM PDT 24
Peak memory 223016 kb
Host smart-ce3291c5-5a9a-480a-8f69-827dab6dc15c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4221745041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4221745041
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3258577845
Short name T446
Test name
Test status
Simulation time 13028344610 ps
CPU time 18.66 seconds
Started Jun 02 03:17:43 PM PDT 24
Finished Jun 02 03:18:02 PM PDT 24
Peak memory 218452 kb
Host smart-1ebf0ca8-cd5a-482a-a9dd-7b1f830ba9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258577845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3258577845
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.736542304
Short name T739
Test name
Test status
Simulation time 13837984084 ps
CPU time 9.2 seconds
Started Jun 02 03:17:43 PM PDT 24
Finished Jun 02 03:17:53 PM PDT 24
Peak memory 216076 kb
Host smart-13dd60e7-8dd8-4b0d-92cb-cd2bc7bd0a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736542304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.736542304
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1625550072
Short name T448
Test name
Test status
Simulation time 10453825 ps
CPU time 0.71 seconds
Started Jun 02 03:17:43 PM PDT 24
Finished Jun 02 03:17:45 PM PDT 24
Peak memory 205456 kb
Host smart-fa641fb7-cd50-439d-bee1-ec487054a7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625550072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1625550072
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2888839862
Short name T515
Test name
Test status
Simulation time 137561360 ps
CPU time 1.04 seconds
Started Jun 02 03:17:45 PM PDT 24
Finished Jun 02 03:17:47 PM PDT 24
Peak memory 206660 kb
Host smart-4fdd8cd9-b2f6-4da5-84f0-500d9ce219d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888839862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2888839862
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2846782110
Short name T842
Test name
Test status
Simulation time 796450576 ps
CPU time 2.31 seconds
Started Jun 02 03:17:50 PM PDT 24
Finished Jun 02 03:17:53 PM PDT 24
Peak memory 218324 kb
Host smart-8c9b048f-0706-4d03-b834-be7b7049ffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846782110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2846782110
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3637068743
Short name T680
Test name
Test status
Simulation time 89685011 ps
CPU time 0.73 seconds
Started Jun 02 03:17:55 PM PDT 24
Finished Jun 02 03:17:56 PM PDT 24
Peak memory 205660 kb
Host smart-b47afd69-5742-4a1e-9d77-aa3bded26185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637068743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3637068743
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1345830328
Short name T706
Test name
Test status
Simulation time 221504237 ps
CPU time 4.04 seconds
Started Jun 02 03:17:58 PM PDT 24
Finished Jun 02 03:18:03 PM PDT 24
Peak memory 233660 kb
Host smart-2991bd71-ee7b-471b-9b7a-ce1e0c091b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345830328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1345830328
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3246149848
Short name T761
Test name
Test status
Simulation time 23396247 ps
CPU time 0.75 seconds
Started Jun 02 03:17:53 PM PDT 24
Finished Jun 02 03:17:55 PM PDT 24
Peak memory 205388 kb
Host smart-6a669920-eaa1-4633-9f4c-bd9337f8acf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246149848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3246149848
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1672055514
Short name T937
Test name
Test status
Simulation time 9883494285 ps
CPU time 54.73 seconds
Started Jun 02 03:17:58 PM PDT 24
Finished Jun 02 03:18:53 PM PDT 24
Peak memory 248952 kb
Host smart-18845820-7fe7-4284-801d-2b3251af7180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672055514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1672055514
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3647894667
Short name T165
Test name
Test status
Simulation time 2903623447 ps
CPU time 17.1 seconds
Started Jun 02 03:17:55 PM PDT 24
Finished Jun 02 03:18:13 PM PDT 24
Peak memory 224452 kb
Host smart-9ecc79e1-26f6-4c02-808d-74133d2f87d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647894667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3647894667
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.434413862
Short name T814
Test name
Test status
Simulation time 10131199591 ps
CPU time 94.02 seconds
Started Jun 02 03:17:56 PM PDT 24
Finished Jun 02 03:19:31 PM PDT 24
Peak memory 273024 kb
Host smart-b951e981-60a2-4f2b-92a2-585b9e1e3ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434413862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.434413862
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.139964957
Short name T960
Test name
Test status
Simulation time 3384772684 ps
CPU time 14.3 seconds
Started Jun 02 03:17:55 PM PDT 24
Finished Jun 02 03:18:10 PM PDT 24
Peak memory 224424 kb
Host smart-116dad44-4ae8-47cd-83d9-1ef8384b16e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139964957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.139964957
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1823403739
Short name T231
Test name
Test status
Simulation time 316997097 ps
CPU time 4.48 seconds
Started Jun 02 03:17:50 PM PDT 24
Finished Jun 02 03:17:54 PM PDT 24
Peak memory 233440 kb
Host smart-848f7428-da17-4d1a-a204-24888bc32628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823403739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1823403739
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3520415145
Short name T815
Test name
Test status
Simulation time 12374868728 ps
CPU time 20.16 seconds
Started Jun 02 03:17:50 PM PDT 24
Finished Jun 02 03:18:11 PM PDT 24
Peak memory 233972 kb
Host smart-0262c6c4-19c9-4c4a-9f6f-8b12a5bc0fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520415145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3520415145
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1803246052
Short name T37
Test name
Test status
Simulation time 3530309028 ps
CPU time 11.42 seconds
Started Jun 02 03:17:53 PM PDT 24
Finished Jun 02 03:18:05 PM PDT 24
Peak memory 234872 kb
Host smart-6c017e54-691c-4634-bf46-ae7d116913f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803246052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1803246052
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2121762904
Short name T741
Test name
Test status
Simulation time 2935839907 ps
CPU time 13.24 seconds
Started Jun 02 03:17:50 PM PDT 24
Finished Jun 02 03:18:03 PM PDT 24
Peak memory 232576 kb
Host smart-2ab6890f-345d-4c51-b505-79ea820f85a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121762904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2121762904
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.197572026
Short name T43
Test name
Test status
Simulation time 1071177268 ps
CPU time 5.42 seconds
Started Jun 02 03:17:55 PM PDT 24
Finished Jun 02 03:18:01 PM PDT 24
Peak memory 222080 kb
Host smart-29286b5b-629e-49c5-af86-0ac9eb9f3d40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=197572026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.197572026
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4151425574
Short name T672
Test name
Test status
Simulation time 140062492 ps
CPU time 0.91 seconds
Started Jun 02 03:17:58 PM PDT 24
Finished Jun 02 03:17:59 PM PDT 24
Peak memory 205552 kb
Host smart-c25f6fcb-9660-4c52-800d-5add592889f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151425574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4151425574
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3836646977
Short name T344
Test name
Test status
Simulation time 2570978923 ps
CPU time 21.09 seconds
Started Jun 02 03:17:54 PM PDT 24
Finished Jun 02 03:18:16 PM PDT 24
Peak memory 216232 kb
Host smart-1d3e4f16-0a0e-468d-a0b1-b282558b6076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836646977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3836646977
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2325529122
Short name T366
Test name
Test status
Simulation time 13519194813 ps
CPU time 12.39 seconds
Started Jun 02 03:17:50 PM PDT 24
Finished Jun 02 03:18:03 PM PDT 24
Peak memory 216168 kb
Host smart-384bcf61-5d57-48ed-82ed-ae70b472ec02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325529122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2325529122
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3707657977
Short name T591
Test name
Test status
Simulation time 71145154 ps
CPU time 1.8 seconds
Started Jun 02 03:17:51 PM PDT 24
Finished Jun 02 03:17:54 PM PDT 24
Peak memory 216416 kb
Host smart-356c28b3-7290-4ef4-a4d2-6e4f7e330714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707657977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3707657977
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3468556746
Short name T630
Test name
Test status
Simulation time 28042458 ps
CPU time 0.75 seconds
Started Jun 02 03:17:51 PM PDT 24
Finished Jun 02 03:17:53 PM PDT 24
Peak memory 205656 kb
Host smart-669d4fc4-e172-46d7-a91e-0cb59e4fe35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468556746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3468556746
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2234658156
Short name T186
Test name
Test status
Simulation time 2803008223 ps
CPU time 13.53 seconds
Started Jun 02 03:17:51 PM PDT 24
Finished Jun 02 03:18:05 PM PDT 24
Peak memory 235520 kb
Host smart-f8140460-921a-4d87-b0bf-28e65f27af34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234658156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2234658156
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.342748038
Short name T698
Test name
Test status
Simulation time 24173446 ps
CPU time 0.72 seconds
Started Jun 02 03:15:27 PM PDT 24
Finished Jun 02 03:15:29 PM PDT 24
Peak memory 205380 kb
Host smart-0e42cff7-b7ba-4da5-b3c0-42b5026ae846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342748038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.342748038
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3027621403
Short name T492
Test name
Test status
Simulation time 86308197 ps
CPU time 2.59 seconds
Started Jun 02 03:15:28 PM PDT 24
Finished Jun 02 03:15:32 PM PDT 24
Peak memory 233864 kb
Host smart-baf622e8-e92a-4c27-8a9b-34d684fa5e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027621403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3027621403
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1195314612
Short name T426
Test name
Test status
Simulation time 53423268 ps
CPU time 0.79 seconds
Started Jun 02 03:15:26 PM PDT 24
Finished Jun 02 03:15:28 PM PDT 24
Peak memory 206616 kb
Host smart-34657d5e-4788-4206-b5a6-fa24bfa99e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195314612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1195314612
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1483283426
Short name T69
Test name
Test status
Simulation time 37040272123 ps
CPU time 65.83 seconds
Started Jun 02 03:15:27 PM PDT 24
Finished Jun 02 03:16:35 PM PDT 24
Peak memory 250840 kb
Host smart-a8b477e9-c17d-44de-aef9-26014e60f0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483283426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1483283426
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3120875727
Short name T811
Test name
Test status
Simulation time 10218239310 ps
CPU time 36.17 seconds
Started Jun 02 03:15:34 PM PDT 24
Finished Jun 02 03:16:11 PM PDT 24
Peak memory 224560 kb
Host smart-da7fec0f-3563-4e57-b050-9f29f8dbb016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120875727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3120875727
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3476084644
Short name T449
Test name
Test status
Simulation time 8965311584 ps
CPU time 62.26 seconds
Started Jun 02 03:15:28 PM PDT 24
Finished Jun 02 03:16:31 PM PDT 24
Peak memory 249112 kb
Host smart-da63e0dd-096e-4b29-98b0-6ba22d2f4a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476084644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3476084644
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.698435127
Short name T41
Test name
Test status
Simulation time 342675736 ps
CPU time 6.43 seconds
Started Jun 02 03:15:27 PM PDT 24
Finished Jun 02 03:15:35 PM PDT 24
Peak memory 249000 kb
Host smart-0cea2c9b-4f1d-4a12-9835-7cbe5c5162e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698435127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.698435127
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.463042823
Short name T223
Test name
Test status
Simulation time 2000369489 ps
CPU time 21.79 seconds
Started Jun 02 03:15:26 PM PDT 24
Finished Jun 02 03:15:48 PM PDT 24
Peak memory 234060 kb
Host smart-5d5b5577-443b-4222-b9b2-f8cc56440fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463042823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.463042823
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3952542261
Short name T856
Test name
Test status
Simulation time 418758897 ps
CPU time 8.47 seconds
Started Jun 02 03:15:28 PM PDT 24
Finished Jun 02 03:15:38 PM PDT 24
Peak memory 238280 kb
Host smart-fb525151-8e09-4c9b-8380-dbc4e3bea43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952542261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3952542261
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2068947419
Short name T763
Test name
Test status
Simulation time 429284217 ps
CPU time 6.1 seconds
Started Jun 02 03:15:29 PM PDT 24
Finished Jun 02 03:15:36 PM PDT 24
Peak memory 228312 kb
Host smart-3c83816d-e24d-44ca-bd41-b7a17b871b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068947419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2068947419
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.344676379
Short name T10
Test name
Test status
Simulation time 1445742474 ps
CPU time 7.02 seconds
Started Jun 02 03:15:32 PM PDT 24
Finished Jun 02 03:15:39 PM PDT 24
Peak memory 220360 kb
Host smart-ef7a70c0-8612-478a-aa07-e52d0306ff09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=344676379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.344676379
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1271471307
Short name T66
Test name
Test status
Simulation time 43840790 ps
CPU time 1 seconds
Started Jun 02 03:15:27 PM PDT 24
Finished Jun 02 03:15:30 PM PDT 24
Peak memory 235108 kb
Host smart-433e2ca3-9fd9-4519-a583-668381d2dc5d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271471307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1271471307
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1773873226
Short name T13
Test name
Test status
Simulation time 43280702 ps
CPU time 0.92 seconds
Started Jun 02 03:15:31 PM PDT 24
Finished Jun 02 03:15:33 PM PDT 24
Peak memory 205340 kb
Host smart-ee182b0d-bfb8-426a-b5a3-60fcc3b1f960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773873226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1773873226
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.4282493919
Short name T323
Test name
Test status
Simulation time 17254969 ps
CPU time 0.73 seconds
Started Jun 02 03:15:29 PM PDT 24
Finished Jun 02 03:15:31 PM PDT 24
Peak memory 205528 kb
Host smart-ed658bc1-8ad4-4be3-9331-cc32ce63a089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282493919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4282493919
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.4253740221
Short name T718
Test name
Test status
Simulation time 727273078 ps
CPU time 5.51 seconds
Started Jun 02 03:15:30 PM PDT 24
Finished Jun 02 03:15:37 PM PDT 24
Peak memory 216080 kb
Host smart-09af8fcc-5c51-4775-9ebf-a632f97fee76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253740221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.4253740221
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1101842636
Short name T881
Test name
Test status
Simulation time 242929886 ps
CPU time 1.83 seconds
Started Jun 02 03:15:27 PM PDT 24
Finished Jun 02 03:15:30 PM PDT 24
Peak memory 216148 kb
Host smart-4b198b82-06ba-4a57-9c71-7827b89436c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101842636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1101842636
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1308681763
Short name T720
Test name
Test status
Simulation time 112491326 ps
CPU time 0.8 seconds
Started Jun 02 03:15:28 PM PDT 24
Finished Jun 02 03:15:30 PM PDT 24
Peak memory 205664 kb
Host smart-295ae2fc-7577-40e9-ac10-2faee90afd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308681763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1308681763
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2991917878
Short name T256
Test name
Test status
Simulation time 3808978178 ps
CPU time 3.48 seconds
Started Jun 02 03:15:33 PM PDT 24
Finished Jun 02 03:15:37 PM PDT 24
Peak memory 218392 kb
Host smart-94018261-692d-4b35-ad10-9516e9a6df5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991917878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2991917878
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1524262424
Short name T829
Test name
Test status
Simulation time 171829471 ps
CPU time 0.71 seconds
Started Jun 02 03:18:06 PM PDT 24
Finished Jun 02 03:18:08 PM PDT 24
Peak memory 205368 kb
Host smart-c8466087-d740-40ad-b104-c70f3133053f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524262424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1524262424
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2397539114
Short name T588
Test name
Test status
Simulation time 283573994 ps
CPU time 5.61 seconds
Started Jun 02 03:17:58 PM PDT 24
Finished Jun 02 03:18:04 PM PDT 24
Peak memory 219804 kb
Host smart-2021edc2-3cf7-4c43-aea4-f8558eb4e938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397539114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2397539114
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1620081301
Short name T635
Test name
Test status
Simulation time 23899741 ps
CPU time 0.75 seconds
Started Jun 02 03:17:58 PM PDT 24
Finished Jun 02 03:17:59 PM PDT 24
Peak memory 206412 kb
Host smart-6135ba4d-144e-483f-bb40-52dc4bf5777c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620081301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1620081301
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2768604988
Short name T600
Test name
Test status
Simulation time 27298718098 ps
CPU time 208.5 seconds
Started Jun 02 03:17:55 PM PDT 24
Finished Jun 02 03:21:24 PM PDT 24
Peak memory 250716 kb
Host smart-1274ed8f-9174-4b53-bd7b-2c47f5514819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768604988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2768604988
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2984101001
Short name T32
Test name
Test status
Simulation time 3624758900 ps
CPU time 72.78 seconds
Started Jun 02 03:17:57 PM PDT 24
Finished Jun 02 03:19:10 PM PDT 24
Peak memory 249100 kb
Host smart-4466c9f8-0ada-4e87-8b67-b8d7c4e7b74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984101001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2984101001
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3787451208
Short name T620
Test name
Test status
Simulation time 136629217157 ps
CPU time 271.27 seconds
Started Jun 02 03:17:55 PM PDT 24
Finished Jun 02 03:22:28 PM PDT 24
Peak memory 251188 kb
Host smart-f15b2b36-92a5-4c46-8740-e02411716874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787451208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3787451208
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2926054064
Short name T892
Test name
Test status
Simulation time 53665922 ps
CPU time 3.7 seconds
Started Jun 02 03:17:55 PM PDT 24
Finished Jun 02 03:17:59 PM PDT 24
Peak memory 232572 kb
Host smart-828e6e9c-5a72-4731-ae8d-4bfd3f305cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926054064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2926054064
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2217168278
Short name T373
Test name
Test status
Simulation time 171971035 ps
CPU time 5.39 seconds
Started Jun 02 03:17:55 PM PDT 24
Finished Jun 02 03:18:02 PM PDT 24
Peak memory 234540 kb
Host smart-30139758-98ab-4cff-9eda-e7355c140b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217168278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2217168278
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3300850732
Short name T736
Test name
Test status
Simulation time 7437540325 ps
CPU time 69.03 seconds
Started Jun 02 03:17:55 PM PDT 24
Finished Jun 02 03:19:05 PM PDT 24
Peak memory 218588 kb
Host smart-6cdd517a-82ab-4b4f-b36c-d0554a3eafcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300850732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3300850732
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1086289090
Short name T602
Test name
Test status
Simulation time 534394788 ps
CPU time 7.85 seconds
Started Jun 02 03:17:55 PM PDT 24
Finished Jun 02 03:18:04 PM PDT 24
Peak memory 239684 kb
Host smart-c1caba28-2b1e-4968-9cdf-6f810ab4f8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086289090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1086289090
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3196625153
Short name T689
Test name
Test status
Simulation time 1840411641 ps
CPU time 4.6 seconds
Started Jun 02 03:17:56 PM PDT 24
Finished Jun 02 03:18:01 PM PDT 24
Peak memory 224332 kb
Host smart-320b551c-9f0e-4474-8f6c-6f2b8924d8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196625153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3196625153
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2255099182
Short name T147
Test name
Test status
Simulation time 209262768 ps
CPU time 3.91 seconds
Started Jun 02 03:17:57 PM PDT 24
Finished Jun 02 03:18:02 PM PDT 24
Peak memory 219820 kb
Host smart-a207f848-5f64-4454-b7ff-d427b18d8b5c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2255099182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2255099182
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2804922505
Short name T567
Test name
Test status
Simulation time 229254993 ps
CPU time 0.98 seconds
Started Jun 02 03:18:01 PM PDT 24
Finished Jun 02 03:18:03 PM PDT 24
Peak memory 206740 kb
Host smart-8c6d4bb3-412c-4c6f-8576-0a63f62f8ebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804922505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2804922505
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3373125376
Short name T904
Test name
Test status
Simulation time 1823227454 ps
CPU time 11.47 seconds
Started Jun 02 03:17:55 PM PDT 24
Finished Jun 02 03:18:07 PM PDT 24
Peak memory 216368 kb
Host smart-0a864d97-67f1-4316-ad1b-00f1ab2364e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373125376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3373125376
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3182185613
Short name T703
Test name
Test status
Simulation time 14292760660 ps
CPU time 14.8 seconds
Started Jun 02 03:17:57 PM PDT 24
Finished Jun 02 03:18:12 PM PDT 24
Peak memory 216156 kb
Host smart-8a6a9f02-f5db-418d-9690-ee2819c5ac48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182185613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3182185613
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2420958997
Short name T935
Test name
Test status
Simulation time 103016681 ps
CPU time 2.23 seconds
Started Jun 02 03:17:54 PM PDT 24
Finished Jun 02 03:17:56 PM PDT 24
Peak memory 216176 kb
Host smart-cbd33796-4aaa-46b9-966e-563d202b1029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420958997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2420958997
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3194296713
Short name T693
Test name
Test status
Simulation time 384815989 ps
CPU time 0.97 seconds
Started Jun 02 03:17:55 PM PDT 24
Finished Jun 02 03:17:57 PM PDT 24
Peak memory 206120 kb
Host smart-fa00472d-55d4-4b2f-a0e0-505bcc202eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194296713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3194296713
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2035592074
Short name T924
Test name
Test status
Simulation time 2061040518 ps
CPU time 10.66 seconds
Started Jun 02 03:17:58 PM PDT 24
Finished Jun 02 03:18:09 PM PDT 24
Peak memory 232532 kb
Host smart-59206d05-0a51-4e41-98c7-073e9385f861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035592074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2035592074
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.137192464
Short name T390
Test name
Test status
Simulation time 25848277 ps
CPU time 0.73 seconds
Started Jun 02 03:18:01 PM PDT 24
Finished Jun 02 03:18:02 PM PDT 24
Peak memory 204816 kb
Host smart-23ee588c-0a2d-4ca8-9829-25228fd0330d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137192464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.137192464
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1336571335
Short name T608
Test name
Test status
Simulation time 3969437945 ps
CPU time 6.43 seconds
Started Jun 02 03:18:01 PM PDT 24
Finished Jun 02 03:18:07 PM PDT 24
Peak memory 233224 kb
Host smart-ac304e02-4d9a-4314-8db7-dd230c459b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336571335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1336571335
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1154832512
Short name T767
Test name
Test status
Simulation time 141681501 ps
CPU time 0.79 seconds
Started Jun 02 03:18:02 PM PDT 24
Finished Jun 02 03:18:03 PM PDT 24
Peak memory 205276 kb
Host smart-5f84f51b-df9c-4063-a799-a7b53c6b56fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154832512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1154832512
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1918169533
Short name T238
Test name
Test status
Simulation time 138463325442 ps
CPU time 230.23 seconds
Started Jun 02 03:18:06 PM PDT 24
Finished Jun 02 03:21:57 PM PDT 24
Peak memory 248988 kb
Host smart-cfc48d38-7b77-462c-8c8b-fd67fbe59a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918169533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1918169533
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.801865858
Short name T806
Test name
Test status
Simulation time 55628891710 ps
CPU time 222.9 seconds
Started Jun 02 03:18:06 PM PDT 24
Finished Jun 02 03:21:50 PM PDT 24
Peak memory 249508 kb
Host smart-60d9242d-dc2c-4c95-8917-96d48ddd8e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801865858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.801865858
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3262836613
Short name T585
Test name
Test status
Simulation time 3492220438 ps
CPU time 14.06 seconds
Started Jun 02 03:18:04 PM PDT 24
Finished Jun 02 03:18:19 PM PDT 24
Peak memory 217076 kb
Host smart-7391b266-7c21-4423-8abb-f6cca175a4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262836613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3262836613
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2358118878
Short name T603
Test name
Test status
Simulation time 4943201520 ps
CPU time 28.57 seconds
Started Jun 02 03:18:06 PM PDT 24
Finished Jun 02 03:18:35 PM PDT 24
Peak memory 240856 kb
Host smart-61b14656-f3a3-40b9-96cf-988b2f82df39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358118878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2358118878
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1593117037
Short name T551
Test name
Test status
Simulation time 320887651 ps
CPU time 3.93 seconds
Started Jun 02 03:18:03 PM PDT 24
Finished Jun 02 03:18:08 PM PDT 24
Peak memory 217592 kb
Host smart-0bfd110a-8ebe-42f8-b031-d1eb30086f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593117037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1593117037
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2761477085
Short name T623
Test name
Test status
Simulation time 13922394935 ps
CPU time 29.01 seconds
Started Jun 02 03:18:02 PM PDT 24
Finished Jun 02 03:18:32 PM PDT 24
Peak memory 229340 kb
Host smart-cfbb084e-ebfc-4464-bb68-abe5733e8b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761477085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2761477085
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2718558805
Short name T800
Test name
Test status
Simulation time 1052120530 ps
CPU time 3.2 seconds
Started Jun 02 03:18:06 PM PDT 24
Finished Jun 02 03:18:10 PM PDT 24
Peak memory 216504 kb
Host smart-ddf07bf2-c811-48f4-b0d8-6ce690b13116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718558805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2718558805
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2988442902
Short name T243
Test name
Test status
Simulation time 6893714633 ps
CPU time 17.32 seconds
Started Jun 02 03:18:02 PM PDT 24
Finished Jun 02 03:18:20 PM PDT 24
Peak memory 218452 kb
Host smart-5e335e15-9c7b-4295-92d0-63e6d4c88129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988442902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2988442902
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2035291002
Short name T360
Test name
Test status
Simulation time 1114177878 ps
CPU time 8.69 seconds
Started Jun 02 03:18:01 PM PDT 24
Finished Jun 02 03:18:11 PM PDT 24
Peak memory 218744 kb
Host smart-68da5d31-dae5-47c0-922d-36d239dd3c62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2035291002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2035291002
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.714619602
Short name T255
Test name
Test status
Simulation time 26969606907 ps
CPU time 258.6 seconds
Started Jun 02 03:18:03 PM PDT 24
Finished Jun 02 03:22:22 PM PDT 24
Peak memory 263476 kb
Host smart-91d3df42-564b-4854-aee0-205932534925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714619602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.714619602
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.544662414
Short name T792
Test name
Test status
Simulation time 2424851964 ps
CPU time 14.32 seconds
Started Jun 02 03:18:04 PM PDT 24
Finished Jun 02 03:18:19 PM PDT 24
Peak memory 216300 kb
Host smart-41097b4f-68d4-45c5-a132-8d04a7c794c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544662414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.544662414
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1192773227
Short name T746
Test name
Test status
Simulation time 12610944873 ps
CPU time 9.64 seconds
Started Jun 02 03:18:03 PM PDT 24
Finished Jun 02 03:18:14 PM PDT 24
Peak memory 216140 kb
Host smart-456978c1-4374-45a4-9b03-8fc177e620b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192773227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1192773227
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2096236361
Short name T627
Test name
Test status
Simulation time 69742199 ps
CPU time 1.44 seconds
Started Jun 02 03:18:01 PM PDT 24
Finished Jun 02 03:18:03 PM PDT 24
Peak memory 216172 kb
Host smart-21b92c82-432d-49af-a609-3a16bc7c7467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096236361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2096236361
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3688205305
Short name T716
Test name
Test status
Simulation time 39323991 ps
CPU time 0.78 seconds
Started Jun 02 03:18:03 PM PDT 24
Finished Jun 02 03:18:04 PM PDT 24
Peak memory 205652 kb
Host smart-b4a9fa14-0d94-4c59-9f26-d264ad9142ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688205305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3688205305
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.155577626
Short name T210
Test name
Test status
Simulation time 519383057 ps
CPU time 5.39 seconds
Started Jun 02 03:18:01 PM PDT 24
Finished Jun 02 03:18:07 PM PDT 24
Peak memory 218364 kb
Host smart-fc074083-f07e-4e7e-9e95-9c2dc67f0d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155577626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.155577626
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1686039546
Short name T399
Test name
Test status
Simulation time 18588461 ps
CPU time 0.76 seconds
Started Jun 02 03:18:08 PM PDT 24
Finished Jun 02 03:18:09 PM PDT 24
Peak memory 205412 kb
Host smart-5955d708-76e7-4e36-b194-1cb5f441073e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686039546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1686039546
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2943558559
Short name T832
Test name
Test status
Simulation time 3923634102 ps
CPU time 13.5 seconds
Started Jun 02 03:18:10 PM PDT 24
Finished Jun 02 03:18:24 PM PDT 24
Peak memory 233756 kb
Host smart-edcabade-eaec-4c6b-88c1-090bf07ed3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943558559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2943558559
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1513910008
Short name T367
Test name
Test status
Simulation time 17576443 ps
CPU time 0.8 seconds
Started Jun 02 03:18:02 PM PDT 24
Finished Jun 02 03:18:04 PM PDT 24
Peak memory 206452 kb
Host smart-8ba04c62-58c3-4a57-b925-ee955d6f8ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513910008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1513910008
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1997844135
Short name T516
Test name
Test status
Simulation time 3811713325 ps
CPU time 28.66 seconds
Started Jun 02 03:18:16 PM PDT 24
Finished Jun 02 03:18:46 PM PDT 24
Peak memory 224384 kb
Host smart-48d1f0aa-722c-4a7b-86e8-276bcc6ea400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997844135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1997844135
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1117847219
Short name T190
Test name
Test status
Simulation time 4141836214 ps
CPU time 96.96 seconds
Started Jun 02 03:18:08 PM PDT 24
Finished Jun 02 03:19:46 PM PDT 24
Peak memory 254152 kb
Host smart-024e0db7-e2e7-4d28-b4f2-0a0ec31c28b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117847219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1117847219
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.884761747
Short name T172
Test name
Test status
Simulation time 11206299953 ps
CPU time 102.83 seconds
Started Jun 02 03:18:07 PM PDT 24
Finished Jun 02 03:19:50 PM PDT 24
Peak memory 236128 kb
Host smart-81c76942-d0db-4a22-b81c-ad926bf73f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884761747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.884761747
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.609747972
Short name T648
Test name
Test status
Simulation time 1447787080 ps
CPU time 7.79 seconds
Started Jun 02 03:18:06 PM PDT 24
Finished Jun 02 03:18:14 PM PDT 24
Peak memory 224372 kb
Host smart-b3d1da36-7395-4547-b9d3-fc3b3cadb898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609747972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.609747972
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.345400808
Short name T189
Test name
Test status
Simulation time 3493599761 ps
CPU time 31.07 seconds
Started Jun 02 03:18:03 PM PDT 24
Finished Jun 02 03:18:34 PM PDT 24
Peak memory 235044 kb
Host smart-11302cd8-d5ec-4e2b-89f8-cbcf5fad1227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345400808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.345400808
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.398459981
Short name T92
Test name
Test status
Simulation time 987418636 ps
CPU time 8.89 seconds
Started Jun 02 03:18:04 PM PDT 24
Finished Jun 02 03:18:13 PM PDT 24
Peak memory 233652 kb
Host smart-7c7d532a-8fc9-45b3-b637-73c8e996cb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398459981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.398459981
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2371975144
Short name T876
Test name
Test status
Simulation time 118706861 ps
CPU time 2.1 seconds
Started Jun 02 03:18:02 PM PDT 24
Finished Jun 02 03:18:05 PM PDT 24
Peak memory 216016 kb
Host smart-8c8a709e-d7bd-4259-a4ff-3d6942339071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371975144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2371975144
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2860966954
Short name T77
Test name
Test status
Simulation time 9258836890 ps
CPU time 12.39 seconds
Started Jun 02 03:18:04 PM PDT 24
Finished Jun 02 03:18:17 PM PDT 24
Peak memory 237476 kb
Host smart-defcbec9-731d-45ee-bcca-75ee088348a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860966954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2860966954
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1619948977
Short name T879
Test name
Test status
Simulation time 1832967447 ps
CPU time 14.02 seconds
Started Jun 02 03:18:10 PM PDT 24
Finished Jun 02 03:18:25 PM PDT 24
Peak memory 219924 kb
Host smart-fb9a195c-95b6-4a9f-880d-206f175c5f78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1619948977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1619948977
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1702767213
Short name T962
Test name
Test status
Simulation time 233218215 ps
CPU time 1.07 seconds
Started Jun 02 03:18:09 PM PDT 24
Finished Jun 02 03:18:11 PM PDT 24
Peak memory 207048 kb
Host smart-8c96066b-a174-4416-b796-9c12e1ab81bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702767213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1702767213
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2627279206
Short name T846
Test name
Test status
Simulation time 281303228 ps
CPU time 4.19 seconds
Started Jun 02 03:18:02 PM PDT 24
Finished Jun 02 03:18:06 PM PDT 24
Peak memory 216404 kb
Host smart-db976c42-70ec-407f-82ff-1abead535e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627279206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2627279206
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3858927011
Short name T352
Test name
Test status
Simulation time 1518222348 ps
CPU time 4.99 seconds
Started Jun 02 03:18:06 PM PDT 24
Finished Jun 02 03:18:12 PM PDT 24
Peak memory 215808 kb
Host smart-ad0095f5-cca5-416e-985f-9e70ffe82913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858927011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3858927011
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3602737127
Short name T762
Test name
Test status
Simulation time 454290529 ps
CPU time 2.16 seconds
Started Jun 02 03:18:03 PM PDT 24
Finished Jun 02 03:18:06 PM PDT 24
Peak memory 216248 kb
Host smart-ea93ffd1-d90c-4026-8474-ef40bd2ec8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602737127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3602737127
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.397619647
Short name T407
Test name
Test status
Simulation time 133750696 ps
CPU time 0.96 seconds
Started Jun 02 03:18:02 PM PDT 24
Finished Jun 02 03:18:03 PM PDT 24
Peak memory 205580 kb
Host smart-cfde7dcb-1459-477d-bd42-eba4b415eb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397619647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.397619647
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3599392985
Short name T896
Test name
Test status
Simulation time 1312495666 ps
CPU time 8.03 seconds
Started Jun 02 03:18:10 PM PDT 24
Finished Jun 02 03:18:19 PM PDT 24
Peak memory 235120 kb
Host smart-0821077f-2472-43f4-b8e0-8676a8933117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599392985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3599392985
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3878644700
Short name T673
Test name
Test status
Simulation time 19684832 ps
CPU time 0.72 seconds
Started Jun 02 03:18:09 PM PDT 24
Finished Jun 02 03:18:10 PM PDT 24
Peak memory 205416 kb
Host smart-687b5822-cef3-4cd7-a533-169ff0fd4683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878644700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3878644700
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3162996926
Short name T90
Test name
Test status
Simulation time 148319708 ps
CPU time 2.77 seconds
Started Jun 02 03:18:09 PM PDT 24
Finished Jun 02 03:18:13 PM PDT 24
Peak memory 218584 kb
Host smart-4bae5f3d-c133-4262-9c28-2cd50a04e5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162996926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3162996926
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2431210580
Short name T338
Test name
Test status
Simulation time 14208645 ps
CPU time 0.75 seconds
Started Jun 02 03:18:07 PM PDT 24
Finished Jun 02 03:18:09 PM PDT 24
Peak memory 206392 kb
Host smart-4764fc84-87d9-4f6c-9f05-a8a0a2c1a39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431210580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2431210580
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2781917472
Short name T257
Test name
Test status
Simulation time 10078692448 ps
CPU time 30.82 seconds
Started Jun 02 03:18:10 PM PDT 24
Finished Jun 02 03:18:41 PM PDT 24
Peak memory 237376 kb
Host smart-b8fb4444-d591-4721-9f5d-46fba43711b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781917472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2781917472
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1581154296
Short name T191
Test name
Test status
Simulation time 38516584295 ps
CPU time 401.41 seconds
Started Jun 02 03:18:08 PM PDT 24
Finished Jun 02 03:24:50 PM PDT 24
Peak memory 255064 kb
Host smart-e5e27c2f-4500-4835-ae9b-a7d13eec5366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581154296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1581154296
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.107847593
Short name T232
Test name
Test status
Simulation time 27356757753 ps
CPU time 80.36 seconds
Started Jun 02 03:18:08 PM PDT 24
Finished Jun 02 03:19:29 PM PDT 24
Peak memory 238228 kb
Host smart-895b677e-f0df-4997-8c81-03266695e5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107847593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.107847593
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1064682643
Short name T300
Test name
Test status
Simulation time 3820560944 ps
CPU time 19.94 seconds
Started Jun 02 03:18:07 PM PDT 24
Finished Jun 02 03:18:28 PM PDT 24
Peak memory 250100 kb
Host smart-8d024b14-6bf9-4e85-bb22-21a26631612b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064682643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1064682643
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.805200217
Short name T889
Test name
Test status
Simulation time 257639213 ps
CPU time 5 seconds
Started Jun 02 03:18:08 PM PDT 24
Finished Jun 02 03:18:13 PM PDT 24
Peak memory 234708 kb
Host smart-7a28a813-287a-4c2b-8f4e-4113f26fb159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805200217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.805200217
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1937417065
Short name T804
Test name
Test status
Simulation time 86502462 ps
CPU time 2.14 seconds
Started Jun 02 03:18:09 PM PDT 24
Finished Jun 02 03:18:12 PM PDT 24
Peak memory 215980 kb
Host smart-f5a8f8e1-12c8-4343-b789-f219e795d780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937417065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1937417065
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.4019663017
Short name T50
Test name
Test status
Simulation time 121884660 ps
CPU time 2.45 seconds
Started Jun 02 03:18:11 PM PDT 24
Finished Jun 02 03:18:14 PM PDT 24
Peak memory 221144 kb
Host smart-9bdf04c3-9559-4b7c-be2d-c7f56c2c8675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019663017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.4019663017
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.21557245
Short name T136
Test name
Test status
Simulation time 490486806 ps
CPU time 3.82 seconds
Started Jun 02 03:18:16 PM PDT 24
Finished Jun 02 03:18:21 PM PDT 24
Peak memory 224416 kb
Host smart-340616a5-9000-4906-b9e3-e03292fa20a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21557245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.21557245
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4103161210
Short name T647
Test name
Test status
Simulation time 3215791194 ps
CPU time 7.14 seconds
Started Jun 02 03:18:09 PM PDT 24
Finished Jun 02 03:18:16 PM PDT 24
Peak memory 222528 kb
Host smart-1bc87937-d845-43e3-afad-1d9bfc7913b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4103161210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4103161210
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3577284716
Short name T955
Test name
Test status
Simulation time 51142153408 ps
CPU time 130.42 seconds
Started Jun 02 03:18:16 PM PDT 24
Finished Jun 02 03:20:28 PM PDT 24
Peak memory 250984 kb
Host smart-72b516dd-4435-4c20-8c44-0c247419a744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577284716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3577284716
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1265331003
Short name T798
Test name
Test status
Simulation time 28140240 ps
CPU time 0.76 seconds
Started Jun 02 03:18:09 PM PDT 24
Finished Jun 02 03:18:11 PM PDT 24
Peak memory 205492 kb
Host smart-e0fb0a0b-fcbb-4117-a33c-f8140260bd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265331003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1265331003
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2883647175
Short name T358
Test name
Test status
Simulation time 1514673321 ps
CPU time 4.38 seconds
Started Jun 02 03:18:09 PM PDT 24
Finished Jun 02 03:18:14 PM PDT 24
Peak memory 216168 kb
Host smart-c6648e0f-7f1e-4480-b7b7-0eaf8f81385b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883647175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2883647175
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3703920025
Short name T757
Test name
Test status
Simulation time 137618818 ps
CPU time 1.48 seconds
Started Jun 02 03:18:09 PM PDT 24
Finished Jun 02 03:18:11 PM PDT 24
Peak memory 216168 kb
Host smart-ba91b367-1b80-41f0-bfe0-ea809074e6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703920025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3703920025
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.937888515
Short name T411
Test name
Test status
Simulation time 446766753 ps
CPU time 0.99 seconds
Started Jun 02 03:18:10 PM PDT 24
Finished Jun 02 03:18:11 PM PDT 24
Peak memory 205896 kb
Host smart-087af66c-d32d-4b0c-94f8-290b8a701173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937888515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.937888515
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3235192816
Short name T773
Test name
Test status
Simulation time 17421505814 ps
CPU time 13.98 seconds
Started Jun 02 03:18:08 PM PDT 24
Finished Jun 02 03:18:22 PM PDT 24
Peak memory 219008 kb
Host smart-6702b5b1-8e84-434e-9063-81e89ff76ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235192816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3235192816
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.876475584
Short name T413
Test name
Test status
Simulation time 24573190 ps
CPU time 0.73 seconds
Started Jun 02 03:18:16 PM PDT 24
Finished Jun 02 03:18:18 PM PDT 24
Peak memory 204840 kb
Host smart-3951d759-538b-4109-b2a9-f497ab9c1e9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876475584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.876475584
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3699081009
Short name T544
Test name
Test status
Simulation time 103627717 ps
CPU time 3.05 seconds
Started Jun 02 03:18:17 PM PDT 24
Finished Jun 02 03:18:21 PM PDT 24
Peak memory 234320 kb
Host smart-04bd463d-1929-48f9-8985-c8687a421f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699081009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3699081009
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3879388070
Short name T335
Test name
Test status
Simulation time 47174802 ps
CPU time 0.74 seconds
Started Jun 02 03:18:16 PM PDT 24
Finished Jun 02 03:18:17 PM PDT 24
Peak memory 205404 kb
Host smart-88756f7c-bb64-4bba-8cce-b38be5271c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879388070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3879388070
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1140462226
Short name T278
Test name
Test status
Simulation time 287349982988 ps
CPU time 199.83 seconds
Started Jun 02 03:18:17 PM PDT 24
Finished Jun 02 03:21:38 PM PDT 24
Peak memory 240852 kb
Host smart-15311c97-dbd1-42e9-bbf7-c0698a999832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140462226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1140462226
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1474803813
Short name T442
Test name
Test status
Simulation time 10886477238 ps
CPU time 55.23 seconds
Started Jun 02 03:18:18 PM PDT 24
Finished Jun 02 03:19:14 PM PDT 24
Peak memory 261212 kb
Host smart-664b6c79-ee75-4382-ba04-86fe7fb65467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474803813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1474803813
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2313147748
Short name T279
Test name
Test status
Simulation time 11655300696 ps
CPU time 65.6 seconds
Started Jun 02 03:18:18 PM PDT 24
Finished Jun 02 03:19:25 PM PDT 24
Peak memory 253920 kb
Host smart-3eb1bf1d-b99c-4587-8da9-bf8df974812b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313147748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2313147748
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2694341903
Short name T584
Test name
Test status
Simulation time 2626185166 ps
CPU time 8.08 seconds
Started Jun 02 03:18:16 PM PDT 24
Finished Jun 02 03:18:25 PM PDT 24
Peak memory 224428 kb
Host smart-0d899c3d-93b1-4aab-8ab8-8004e6e9fc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694341903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2694341903
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3438372556
Short name T728
Test name
Test status
Simulation time 226404418 ps
CPU time 4.03 seconds
Started Jun 02 03:18:16 PM PDT 24
Finished Jun 02 03:18:21 PM PDT 24
Peak memory 232492 kb
Host smart-e3b8dd77-e3e5-485d-b66f-f3baf0be0942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438372556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3438372556
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.754334941
Short name T253
Test name
Test status
Simulation time 3571983517 ps
CPU time 35.15 seconds
Started Jun 02 03:18:16 PM PDT 24
Finished Jun 02 03:18:52 PM PDT 24
Peak memory 234920 kb
Host smart-b40ba0cd-3a80-4d37-8b12-847780e8c8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754334941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.754334941
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2505768595
Short name T331
Test name
Test status
Simulation time 31412027 ps
CPU time 2.12 seconds
Started Jun 02 03:18:09 PM PDT 24
Finished Jun 02 03:18:11 PM PDT 24
Peak memory 215968 kb
Host smart-32f7d076-093e-4eeb-b1d6-3dafccc77a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505768595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2505768595
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2239541799
Short name T574
Test name
Test status
Simulation time 85390732 ps
CPU time 2.31 seconds
Started Jun 02 03:18:11 PM PDT 24
Finished Jun 02 03:18:14 PM PDT 24
Peak memory 218520 kb
Host smart-fa4ed972-8bce-422f-89fc-0939b520341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239541799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2239541799
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3503027524
Short name T711
Test name
Test status
Simulation time 2329745133 ps
CPU time 5.32 seconds
Started Jun 02 03:18:14 PM PDT 24
Finished Jun 02 03:18:20 PM PDT 24
Peak memory 219260 kb
Host smart-197d1b4c-09c9-40ff-8f55-43ea14ba54f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3503027524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3503027524
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3831755264
Short name T916
Test name
Test status
Simulation time 3086313569 ps
CPU time 13.2 seconds
Started Jun 02 03:18:09 PM PDT 24
Finished Jun 02 03:18:23 PM PDT 24
Peak memory 218076 kb
Host smart-ebccf514-f2da-4330-bc01-76e1f8427408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831755264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3831755264
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1882199409
Short name T707
Test name
Test status
Simulation time 40273860 ps
CPU time 0.68 seconds
Started Jun 02 03:18:09 PM PDT 24
Finished Jun 02 03:18:11 PM PDT 24
Peak memory 205496 kb
Host smart-fed25dc0-91e6-46c4-808f-753db7dc6bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882199409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1882199409
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2137578646
Short name T76
Test name
Test status
Simulation time 40225146 ps
CPU time 1.32 seconds
Started Jun 02 03:18:09 PM PDT 24
Finished Jun 02 03:18:11 PM PDT 24
Peak memory 216136 kb
Host smart-595378b6-9492-4e73-af29-5401fb22c5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137578646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2137578646
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2609820641
Short name T472
Test name
Test status
Simulation time 103150398 ps
CPU time 0.89 seconds
Started Jun 02 03:18:09 PM PDT 24
Finished Jun 02 03:18:10 PM PDT 24
Peak memory 205636 kb
Host smart-7a4717c0-3527-456b-ab8f-1b2500453053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609820641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2609820641
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2346429847
Short name T435
Test name
Test status
Simulation time 13807057721 ps
CPU time 21.59 seconds
Started Jun 02 03:18:16 PM PDT 24
Finished Jun 02 03:18:38 PM PDT 24
Peak memory 219924 kb
Host smart-9e3a7a9a-cee5-49e5-a470-d0c105e2cde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346429847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2346429847
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1092951245
Short name T606
Test name
Test status
Simulation time 29297454 ps
CPU time 0.7 seconds
Started Jun 02 03:18:16 PM PDT 24
Finished Jun 02 03:18:17 PM PDT 24
Peak memory 204804 kb
Host smart-0f549c3b-1438-49a1-97dd-a83f4c86cae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092951245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1092951245
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1499476168
Short name T778
Test name
Test status
Simulation time 1695252015 ps
CPU time 2.88 seconds
Started Jun 02 03:18:17 PM PDT 24
Finished Jun 02 03:18:21 PM PDT 24
Peak memory 218384 kb
Host smart-16c77077-4cc0-43bc-ad86-075a4e75ca1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499476168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1499476168
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.4259863622
Short name T849
Test name
Test status
Simulation time 40830173 ps
CPU time 0.76 seconds
Started Jun 02 03:18:16 PM PDT 24
Finished Jun 02 03:18:17 PM PDT 24
Peak memory 206356 kb
Host smart-939378c1-92fd-41dc-87eb-a952e118c8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259863622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.4259863622
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3751987603
Short name T235
Test name
Test status
Simulation time 15480627726 ps
CPU time 65.93 seconds
Started Jun 02 03:18:19 PM PDT 24
Finished Jun 02 03:19:25 PM PDT 24
Peak memory 251428 kb
Host smart-ae5c204b-d2e5-47c0-bf30-eb094de6fa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751987603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3751987603
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1951154373
Short name T819
Test name
Test status
Simulation time 16686851209 ps
CPU time 167.99 seconds
Started Jun 02 03:18:15 PM PDT 24
Finished Jun 02 03:21:03 PM PDT 24
Peak memory 250544 kb
Host smart-3c35803c-20f7-4601-a767-bcad8ca8e588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951154373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1951154373
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2637346904
Short name T262
Test name
Test status
Simulation time 27905111201 ps
CPU time 124.29 seconds
Started Jun 02 03:18:15 PM PDT 24
Finished Jun 02 03:20:19 PM PDT 24
Peak memory 248976 kb
Host smart-002925e9-b3b6-4c10-93de-f814940b4c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637346904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2637346904
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1335179010
Short name T306
Test name
Test status
Simulation time 162105429 ps
CPU time 5.95 seconds
Started Jun 02 03:18:17 PM PDT 24
Finished Jun 02 03:18:24 PM PDT 24
Peak memory 232572 kb
Host smart-5261b87a-361f-420d-a5be-a2de01095de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335179010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1335179010
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3782454801
Short name T610
Test name
Test status
Simulation time 425506250 ps
CPU time 2.4 seconds
Started Jun 02 03:18:17 PM PDT 24
Finished Jun 02 03:18:21 PM PDT 24
Peak memory 215968 kb
Host smart-1475190f-9610-4d05-9082-0b14874b7dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782454801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3782454801
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1458007698
Short name T898
Test name
Test status
Simulation time 1158233121 ps
CPU time 12.15 seconds
Started Jun 02 03:18:18 PM PDT 24
Finished Jun 02 03:18:31 PM PDT 24
Peak memory 227260 kb
Host smart-6a3af2e6-d571-4b7a-b8de-6d526a286f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458007698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1458007698
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3226768080
Short name T861
Test name
Test status
Simulation time 33270168238 ps
CPU time 22.08 seconds
Started Jun 02 03:18:18 PM PDT 24
Finished Jun 02 03:18:41 PM PDT 24
Peak memory 229256 kb
Host smart-5c768d91-25ee-46bf-9001-a4e5aec9c5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226768080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3226768080
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.945229766
Short name T652
Test name
Test status
Simulation time 1061893187 ps
CPU time 7.7 seconds
Started Jun 02 03:18:17 PM PDT 24
Finished Jun 02 03:18:26 PM PDT 24
Peak memory 233924 kb
Host smart-aa51ff8e-4be8-40e8-a518-4a3d82a71e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945229766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.945229766
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.693901037
Short name T494
Test name
Test status
Simulation time 658136431 ps
CPU time 5.7 seconds
Started Jun 02 03:18:17 PM PDT 24
Finished Jun 02 03:18:24 PM PDT 24
Peak memory 220344 kb
Host smart-50466202-8854-47a1-8a3c-6963054f57da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=693901037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.693901037
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2835107196
Short name T274
Test name
Test status
Simulation time 245789800986 ps
CPU time 594.74 seconds
Started Jun 02 03:18:15 PM PDT 24
Finished Jun 02 03:28:10 PM PDT 24
Peak memory 273652 kb
Host smart-fbb9eb55-aac2-412c-9148-a3ae1808684d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835107196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2835107196
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2369009000
Short name T320
Test name
Test status
Simulation time 19618610 ps
CPU time 0.74 seconds
Started Jun 02 03:18:18 PM PDT 24
Finished Jun 02 03:18:19 PM PDT 24
Peak memory 205876 kb
Host smart-2a66bfdb-f4de-4e17-bd3f-9438d968c443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369009000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2369009000
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2543636870
Short name T665
Test name
Test status
Simulation time 4235832743 ps
CPU time 3.91 seconds
Started Jun 02 03:18:17 PM PDT 24
Finished Jun 02 03:18:22 PM PDT 24
Peak memory 216052 kb
Host smart-25922843-1a16-4d32-846b-24c5185c0aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543636870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2543636870
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2639743415
Short name T754
Test name
Test status
Simulation time 80216293 ps
CPU time 0.84 seconds
Started Jun 02 03:18:15 PM PDT 24
Finished Jun 02 03:18:16 PM PDT 24
Peak memory 206728 kb
Host smart-03fd04bc-ca42-45e0-ba8c-f620fab593ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639743415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2639743415
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.168784995
Short name T430
Test name
Test status
Simulation time 103892616 ps
CPU time 0.98 seconds
Started Jun 02 03:18:17 PM PDT 24
Finished Jun 02 03:18:19 PM PDT 24
Peak memory 205636 kb
Host smart-b8556aa4-bbba-4146-8823-ffd7d2172167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168784995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.168784995
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.53608620
Short name T491
Test name
Test status
Simulation time 68342657 ps
CPU time 2.46 seconds
Started Jun 02 03:18:17 PM PDT 24
Finished Jun 02 03:18:20 PM PDT 24
Peak memory 213044 kb
Host smart-eb983a4f-e5de-4fe0-84c1-c6f1f068166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53608620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.53608620
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1349203441
Short name T864
Test name
Test status
Simulation time 23168086 ps
CPU time 0.73 seconds
Started Jun 02 03:18:21 PM PDT 24
Finished Jun 02 03:18:23 PM PDT 24
Peak memory 205740 kb
Host smart-d0e881c3-8871-4ed2-8c9c-8b8f45166a71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349203441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1349203441
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2735414607
Short name T694
Test name
Test status
Simulation time 6816474592 ps
CPU time 18.92 seconds
Started Jun 02 03:18:24 PM PDT 24
Finished Jun 02 03:18:43 PM PDT 24
Peak memory 234460 kb
Host smart-d1e2da80-a3e5-421e-afc6-b1fb1e2d6493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735414607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2735414607
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.229231353
Short name T847
Test name
Test status
Simulation time 14898525 ps
CPU time 0.77 seconds
Started Jun 02 03:18:18 PM PDT 24
Finished Jun 02 03:18:20 PM PDT 24
Peak memory 205352 kb
Host smart-ad77a2e9-abaa-4b03-9894-49c1ebdd7063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229231353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.229231353
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.661996007
Short name T276
Test name
Test status
Simulation time 237973470433 ps
CPU time 384.03 seconds
Started Jun 02 03:18:21 PM PDT 24
Finished Jun 02 03:24:46 PM PDT 24
Peak memory 261880 kb
Host smart-912dc97a-8203-4bda-82e2-05d79f19b9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661996007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.661996007
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2376572750
Short name T297
Test name
Test status
Simulation time 9682701636 ps
CPU time 48.83 seconds
Started Jun 02 03:18:21 PM PDT 24
Finished Jun 02 03:19:11 PM PDT 24
Peak memory 240872 kb
Host smart-4986028d-2f13-4e4c-8daf-917ce17dff6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376572750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2376572750
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2904942886
Short name T780
Test name
Test status
Simulation time 2433969457 ps
CPU time 7.52 seconds
Started Jun 02 03:18:23 PM PDT 24
Finished Jun 02 03:18:31 PM PDT 24
Peak memory 240460 kb
Host smart-8327317c-0155-4ce5-a216-95762d018043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904942886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2904942886
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1736342282
Short name T865
Test name
Test status
Simulation time 460127689 ps
CPU time 6.47 seconds
Started Jun 02 03:18:33 PM PDT 24
Finished Jun 02 03:18:40 PM PDT 24
Peak memory 218460 kb
Host smart-8fa0583d-1f71-481e-ad8f-69e17338301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736342282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1736342282
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3287358443
Short name T396
Test name
Test status
Simulation time 159689044 ps
CPU time 4.9 seconds
Started Jun 02 03:18:34 PM PDT 24
Finished Jun 02 03:18:40 PM PDT 24
Peak memory 233492 kb
Host smart-6c8b90b6-53cb-4b1d-abcb-b1880590107b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287358443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3287358443
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2441699656
Short name T702
Test name
Test status
Simulation time 430396524 ps
CPU time 2.47 seconds
Started Jun 02 03:18:22 PM PDT 24
Finished Jun 02 03:18:25 PM PDT 24
Peak memory 216020 kb
Host smart-ca4f4d72-ff9a-4b74-912e-c0eb53ad3bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441699656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2441699656
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.701815317
Short name T40
Test name
Test status
Simulation time 11037065574 ps
CPU time 9.64 seconds
Started Jun 02 03:18:23 PM PDT 24
Finished Jun 02 03:18:33 PM PDT 24
Peak memory 232648 kb
Host smart-5bd95640-98d4-4573-abbb-956d95172c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701815317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.701815317
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2071842071
Short name T368
Test name
Test status
Simulation time 1487730993 ps
CPU time 17.83 seconds
Started Jun 02 03:18:33 PM PDT 24
Finished Jun 02 03:18:51 PM PDT 24
Peak memory 220164 kb
Host smart-bce0c4b4-28f4-4488-ac67-cc2dadd7821d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2071842071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2071842071
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4066428515
Short name T33
Test name
Test status
Simulation time 38403806125 ps
CPU time 376.56 seconds
Started Jun 02 03:18:21 PM PDT 24
Finished Jun 02 03:24:39 PM PDT 24
Peak memory 254432 kb
Host smart-4a649f52-d12f-47ff-8e31-fb09821a1f9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066428515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4066428515
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.767947477
Short name T307
Test name
Test status
Simulation time 115953317384 ps
CPU time 42.28 seconds
Started Jun 02 03:18:17 PM PDT 24
Finished Jun 02 03:19:00 PM PDT 24
Peak memory 216296 kb
Host smart-31ffeb82-735f-42be-8aa1-ab32a6e69c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767947477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.767947477
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2406563063
Short name T400
Test name
Test status
Simulation time 472453854 ps
CPU time 1.52 seconds
Started Jun 02 03:18:17 PM PDT 24
Finished Jun 02 03:18:19 PM PDT 24
Peak memory 207576 kb
Host smart-e40f2baa-f3ae-4d9f-92b6-eb0e34fbc030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406563063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2406563063
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.595548825
Short name T930
Test name
Test status
Simulation time 138758151 ps
CPU time 1.08 seconds
Started Jun 02 03:18:15 PM PDT 24
Finished Jun 02 03:18:16 PM PDT 24
Peak memory 207224 kb
Host smart-291389d5-7156-4abe-afa3-6391b99b7d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595548825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.595548825
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1905370211
Short name T425
Test name
Test status
Simulation time 89080864 ps
CPU time 0.82 seconds
Started Jun 02 03:18:17 PM PDT 24
Finished Jun 02 03:18:19 PM PDT 24
Peak memory 205656 kb
Host smart-852e20a0-2244-4f49-a780-de9716d2807a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905370211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1905370211
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.393966302
Short name T380
Test name
Test status
Simulation time 953894230 ps
CPU time 8.01 seconds
Started Jun 02 03:18:34 PM PDT 24
Finished Jun 02 03:18:43 PM PDT 24
Peak memory 234552 kb
Host smart-fa83d421-f3ee-4af8-867a-131517229d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393966302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.393966302
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2292397228
Short name T933
Test name
Test status
Simulation time 30002607 ps
CPU time 0.74 seconds
Started Jun 02 03:18:23 PM PDT 24
Finished Jun 02 03:18:24 PM PDT 24
Peak memory 205376 kb
Host smart-014be48a-f8ef-4041-8c4e-9c716dc7e202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292397228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2292397228
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.797545823
Short name T250
Test name
Test status
Simulation time 227301262 ps
CPU time 4.1 seconds
Started Jun 02 03:18:24 PM PDT 24
Finished Jun 02 03:18:28 PM PDT 24
Peak memory 233580 kb
Host smart-56415bf3-2243-4518-8d11-beea0eb5e2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797545823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.797545823
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.296597454
Short name T326
Test name
Test status
Simulation time 16430639 ps
CPU time 0.82 seconds
Started Jun 02 03:18:22 PM PDT 24
Finished Jun 02 03:18:23 PM PDT 24
Peak memory 206348 kb
Host smart-58f16af9-c0a9-420c-a468-313ad0205c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296597454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.296597454
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.887178575
Short name T536
Test name
Test status
Simulation time 128865688705 ps
CPU time 215.39 seconds
Started Jun 02 03:18:22 PM PDT 24
Finished Jun 02 03:21:58 PM PDT 24
Peak memory 255564 kb
Host smart-213c5ee9-93ab-4a51-a9f2-846d55be211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887178575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.887178575
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2887277685
Short name T28
Test name
Test status
Simulation time 11227219020 ps
CPU time 55.32 seconds
Started Jun 02 03:18:34 PM PDT 24
Finished Jun 02 03:19:30 PM PDT 24
Peak memory 249068 kb
Host smart-6a66cddf-a896-497c-b611-39b1809e89e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887277685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2887277685
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1422697430
Short name T884
Test name
Test status
Simulation time 16166802494 ps
CPU time 131.85 seconds
Started Jun 02 03:18:21 PM PDT 24
Finished Jun 02 03:20:34 PM PDT 24
Peak memory 249056 kb
Host smart-bb44ebe0-4480-475e-829f-35952ceb9e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422697430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1422697430
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1411558219
Short name T518
Test name
Test status
Simulation time 588970789 ps
CPU time 5.66 seconds
Started Jun 02 03:18:24 PM PDT 24
Finished Jun 02 03:18:30 PM PDT 24
Peak memory 224340 kb
Host smart-d34fde35-3de1-44fd-a0e8-bee98a7d4179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411558219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1411558219
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2281231096
Short name T715
Test name
Test status
Simulation time 254222066 ps
CPU time 5.23 seconds
Started Jun 02 03:18:34 PM PDT 24
Finished Jun 02 03:18:40 PM PDT 24
Peak memory 219684 kb
Host smart-f181bd2d-f699-403c-883d-d683951f2805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281231096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2281231096
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1210550455
Short name T458
Test name
Test status
Simulation time 4792908078 ps
CPU time 16.9 seconds
Started Jun 02 03:18:20 PM PDT 24
Finished Jun 02 03:18:38 PM PDT 24
Peak memory 231356 kb
Host smart-92227690-7f44-452a-a53d-14d23baf063e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210550455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1210550455
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.984120554
Short name T619
Test name
Test status
Simulation time 304523838 ps
CPU time 5.46 seconds
Started Jun 02 03:18:20 PM PDT 24
Finished Jun 02 03:18:26 PM PDT 24
Peak memory 227460 kb
Host smart-dd7263d9-a9f0-4af7-913a-0b3299192152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984120554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.984120554
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1967314082
Short name T790
Test name
Test status
Simulation time 11470476319 ps
CPU time 8.14 seconds
Started Jun 02 03:18:20 PM PDT 24
Finished Jun 02 03:18:29 PM PDT 24
Peak memory 234348 kb
Host smart-2258e5df-5cda-4905-a0e8-b447a03c8a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967314082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1967314082
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2452004300
Short name T709
Test name
Test status
Simulation time 318687746 ps
CPU time 3.9 seconds
Started Jun 02 03:18:21 PM PDT 24
Finished Jun 02 03:18:26 PM PDT 24
Peak memory 220156 kb
Host smart-74074728-01f4-4012-884b-fdfa0fbf2918
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2452004300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2452004300
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.767428648
Short name T161
Test name
Test status
Simulation time 38848592543 ps
CPU time 496.64 seconds
Started Jun 02 03:18:21 PM PDT 24
Finished Jun 02 03:26:38 PM PDT 24
Peak memory 289776 kb
Host smart-e97bc8fb-6fe5-4b21-bb7b-523bc726e2ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767428648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.767428648
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.777472086
Short name T781
Test name
Test status
Simulation time 3791499917 ps
CPU time 10.62 seconds
Started Jun 02 03:18:32 PM PDT 24
Finished Jun 02 03:18:44 PM PDT 24
Peak memory 219780 kb
Host smart-fcd39281-5c4f-42a3-82fb-f4ae3cb181b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777472086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.777472086
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3699067737
Short name T359
Test name
Test status
Simulation time 2445116701 ps
CPU time 4.36 seconds
Started Jun 02 03:18:21 PM PDT 24
Finished Jun 02 03:18:26 PM PDT 24
Peak memory 216204 kb
Host smart-42c7c326-5483-4d8b-9c1f-030e252d953a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699067737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3699067737
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3448745343
Short name T405
Test name
Test status
Simulation time 31204916 ps
CPU time 1.28 seconds
Started Jun 02 03:18:23 PM PDT 24
Finished Jun 02 03:18:24 PM PDT 24
Peak memory 216116 kb
Host smart-867ee176-9254-4dee-a18a-9a7bee781948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448745343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3448745343
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3588898757
Short name T364
Test name
Test status
Simulation time 56879072 ps
CPU time 0.93 seconds
Started Jun 02 03:18:22 PM PDT 24
Finished Jun 02 03:18:23 PM PDT 24
Peak memory 206176 kb
Host smart-69800c47-8982-4235-af9f-6835f472f10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588898757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3588898757
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3138007510
Short name T209
Test name
Test status
Simulation time 17191402808 ps
CPU time 25.42 seconds
Started Jun 02 03:18:24 PM PDT 24
Finished Jun 02 03:18:50 PM PDT 24
Peak memory 220960 kb
Host smart-5d4234d1-235e-4da6-b222-b57048b9e19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138007510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3138007510
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2085925321
Short name T455
Test name
Test status
Simulation time 13084293 ps
CPU time 0.68 seconds
Started Jun 02 03:18:30 PM PDT 24
Finished Jun 02 03:18:31 PM PDT 24
Peak memory 204804 kb
Host smart-b730786e-bfe8-474d-b954-b633e1cad2bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085925321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2085925321
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2984249956
Short name T406
Test name
Test status
Simulation time 2307400354 ps
CPU time 9.8 seconds
Started Jun 02 03:18:31 PM PDT 24
Finished Jun 02 03:18:41 PM PDT 24
Peak memory 219700 kb
Host smart-9c7cd814-652b-4ff7-bd8a-0492820d139a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984249956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2984249956
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.111238303
Short name T354
Test name
Test status
Simulation time 18336083 ps
CPU time 0.77 seconds
Started Jun 02 03:18:21 PM PDT 24
Finished Jun 02 03:18:22 PM PDT 24
Peak memory 206432 kb
Host smart-a6ff9152-2420-4efe-b74a-d1d672f145b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111238303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.111238303
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3604953753
Short name T275
Test name
Test status
Simulation time 237711281649 ps
CPU time 334.34 seconds
Started Jun 02 03:18:30 PM PDT 24
Finished Jun 02 03:24:05 PM PDT 24
Peak memory 250708 kb
Host smart-a346a501-52e7-49fb-8c3e-702004a49e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604953753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3604953753
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3395547703
Short name T885
Test name
Test status
Simulation time 538703923 ps
CPU time 6.25 seconds
Started Jun 02 03:18:29 PM PDT 24
Finished Jun 02 03:18:36 PM PDT 24
Peak memory 235588 kb
Host smart-6a2e19c4-6506-44c2-be63-2aeb3f8a2db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395547703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3395547703
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3640538501
Short name T951
Test name
Test status
Simulation time 1384234359 ps
CPU time 3.73 seconds
Started Jun 02 03:18:27 PM PDT 24
Finished Jun 02 03:18:32 PM PDT 24
Peak memory 234804 kb
Host smart-bf6d411e-4b2f-4b2e-ab64-6a9c29a32864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640538501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3640538501
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.934360576
Short name T965
Test name
Test status
Simulation time 10569949209 ps
CPU time 27.15 seconds
Started Jun 02 03:18:29 PM PDT 24
Finished Jun 02 03:18:57 PM PDT 24
Peak memory 218624 kb
Host smart-a993718e-21d6-4442-9692-ca31cf887ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934360576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.934360576
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3199009201
Short name T526
Test name
Test status
Simulation time 491585349 ps
CPU time 5.7 seconds
Started Jun 02 03:18:26 PM PDT 24
Finished Jun 02 03:18:32 PM PDT 24
Peak memory 238336 kb
Host smart-6db8da85-a27f-478c-89bf-8faf098f38cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199009201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3199009201
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3209356109
Short name T72
Test name
Test status
Simulation time 58910408575 ps
CPU time 13.08 seconds
Started Jun 02 03:18:28 PM PDT 24
Finished Jun 02 03:18:42 PM PDT 24
Peak memory 224400 kb
Host smart-09763fd1-9e41-4413-b956-95d94ed1c2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209356109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3209356109
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.970308956
Short name T770
Test name
Test status
Simulation time 200231532 ps
CPU time 5.55 seconds
Started Jun 02 03:18:28 PM PDT 24
Finished Jun 02 03:18:34 PM PDT 24
Peak memory 222820 kb
Host smart-576579da-771b-4417-8d3a-cd3dc1b1050a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=970308956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.970308956
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1217814062
Short name T777
Test name
Test status
Simulation time 57152958310 ps
CPU time 162.49 seconds
Started Jun 02 03:18:28 PM PDT 24
Finished Jun 02 03:21:11 PM PDT 24
Peak memory 253248 kb
Host smart-1ae0f58e-f4b2-4717-a7e4-246a52616301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217814062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1217814062
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3217226265
Short name T376
Test name
Test status
Simulation time 935056346 ps
CPU time 11.12 seconds
Started Jun 02 03:18:27 PM PDT 24
Finished Jun 02 03:18:39 PM PDT 24
Peak memory 216200 kb
Host smart-282d070c-3f67-4cae-add3-6b6c2ea58507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217226265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3217226265
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1769568076
Short name T20
Test name
Test status
Simulation time 2595251848 ps
CPU time 2.97 seconds
Started Jun 02 03:18:28 PM PDT 24
Finished Jun 02 03:18:32 PM PDT 24
Peak memory 215996 kb
Host smart-c5747746-6453-4ead-8852-fc6cf3d6a43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769568076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1769568076
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2353741209
Short name T135
Test name
Test status
Simulation time 776680616 ps
CPU time 4.57 seconds
Started Jun 02 03:18:30 PM PDT 24
Finished Jun 02 03:18:35 PM PDT 24
Peak memory 216204 kb
Host smart-60fddef0-3346-44f6-8279-6ced011469e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353741209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2353741209
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1632247209
Short name T372
Test name
Test status
Simulation time 107103895 ps
CPU time 0.72 seconds
Started Jun 02 03:18:29 PM PDT 24
Finished Jun 02 03:18:30 PM PDT 24
Peak memory 205612 kb
Host smart-190eacd0-5ac3-4459-89d2-2492259031be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632247209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1632247209
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.256560
Short name T418
Test name
Test status
Simulation time 484877878 ps
CPU time 6.25 seconds
Started Jun 02 03:18:29 PM PDT 24
Finished Jun 02 03:18:36 PM PDT 24
Peak memory 232624 kb
Host smart-8150e582-21bd-481d-8df7-983b994b5400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.256560
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.313797781
Short name T350
Test name
Test status
Simulation time 15805329 ps
CPU time 0.73 seconds
Started Jun 02 03:18:34 PM PDT 24
Finished Jun 02 03:18:35 PM PDT 24
Peak memory 204832 kb
Host smart-7ed7b047-6638-4ddd-8a9e-863971b1dd12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313797781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.313797781
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.117134320
Short name T796
Test name
Test status
Simulation time 5852089018 ps
CPU time 5.98 seconds
Started Jun 02 03:18:35 PM PDT 24
Finished Jun 02 03:18:42 PM PDT 24
Peak memory 217724 kb
Host smart-71626973-0c2d-4521-9f30-c351b303ca05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117134320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.117134320
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2931974924
Short name T593
Test name
Test status
Simulation time 40143496 ps
CPU time 0.75 seconds
Started Jun 02 03:18:29 PM PDT 24
Finished Jun 02 03:18:30 PM PDT 24
Peak memory 205660 kb
Host smart-25b6319f-e413-4404-8fb9-28c45e29b1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931974924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2931974924
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3263746224
Short name T738
Test name
Test status
Simulation time 58633349 ps
CPU time 0.77 seconds
Started Jun 02 03:18:36 PM PDT 24
Finished Jun 02 03:18:37 PM PDT 24
Peak memory 215740 kb
Host smart-c77af00a-9b89-44a3-a901-5e7b52501dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263746224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3263746224
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1720732527
Short name T35
Test name
Test status
Simulation time 126890667932 ps
CPU time 371.31 seconds
Started Jun 02 03:18:36 PM PDT 24
Finished Jun 02 03:24:48 PM PDT 24
Peak memory 262716 kb
Host smart-ce1c01b2-f59d-4e79-a8f2-f4053ad6a5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720732527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1720732527
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3614622169
Short name T224
Test name
Test status
Simulation time 498887853542 ps
CPU time 355.51 seconds
Started Jun 02 03:18:33 PM PDT 24
Finished Jun 02 03:24:29 PM PDT 24
Peak memory 252960 kb
Host smart-4bc845d3-c960-4d21-8991-00dbfe3a16d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614622169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3614622169
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1999002859
Short name T304
Test name
Test status
Simulation time 7481175417 ps
CPU time 29.1 seconds
Started Jun 02 03:18:37 PM PDT 24
Finished Jun 02 03:19:07 PM PDT 24
Peak memory 232624 kb
Host smart-41569e4b-9758-45b1-878b-5828fefb83f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999002859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1999002859
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3701086103
Short name T241
Test name
Test status
Simulation time 4438980039 ps
CPU time 11.08 seconds
Started Jun 02 03:18:27 PM PDT 24
Finished Jun 02 03:18:39 PM PDT 24
Peak memory 233828 kb
Host smart-49ae3127-1aaa-44f9-8b76-4afd6e5b4336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701086103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3701086103
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1008153037
Short name T198
Test name
Test status
Simulation time 574619283 ps
CPU time 10.34 seconds
Started Jun 02 03:18:28 PM PDT 24
Finished Jun 02 03:18:39 PM PDT 24
Peak memory 237436 kb
Host smart-7d1f8b7d-98db-4e7d-9537-caed3917ad9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008153037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1008153037
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.121086286
Short name T267
Test name
Test status
Simulation time 3184433501 ps
CPU time 3.69 seconds
Started Jun 02 03:18:29 PM PDT 24
Finished Jun 02 03:18:33 PM PDT 24
Peak memory 234820 kb
Host smart-8c082aa3-35ad-46b6-9a41-5b4908999176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121086286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.121086286
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3202140373
Short name T93
Test name
Test status
Simulation time 4311551915 ps
CPU time 12.49 seconds
Started Jun 02 03:18:30 PM PDT 24
Finished Jun 02 03:18:43 PM PDT 24
Peak memory 218844 kb
Host smart-4048ef01-04d9-4f83-a5dc-e9f6c24a24ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202140373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3202140373
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1824907005
Short name T548
Test name
Test status
Simulation time 278182626 ps
CPU time 5.58 seconds
Started Jun 02 03:18:35 PM PDT 24
Finished Jun 02 03:18:41 PM PDT 24
Peak memory 221648 kb
Host smart-cdd57c73-c0e5-4aaf-a8db-c480c8c808f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1824907005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1824907005
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.50292945
Short name T175
Test name
Test status
Simulation time 107140606126 ps
CPU time 285.92 seconds
Started Jun 02 03:18:34 PM PDT 24
Finished Jun 02 03:23:21 PM PDT 24
Peak memory 265500 kb
Host smart-26bc8d8c-8cc3-4654-a24b-94798d1f603a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50292945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress
_all.50292945
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1137545918
Short name T637
Test name
Test status
Simulation time 1948470661 ps
CPU time 21.86 seconds
Started Jun 02 03:18:28 PM PDT 24
Finished Jun 02 03:18:50 PM PDT 24
Peak memory 216448 kb
Host smart-4560cd72-ad23-403d-9f98-b104ccedb83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137545918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1137545918
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1832396490
Short name T473
Test name
Test status
Simulation time 2615743824 ps
CPU time 5.22 seconds
Started Jun 02 03:18:27 PM PDT 24
Finished Jun 02 03:18:33 PM PDT 24
Peak memory 216144 kb
Host smart-788ceeee-f988-4082-906c-3b2cf053d847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832396490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1832396490
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1729492944
Short name T498
Test name
Test status
Simulation time 282930140 ps
CPU time 4.03 seconds
Started Jun 02 03:18:30 PM PDT 24
Finished Jun 02 03:18:35 PM PDT 24
Peak memory 216184 kb
Host smart-530ddf3d-f3d3-4099-a970-883758f82726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729492944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1729492944
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1431459396
Short name T732
Test name
Test status
Simulation time 29885409 ps
CPU time 0.77 seconds
Started Jun 02 03:18:27 PM PDT 24
Finished Jun 02 03:18:29 PM PDT 24
Peak memory 205664 kb
Host smart-863019be-22ec-41b5-83fc-ca62730d74e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431459396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1431459396
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1959302399
Short name T49
Test name
Test status
Simulation time 1412955297 ps
CPU time 3.94 seconds
Started Jun 02 03:18:27 PM PDT 24
Finished Jun 02 03:18:32 PM PDT 24
Peak memory 234536 kb
Host smart-5e7d216f-99e6-4f6e-8174-f51905bad8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959302399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1959302399
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1963515407
Short name T747
Test name
Test status
Simulation time 45497952 ps
CPU time 0.68 seconds
Started Jun 02 03:15:36 PM PDT 24
Finished Jun 02 03:15:37 PM PDT 24
Peak memory 205336 kb
Host smart-0b48038a-9294-408e-8a22-ee1c06d96025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963515407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
963515407
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.608863832
Short name T463
Test name
Test status
Simulation time 496904055 ps
CPU time 4.52 seconds
Started Jun 02 03:15:34 PM PDT 24
Finished Jun 02 03:15:39 PM PDT 24
Peak memory 234068 kb
Host smart-39cf4866-c4e0-45f0-9609-5e13a9379a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608863832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.608863832
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4272466136
Short name T484
Test name
Test status
Simulation time 58650573 ps
CPU time 0.8 seconds
Started Jun 02 03:15:28 PM PDT 24
Finished Jun 02 03:15:30 PM PDT 24
Peak memory 206760 kb
Host smart-0086cafe-b554-4f1e-8b11-5dbb68acf8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272466136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4272466136
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3118096363
Short name T240
Test name
Test status
Simulation time 8521129229 ps
CPU time 17.21 seconds
Started Jun 02 03:15:35 PM PDT 24
Finished Jun 02 03:15:53 PM PDT 24
Peak memory 235096 kb
Host smart-f161736e-0f3a-4ccc-ab9d-b4ad068867c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118096363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3118096363
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2320762166
Short name T138
Test name
Test status
Simulation time 7520977250 ps
CPU time 126.36 seconds
Started Jun 02 03:15:34 PM PDT 24
Finished Jun 02 03:17:41 PM PDT 24
Peak memory 256848 kb
Host smart-5cdcc998-d1fb-4179-b571-3388fd5ac571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320762166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2320762166
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1209364828
Short name T45
Test name
Test status
Simulation time 26267970682 ps
CPU time 40.98 seconds
Started Jun 02 03:15:34 PM PDT 24
Finished Jun 02 03:16:16 PM PDT 24
Peak memory 238260 kb
Host smart-08294b81-5e90-49b9-b39b-c33fad5a9fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209364828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1209364828
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2260828682
Short name T557
Test name
Test status
Simulation time 110553362 ps
CPU time 3.52 seconds
Started Jun 02 03:15:35 PM PDT 24
Finished Jun 02 03:15:39 PM PDT 24
Peak memory 224372 kb
Host smart-bbd72696-6943-4abf-a0ea-ff0c5a59c72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260828682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2260828682
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3395883851
Short name T724
Test name
Test status
Simulation time 114972183 ps
CPU time 2.57 seconds
Started Jun 02 03:15:33 PM PDT 24
Finished Jun 02 03:15:36 PM PDT 24
Peak memory 234920 kb
Host smart-64e74b39-1e37-4963-9a08-0948f7f16149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395883851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3395883851
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2948806734
Short name T794
Test name
Test status
Simulation time 1992639171 ps
CPU time 27.67 seconds
Started Jun 02 03:15:32 PM PDT 24
Finished Jun 02 03:16:00 PM PDT 24
Peak memory 227640 kb
Host smart-434e9b6b-a722-49ea-a33c-b20576e3d086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948806734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2948806734
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3651306519
Short name T519
Test name
Test status
Simulation time 339704884 ps
CPU time 3.83 seconds
Started Jun 02 03:15:35 PM PDT 24
Finished Jun 02 03:15:39 PM PDT 24
Peak memory 233252 kb
Host smart-9737f0c3-2b9c-4eee-8b60-770f2500728a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651306519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3651306519
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2978977085
Short name T36
Test name
Test status
Simulation time 1127641503 ps
CPU time 2.5 seconds
Started Jun 02 03:15:33 PM PDT 24
Finished Jun 02 03:15:36 PM PDT 24
Peak memory 216776 kb
Host smart-a0b6a6cc-060a-4af8-8d9c-b12426b53448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978977085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2978977085
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3332815394
Short name T132
Test name
Test status
Simulation time 1692259639 ps
CPU time 12.85 seconds
Started Jun 02 03:15:33 PM PDT 24
Finished Jun 02 03:15:47 PM PDT 24
Peak memory 221924 kb
Host smart-02a644f1-1580-4274-931a-ea1407250f09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3332815394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3332815394
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1822850664
Short name T609
Test name
Test status
Simulation time 81604588497 ps
CPU time 125.12 seconds
Started Jun 02 03:15:33 PM PDT 24
Finished Jun 02 03:17:39 PM PDT 24
Peak memory 252224 kb
Host smart-be86e951-734b-4bdb-8096-21130ac2fecf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822850664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1822850664
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3165334600
Short name T782
Test name
Test status
Simulation time 23074276141 ps
CPU time 38.74 seconds
Started Jun 02 03:15:33 PM PDT 24
Finished Jun 02 03:16:12 PM PDT 24
Peak memory 216108 kb
Host smart-6bc85f32-22d9-4c42-824c-1461015ce152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165334600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3165334600
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3593468049
Short name T353
Test name
Test status
Simulation time 43242214 ps
CPU time 0.7 seconds
Started Jun 02 03:15:35 PM PDT 24
Finished Jun 02 03:15:36 PM PDT 24
Peak memory 205408 kb
Host smart-5d6f11d4-8691-4c9d-87a8-2f6f96107cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593468049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3593468049
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2947033941
Short name T512
Test name
Test status
Simulation time 73656031 ps
CPU time 1 seconds
Started Jun 02 03:15:34 PM PDT 24
Finished Jun 02 03:15:35 PM PDT 24
Peak memory 207424 kb
Host smart-65e8eb6d-11fe-48ae-b843-d775f492c5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947033941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2947033941
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3014459319
Short name T333
Test name
Test status
Simulation time 90988722 ps
CPU time 1.04 seconds
Started Jun 02 03:15:31 PM PDT 24
Finished Jun 02 03:15:33 PM PDT 24
Peak memory 205612 kb
Host smart-2148a5cd-c361-40b1-bee0-2411d3157bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014459319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3014459319
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2748486746
Short name T851
Test name
Test status
Simulation time 18835151592 ps
CPU time 19.36 seconds
Started Jun 02 03:15:35 PM PDT 24
Finished Jun 02 03:15:55 PM PDT 24
Peak memory 239732 kb
Host smart-1b0666eb-de02-4af7-8118-e44560d7f8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748486746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2748486746
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.584045142
Short name T601
Test name
Test status
Simulation time 48772836 ps
CPU time 0.74 seconds
Started Jun 02 03:15:39 PM PDT 24
Finished Jun 02 03:15:40 PM PDT 24
Peak memory 205344 kb
Host smart-725f5224-06dc-4687-8daa-3ffc697613e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584045142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.584045142
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1204379758
Short name T362
Test name
Test status
Simulation time 19350703809 ps
CPU time 53.15 seconds
Started Jun 02 03:15:39 PM PDT 24
Finished Jun 02 03:16:33 PM PDT 24
Peak memory 220444 kb
Host smart-39e0c69f-1d7e-46a6-9e24-832f2e4ee570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204379758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1204379758
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.4267350573
Short name T58
Test name
Test status
Simulation time 13574394 ps
CPU time 0.77 seconds
Started Jun 02 03:15:32 PM PDT 24
Finished Jun 02 03:15:34 PM PDT 24
Peak memory 206456 kb
Host smart-0d63a9a5-969f-449d-bf85-25b51b357311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267350573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.4267350573
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3062007812
Short name T508
Test name
Test status
Simulation time 7026516844 ps
CPU time 39.8 seconds
Started Jun 02 03:15:40 PM PDT 24
Finished Jun 02 03:16:20 PM PDT 24
Peak memory 253652 kb
Host smart-f626ba64-3ce2-4f07-a8de-93d26376ec4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062007812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3062007812
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2875770387
Short name T239
Test name
Test status
Simulation time 6863966944 ps
CPU time 113.09 seconds
Started Jun 02 03:15:40 PM PDT 24
Finished Jun 02 03:17:34 PM PDT 24
Peak memory 256124 kb
Host smart-73462580-2bc7-4fd2-8ebb-eea27df29696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875770387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2875770387
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.452036947
Short name T79
Test name
Test status
Simulation time 68582001850 ps
CPU time 613.85 seconds
Started Jun 02 03:15:39 PM PDT 24
Finished Jun 02 03:25:53 PM PDT 24
Peak memory 254936 kb
Host smart-8484a7d1-cc67-4b80-aea0-3f1f0749ea49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452036947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
452036947
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3411294843
Short name T169
Test name
Test status
Simulation time 1832115025 ps
CPU time 7.92 seconds
Started Jun 02 03:15:40 PM PDT 24
Finished Jun 02 03:15:49 PM PDT 24
Peak memory 232512 kb
Host smart-ffddd442-c90a-4cbf-8823-9bebe7c5c791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411294843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3411294843
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2749513014
Short name T195
Test name
Test status
Simulation time 434510734 ps
CPU time 6.44 seconds
Started Jun 02 03:15:46 PM PDT 24
Finished Jun 02 03:15:53 PM PDT 24
Peak memory 218612 kb
Host smart-c91e032d-42ad-4882-8688-99d82cdd8a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749513014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2749513014
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3713532138
Short name T565
Test name
Test status
Simulation time 269932845 ps
CPU time 6.8 seconds
Started Jun 02 03:15:43 PM PDT 24
Finished Jun 02 03:15:50 PM PDT 24
Peak memory 233900 kb
Host smart-ea0d6ccc-73b9-4ad5-9ef9-9a5ebd8a168e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713532138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3713532138
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2859305266
Short name T576
Test name
Test status
Simulation time 1107594305 ps
CPU time 4.57 seconds
Started Jun 02 03:15:42 PM PDT 24
Finished Jun 02 03:15:47 PM PDT 24
Peak memory 235492 kb
Host smart-0ef86dd8-daab-482e-8630-a784c7e0e9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859305266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2859305266
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.188718457
Short name T502
Test name
Test status
Simulation time 41906957426 ps
CPU time 27.6 seconds
Started Jun 02 03:15:47 PM PDT 24
Finished Jun 02 03:16:15 PM PDT 24
Peak memory 238144 kb
Host smart-a9ebef81-86c4-4274-89c7-5419c3117be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188718457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.188718457
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.99685440
Short name T959
Test name
Test status
Simulation time 6168520368 ps
CPU time 12.38 seconds
Started Jun 02 03:15:45 PM PDT 24
Finished Jun 02 03:15:58 PM PDT 24
Peak memory 218912 kb
Host smart-9aa5add3-5ba9-484c-9645-a5c4c58f5b46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=99685440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct
.99685440
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3493018760
Short name T616
Test name
Test status
Simulation time 20715017 ps
CPU time 0.75 seconds
Started Jun 02 03:15:43 PM PDT 24
Finished Jun 02 03:15:45 PM PDT 24
Peak memory 205316 kb
Host smart-219a3dc7-7e14-4e39-a096-ac7bcbdd87d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493018760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3493018760
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3945178230
Short name T417
Test name
Test status
Simulation time 20432517627 ps
CPU time 13.47 seconds
Started Jun 02 03:15:47 PM PDT 24
Finished Jun 02 03:16:01 PM PDT 24
Peak memory 216160 kb
Host smart-6713dbcd-d2b3-458c-bd2c-ff08b0a596cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945178230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3945178230
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.437155229
Short name T365
Test name
Test status
Simulation time 299200703 ps
CPU time 1.78 seconds
Started Jun 02 03:15:42 PM PDT 24
Finished Jun 02 03:15:44 PM PDT 24
Peak memory 216136 kb
Host smart-51e4ad89-1b1a-440f-8cf8-18a624aa704e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437155229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.437155229
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3602716862
Short name T662
Test name
Test status
Simulation time 222965287 ps
CPU time 0.89 seconds
Started Jun 02 03:15:40 PM PDT 24
Finished Jun 02 03:15:42 PM PDT 24
Peak memory 205596 kb
Host smart-5a661b8b-d228-47e8-bfd5-005517c43cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602716862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3602716862
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2172029373
Short name T420
Test name
Test status
Simulation time 586943425 ps
CPU time 7.21 seconds
Started Jun 02 03:15:42 PM PDT 24
Finished Jun 02 03:15:50 PM PDT 24
Peak memory 234136 kb
Host smart-029e0408-3b83-42f6-b46d-810521091eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172029373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2172029373
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4285368547
Short name T385
Test name
Test status
Simulation time 42099960 ps
CPU time 0.68 seconds
Started Jun 02 03:15:45 PM PDT 24
Finished Jun 02 03:15:46 PM PDT 24
Peak memory 204820 kb
Host smart-8428aeff-b98b-4889-82ed-6b76f48d3592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285368547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
285368547
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.265593950
Short name T748
Test name
Test status
Simulation time 660440367 ps
CPU time 4.44 seconds
Started Jun 02 03:15:41 PM PDT 24
Finished Jun 02 03:15:46 PM PDT 24
Peak memory 233948 kb
Host smart-5332bdca-9b48-4233-9ce6-9813e7720f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265593950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.265593950
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.788932025
Short name T351
Test name
Test status
Simulation time 53814013 ps
CPU time 0.75 seconds
Started Jun 02 03:15:41 PM PDT 24
Finished Jun 02 03:15:42 PM PDT 24
Peak memory 205356 kb
Host smart-3013aac9-ec45-43b7-8803-d8436d547c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788932025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.788932025
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3568994359
Short name T622
Test name
Test status
Simulation time 32018893925 ps
CPU time 116.78 seconds
Started Jun 02 03:15:52 PM PDT 24
Finished Jun 02 03:17:50 PM PDT 24
Peak memory 250092 kb
Host smart-5f1a7f7a-dfa0-4f41-a786-2a73a6f8bb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568994359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3568994359
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2086955448
Short name T233
Test name
Test status
Simulation time 15052307426 ps
CPU time 75.4 seconds
Started Jun 02 03:15:47 PM PDT 24
Finished Jun 02 03:17:03 PM PDT 24
Peak memory 249352 kb
Host smart-2e360604-c28b-4cf4-9b2c-6e597ac415a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086955448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2086955448
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1201980356
Short name T281
Test name
Test status
Simulation time 4375391234 ps
CPU time 29.27 seconds
Started Jun 02 03:15:47 PM PDT 24
Finished Jun 02 03:16:17 PM PDT 24
Peak memory 238352 kb
Host smart-ff05529c-8597-404d-8305-e40919ca0651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201980356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1201980356
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4098837005
Short name T922
Test name
Test status
Simulation time 4455611077 ps
CPU time 40.5 seconds
Started Jun 02 03:15:38 PM PDT 24
Finished Jun 02 03:16:18 PM PDT 24
Peak memory 232680 kb
Host smart-f99689e9-5a4c-4d52-ab82-1d77242d2578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098837005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4098837005
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1984078041
Short name T822
Test name
Test status
Simulation time 119479903 ps
CPU time 2.41 seconds
Started Jun 02 03:15:45 PM PDT 24
Finished Jun 02 03:15:48 PM PDT 24
Peak memory 232660 kb
Host smart-0eaec3e4-628d-4c93-8a4b-6c2f5ec0f603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984078041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1984078041
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.480517833
Short name T661
Test name
Test status
Simulation time 5410454466 ps
CPU time 54.83 seconds
Started Jun 02 03:15:41 PM PDT 24
Finished Jun 02 03:16:36 PM PDT 24
Peak memory 234016 kb
Host smart-4f8dae10-6412-4584-b036-ed65b9138323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480517833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.480517833
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1291251820
Short name T939
Test name
Test status
Simulation time 1022736971 ps
CPU time 8.59 seconds
Started Jun 02 03:15:41 PM PDT 24
Finished Jun 02 03:15:50 PM PDT 24
Peak memory 233824 kb
Host smart-678549e9-96a2-4f7a-8ac0-f912c99797d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291251820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1291251820
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2803295879
Short name T595
Test name
Test status
Simulation time 872181739 ps
CPU time 9.66 seconds
Started Jun 02 03:15:48 PM PDT 24
Finished Jun 02 03:15:58 PM PDT 24
Peak memory 221268 kb
Host smart-f3b16199-19bf-4778-b3ef-1af2df9f1884
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2803295879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2803295879
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.934403989
Short name T917
Test name
Test status
Simulation time 24189240764 ps
CPU time 92.32 seconds
Started Jun 02 03:15:49 PM PDT 24
Finished Jun 02 03:17:22 PM PDT 24
Peak memory 250592 kb
Host smart-2c27f11a-faf4-40d3-92a7-53ebb7d3673e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934403989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.934403989
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.918993759
Short name T511
Test name
Test status
Simulation time 1982896914 ps
CPU time 8.5 seconds
Started Jun 02 03:15:39 PM PDT 24
Finished Jun 02 03:15:49 PM PDT 24
Peak memory 216496 kb
Host smart-8ce72bf8-7b2b-4027-ac6b-f5ed130cf858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918993759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.918993759
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2074692707
Short name T361
Test name
Test status
Simulation time 19043238169 ps
CPU time 27.5 seconds
Started Jun 02 03:15:43 PM PDT 24
Finished Jun 02 03:16:11 PM PDT 24
Peak memory 215944 kb
Host smart-38854cff-8281-49bf-8a14-330e4d5d82aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074692707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2074692707
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3476364695
Short name T466
Test name
Test status
Simulation time 215360314 ps
CPU time 5.96 seconds
Started Jun 02 03:15:39 PM PDT 24
Finished Jun 02 03:15:46 PM PDT 24
Peak memory 216272 kb
Host smart-97882a19-ad13-4c13-885e-a9e19b28a7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476364695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3476364695
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3472604867
Short name T779
Test name
Test status
Simulation time 116122251 ps
CPU time 1 seconds
Started Jun 02 03:15:42 PM PDT 24
Finished Jun 02 03:15:43 PM PDT 24
Peak memory 206632 kb
Host smart-3bac0ccc-a902-478a-97da-ef714cdaf4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472604867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3472604867
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2727747763
Short name T505
Test name
Test status
Simulation time 1016100240 ps
CPU time 2.96 seconds
Started Jun 02 03:15:38 PM PDT 24
Finished Jun 02 03:15:42 PM PDT 24
Peak memory 233488 kb
Host smart-150a0914-51cc-49ab-ad1c-8a17bff8c1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727747763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2727747763
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1278648263
Short name T501
Test name
Test status
Simulation time 23361244 ps
CPU time 0.77 seconds
Started Jun 02 03:15:50 PM PDT 24
Finished Jun 02 03:15:51 PM PDT 24
Peak memory 205324 kb
Host smart-b3f14da1-7cec-43e4-9069-2a70e2729de1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278648263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
278648263
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.576929126
Short name T820
Test name
Test status
Simulation time 1129505561 ps
CPU time 4.71 seconds
Started Jun 02 03:15:46 PM PDT 24
Finished Jun 02 03:15:52 PM PDT 24
Peak memory 234356 kb
Host smart-4d55a4c9-8956-4147-bd07-e07db45e4aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576929126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.576929126
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1884661962
Short name T549
Test name
Test status
Simulation time 165279346 ps
CPU time 0.82 seconds
Started Jun 02 03:15:47 PM PDT 24
Finished Jun 02 03:15:48 PM PDT 24
Peak memory 206436 kb
Host smart-8a9706e9-9c21-42f6-9123-4ab7d5d94fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884661962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1884661962
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.288645539
Short name T537
Test name
Test status
Simulation time 1866403615 ps
CPU time 22.72 seconds
Started Jun 02 03:15:47 PM PDT 24
Finished Jun 02 03:16:10 PM PDT 24
Peak memory 248480 kb
Host smart-4e41f9bf-3f62-4a93-8e65-f596a810f0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288645539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.288645539
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.581618301
Short name T685
Test name
Test status
Simulation time 6778216153 ps
CPU time 91.83 seconds
Started Jun 02 03:15:46 PM PDT 24
Finished Jun 02 03:17:18 PM PDT 24
Peak memory 255520 kb
Host smart-3aff79f7-0a86-4f92-b89e-31837c4bd684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581618301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.581618301
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3276505647
Short name T166
Test name
Test status
Simulation time 15992944603 ps
CPU time 156.36 seconds
Started Jun 02 03:15:48 PM PDT 24
Finished Jun 02 03:18:25 PM PDT 24
Peak memory 250628 kb
Host smart-2ea22616-e3a3-48b5-b62d-d33b0c8d916b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276505647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3276505647
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3915627685
Short name T655
Test name
Test status
Simulation time 95392550 ps
CPU time 3.33 seconds
Started Jun 02 03:15:46 PM PDT 24
Finished Jun 02 03:15:50 PM PDT 24
Peak memory 224336 kb
Host smart-24939b2f-cb8d-4061-bf78-8df4602103ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915627685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3915627685
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2421866958
Short name T242
Test name
Test status
Simulation time 6376103845 ps
CPU time 20.92 seconds
Started Jun 02 03:15:46 PM PDT 24
Finished Jun 02 03:16:07 PM PDT 24
Peak memory 234028 kb
Host smart-b9dbe2d3-fdb1-4e2f-ab9c-1ce37fd170d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421866958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2421866958
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.138152878
Short name T833
Test name
Test status
Simulation time 11031543273 ps
CPU time 40.56 seconds
Started Jun 02 03:15:47 PM PDT 24
Finished Jun 02 03:16:29 PM PDT 24
Peak memory 218536 kb
Host smart-603e70ab-36df-4624-acf7-03e20c998918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138152878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.138152878
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1036893640
Short name T521
Test name
Test status
Simulation time 1187006025 ps
CPU time 3.5 seconds
Started Jun 02 03:15:50 PM PDT 24
Finished Jun 02 03:15:54 PM PDT 24
Peak memory 234348 kb
Host smart-5d5d5b42-0d9f-455c-9462-d1c220ab9b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036893640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1036893640
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2883762810
Short name T877
Test name
Test status
Simulation time 159125095 ps
CPU time 2.63 seconds
Started Jun 02 03:15:47 PM PDT 24
Finished Jun 02 03:15:50 PM PDT 24
Peak memory 232976 kb
Host smart-c543e297-b022-4ca3-b9fd-a87aa5f6a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883762810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2883762810
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.952591888
Short name T912
Test name
Test status
Simulation time 618539122 ps
CPU time 3.74 seconds
Started Jun 02 03:15:50 PM PDT 24
Finished Jun 02 03:15:54 PM PDT 24
Peak memory 219068 kb
Host smart-cf1dff04-f7bc-47b3-9e75-b3d08eb4e876
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=952591888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.952591888
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3969309533
Short name T897
Test name
Test status
Simulation time 8542542855 ps
CPU time 31.19 seconds
Started Jun 02 03:15:48 PM PDT 24
Finished Jun 02 03:16:20 PM PDT 24
Peak memory 216364 kb
Host smart-6850901e-46b9-4c94-b4d3-af79393272b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969309533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3969309533
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.90733527
Short name T495
Test name
Test status
Simulation time 8125984178 ps
CPU time 6.73 seconds
Started Jun 02 03:15:52 PM PDT 24
Finished Jun 02 03:16:00 PM PDT 24
Peak memory 216168 kb
Host smart-607d9993-4e1e-4af1-9c4c-229c52531348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90733527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.90733527
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3432004014
Short name T687
Test name
Test status
Simulation time 236436234 ps
CPU time 0.93 seconds
Started Jun 02 03:15:47 PM PDT 24
Finished Jun 02 03:15:49 PM PDT 24
Peak memory 205728 kb
Host smart-bf6f3854-b178-4efd-8f43-de4c9460dab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432004014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3432004014
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1891883305
Short name T421
Test name
Test status
Simulation time 31422730 ps
CPU time 0.83 seconds
Started Jun 02 03:15:46 PM PDT 24
Finished Jun 02 03:15:48 PM PDT 24
Peak memory 205568 kb
Host smart-031084aa-bb1a-4602-bc5e-6cb93945837c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891883305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1891883305
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4134889858
Short name T270
Test name
Test status
Simulation time 625377862 ps
CPU time 5.92 seconds
Started Jun 02 03:15:47 PM PDT 24
Finished Jun 02 03:15:54 PM PDT 24
Peak memory 217916 kb
Host smart-fbf0210d-691b-4ec8-84bf-04d898caf3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134889858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4134889858
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1180311269
Short name T654
Test name
Test status
Simulation time 13702405 ps
CPU time 0.74 seconds
Started Jun 02 03:15:53 PM PDT 24
Finished Jun 02 03:15:54 PM PDT 24
Peak memory 204832 kb
Host smart-e054c35c-1b2d-4d93-874c-3c19cb049bca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180311269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
180311269
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2390470591
Short name T759
Test name
Test status
Simulation time 951628983 ps
CPU time 8.6 seconds
Started Jun 02 03:16:00 PM PDT 24
Finished Jun 02 03:16:09 PM PDT 24
Peak memory 217552 kb
Host smart-da85bc90-14e2-426d-8342-a8de5dca7af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390470591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2390470591
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1257308173
Short name T863
Test name
Test status
Simulation time 82101888 ps
CPU time 0.82 seconds
Started Jun 02 03:15:45 PM PDT 24
Finished Jun 02 03:15:46 PM PDT 24
Peak memory 206696 kb
Host smart-dd8ae2d7-e423-413d-b910-2cdb2c269062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257308173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1257308173
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1935585074
Short name T370
Test name
Test status
Simulation time 14200591126 ps
CPU time 100.29 seconds
Started Jun 02 03:15:52 PM PDT 24
Finished Jun 02 03:17:33 PM PDT 24
Peak memory 249016 kb
Host smart-1291acc3-29f5-453f-b5d2-51bd6c4c0ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935585074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1935585074
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.614636900
Short name T419
Test name
Test status
Simulation time 10622330047 ps
CPU time 19.81 seconds
Started Jun 02 03:15:54 PM PDT 24
Finished Jun 02 03:16:14 PM PDT 24
Peak memory 217252 kb
Host smart-a974d156-7aa9-4cc4-b7f2-49b6ccc93695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614636900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
614636900
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4243259792
Short name T441
Test name
Test status
Simulation time 1598935469 ps
CPU time 6.01 seconds
Started Jun 02 03:15:55 PM PDT 24
Finished Jun 02 03:16:01 PM PDT 24
Peak memory 238144 kb
Host smart-18ef292f-7323-4cb1-b545-54330d03d2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243259792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4243259792
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3515394997
Short name T268
Test name
Test status
Simulation time 469727119 ps
CPU time 3.06 seconds
Started Jun 02 03:15:55 PM PDT 24
Finished Jun 02 03:15:58 PM PDT 24
Peak memory 217968 kb
Host smart-61f734e6-932c-4beb-bd28-7907c4f5dbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515394997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3515394997
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.895903993
Short name T470
Test name
Test status
Simulation time 116084242 ps
CPU time 2.67 seconds
Started Jun 02 03:15:56 PM PDT 24
Finished Jun 02 03:15:59 PM PDT 24
Peak memory 218400 kb
Host smart-ce334b2e-c384-42cd-9b50-48f3377cc67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895903993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.895903993
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1832376324
Short name T826
Test name
Test status
Simulation time 789797256 ps
CPU time 5.24 seconds
Started Jun 02 03:15:52 PM PDT 24
Finished Jun 02 03:15:58 PM PDT 24
Peak memory 218436 kb
Host smart-4de60023-05d1-43da-a8dc-e285ac1af886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832376324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1832376324
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1506377863
Short name T522
Test name
Test status
Simulation time 196459511 ps
CPU time 2.26 seconds
Started Jun 02 03:15:56 PM PDT 24
Finished Jun 02 03:15:59 PM PDT 24
Peak memory 218660 kb
Host smart-19b269c1-9ae7-4956-889e-75de057b9fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506377863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1506377863
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2618216269
Short name T566
Test name
Test status
Simulation time 130693343 ps
CPU time 4.69 seconds
Started Jun 02 03:15:55 PM PDT 24
Finished Jun 02 03:16:00 PM PDT 24
Peak memory 222652 kb
Host smart-20562db2-60d8-40a0-8d52-f17fe4cfa6a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2618216269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2618216269
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2057590608
Short name T282
Test name
Test status
Simulation time 299225661734 ps
CPU time 543.58 seconds
Started Jun 02 03:15:59 PM PDT 24
Finished Jun 02 03:25:03 PM PDT 24
Peak memory 272884 kb
Host smart-e13ee248-a39d-4bc6-b52a-c14f67bc6e31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057590608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2057590608
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.986101490
Short name T412
Test name
Test status
Simulation time 332479209 ps
CPU time 2.08 seconds
Started Jun 02 03:15:47 PM PDT 24
Finished Jun 02 03:15:50 PM PDT 24
Peak memory 216180 kb
Host smart-337724a5-726e-4b3c-8f4f-e8664ad75583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986101490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.986101490
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3883981203
Short name T539
Test name
Test status
Simulation time 481580306 ps
CPU time 2.37 seconds
Started Jun 02 03:15:51 PM PDT 24
Finished Jun 02 03:15:54 PM PDT 24
Peak memory 207652 kb
Host smart-b2ebbff5-b4c9-45cb-a488-bd26aaf3d995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883981203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3883981203
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1380839270
Short name T949
Test name
Test status
Simulation time 346494884 ps
CPU time 5.36 seconds
Started Jun 02 03:15:53 PM PDT 24
Finished Jun 02 03:15:59 PM PDT 24
Peak memory 216152 kb
Host smart-77b13912-7a39-479a-bd1c-8f34676d70a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380839270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1380839270
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2627910186
Short name T556
Test name
Test status
Simulation time 222041199 ps
CPU time 0.9 seconds
Started Jun 02 03:15:47 PM PDT 24
Finished Jun 02 03:15:49 PM PDT 24
Peak memory 205656 kb
Host smart-e3b596eb-7841-4bdd-bb68-66b2e16159fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627910186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2627910186
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3739866552
Short name T676
Test name
Test status
Simulation time 84461597 ps
CPU time 2.13 seconds
Started Jun 02 03:16:05 PM PDT 24
Finished Jun 02 03:16:07 PM PDT 24
Peak memory 216228 kb
Host smart-229271c1-fe5d-4ced-8056-82d8e002b5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739866552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3739866552
Directory /workspace/9.spi_device_upload/latest
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