Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3494565	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3862256

1

T1

1616

T2

883

T3

895

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4171193	1			T1	937		T2	5		T3	7
values[0x0]	1591585	1			T1	579		T2	431		T3	405
values[0x1]	1594043	1			T1	561		T2	448		T3	490

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2480339	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4876482

1

T1

1707

T2

883

T3

895

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26264	1			T1	8		T2	5		T3	2
valid_sources[0x01]	30444	1			T1	11		T2	4		T3	4
valid_sources[0x02]	24765	1			T1	7		T2	2		T3	6
valid_sources[0x03]	43548	1			T1	5		T2	3		T4	29
valid_sources[0x04]	27444	1			T1	3		T2	4		T3	2
valid_sources[0x05]	27006	1			T1	9		T2	5		T3	3
valid_sources[0x06]	26760	1			T1	9		T2	1		T3	1
valid_sources[0x07]	27257	1			T1	3		T2	6		T3	7
valid_sources[0x08]	30047	1			T1	8		T2	1		T3	4
valid_sources[0x09]	39039	1			T1	4		T2	1		T3	4
valid_sources[0x0a]	26615	1			T1	8		T2	5		T3	12
valid_sources[0x0b]	29397	1			T1	10		T2	3		T4	26
valid_sources[0x0c]	27313	1			T1	6		T2	7		T3	2
valid_sources[0x0d]	29333	1			T1	8		T2	3		T3	9
valid_sources[0x0e]	26220	1			T1	11		T2	4		T3	6
valid_sources[0x0f]	26425	1			T1	18		T2	3		T3	2
valid_sources[0x10]	27565	1			T1	6		T3	3		T4	33
valid_sources[0x11]	27769	1			T1	7		T2	6		T3	13
valid_sources[0x12]	25066	1			T1	7		T2	1		T3	4
valid_sources[0x13]	27863	1			T1	8		T2	6		T3	1
valid_sources[0x14]	26280	1			T1	6		T2	6		T3	1
valid_sources[0x15]	27968	1			T1	7		T2	3		T4	63
valid_sources[0x16]	28108	1			T1	8		T2	2		T4	40
valid_sources[0x17]	27409	1			T1	18		T2	2		T3	1
valid_sources[0x18]	25760	1			T1	5		T2	4		T3	1
valid_sources[0x19]	28764	1			T1	9		T2	3		T3	2
valid_sources[0x1a]	34094	1			T1	5		T2	2		T3	6
valid_sources[0x1b]	28488	1			T1	7		T2	2		T3	7
valid_sources[0x1c]	41278	1			T1	9		T2	2		T4	38
valid_sources[0x1d]	28615	1			T1	7		T2	1		T3	8
valid_sources[0x1e]	30253	1			T1	8		T2	2		T3	1
valid_sources[0x1f]	26826	1			T1	8		T2	4		T3	4
valid_sources[0x20]	30057	1			T1	8		T2	3		T3	12
valid_sources[0x21]	27230	1			T1	12		T2	3		T3	1
valid_sources[0x22]	34734	1			T1	11		T2	4		T3	1
valid_sources[0x23]	28038	1			T1	10		T2	5		T3	1
valid_sources[0x24]	26625	1			T1	5		T2	3		T3	10
valid_sources[0x25]	26831	1			T1	6		T2	3		T3	8
valid_sources[0x26]	28624	1			T1	7		T2	4		T3	6
valid_sources[0x27]	31678	1			T1	8		T2	6		T3	2
valid_sources[0x28]	24760	1			T1	7		T2	7		T3	9
valid_sources[0x29]	29998	1			T1	9		T2	2		T3	2
valid_sources[0x2a]	27154	1			T1	1		T2	7		T3	5
valid_sources[0x2b]	25927	1			T1	12		T2	3		T3	6
valid_sources[0x2c]	25576	1			T1	6		T2	2		T3	5
valid_sources[0x2d]	28268	1			T1	13		T2	4		T3	1
valid_sources[0x2e]	28232	1			T1	20		T2	3		T3	5
valid_sources[0x2f]	28271	1			T1	7		T3	1		T4	16
valid_sources[0x30]	25689	1			T1	13		T2	2		T4	26
valid_sources[0x31]	56189	1			T1	9		T2	4		T3	3
valid_sources[0x32]	25990	1			T1	7		T2	4		T3	2
valid_sources[0x33]	28390	1			T1	11		T2	2		T3	10
valid_sources[0x34]	27550	1			T1	8		T2	5		T3	8
valid_sources[0x35]	26534	1			T1	10		T2	3		T3	4
valid_sources[0x36]	27417	1			T1	6		T2	5		T3	10
valid_sources[0x37]	26794	1			T1	6		T2	4		T3	5
valid_sources[0x38]	25933	1			T1	10		T2	3		T3	11
valid_sources[0x39]	26111	1			T1	7		T2	2		T3	2
valid_sources[0x3a]	26398	1			T1	7		T2	3		T3	2
valid_sources[0x3b]	31962	1			T1	5		T2	3		T3	4
valid_sources[0x3c]	28750	1			T1	8		T2	6		T3	9
valid_sources[0x3d]	29755	1			T1	6		T2	5		T3	5
valid_sources[0x3e]	23889	1			T1	10		T2	1		T3	3
valid_sources[0x3f]	25626	1			T1	9		T2	4		T4	32
valid_sources[0x40]	28818	1			T1	17		T2	4		T3	6
valid_sources[0x41]	25264	1			T1	5		T2	5		T3	2
valid_sources[0x42]	28756	1			T1	4		T2	5		T3	5
valid_sources[0x43]	28478	1			T1	4		T2	2		T3	7
valid_sources[0x44]	27955	1			T1	8		T2	4		T3	3
valid_sources[0x45]	24248	1			T1	8		T2	8		T3	9
valid_sources[0x46]	27744	1			T1	3		T2	1		T3	3
valid_sources[0x47]	27805	1			T1	8		T2	4		T3	3
valid_sources[0x48]	27402	1			T1	5		T2	2		T3	8
valid_sources[0x49]	25021	1			T1	6		T2	3		T3	1
valid_sources[0x4a]	28961	1			T1	10		T3	5		T4	18
valid_sources[0x4b]	25556	1			T1	16		T2	5		T3	7
valid_sources[0x4c]	27604	1			T1	6		T2	2		T3	4
valid_sources[0x4d]	27296	1			T1	10		T2	3		T3	1
valid_sources[0x4e]	26057	1			T1	17		T2	4		T3	3
valid_sources[0x4f]	30342	1			T1	11		T2	3		T3	4
valid_sources[0x50]	27942	1			T1	3		T2	5		T3	5
valid_sources[0x51]	27353	1			T1	9		T2	4		T3	4
valid_sources[0x52]	25002	1			T1	9		T2	3		T3	5
valid_sources[0x53]	25582	1			T1	5		T2	3		T3	4
valid_sources[0x54]	27301	1			T1	9		T2	2		T3	1
valid_sources[0x55]	26818	1			T1	4		T2	5		T3	8
valid_sources[0x56]	24982	1			T1	6		T2	6		T3	1
valid_sources[0x57]	27258	1			T1	12		T2	5		T3	1
valid_sources[0x58]	24790	1			T1	9		T2	5		T3	1
valid_sources[0x59]	25659	1			T1	9		T2	5		T3	10
valid_sources[0x5a]	32417	1			T1	9		T3	7		T4	40
valid_sources[0x5b]	27491	1			T1	12		T2	7		T3	2
valid_sources[0x5c]	31699	1			T1	10		T2	2		T3	6
valid_sources[0x5d]	27940	1			T1	8		T2	4		T3	2
valid_sources[0x5e]	28151	1			T1	9		T2	6		T3	3
valid_sources[0x5f]	29359	1			T1	8		T2	3		T3	6
valid_sources[0x60]	27147	1			T1	10		T2	4		T3	3
valid_sources[0x61]	27464	1			T1	3		T2	5		T3	7
valid_sources[0x62]	25558	1			T1	6		T2	2		T3	2
valid_sources[0x63]	28652	1			T1	9		T2	1		T3	6
valid_sources[0x64]	27933	1			T1	11		T2	6		T3	3
valid_sources[0x65]	28009	1			T1	12		T2	6		T3	3
valid_sources[0x66]	34056	1			T1	5		T2	6		T3	4
valid_sources[0x67]	29280	1			T1	6		T2	4		T3	6
valid_sources[0x68]	30295	1			T1	1		T2	7		T3	4
valid_sources[0x69]	29376	1			T1	9		T2	4		T3	3
valid_sources[0x6a]	26717	1			T1	3		T2	5		T3	1
valid_sources[0x6b]	35259	1			T1	7		T2	4		T3	2
valid_sources[0x6c]	31299	1			T1	9		T2	1		T3	4
valid_sources[0x6d]	27170	1			T1	9		T2	5		T3	5
valid_sources[0x6e]	30047	1			T1	10		T2	3		T3	9
valid_sources[0x6f]	29691	1			T1	6		T2	2		T3	5
valid_sources[0x70]	25623	1			T1	7		T2	9		T3	2
valid_sources[0x71]	28441	1			T1	8		T2	4		T3	3
valid_sources[0x72]	31508	1			T1	6		T2	2		T3	3
valid_sources[0x73]	28125	1			T1	5		T2	2		T3	10
valid_sources[0x74]	29434	1			T1	8		T2	6		T3	3
valid_sources[0x75]	26913	1			T1	8		T2	3		T3	6
valid_sources[0x76]	27566	1			T1	10		T2	3		T3	3
valid_sources[0x77]	31047	1			T1	18		T2	9		T3	4
valid_sources[0x78]	37540	1			T1	10		T2	1		T4	39
valid_sources[0x79]	24890	1			T1	4		T2	5		T3	4
valid_sources[0x7a]	30839	1			T1	8		T2	3		T3	2
valid_sources[0x7b]	28544	1			T1	12		T2	4		T3	2
valid_sources[0x7c]	26982	1			T1	9		T2	4		T3	1
valid_sources[0x7d]	25629	1			T1	8		T2	3		T3	4
valid_sources[0x7e]	25711	1			T1	11		T2	4		T3	2
valid_sources[0x7f]	29713	1			T1	6		T2	4		T3	1
valid_sources[0x80]	31463	1			T1	10		T2	5		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

999421

1

T1

480

T2

5

T3

3

values[0x0]

all_enables

biggest_size

1442354

1

T1

578

T2

431

T3

403

values[0x1]

all_enables

biggest_size

1420481

1

T1

558

T2

447

T3

489