Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3512622

1

T1

461

T2

1

T3

7

full_word

3863309

1

T1

1616

T2

883

T3

895

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7375541	1			T1	2077		T2	884		T3	902
auto[TlIntgErrCmd]	124	1			T62	8		T95	5		T96	12
auto[TlIntgErrData]	133	1			T62	6		T95	12		T96	12
auto[TlIntgErrBoth]	133	1			T62	6		T95	13		T96	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4174342

1

T1

937

T2

5

T3

7

auto[1]

3201589

1

T1

1140

T2

879

T3

895

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3174513	1			T1	457		T3	4		T4	1052
auto[TlIntgErrNone]	partial	auto[1]	337747	1			T1	4		T2	1		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	999644	1			T1	480		T2	5		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	2863637	1			T1	1136		T2	878		T3	892
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T62	4		T95	1		T96	7
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T62	4		T95	4		T96	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T284	1		T285	2		T286	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T281	1		T287	2		T288	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T62	2		T95	6		T96	7
auto[TlIntgErrData]	partial	auto[1]	56	1			T62	4		T95	5		T96	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T96	1		T289	1		T287	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T95	1		T116	1		T283	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T62	1		T95	5		T96	4
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T62	4		T95	8		T96	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T283	1		T284	1		T290	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T62	1		T288	1		T286	3