Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399233932	2451827	0	0
DepthKnown_A	399233932	399105973	0	0
RvalidKnown_A	399233932	399105973	0	0
WreadyKnown_A	399233932	399105973	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	2451827	0	0
T1	182134	1343	0	0
T2	58598	832	0	0
T3	30848	1663	0	0
T4	190973	6654	0	0
T5	32397	1672	0	0
T6	103433	832	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	14261	1667	0	0
T10	607039	0	0	0
T12	0	832	0	0
T15	0	832	0	0
T16	0	2495	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399233932	2769132	0	0
DepthKnown_A	399233932	399105973	0	0
RvalidKnown_A	399233932	399105973	0	0
WreadyKnown_A	399233932	399105973	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	2769132	0	0
T1	182134	1088	0	0
T2	58598	832	0	0
T3	30848	832	0	0
T4	190973	4992	0	0
T5	32397	841	0	0
T6	103433	2452	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	14261	836	0	0
T10	607039	0	0	0
T12	0	3797	0	0
T15	0	2628	0	0
T16	0	1664	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399233932	155921	0	0
DepthKnown_A	399233932	399105973	0	0
RvalidKnown_A	399233932	399105973	0	0
WreadyKnown_A	399233932	399105973	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	155921	0	0
T4	190973	430	0	0
T5	32397	0	0	0
T6	103433	0	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	14261	0	0	0
T10	607039	0	0	0
T11	6551	0	0	0
T12	30747	0	0	0
T13	49098	0	0	0
T14	0	861	0	0
T16	0	660	0	0
T17	0	31	0	0
T18	0	376	0	0
T21	0	128	0	0
T24	0	48	0	0
T25	0	783	0	0
T26	0	320	0	0
T27	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399233932	366695	0	0
DepthKnown_A	399233932	399105973	0	0
RvalidKnown_A	399233932	399105973	0	0
WreadyKnown_A	399233932	399105973	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	366695	0	0
T4	190973	429	0	0
T5	32397	0	0	0
T6	103433	0	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	14261	0	0	0
T10	607039	0	0	0
T11	6551	0	0	0
T12	30747	0	0	0
T13	49098	0	0	0
T14	0	861	0	0
T16	0	660	0	0
T17	0	142	0	0
T18	0	1787	0	0
T21	0	593	0	0
T24	0	201	0	0
T25	0	3443	0	0
T26	0	967	0	0
T27	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399233932	6035623	0	0
DepthKnown_A	399233932	399105973	0	0
RvalidKnown_A	399233932	399105973	0	0
WreadyKnown_A	399233932	399105973	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	6035623	0	0
T1	182134	993	0	0
T2	58598	52	0	0
T3	30848	70	0	0
T4	190973	2646	0	0
T5	32397	75	0	0
T6	103433	3435	0	0
T7	1045	18	0	0
T8	1603	59	0	0
T9	14261	419	0	0
T10	607039	874	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399233932	13531342	0	0
DepthKnown_A	399233932	399105973	0	0
RvalidKnown_A	399233932	399105973	0	0
WreadyKnown_A	399233932	399105973	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	13531342	0	0
T1	182134	4233	0	0
T2	58598	52	0	0
T3	30848	194	0	0
T4	190973	2628	0	0
T5	32397	288	0	0
T6	103433	10793	0	0
T7	1045	102	0	0
T8	1603	167	0	0
T9	14261	1778	0	0
T10	607039	874	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233932	399105973	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0