Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T14,T16
1	0	Covered	T4,T14,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T10,T11
1	0	Unreachable
1	1	Covered	T4,T14,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T16,T21

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T16,T21
1	0	Covered	T4,T16,T21

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T16,T21

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T14,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T14,T16
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T14,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	652568120	523320251	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	652568120	3028911	0	0
GntImpliesValid_A	652568120	3028911	0	0
GrantKnown_A	652568120	523320251	0	0
IdxKnown_A	652568120	523320251	0	0
IndexIsCorrect_A	652568120	3028911	0	0
LockArbDecision_A	652568120	0	0	0
NoReadyValidNoGrant_A	652568120	0	0	0
ReadyAndValidImplyGrant_A	652568120	3028911	0	0
ReqAndReadyImplyGrant_A	652568120	3028911	0	0
ReqImpliesValid_A	652568120	3028911	0	0
ReqStaysHighUntilGranted0_M	652568120	0	0	0
RoundRobin_A	652568120	4	0	906
ValidKnown_A	652568120	523320251	0	0
gen_data_port_assertion.DataFlow_A	652568120	3028911	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652568120	523320251	0	0
T1	207853	207282	0	0
T2	114518	114431	0	0
T3	141738	141666	0	0
T4	971579	577802	0	0
T5	259609	145948	0	0
T6	134685	118975	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	96605	55185	0	0
T10	808203	702136	0	0
T11	1152	576	0	0
T12	39962	19981	0	0
T13	57921	54256	0	0
T14	127392	124816	0	0
T15	25888	25888	0	0
T16	0	193347	0	0
T17	0	2784	0	0
T18	0	47560	0	0
T24	0	5280	0	0
T25	0	65016	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652568120	3028911	0	0
T1	182134	1088	0	0
T2	58598	832	0	0
T3	30848	832	0	0
T4	971579	13799	0	0
T5	259609	832	0	0
T6	134685	832	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	96605	832	0	0
T10	808203	0	0	0
T11	1152	0	0	0
T12	39962	832	0	0
T13	115842	0	0	0
T14	254784	6616	0	0
T15	51776	832	0	0
T16	0	3785	0	0
T17	0	148	0	0
T18	0	1986	0	0
T21	0	2886	0	0
T24	0	275	0	0
T25	0	4323	0	0
T26	0	4104	0	0
T27	0	111	0	0
T31	0	7121	0	0
T42	0	4931	0	0
T43	0	6199	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652568120	3028911	0	0
T1	182134	1088	0	0
T2	58598	832	0	0
T3	30848	832	0	0
T4	971579	13799	0	0
T5	259609	832	0	0
T6	134685	832	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	96605	832	0	0
T10	808203	0	0	0
T11	1152	0	0	0
T12	39962	832	0	0
T13	115842	0	0	0
T14	254784	6616	0	0
T15	51776	832	0	0
T16	0	3785	0	0
T17	0	148	0	0
T18	0	1986	0	0
T21	0	2886	0	0
T24	0	275	0	0
T25	0	4323	0	0
T26	0	4104	0	0
T27	0	111	0	0
T31	0	7121	0	0
T42	0	4931	0	0
T43	0	6199	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652568120	523320251	0	0
T1	207853	207282	0	0
T2	114518	114431	0	0
T3	141738	141666	0	0
T4	971579	577802	0	0
T5	259609	145948	0	0
T6	134685	118975	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	96605	55185	0	0
T10	808203	702136	0	0
T11	1152	576	0	0
T12	39962	19981	0	0
T13	57921	54256	0	0
T14	127392	124816	0	0
T15	25888	25888	0	0
T16	0	193347	0	0
T17	0	2784	0	0
T18	0	47560	0	0
T24	0	5280	0	0
T25	0	65016	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652568120	523320251	0	0
T1	207853	207282	0	0
T2	114518	114431	0	0
T3	141738	141666	0	0
T4	971579	577802	0	0
T5	259609	145948	0	0
T6	134685	118975	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	96605	55185	0	0
T10	808203	702136	0	0
T11	1152	576	0	0
T12	39962	19981	0	0
T13	57921	54256	0	0
T14	127392	124816	0	0
T15	25888	25888	0	0
T16	0	193347	0	0
T17	0	2784	0	0
T18	0	47560	0	0
T24	0	5280	0	0
T25	0	65016	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652568120	3028911	0	0
T1	182134	1088	0	0
T2	58598	832	0	0
T3	30848	832	0	0
T4	971579	13799	0	0
T5	259609	832	0	0
T6	134685	832	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	96605	832	0	0
T10	808203	0	0	0
T11	1152	0	0	0
T12	39962	832	0	0
T13	115842	0	0	0
T14	254784	6616	0	0
T15	51776	832	0	0
T16	0	3785	0	0
T17	0	148	0	0
T18	0	1986	0	0
T21	0	2886	0	0
T24	0	275	0	0
T25	0	4323	0	0
T26	0	4104	0	0
T27	0	111	0	0
T31	0	7121	0	0
T42	0	4931	0	0
T43	0	6199	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652568120	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652568120	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652568120	3028911	0	0
T1	182134	1088	0	0
T2	58598	832	0	0
T3	30848	832	0	0
T4	971579	13799	0	0
T5	259609	832	0	0
T6	134685	832	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	96605	832	0	0
T10	808203	0	0	0
T11	1152	0	0	0
T12	39962	832	0	0
T13	115842	0	0	0
T14	254784	6616	0	0
T15	51776	832	0	0
T16	0	3785	0	0
T17	0	148	0	0
T18	0	1986	0	0
T21	0	2886	0	0
T24	0	275	0	0
T25	0	4323	0	0
T26	0	4104	0	0
T27	0	111	0	0
T31	0	7121	0	0
T42	0	4931	0	0
T43	0	6199	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652568120	3028911	0	0
T1	182134	1088	0	0
T2	58598	832	0	0
T3	30848	832	0	0
T4	971579	13799	0	0
T5	259609	832	0	0
T6	134685	832	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	96605	832	0	0
T10	808203	0	0	0
T11	1152	0	0	0
T12	39962	832	0	0
T13	115842	0	0	0
T14	254784	6616	0	0
T15	51776	832	0	0
T16	0	3785	0	0
T17	0	148	0	0
T18	0	1986	0	0
T21	0	2886	0	0
T24	0	275	0	0
T25	0	4323	0	0
T26	0	4104	0	0
T27	0	111	0	0
T31	0	7121	0	0
T42	0	4931	0	0
T43	0	6199	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652568120	3028911	0	0
T1	182134	1088	0	0
T2	58598	832	0	0
T3	30848	832	0	0
T4	971579	13799	0	0
T5	259609	832	0	0
T6	134685	832	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	96605	832	0	0
T10	808203	0	0	0
T11	1152	0	0	0
T12	39962	832	0	0
T13	115842	0	0	0
T14	254784	6616	0	0
T15	51776	832	0	0
T16	0	3785	0	0
T17	0	148	0	0
T18	0	1986	0	0
T21	0	2886	0	0
T24	0	275	0	0
T25	0	4323	0	0
T26	0	4104	0	0
T27	0	111	0	0
T31	0	7121	0	0
T42	0	4931	0	0
T43	0	6199	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	652568120	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652568120	4	0	906
T44	860748	1	0	1
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	80957	0	0	1
T49	335198	0	0	1
T50	960	0	0	1
T51	128953	0	0	1
T52	1502	0	0	1
T53	1371	0	0	1
T54	289680	0	0	1
T55	14543	0	0	1
T56	23181	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652568120	523320251	0	0
T1	207853	207282	0	0
T2	114518	114431	0	0
T3	141738	141666	0	0
T4	971579	577802	0	0
T5	259609	145948	0	0
T6	134685	118975	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	96605	55185	0	0
T10	808203	702136	0	0
T11	1152	576	0	0
T12	39962	19981	0	0
T13	57921	54256	0	0
T14	127392	124816	0	0
T15	25888	25888	0	0
T16	0	193347	0	0
T17	0	2784	0	0
T18	0	47560	0	0
T24	0	5280	0	0
T25	0	65016	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652568120	3028911	0	0
T1	182134	1088	0	0
T2	58598	832	0	0
T3	30848	832	0	0
T4	971579	13799	0	0
T5	259609	832	0	0
T6	134685	832	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	96605	832	0	0
T10	808203	0	0	0
T11	1152	0	0	0
T12	39962	832	0	0
T13	115842	0	0	0
T14	254784	6616	0	0
T15	51776	832	0	0
T16	0	3785	0	0
T17	0	148	0	0
T18	0	1986	0	0
T21	0	2886	0	0
T24	0	275	0	0
T25	0	4323	0	0
T26	0	4104	0	0
T27	0	111	0	0
T31	0	7121	0	0
T42	0	4931	0	0
T43	0	6199	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T14,T16
1	0	Covered	T4,T14,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T10,T11
1	0	Unreachable
1	1	Covered	T4,T14,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T14,T16
0	0	1	Unreachable
0	0	0	Covered	T4,T10,T11

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T14,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T14,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	127853152	28478266	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	127853152	634211	0	0
GntImpliesValid_A	127853152	634211	0	0
GrantKnown_A	127853152	28478266	0	0
IdxKnown_A	127853152	28478266	0	0
IndexIsCorrect_A	127853152	634211	0	0
LockArbDecision_A	127853152	0	0	0
NoReadyValidNoGrant_A	127853152	0	0	0
ReadyAndValidImplyGrant_A	127853152	634211	0	0
ReqAndReadyImplyGrant_A	127853152	634211	0	0
ReqImpliesValid_A	127853152	634211	0	0
ReqStaysHighUntilGranted0_M	127853152	0	0	0
RoundRobin_A	127853152	0	0	0
ValidKnown_A	127853152	28478266	0	0
gen_data_port_assertion.DataFlow_A	127853152	634211	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	28478266	0	0
T4	390303	78600	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	95176	0	0
T11	576	576	0	0
T12	19981	0	0	0
T13	57921	54256	0	0
T14	127392	124816	0	0
T15	25888	0	0	0
T16	0	87952	0	0
T17	0	2784	0	0
T18	0	47560	0	0
T24	0	5280	0	0
T25	0	65016	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	634211	0	0
T4	390303	938	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	0	0	0
T13	57921	0	0	0
T14	127392	4583	0	0
T15	25888	0	0	0
T16	0	3781	0	0
T17	0	148	0	0
T18	0	1986	0	0
T24	0	275	0	0
T25	0	2889	0	0
T27	0	111	0	0
T42	0	4918	0	0
T43	0	6199	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	634211	0	0
T4	390303	938	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	0	0	0
T13	57921	0	0	0
T14	127392	4583	0	0
T15	25888	0	0	0
T16	0	3781	0	0
T17	0	148	0	0
T18	0	1986	0	0
T24	0	275	0	0
T25	0	2889	0	0
T27	0	111	0	0
T42	0	4918	0	0
T43	0	6199	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	28478266	0	0
T4	390303	78600	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	95176	0	0
T11	576	576	0	0
T12	19981	0	0	0
T13	57921	54256	0	0
T14	127392	124816	0	0
T15	25888	0	0	0
T16	0	87952	0	0
T17	0	2784	0	0
T18	0	47560	0	0
T24	0	5280	0	0
T25	0	65016	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	28478266	0	0
T4	390303	78600	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	95176	0	0
T11	576	576	0	0
T12	19981	0	0	0
T13	57921	54256	0	0
T14	127392	124816	0	0
T15	25888	0	0	0
T16	0	87952	0	0
T17	0	2784	0	0
T18	0	47560	0	0
T24	0	5280	0	0
T25	0	65016	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	634211	0	0
T4	390303	938	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	0	0	0
T13	57921	0	0	0
T14	127392	4583	0	0
T15	25888	0	0	0
T16	0	3781	0	0
T17	0	148	0	0
T18	0	1986	0	0
T24	0	275	0	0
T25	0	2889	0	0
T27	0	111	0	0
T42	0	4918	0	0
T43	0	6199	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	634211	0	0
T4	390303	938	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	0	0	0
T13	57921	0	0	0
T14	127392	4583	0	0
T15	25888	0	0	0
T16	0	3781	0	0
T17	0	148	0	0
T18	0	1986	0	0
T24	0	275	0	0
T25	0	2889	0	0
T27	0	111	0	0
T42	0	4918	0	0
T43	0	6199	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	634211	0	0
T4	390303	938	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	0	0	0
T13	57921	0	0	0
T14	127392	4583	0	0
T15	25888	0	0	0
T16	0	3781	0	0
T17	0	148	0	0
T18	0	1986	0	0
T24	0	275	0	0
T25	0	2889	0	0
T27	0	111	0	0
T42	0	4918	0	0
T43	0	6199	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	634211	0	0
T4	390303	938	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	0	0	0
T13	57921	0	0	0
T14	127392	4583	0	0
T15	25888	0	0	0
T16	0	3781	0	0
T17	0	148	0	0
T18	0	1986	0	0
T24	0	275	0	0
T25	0	2889	0	0
T27	0	111	0	0
T42	0	4918	0	0
T43	0	6199	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	28478266	0	0
T4	390303	78600	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	95176	0	0
T11	576	576	0	0
T12	19981	0	0	0
T13	57921	54256	0	0
T14	127392	124816	0	0
T15	25888	0	0	0
T16	0	87952	0	0
T17	0	2784	0	0
T18	0	47560	0	0
T24	0	5280	0	0
T25	0	65016	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	634211	0	0
T4	390303	938	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	0	0	0
T13	57921	0	0	0
T14	127392	4583	0	0
T15	25888	0	0	0
T16	0	3781	0	0
T17	0	148	0	0
T18	0	1986	0	0
T24	0	275	0	0
T25	0	2889	0	0
T27	0	111	0	0
T42	0	4918	0	0
T43	0	6199	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T16,T21

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T16,T21
1	0	Covered	T4,T16,T21

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T4,T16,T21

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T16,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T16,T21
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T16,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T16,T21
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	127853152	98064096	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	127853152	450323	0	0
GntImpliesValid_A	127853152	450323	0	0
GrantKnown_A	127853152	98064096	0	0
IdxKnown_A	127853152	98064096	0	0
IndexIsCorrect_A	127853152	450323	0	0
LockArbDecision_A	127853152	0	0	0
NoReadyValidNoGrant_A	127853152	0	0	0
ReadyAndValidImplyGrant_A	127853152	450323	0	0
ReqAndReadyImplyGrant_A	127853152	450323	0	0
ReqImpliesValid_A	127853152	450323	0	0
ReqStaysHighUntilGranted0_M	127853152	0	0	0
RoundRobin_A	127853152	0	0	0
ValidKnown_A	127853152	98064096	0	0
gen_data_port_assertion.DataFlow_A	127853152	450323	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	98064096	0	0
T1	25719	25230	0	0
T2	55920	55920	0	0
T3	110890	110890	0	0
T4	390303	308279	0	0
T5	113606	113606	0	0
T6	15626	15626	0	0
T9	41172	41012	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	19981	0	0
T15	0	25888	0	0
T16	0	105395	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	450323	0	0
T4	390303	7097	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	0	0	0
T13	57921	0	0	0
T14	127392	0	0	0
T15	25888	0	0	0
T16	0	4	0	0
T21	0	2886	0	0
T25	0	1434	0	0
T26	0	4104	0	0
T29	0	9517	0	0
T31	0	7121	0	0
T32	0	724	0	0
T42	0	13	0	0
T57	0	3333	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	450323	0	0
T4	390303	7097	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	0	0	0
T13	57921	0	0	0
T14	127392	0	0	0
T15	25888	0	0	0
T16	0	4	0	0
T21	0	2886	0	0
T25	0	1434	0	0
T26	0	4104	0	0
T29	0	9517	0	0
T31	0	7121	0	0
T32	0	724	0	0
T42	0	13	0	0
T57	0	3333	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	98064096	0	0
T1	25719	25230	0	0
T2	55920	55920	0	0
T3	110890	110890	0	0
T4	390303	308279	0	0
T5	113606	113606	0	0
T6	15626	15626	0	0
T9	41172	41012	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	19981	0	0
T15	0	25888	0	0
T16	0	105395	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	98064096	0	0
T1	25719	25230	0	0
T2	55920	55920	0	0
T3	110890	110890	0	0
T4	390303	308279	0	0
T5	113606	113606	0	0
T6	15626	15626	0	0
T9	41172	41012	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	19981	0	0
T15	0	25888	0	0
T16	0	105395	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	450323	0	0
T4	390303	7097	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	0	0	0
T13	57921	0	0	0
T14	127392	0	0	0
T15	25888	0	0	0
T16	0	4	0	0
T21	0	2886	0	0
T25	0	1434	0	0
T26	0	4104	0	0
T29	0	9517	0	0
T31	0	7121	0	0
T32	0	724	0	0
T42	0	13	0	0
T57	0	3333	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	450323	0	0
T4	390303	7097	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	0	0	0
T13	57921	0	0	0
T14	127392	0	0	0
T15	25888	0	0	0
T16	0	4	0	0
T21	0	2886	0	0
T25	0	1434	0	0
T26	0	4104	0	0
T29	0	9517	0	0
T31	0	7121	0	0
T32	0	724	0	0
T42	0	13	0	0
T57	0	3333	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	450323	0	0
T4	390303	7097	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	0	0	0
T13	57921	0	0	0
T14	127392	0	0	0
T15	25888	0	0	0
T16	0	4	0	0
T21	0	2886	0	0
T25	0	1434	0	0
T26	0	4104	0	0
T29	0	9517	0	0
T31	0	7121	0	0
T32	0	724	0	0
T42	0	13	0	0
T57	0	3333	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	450323	0	0
T4	390303	7097	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	0	0	0
T13	57921	0	0	0
T14	127392	0	0	0
T15	25888	0	0	0
T16	0	4	0	0
T21	0	2886	0	0
T25	0	1434	0	0
T26	0	4104	0	0
T29	0	9517	0	0
T31	0	7121	0	0
T32	0	724	0	0
T42	0	13	0	0
T57	0	3333	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	98064096	0	0
T1	25719	25230	0	0
T2	55920	55920	0	0
T3	110890	110890	0	0
T4	390303	308279	0	0
T5	113606	113606	0	0
T6	15626	15626	0	0
T9	41172	41012	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	19981	0	0
T15	0	25888	0	0
T16	0	105395	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127853152	450323	0	0
T4	390303	7097	0	0
T5	113606	0	0	0
T6	15626	0	0	0
T9	41172	0	0	0
T10	100582	0	0	0
T11	576	0	0	0
T12	19981	0	0	0
T13	57921	0	0	0
T14	127392	0	0	0
T15	25888	0	0	0
T16	0	4	0	0
T21	0	2886	0	0
T25	0	1434	0	0
T26	0	4104	0	0
T29	0	9517	0	0
T31	0	7121	0	0
T32	0	724	0	0
T42	0	13	0	0
T57	0	3333	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T14,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T14,T16
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T14,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396861816	396777889	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	396861816	1944377	0	0
GntImpliesValid_A	396861816	1944377	0	0
GrantKnown_A	396861816	396777889	0	0
IdxKnown_A	396861816	396777889	0	0
IndexIsCorrect_A	396861816	1944377	0	0
LockArbDecision_A	396861816	0	0	0
NoReadyValidNoGrant_A	396861816	0	0	0
ReadyAndValidImplyGrant_A	396861816	1944377	0	0
ReqAndReadyImplyGrant_A	396861816	1944377	0	0
ReqImpliesValid_A	396861816	1944377	0	0
ReqStaysHighUntilGranted0_M	396861816	0	0	0
RoundRobin_A	396861816	4	0	906
ValidKnown_A	396861816	396777889	0	0
gen_data_port_assertion.DataFlow_A	396861816	1944377	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396861816	396777889	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396861816	1944377	0	0
T1	182134	1088	0	0
T2	58598	832	0	0
T3	30848	832	0	0
T4	190973	5764	0	0
T5	32397	832	0	0
T6	103433	832	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	14261	832	0	0
T10	607039	0	0	0
T12	0	832	0	0
T14	0	2033	0	0
T15	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396861816	1944377	0	0
T1	182134	1088	0	0
T2	58598	832	0	0
T3	30848	832	0	0
T4	190973	5764	0	0
T5	32397	832	0	0
T6	103433	832	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	14261	832	0	0
T10	607039	0	0	0
T12	0	832	0	0
T14	0	2033	0	0
T15	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396861816	396777889	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396861816	396777889	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396861816	1944377	0	0
T1	182134	1088	0	0
T2	58598	832	0	0
T3	30848	832	0	0
T4	190973	5764	0	0
T5	32397	832	0	0
T6	103433	832	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	14261	832	0	0
T10	607039	0	0	0
T12	0	832	0	0
T14	0	2033	0	0
T15	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396861816	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396861816	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396861816	1944377	0	0
T1	182134	1088	0	0
T2	58598	832	0	0
T3	30848	832	0	0
T4	190973	5764	0	0
T5	32397	832	0	0
T6	103433	832	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	14261	832	0	0
T10	607039	0	0	0
T12	0	832	0	0
T14	0	2033	0	0
T15	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396861816	1944377	0	0
T1	182134	1088	0	0
T2	58598	832	0	0
T3	30848	832	0	0
T4	190973	5764	0	0
T5	32397	832	0	0
T6	103433	832	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	14261	832	0	0
T10	607039	0	0	0
T12	0	832	0	0
T14	0	2033	0	0
T15	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396861816	1944377	0	0
T1	182134	1088	0	0
T2	58598	832	0	0
T3	30848	832	0	0
T4	190973	5764	0	0
T5	32397	832	0	0
T6	103433	832	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	14261	832	0	0
T10	607039	0	0	0
T12	0	832	0	0
T14	0	2033	0	0
T15	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396861816	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396861816	4	0	906
T44	860748	1	0	1
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	80957	0	0	1
T49	335198	0	0	1
T50	960	0	0	1
T51	128953	0	0	1
T52	1502	0	0	1
T53	1371	0	0	1
T54	289680	0	0	1
T55	14543	0	0	1
T56	23181	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396861816	396777889	0	0
T1	182134	182052	0	0
T2	58598	58511	0	0
T3	30848	30776	0	0
T4	190973	190923	0	0
T5	32397	32342	0	0
T6	103433	103349	0	0
T7	1045	987	0	0
T8	1603	1503	0	0
T9	14261	14173	0	0
T10	607039	606960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396861816	1944377	0	0
T1	182134	1088	0	0
T2	58598	832	0	0
T3	30848	832	0	0
T4	190973	5764	0	0
T5	32397	832	0	0
T6	103433	832	0	0
T7	1045	0	0	0
T8	1603	0	0	0
T9	14261	832	0	0
T10	607039	0	0	0
T12	0	832	0	0
T14	0	2033	0	0
T15	0	832	0	0