Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
2799 |
0 |
0 |
T62 |
19652 |
3 |
0 |
0 |
T63 |
5100 |
145 |
0 |
0 |
T64 |
6308 |
2 |
0 |
0 |
T94 |
11681 |
176 |
0 |
0 |
T95 |
29582 |
1 |
0 |
0 |
T96 |
79610 |
7 |
0 |
0 |
T97 |
5604 |
103 |
0 |
0 |
T113 |
2443 |
6 |
0 |
0 |
T116 |
94204 |
6 |
0 |
0 |
T117 |
57121 |
4 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3230 |
0 |
0 |
T64 |
6308 |
5 |
0 |
0 |
T116 |
94204 |
67 |
0 |
0 |
T118 |
5943 |
5 |
0 |
0 |
T121 |
3884 |
1 |
0 |
0 |
T122 |
270676 |
686 |
0 |
0 |
T124 |
115963 |
771 |
0 |
0 |
T125 |
8005 |
6 |
0 |
0 |
T151 |
42087 |
236 |
0 |
0 |
T152 |
7613 |
39 |
0 |
0 |
T153 |
124077 |
796 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3090 |
0 |
0 |
T64 |
6308 |
6 |
0 |
0 |
T116 |
94204 |
67 |
0 |
0 |
T118 |
5943 |
12 |
0 |
0 |
T122 |
270676 |
638 |
0 |
0 |
T124 |
115963 |
789 |
0 |
0 |
T125 |
8005 |
3 |
0 |
0 |
T126 |
3521 |
1 |
0 |
0 |
T151 |
42087 |
257 |
0 |
0 |
T152 |
7613 |
30 |
0 |
0 |
T153 |
124077 |
727 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3547 |
0 |
0 |
T64 |
6308 |
12 |
0 |
0 |
T116 |
94204 |
158 |
0 |
0 |
T118 |
5943 |
10 |
0 |
0 |
T121 |
3884 |
3 |
0 |
0 |
T122 |
270676 |
724 |
0 |
0 |
T124 |
115963 |
696 |
0 |
0 |
T126 |
3521 |
5 |
0 |
0 |
T151 |
42087 |
285 |
0 |
0 |
T152 |
7613 |
15 |
0 |
0 |
T153 |
124077 |
799 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
7780 |
0 |
0 |
T64 |
6308 |
124 |
0 |
0 |
T97 |
5604 |
5 |
0 |
0 |
T116 |
94204 |
1288 |
0 |
0 |
T118 |
5943 |
7 |
0 |
0 |
T121 |
3884 |
8 |
0 |
0 |
T122 |
270676 |
759 |
0 |
0 |
T124 |
115963 |
721 |
0 |
0 |
T125 |
8005 |
50 |
0 |
0 |
T151 |
42087 |
292 |
0 |
0 |
T152 |
7613 |
17 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
7476 |
0 |
0 |
T64 |
6308 |
137 |
0 |
0 |
T116 |
94204 |
1036 |
0 |
0 |
T118 |
5943 |
106 |
0 |
0 |
T121 |
3884 |
4 |
0 |
0 |
T122 |
270676 |
697 |
0 |
0 |
T124 |
115963 |
781 |
0 |
0 |
T125 |
8005 |
48 |
0 |
0 |
T126 |
3521 |
73 |
0 |
0 |
T151 |
42087 |
246 |
0 |
0 |
T152 |
7613 |
19 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
7003 |
0 |
0 |
T64 |
6308 |
135 |
0 |
0 |
T116 |
94204 |
866 |
0 |
0 |
T118 |
5943 |
96 |
0 |
0 |
T121 |
3884 |
3 |
0 |
0 |
T122 |
270676 |
652 |
0 |
0 |
T124 |
115963 |
732 |
0 |
0 |
T125 |
8005 |
77 |
0 |
0 |
T126 |
3521 |
79 |
0 |
0 |
T151 |
42087 |
288 |
0 |
0 |
T152 |
7613 |
3 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
7208 |
0 |
0 |
T64 |
6308 |
141 |
0 |
0 |
T116 |
94204 |
890 |
0 |
0 |
T118 |
5943 |
15 |
0 |
0 |
T121 |
3884 |
5 |
0 |
0 |
T122 |
270676 |
722 |
0 |
0 |
T124 |
115963 |
706 |
0 |
0 |
T125 |
8005 |
53 |
0 |
0 |
T126 |
3521 |
2 |
0 |
0 |
T151 |
42087 |
262 |
0 |
0 |
T152 |
7613 |
1 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
8145 |
0 |
0 |
T64 |
6308 |
8 |
0 |
0 |
T116 |
94204 |
1136 |
0 |
0 |
T118 |
5943 |
140 |
0 |
0 |
T121 |
3884 |
119 |
0 |
0 |
T122 |
270676 |
669 |
0 |
0 |
T124 |
115963 |
788 |
0 |
0 |
T125 |
8005 |
132 |
0 |
0 |
T126 |
3521 |
4 |
0 |
0 |
T151 |
42087 |
289 |
0 |
0 |
T152 |
7613 |
31 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
7531 |
0 |
0 |
T64 |
6308 |
143 |
0 |
0 |
T116 |
94204 |
962 |
0 |
0 |
T118 |
5943 |
125 |
0 |
0 |
T121 |
3884 |
100 |
0 |
0 |
T122 |
270676 |
672 |
0 |
0 |
T124 |
115963 |
758 |
0 |
0 |
T125 |
8005 |
111 |
0 |
0 |
T126 |
3521 |
49 |
0 |
0 |
T151 |
42087 |
266 |
0 |
0 |
T152 |
7613 |
5 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
6756 |
0 |
0 |
T64 |
6308 |
134 |
0 |
0 |
T116 |
94204 |
957 |
0 |
0 |
T118 |
5943 |
1 |
0 |
0 |
T121 |
3884 |
4 |
0 |
0 |
T122 |
270676 |
702 |
0 |
0 |
T124 |
115963 |
677 |
0 |
0 |
T125 |
8005 |
126 |
0 |
0 |
T126 |
3521 |
3 |
0 |
0 |
T151 |
42087 |
247 |
0 |
0 |
T152 |
7613 |
21 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
7707 |
0 |
0 |
T64 |
6308 |
128 |
0 |
0 |
T116 |
94204 |
1076 |
0 |
0 |
T118 |
5943 |
147 |
0 |
0 |
T121 |
3884 |
7 |
0 |
0 |
T122 |
270676 |
647 |
0 |
0 |
T124 |
115963 |
715 |
0 |
0 |
T125 |
8005 |
143 |
0 |
0 |
T126 |
3521 |
7 |
0 |
0 |
T151 |
42087 |
268 |
0 |
0 |
T152 |
7613 |
39 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4719 |
0 |
0 |
T64 |
6308 |
10 |
0 |
0 |
T116 |
94204 |
370 |
0 |
0 |
T118 |
5943 |
60 |
0 |
0 |
T121 |
3884 |
2 |
0 |
0 |
T122 |
270676 |
666 |
0 |
0 |
T124 |
115963 |
759 |
0 |
0 |
T125 |
8005 |
41 |
0 |
0 |
T151 |
42087 |
259 |
0 |
0 |
T152 |
7613 |
25 |
0 |
0 |
T153 |
124077 |
824 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4684 |
0 |
0 |
T64 |
6308 |
56 |
0 |
0 |
T116 |
94204 |
349 |
0 |
0 |
T118 |
5943 |
10 |
0 |
0 |
T121 |
3884 |
55 |
0 |
0 |
T122 |
270676 |
662 |
0 |
0 |
T124 |
115963 |
720 |
0 |
0 |
T125 |
8005 |
50 |
0 |
0 |
T126 |
3521 |
7 |
0 |
0 |
T151 |
42087 |
305 |
0 |
0 |
T152 |
7613 |
52 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4574 |
0 |
0 |
T64 |
6308 |
59 |
0 |
0 |
T116 |
94204 |
388 |
0 |
0 |
T118 |
5943 |
10 |
0 |
0 |
T121 |
3884 |
3 |
0 |
0 |
T122 |
270676 |
662 |
0 |
0 |
T124 |
115963 |
679 |
0 |
0 |
T125 |
8005 |
5 |
0 |
0 |
T151 |
42087 |
222 |
0 |
0 |
T152 |
7613 |
34 |
0 |
0 |
T153 |
124077 |
796 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4838 |
0 |
0 |
T64 |
6308 |
11 |
0 |
0 |
T116 |
94204 |
459 |
0 |
0 |
T118 |
5943 |
5 |
0 |
0 |
T121 |
3884 |
39 |
0 |
0 |
T122 |
270676 |
615 |
0 |
0 |
T124 |
115963 |
755 |
0 |
0 |
T125 |
8005 |
43 |
0 |
0 |
T126 |
3521 |
5 |
0 |
0 |
T151 |
42087 |
262 |
0 |
0 |
T152 |
7613 |
18 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4986 |
0 |
0 |
T64 |
6308 |
4 |
0 |
0 |
T116 |
94204 |
511 |
0 |
0 |
T118 |
5943 |
49 |
0 |
0 |
T121 |
3884 |
51 |
0 |
0 |
T122 |
270676 |
712 |
0 |
0 |
T124 |
115963 |
705 |
0 |
0 |
T125 |
8005 |
28 |
0 |
0 |
T126 |
3521 |
32 |
0 |
0 |
T151 |
42087 |
323 |
0 |
0 |
T152 |
7613 |
10 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4611 |
0 |
0 |
T64 |
6308 |
13 |
0 |
0 |
T116 |
94204 |
511 |
0 |
0 |
T118 |
5943 |
10 |
0 |
0 |
T121 |
3884 |
53 |
0 |
0 |
T122 |
270676 |
696 |
0 |
0 |
T124 |
115963 |
723 |
0 |
0 |
T125 |
8005 |
37 |
0 |
0 |
T126 |
3521 |
16 |
0 |
0 |
T151 |
42087 |
259 |
0 |
0 |
T152 |
7613 |
31 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4838 |
0 |
0 |
T64 |
6308 |
33 |
0 |
0 |
T116 |
94204 |
401 |
0 |
0 |
T118 |
5943 |
42 |
0 |
0 |
T121 |
3884 |
39 |
0 |
0 |
T122 |
270676 |
738 |
0 |
0 |
T124 |
115963 |
846 |
0 |
0 |
T125 |
8005 |
72 |
0 |
0 |
T151 |
42087 |
244 |
0 |
0 |
T152 |
7613 |
18 |
0 |
0 |
T153 |
124077 |
816 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4740 |
0 |
0 |
T64 |
6308 |
2 |
0 |
0 |
T116 |
94204 |
334 |
0 |
0 |
T118 |
5943 |
8 |
0 |
0 |
T121 |
3884 |
5 |
0 |
0 |
T122 |
270676 |
708 |
0 |
0 |
T124 |
115963 |
718 |
0 |
0 |
T125 |
8005 |
2 |
0 |
0 |
T126 |
3521 |
7 |
0 |
0 |
T151 |
42087 |
253 |
0 |
0 |
T152 |
7613 |
35 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4517 |
0 |
0 |
T64 |
6308 |
65 |
0 |
0 |
T116 |
94204 |
402 |
0 |
0 |
T118 |
5943 |
9 |
0 |
0 |
T121 |
3884 |
10 |
0 |
0 |
T122 |
270676 |
662 |
0 |
0 |
T124 |
115963 |
670 |
0 |
0 |
T125 |
8005 |
4 |
0 |
0 |
T151 |
42087 |
269 |
0 |
0 |
T152 |
7613 |
9 |
0 |
0 |
T153 |
124077 |
753 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4744 |
0 |
0 |
T64 |
6308 |
60 |
0 |
0 |
T116 |
94204 |
365 |
0 |
0 |
T118 |
5943 |
75 |
0 |
0 |
T121 |
3884 |
34 |
0 |
0 |
T122 |
270676 |
688 |
0 |
0 |
T124 |
115963 |
793 |
0 |
0 |
T125 |
8005 |
57 |
0 |
0 |
T151 |
42087 |
281 |
0 |
0 |
T152 |
7613 |
23 |
0 |
0 |
T153 |
124077 |
822 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4752 |
0 |
0 |
T64 |
6308 |
4 |
0 |
0 |
T97 |
5604 |
5 |
0 |
0 |
T116 |
94204 |
304 |
0 |
0 |
T118 |
5943 |
2 |
0 |
0 |
T121 |
3884 |
6 |
0 |
0 |
T122 |
270676 |
703 |
0 |
0 |
T124 |
115963 |
773 |
0 |
0 |
T125 |
8005 |
51 |
0 |
0 |
T151 |
42087 |
223 |
0 |
0 |
T153 |
124077 |
756 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4982 |
0 |
0 |
T64 |
6308 |
62 |
0 |
0 |
T116 |
94204 |
535 |
0 |
0 |
T118 |
5943 |
55 |
0 |
0 |
T121 |
3884 |
4 |
0 |
0 |
T122 |
270676 |
610 |
0 |
0 |
T124 |
115963 |
678 |
0 |
0 |
T125 |
8005 |
88 |
0 |
0 |
T126 |
3521 |
2 |
0 |
0 |
T151 |
42087 |
269 |
0 |
0 |
T152 |
7613 |
11 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4190 |
0 |
0 |
T64 |
6308 |
57 |
0 |
0 |
T116 |
94204 |
272 |
0 |
0 |
T118 |
5943 |
8 |
0 |
0 |
T121 |
3884 |
45 |
0 |
0 |
T122 |
270676 |
666 |
0 |
0 |
T124 |
115963 |
731 |
0 |
0 |
T125 |
8005 |
50 |
0 |
0 |
T151 |
42087 |
271 |
0 |
0 |
T152 |
7613 |
2 |
0 |
0 |
T153 |
124077 |
783 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4560 |
0 |
0 |
T64 |
6308 |
45 |
0 |
0 |
T116 |
94204 |
419 |
0 |
0 |
T118 |
5943 |
45 |
0 |
0 |
T121 |
3884 |
4 |
0 |
0 |
T122 |
270676 |
638 |
0 |
0 |
T124 |
115963 |
729 |
0 |
0 |
T125 |
8005 |
18 |
0 |
0 |
T126 |
3521 |
32 |
0 |
0 |
T151 |
42087 |
268 |
0 |
0 |
T153 |
124077 |
776 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4825 |
0 |
0 |
T64 |
6308 |
1 |
0 |
0 |
T116 |
94204 |
401 |
0 |
0 |
T118 |
5943 |
6 |
0 |
0 |
T121 |
3884 |
2 |
0 |
0 |
T122 |
270676 |
747 |
0 |
0 |
T124 |
115963 |
797 |
0 |
0 |
T125 |
8005 |
27 |
0 |
0 |
T126 |
3521 |
24 |
0 |
0 |
T151 |
42087 |
267 |
0 |
0 |
T152 |
7613 |
22 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4610 |
0 |
0 |
T64 |
6308 |
10 |
0 |
0 |
T116 |
94204 |
433 |
0 |
0 |
T118 |
5943 |
1 |
0 |
0 |
T121 |
3884 |
2 |
0 |
0 |
T122 |
270676 |
675 |
0 |
0 |
T124 |
115963 |
801 |
0 |
0 |
T125 |
8005 |
8 |
0 |
0 |
T126 |
3521 |
13 |
0 |
0 |
T151 |
42087 |
263 |
0 |
0 |
T152 |
7613 |
5 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4797 |
0 |
0 |
T64 |
6308 |
75 |
0 |
0 |
T116 |
94204 |
398 |
0 |
0 |
T118 |
5943 |
7 |
0 |
0 |
T121 |
3884 |
42 |
0 |
0 |
T122 |
270676 |
629 |
0 |
0 |
T124 |
115963 |
712 |
0 |
0 |
T125 |
8005 |
44 |
0 |
0 |
T126 |
3521 |
20 |
0 |
0 |
T151 |
42087 |
237 |
0 |
0 |
T152 |
7613 |
6 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4793 |
0 |
0 |
T64 |
6308 |
8 |
0 |
0 |
T116 |
94204 |
423 |
0 |
0 |
T118 |
5943 |
2 |
0 |
0 |
T121 |
3884 |
7 |
0 |
0 |
T122 |
270676 |
676 |
0 |
0 |
T124 |
115963 |
712 |
0 |
0 |
T125 |
8005 |
51 |
0 |
0 |
T151 |
42087 |
255 |
0 |
0 |
T152 |
7613 |
12 |
0 |
0 |
T153 |
124077 |
810 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4764 |
0 |
0 |
T64 |
6308 |
6 |
0 |
0 |
T116 |
94204 |
505 |
0 |
0 |
T118 |
5943 |
6 |
0 |
0 |
T121 |
3884 |
4 |
0 |
0 |
T122 |
270676 |
596 |
0 |
0 |
T124 |
115963 |
736 |
0 |
0 |
T125 |
8005 |
6 |
0 |
0 |
T151 |
42087 |
274 |
0 |
0 |
T152 |
7613 |
18 |
0 |
0 |
T153 |
124077 |
828 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4763 |
0 |
0 |
T64 |
6308 |
51 |
0 |
0 |
T116 |
94204 |
450 |
0 |
0 |
T118 |
5943 |
2 |
0 |
0 |
T121 |
3884 |
36 |
0 |
0 |
T122 |
270676 |
684 |
0 |
0 |
T124 |
115963 |
698 |
0 |
0 |
T125 |
8005 |
29 |
0 |
0 |
T151 |
42087 |
295 |
0 |
0 |
T152 |
7613 |
38 |
0 |
0 |
T153 |
124077 |
728 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4843 |
0 |
0 |
T64 |
6308 |
64 |
0 |
0 |
T116 |
94204 |
481 |
0 |
0 |
T118 |
5943 |
47 |
0 |
0 |
T121 |
3884 |
3 |
0 |
0 |
T122 |
270676 |
648 |
0 |
0 |
T124 |
115963 |
723 |
0 |
0 |
T125 |
8005 |
1 |
0 |
0 |
T126 |
3521 |
40 |
0 |
0 |
T151 |
42087 |
283 |
0 |
0 |
T152 |
7613 |
18 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4939 |
0 |
0 |
T64 |
6308 |
63 |
0 |
0 |
T116 |
94204 |
427 |
0 |
0 |
T118 |
5943 |
3 |
0 |
0 |
T121 |
3884 |
2 |
0 |
0 |
T122 |
270676 |
656 |
0 |
0 |
T124 |
115963 |
804 |
0 |
0 |
T125 |
8005 |
66 |
0 |
0 |
T126 |
3521 |
13 |
0 |
0 |
T151 |
42087 |
264 |
0 |
0 |
T152 |
7613 |
28 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4728 |
0 |
0 |
T64 |
6308 |
11 |
0 |
0 |
T116 |
94204 |
324 |
0 |
0 |
T118 |
5943 |
66 |
0 |
0 |
T121 |
3884 |
49 |
0 |
0 |
T122 |
270676 |
637 |
0 |
0 |
T124 |
115963 |
687 |
0 |
0 |
T125 |
8005 |
6 |
0 |
0 |
T126 |
3521 |
5 |
0 |
0 |
T151 |
42087 |
235 |
0 |
0 |
T152 |
7613 |
16 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4696 |
0 |
0 |
T64 |
6308 |
61 |
0 |
0 |
T116 |
94204 |
391 |
0 |
0 |
T118 |
5943 |
48 |
0 |
0 |
T121 |
3884 |
43 |
0 |
0 |
T122 |
270676 |
688 |
0 |
0 |
T124 |
115963 |
770 |
0 |
0 |
T125 |
8005 |
4 |
0 |
0 |
T151 |
42087 |
293 |
0 |
0 |
T152 |
7613 |
17 |
0 |
0 |
T153 |
124077 |
812 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3340 |
0 |
0 |
T64 |
6308 |
9 |
0 |
0 |
T116 |
94204 |
94 |
0 |
0 |
T118 |
5943 |
8 |
0 |
0 |
T121 |
3884 |
10 |
0 |
0 |
T122 |
270676 |
687 |
0 |
0 |
T124 |
115963 |
724 |
0 |
0 |
T125 |
8005 |
2 |
0 |
0 |
T126 |
3521 |
6 |
0 |
0 |
T151 |
42087 |
253 |
0 |
0 |
T152 |
7613 |
3 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3263 |
0 |
0 |
T64 |
6308 |
2 |
0 |
0 |
T116 |
94204 |
62 |
0 |
0 |
T118 |
5943 |
5 |
0 |
0 |
T121 |
3884 |
6 |
0 |
0 |
T122 |
270676 |
664 |
0 |
0 |
T124 |
115963 |
691 |
0 |
0 |
T125 |
8005 |
5 |
0 |
0 |
T126 |
3521 |
2 |
0 |
0 |
T151 |
42087 |
277 |
0 |
0 |
T152 |
7613 |
36 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3157 |
0 |
0 |
T64 |
6308 |
11 |
0 |
0 |
T116 |
94204 |
66 |
0 |
0 |
T118 |
5943 |
21 |
0 |
0 |
T122 |
270676 |
626 |
0 |
0 |
T124 |
115963 |
764 |
0 |
0 |
T125 |
8005 |
1 |
0 |
0 |
T126 |
3521 |
4 |
0 |
0 |
T151 |
42087 |
245 |
0 |
0 |
T152 |
7613 |
24 |
0 |
0 |
T153 |
124077 |
752 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3393 |
0 |
0 |
T64 |
6308 |
9 |
0 |
0 |
T116 |
94204 |
76 |
0 |
0 |
T118 |
5943 |
16 |
0 |
0 |
T121 |
3884 |
11 |
0 |
0 |
T122 |
270676 |
666 |
0 |
0 |
T124 |
115963 |
755 |
0 |
0 |
T125 |
8005 |
3 |
0 |
0 |
T126 |
3521 |
12 |
0 |
0 |
T151 |
42087 |
241 |
0 |
0 |
T152 |
7613 |
33 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3622 |
0 |
0 |
T64 |
6308 |
13 |
0 |
0 |
T116 |
94204 |
157 |
0 |
0 |
T118 |
5943 |
23 |
0 |
0 |
T121 |
3884 |
17 |
0 |
0 |
T122 |
270676 |
643 |
0 |
0 |
T124 |
115963 |
731 |
0 |
0 |
T125 |
8005 |
10 |
0 |
0 |
T126 |
3521 |
8 |
0 |
0 |
T151 |
42087 |
242 |
0 |
0 |
T152 |
7613 |
8 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
4896 |
0 |
0 |
T154 |
486614 |
60 |
0 |
0 |
T155 |
0 |
25 |
0 |
0 |
T156 |
0 |
42 |
0 |
0 |
T157 |
0 |
21 |
0 |
0 |
T158 |
0 |
31 |
0 |
0 |
T159 |
0 |
78 |
0 |
0 |
T160 |
0 |
15 |
0 |
0 |
T161 |
0 |
38 |
0 |
0 |
T162 |
0 |
41 |
0 |
0 |
T163 |
0 |
40 |
0 |
0 |
T164 |
123442 |
0 |
0 |
0 |
T165 |
419641 |
0 |
0 |
0 |
T166 |
1545 |
0 |
0 |
0 |
T167 |
7573 |
0 |
0 |
0 |
T168 |
4010 |
0 |
0 |
0 |
T169 |
148220 |
0 |
0 |
0 |
T170 |
72959 |
0 |
0 |
0 |
T171 |
445177 |
0 |
0 |
0 |
T172 |
384152 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3323 |
0 |
0 |
T64 |
6308 |
10 |
0 |
0 |
T116 |
94204 |
95 |
0 |
0 |
T118 |
5943 |
1 |
0 |
0 |
T122 |
270676 |
652 |
0 |
0 |
T124 |
115963 |
759 |
0 |
0 |
T125 |
8005 |
1 |
0 |
0 |
T126 |
3521 |
4 |
0 |
0 |
T151 |
42087 |
253 |
0 |
0 |
T152 |
7613 |
21 |
0 |
0 |
T153 |
124077 |
818 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3409 |
0 |
0 |
T64 |
6308 |
9 |
0 |
0 |
T116 |
94204 |
85 |
0 |
0 |
T118 |
5943 |
8 |
0 |
0 |
T121 |
3884 |
8 |
0 |
0 |
T122 |
270676 |
685 |
0 |
0 |
T124 |
115963 |
664 |
0 |
0 |
T125 |
8005 |
15 |
0 |
0 |
T151 |
42087 |
280 |
0 |
0 |
T152 |
7613 |
24 |
0 |
0 |
T153 |
124077 |
796 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3186 |
0 |
0 |
T64 |
6308 |
16 |
0 |
0 |
T116 |
94204 |
28 |
0 |
0 |
T118 |
5943 |
6 |
0 |
0 |
T121 |
3884 |
9 |
0 |
0 |
T122 |
270676 |
684 |
0 |
0 |
T124 |
115963 |
737 |
0 |
0 |
T131 |
90520 |
198 |
0 |
0 |
T151 |
42087 |
232 |
0 |
0 |
T152 |
7613 |
37 |
0 |
0 |
T153 |
124077 |
835 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3168 |
0 |
0 |
T64 |
6308 |
7 |
0 |
0 |
T116 |
94204 |
61 |
0 |
0 |
T118 |
5943 |
9 |
0 |
0 |
T121 |
3884 |
9 |
0 |
0 |
T122 |
270676 |
707 |
0 |
0 |
T124 |
115963 |
748 |
0 |
0 |
T125 |
8005 |
1 |
0 |
0 |
T126 |
3521 |
5 |
0 |
0 |
T151 |
42087 |
268 |
0 |
0 |
T152 |
7613 |
34 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3077 |
0 |
0 |
T64 |
6308 |
2 |
0 |
0 |
T116 |
94204 |
63 |
0 |
0 |
T118 |
5943 |
10 |
0 |
0 |
T121 |
3884 |
6 |
0 |
0 |
T122 |
270676 |
710 |
0 |
0 |
T124 |
115963 |
674 |
0 |
0 |
T125 |
8005 |
12 |
0 |
0 |
T126 |
3521 |
8 |
0 |
0 |
T151 |
42087 |
270 |
0 |
0 |
T152 |
7613 |
2 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3022 |
0 |
0 |
T64 |
6308 |
8 |
0 |
0 |
T116 |
94204 |
52 |
0 |
0 |
T118 |
5943 |
5 |
0 |
0 |
T121 |
3884 |
7 |
0 |
0 |
T122 |
270676 |
651 |
0 |
0 |
T124 |
115963 |
719 |
0 |
0 |
T125 |
8005 |
1 |
0 |
0 |
T151 |
42087 |
309 |
0 |
0 |
T152 |
7613 |
15 |
0 |
0 |
T153 |
124077 |
737 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3475 |
0 |
0 |
T64 |
6308 |
27 |
0 |
0 |
T116 |
94204 |
148 |
0 |
0 |
T118 |
5943 |
6 |
0 |
0 |
T121 |
3884 |
23 |
0 |
0 |
T122 |
270676 |
673 |
0 |
0 |
T124 |
115963 |
698 |
0 |
0 |
T125 |
8005 |
20 |
0 |
0 |
T126 |
3521 |
5 |
0 |
0 |
T151 |
42087 |
230 |
0 |
0 |
T152 |
7613 |
15 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3320 |
0 |
0 |
T64 |
6308 |
11 |
0 |
0 |
T116 |
94204 |
77 |
0 |
0 |
T118 |
5943 |
17 |
0 |
0 |
T121 |
3884 |
8 |
0 |
0 |
T122 |
270676 |
716 |
0 |
0 |
T124 |
115963 |
811 |
0 |
0 |
T126 |
3521 |
10 |
0 |
0 |
T151 |
42087 |
307 |
0 |
0 |
T152 |
7613 |
21 |
0 |
0 |
T153 |
124077 |
723 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3559 |
0 |
0 |
T64 |
6308 |
11 |
0 |
0 |
T116 |
94204 |
170 |
0 |
0 |
T118 |
5943 |
10 |
0 |
0 |
T122 |
270676 |
676 |
0 |
0 |
T124 |
115963 |
709 |
0 |
0 |
T125 |
8005 |
28 |
0 |
0 |
T126 |
3521 |
7 |
0 |
0 |
T151 |
42087 |
203 |
0 |
0 |
T152 |
7613 |
41 |
0 |
0 |
T153 |
124077 |
797 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3386 |
0 |
0 |
T64 |
6308 |
12 |
0 |
0 |
T116 |
94204 |
101 |
0 |
0 |
T118 |
5943 |
12 |
0 |
0 |
T121 |
3884 |
7 |
0 |
0 |
T122 |
270676 |
688 |
0 |
0 |
T124 |
115963 |
774 |
0 |
0 |
T125 |
8005 |
9 |
0 |
0 |
T126 |
3521 |
1 |
0 |
0 |
T151 |
42087 |
282 |
0 |
0 |
T152 |
7613 |
23 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3242 |
0 |
0 |
T64 |
6308 |
11 |
0 |
0 |
T97 |
5604 |
3 |
0 |
0 |
T116 |
94204 |
65 |
0 |
0 |
T118 |
5943 |
4 |
0 |
0 |
T121 |
3884 |
2 |
0 |
0 |
T122 |
270676 |
704 |
0 |
0 |
T124 |
115963 |
817 |
0 |
0 |
T125 |
8005 |
2 |
0 |
0 |
T151 |
42087 |
233 |
0 |
0 |
T152 |
7613 |
5 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3186 |
0 |
0 |
T64 |
6308 |
2 |
0 |
0 |
T116 |
94204 |
70 |
0 |
0 |
T118 |
5943 |
14 |
0 |
0 |
T121 |
3884 |
2 |
0 |
0 |
T122 |
270676 |
698 |
0 |
0 |
T124 |
115963 |
671 |
0 |
0 |
T125 |
8005 |
5 |
0 |
0 |
T126 |
3521 |
1 |
0 |
0 |
T151 |
42087 |
242 |
0 |
0 |
T152 |
7613 |
54 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3114 |
0 |
0 |
T64 |
6308 |
9 |
0 |
0 |
T116 |
94204 |
94 |
0 |
0 |
T118 |
5943 |
15 |
0 |
0 |
T121 |
3884 |
8 |
0 |
0 |
T122 |
270676 |
682 |
0 |
0 |
T124 |
115963 |
750 |
0 |
0 |
T125 |
8005 |
9 |
0 |
0 |
T151 |
42087 |
283 |
0 |
0 |
T152 |
7613 |
34 |
0 |
0 |
T153 |
124077 |
696 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3179 |
0 |
0 |
T64 |
6308 |
8 |
0 |
0 |
T116 |
94204 |
48 |
0 |
0 |
T118 |
5943 |
4 |
0 |
0 |
T121 |
3884 |
2 |
0 |
0 |
T122 |
270676 |
696 |
0 |
0 |
T124 |
115963 |
695 |
0 |
0 |
T125 |
8005 |
8 |
0 |
0 |
T126 |
3521 |
2 |
0 |
0 |
T151 |
42087 |
248 |
0 |
0 |
T152 |
7613 |
31 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3066 |
0 |
0 |
T64 |
6308 |
9 |
0 |
0 |
T85 |
2261 |
8 |
0 |
0 |
T116 |
94204 |
59 |
0 |
0 |
T118 |
5943 |
11 |
0 |
0 |
T122 |
270676 |
623 |
0 |
0 |
T124 |
115963 |
697 |
0 |
0 |
T131 |
90520 |
239 |
0 |
0 |
T151 |
42087 |
256 |
0 |
0 |
T152 |
7613 |
41 |
0 |
0 |
T153 |
124077 |
706 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399233932 |
3146 |
0 |
0 |
T64 |
6308 |
5 |
0 |
0 |
T116 |
94204 |
63 |
0 |
0 |
T118 |
5943 |
10 |
0 |
0 |
T121 |
3884 |
8 |
0 |
0 |
T122 |
270676 |
690 |
0 |
0 |
T124 |
115963 |
719 |
0 |
0 |
T125 |
8005 |
19 |
0 |
0 |
T151 |
42087 |
269 |
0 |
0 |
T152 |
7613 |
14 |
0 |
0 |
T153 |
124077 |
776 |
0 |
0 |