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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.30 94.11 98.61 89.36 97.14 95.84 99.10


Total test records in report: 1081
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T1015 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2998594117 Jun 04 12:45:22 PM PDT 24 Jun 04 12:45:24 PM PDT 24 25075334 ps
T1016 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3693474198 Jun 04 12:45:30 PM PDT 24 Jun 04 12:45:33 PM PDT 24 183928356 ps
T282 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1498628321 Jun 04 12:45:24 PM PDT 24 Jun 04 12:45:40 PM PDT 24 575418119 ps
T1017 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3993716985 Jun 04 12:45:42 PM PDT 24 Jun 04 12:45:45 PM PDT 24 101502037 ps
T132 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2400066693 Jun 04 12:45:35 PM PDT 24 Jun 04 12:45:40 PM PDT 24 346797922 ps
T1018 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3317206842 Jun 04 12:45:49 PM PDT 24 Jun 04 12:45:51 PM PDT 24 32186549 ps
T284 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.334054669 Jun 04 12:45:40 PM PDT 24 Jun 04 12:45:53 PM PDT 24 197610089 ps
T1019 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1706330130 Jun 04 12:45:26 PM PDT 24 Jun 04 12:45:30 PM PDT 24 18292318 ps
T109 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3363652857 Jun 04 12:45:39 PM PDT 24 Jun 04 12:45:44 PM PDT 24 237677913 ps
T1020 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3807185734 Jun 04 12:45:35 PM PDT 24 Jun 04 12:45:37 PM PDT 24 25612731 ps
T1021 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1584430856 Jun 04 12:45:41 PM PDT 24 Jun 04 12:45:43 PM PDT 24 12399041 ps
T287 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.216897897 Jun 04 12:45:33 PM PDT 24 Jun 04 12:45:48 PM PDT 24 944368189 ps
T107 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1857676159 Jun 04 12:45:40 PM PDT 24 Jun 04 12:45:43 PM PDT 24 43812665 ps
T1022 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2179627476 Jun 04 12:45:41 PM PDT 24 Jun 04 12:45:45 PM PDT 24 31196560 ps
T1023 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.681210423 Jun 04 12:45:41 PM PDT 24 Jun 04 12:45:45 PM PDT 24 118314386 ps
T110 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3213972525 Jun 04 12:45:22 PM PDT 24 Jun 04 12:45:26 PM PDT 24 56021941 ps
T133 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.696305159 Jun 04 12:45:15 PM PDT 24 Jun 04 12:45:49 PM PDT 24 2739289971 ps
T1024 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3692827361 Jun 04 12:45:41 PM PDT 24 Jun 04 12:45:52 PM PDT 24 3858819335 ps
T105 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1912584587 Jun 04 12:45:39 PM PDT 24 Jun 04 12:45:42 PM PDT 24 198784183 ps
T1025 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2723393056 Jun 04 12:45:44 PM PDT 24 Jun 04 12:45:46 PM PDT 24 171199722 ps
T1026 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2387370624 Jun 04 12:45:26 PM PDT 24 Jun 04 12:45:31 PM PDT 24 60043920 ps
T1027 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2001789404 Jun 04 12:45:42 PM PDT 24 Jun 04 12:45:45 PM PDT 24 11564711 ps
T290 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2060963798 Jun 04 12:45:34 PM PDT 24 Jun 04 12:45:41 PM PDT 24 138363979 ps
T106 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.240470806 Jun 04 12:45:23 PM PDT 24 Jun 04 12:45:28 PM PDT 24 546340420 ps
T1028 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.945090620 Jun 04 12:45:45 PM PDT 24 Jun 04 12:45:48 PM PDT 24 15402110 ps
T1029 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3014149122 Jun 04 12:45:33 PM PDT 24 Jun 04 12:45:40 PM PDT 24 947458250 ps
T288 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3484864827 Jun 04 12:45:31 PM PDT 24 Jun 04 12:45:44 PM PDT 24 2742934603 ps
T1030 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.806598104 Jun 04 12:45:36 PM PDT 24 Jun 04 12:45:39 PM PDT 24 249693093 ps
T1031 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2847128935 Jun 04 12:45:23 PM PDT 24 Jun 04 12:45:30 PM PDT 24 520533025 ps
T1032 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2282318126 Jun 04 12:45:33 PM PDT 24 Jun 04 12:45:35 PM PDT 24 18333637 ps
T1033 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.944013177 Jun 04 12:45:42 PM PDT 24 Jun 04 12:45:46 PM PDT 24 119253047 ps
T1034 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1520517403 Jun 04 12:45:24 PM PDT 24 Jun 04 12:45:39 PM PDT 24 2432037517 ps
T1035 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3806334923 Jun 04 12:45:41 PM PDT 24 Jun 04 12:45:43 PM PDT 24 11746289 ps
T1036 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.205421853 Jun 04 12:45:38 PM PDT 24 Jun 04 12:45:40 PM PDT 24 24480021 ps
T1037 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2839144577 Jun 04 12:45:39 PM PDT 24 Jun 04 12:45:41 PM PDT 24 58811382 ps
T1038 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3769765432 Jun 04 12:45:24 PM PDT 24 Jun 04 12:45:29 PM PDT 24 69355333 ps
T1039 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2465488394 Jun 04 12:46:06 PM PDT 24 Jun 04 12:46:08 PM PDT 24 41647331 ps
T1040 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4288493757 Jun 04 12:45:40 PM PDT 24 Jun 04 12:45:43 PM PDT 24 31732712 ps
T1041 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2768302043 Jun 04 12:45:41 PM PDT 24 Jun 04 12:45:46 PM PDT 24 39931042 ps
T1042 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3392871528 Jun 04 12:46:03 PM PDT 24 Jun 04 12:46:05 PM PDT 24 23138088 ps
T1043 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3441500305 Jun 04 12:45:24 PM PDT 24 Jun 04 12:45:29 PM PDT 24 258798845 ps
T1044 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1105813947 Jun 04 12:45:36 PM PDT 24 Jun 04 12:45:41 PM PDT 24 211906357 ps
T1045 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1490138948 Jun 04 12:45:42 PM PDT 24 Jun 04 12:45:44 PM PDT 24 49187049 ps
T1046 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3680814763 Jun 04 12:45:34 PM PDT 24 Jun 04 12:45:37 PM PDT 24 88366327 ps
T1047 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3277294758 Jun 04 12:45:11 PM PDT 24 Jun 04 12:45:14 PM PDT 24 44325666 ps
T1048 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.453717014 Jun 04 12:45:42 PM PDT 24 Jun 04 12:45:46 PM PDT 24 24743100 ps
T1049 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2825540650 Jun 04 12:45:24 PM PDT 24 Jun 04 12:45:30 PM PDT 24 252196946 ps
T1050 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.534423268 Jun 04 12:45:24 PM PDT 24 Jun 04 12:45:27 PM PDT 24 33904260 ps
T1051 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1012235254 Jun 04 12:45:33 PM PDT 24 Jun 04 12:45:36 PM PDT 24 184850475 ps
T1052 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3060526510 Jun 04 12:45:26 PM PDT 24 Jun 04 12:45:31 PM PDT 24 263416280 ps
T285 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.983581080 Jun 04 12:45:14 PM PDT 24 Jun 04 12:45:38 PM PDT 24 4244738272 ps
T1053 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.383001326 Jun 04 12:45:39 PM PDT 24 Jun 04 12:45:41 PM PDT 24 20829851 ps
T1054 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1887737386 Jun 04 12:45:33 PM PDT 24 Jun 04 12:45:37 PM PDT 24 88556651 ps
T1055 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.563785785 Jun 04 12:45:16 PM PDT 24 Jun 04 12:45:18 PM PDT 24 133942801 ps
T1056 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1445723338 Jun 04 12:45:43 PM PDT 24 Jun 04 12:45:46 PM PDT 24 17694117 ps
T1057 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.255328788 Jun 04 12:45:41 PM PDT 24 Jun 04 12:45:49 PM PDT 24 104906492 ps
T1058 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1907667580 Jun 04 12:45:39 PM PDT 24 Jun 04 12:45:41 PM PDT 24 14397489 ps
T1059 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2813190207 Jun 04 12:45:32 PM PDT 24 Jun 04 12:45:37 PM PDT 24 175100121 ps
T1060 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3872897338 Jun 04 12:45:41 PM PDT 24 Jun 04 12:45:47 PM PDT 24 378503051 ps
T1061 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3148616981 Jun 04 12:45:31 PM PDT 24 Jun 04 12:45:36 PM PDT 24 374726898 ps
T1062 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4051168547 Jun 04 12:45:42 PM PDT 24 Jun 04 12:45:45 PM PDT 24 22124352 ps
T1063 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3055644071 Jun 04 12:45:36 PM PDT 24 Jun 04 12:45:40 PM PDT 24 74767625 ps
T1064 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1724256229 Jun 04 12:45:36 PM PDT 24 Jun 04 12:45:41 PM PDT 24 3077456288 ps
T1065 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1311222279 Jun 04 12:46:06 PM PDT 24 Jun 04 12:46:10 PM PDT 24 64130883 ps
T1066 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2797454739 Jun 04 12:45:45 PM PDT 24 Jun 04 12:45:50 PM PDT 24 71282216 ps
T1067 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2445610054 Jun 04 12:45:25 PM PDT 24 Jun 04 12:45:33 PM PDT 24 2374881600 ps
T1068 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1124263846 Jun 04 12:45:25 PM PDT 24 Jun 04 12:45:29 PM PDT 24 135647412 ps
T1069 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2559464212 Jun 04 12:45:41 PM PDT 24 Jun 04 12:45:45 PM PDT 24 52924832 ps
T1070 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2912699319 Jun 04 12:45:32 PM PDT 24 Jun 04 12:45:34 PM PDT 24 24792906 ps
T1071 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1743565156 Jun 04 12:45:19 PM PDT 24 Jun 04 12:45:27 PM PDT 24 317027345 ps
T1072 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1822066013 Jun 04 12:45:45 PM PDT 24 Jun 04 12:45:47 PM PDT 24 60249043 ps
T1073 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.251760598 Jun 04 12:45:33 PM PDT 24 Jun 04 12:45:39 PM PDT 24 55130563 ps
T1074 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1606879846 Jun 04 12:45:32 PM PDT 24 Jun 04 12:45:35 PM PDT 24 50761993 ps
T286 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3533549958 Jun 04 12:45:31 PM PDT 24 Jun 04 12:45:49 PM PDT 24 1111142456 ps
T1075 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.294353014 Jun 04 12:45:32 PM PDT 24 Jun 04 12:45:36 PM PDT 24 171069522 ps
T1076 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2045822655 Jun 04 12:45:16 PM PDT 24 Jun 04 12:45:18 PM PDT 24 65271288 ps
T1077 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.20273191 Jun 04 12:45:49 PM PDT 24 Jun 04 12:45:51 PM PDT 24 75150996 ps
T1078 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2694939265 Jun 04 12:45:31 PM PDT 24 Jun 04 12:45:35 PM PDT 24 784358920 ps
T1079 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1478661307 Jun 04 12:45:34 PM PDT 24 Jun 04 12:45:36 PM PDT 24 15404063 ps
T1080 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3503780957 Jun 04 12:45:38 PM PDT 24 Jun 04 12:45:39 PM PDT 24 62147140 ps
T1081 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1430204010 Jun 04 12:45:42 PM PDT 24 Jun 04 12:45:58 PM PDT 24 1920387903 ps

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.699031144
Short name T4
Test name
Test status
Simulation time 1948705029 ps
CPU time 41.2 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:03:35 PM PDT 24
Peak memory 255368 kb
Host smart-5716f1c4-debe-4d60-92f4-813ddfef1343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699031144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.699031144
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1314078598
Short name T29
Test name
Test status
Simulation time 21148675099 ps
CPU time 287.77 seconds
Started Jun 04 02:04:23 PM PDT 24
Finished Jun 04 02:09:13 PM PDT 24
Peak memory 273504 kb
Host smart-8915cbc6-0f2c-49ef-9c59-aa65e18701d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314078598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1314078598
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1804496508
Short name T81
Test name
Test status
Simulation time 914408286 ps
CPU time 10.63 seconds
Started Jun 04 02:01:47 PM PDT 24
Finished Jun 04 02:01:59 PM PDT 24
Peak memory 233180 kb
Host smart-3324555f-d0b3-4df8-a29b-852177706d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804496508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1804496508
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2681471294
Short name T18
Test name
Test status
Simulation time 18412527133 ps
CPU time 161.01 seconds
Started Jun 04 02:02:40 PM PDT 24
Finished Jun 04 02:05:22 PM PDT 24
Peak memory 240244 kb
Host smart-245a990f-4339-4c69-9910-73250fb2ec51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681471294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2681471294
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.332935080
Short name T116
Test name
Test status
Simulation time 3768212929 ps
CPU time 19.71 seconds
Started Jun 04 12:45:48 PM PDT 24
Finished Jun 04 12:46:09 PM PDT 24
Peak memory 215724 kb
Host smart-7d316afb-9c46-4668-8485-f33cb9ae1648
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332935080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.332935080
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.52879907
Short name T155
Test name
Test status
Simulation time 46432069473 ps
CPU time 414.1 seconds
Started Jun 04 02:01:32 PM PDT 24
Finished Jun 04 02:08:27 PM PDT 24
Peak memory 265508 kb
Host smart-afa2c109-1902-4c01-880b-211f68b2f046
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52879907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_
all.52879907
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2771854858
Short name T65
Test name
Test status
Simulation time 31735774 ps
CPU time 0.76 seconds
Started Jun 04 02:01:18 PM PDT 24
Finished Jun 04 02:01:21 PM PDT 24
Peak memory 216052 kb
Host smart-e3a89308-8846-43f9-8927-94c3ef8d85ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771854858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2771854858
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3877672170
Short name T35
Test name
Test status
Simulation time 392524789657 ps
CPU time 662.71 seconds
Started Jun 04 02:01:34 PM PDT 24
Finished Jun 04 02:12:38 PM PDT 24
Peak memory 256980 kb
Host smart-8b7c274d-1fb1-4d67-a529-e0c6e2a270df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877672170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3877672170
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2398508788
Short name T32
Test name
Test status
Simulation time 33354690143 ps
CPU time 296.14 seconds
Started Jun 04 02:01:26 PM PDT 24
Finished Jun 04 02:06:24 PM PDT 24
Peak memory 250200 kb
Host smart-d72d60eb-16c4-4afa-99ab-7a6449239d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398508788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2398508788
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3705390031
Short name T31
Test name
Test status
Simulation time 288577651573 ps
CPU time 441.95 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:10:16 PM PDT 24
Peak memory 269108 kb
Host smart-e0bddb67-5b63-47a1-b9cf-ceb9c4098a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705390031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3705390031
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.651308086
Short name T63
Test name
Test status
Simulation time 54273321 ps
CPU time 3.27 seconds
Started Jun 04 12:45:32 PM PDT 24
Finished Jun 04 12:45:36 PM PDT 24
Peak memory 215252 kb
Host smart-e90f06f2-ca9b-4cf8-9265-2f37e64bdc65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651308086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.651308086
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1112235589
Short name T195
Test name
Test status
Simulation time 179920824154 ps
CPU time 583.47 seconds
Started Jun 04 02:01:40 PM PDT 24
Finished Jun 04 02:11:24 PM PDT 24
Peak memory 255600 kb
Host smart-407b0673-71d1-4c73-9797-5cc02d48fe12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112235589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1112235589
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3473217729
Short name T178
Test name
Test status
Simulation time 65548185822 ps
CPU time 182.53 seconds
Started Jun 04 02:03:08 PM PDT 24
Finished Jun 04 02:06:12 PM PDT 24
Peak memory 251196 kb
Host smart-31a797a4-1057-460f-ad00-215b334f2431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473217729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3473217729
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2577971659
Short name T140
Test name
Test status
Simulation time 348855887992 ps
CPU time 584.43 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:11:06 PM PDT 24
Peak memory 270096 kb
Host smart-304ae8ba-9b54-4a76-9fa9-a3a0dde78335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577971659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2577971659
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3710864110
Short name T7
Test name
Test status
Simulation time 40247750 ps
CPU time 0.7 seconds
Started Jun 04 02:03:38 PM PDT 24
Finished Jun 04 02:03:40 PM PDT 24
Peak memory 204764 kb
Host smart-fa05be04-41ba-4de9-8217-dc141e481f76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710864110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3710864110
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3953539327
Short name T148
Test name
Test status
Simulation time 13232275897 ps
CPU time 37.98 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:04:02 PM PDT 24
Peak memory 238660 kb
Host smart-059e981d-2ca8-420a-8d50-441e57d3534c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953539327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3953539327
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3014685824
Short name T176
Test name
Test status
Simulation time 34246430279 ps
CPU time 289.96 seconds
Started Jun 04 02:04:09 PM PDT 24
Finished Jun 04 02:08:59 PM PDT 24
Peak memory 261188 kb
Host smart-8e903425-cf1d-4d1c-9cd8-3c3b5715617e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014685824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3014685824
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1302295184
Short name T125
Test name
Test status
Simulation time 81702684 ps
CPU time 2.11 seconds
Started Jun 04 12:45:36 PM PDT 24
Finished Jun 04 12:45:39 PM PDT 24
Peak memory 206896 kb
Host smart-5190dbce-ccfa-4606-8a4c-92905db5f8db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302295184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1302295184
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1145807792
Short name T205
Test name
Test status
Simulation time 662159611332 ps
CPU time 630.2 seconds
Started Jun 04 02:02:32 PM PDT 24
Finished Jun 04 02:13:03 PM PDT 24
Peak memory 265480 kb
Host smart-0f1840ca-ec75-499c-bcd5-efde8a0bf7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145807792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1145807792
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.4181985832
Short name T242
Test name
Test status
Simulation time 10055673314 ps
CPU time 124.55 seconds
Started Jun 04 02:04:09 PM PDT 24
Finished Jun 04 02:06:14 PM PDT 24
Peak memory 251220 kb
Host smart-bb93adf5-f8c2-48dc-886e-b85c6a7fc504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181985832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4181985832
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3716003174
Short name T208
Test name
Test status
Simulation time 20379255419 ps
CPU time 135.19 seconds
Started Jun 04 02:01:21 PM PDT 24
Finished Jun 04 02:03:38 PM PDT 24
Peak memory 272128 kb
Host smart-8ad07851-5ee6-47aa-aa96-717fab74a2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716003174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3716003174
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.4200831454
Short name T266
Test name
Test status
Simulation time 97784664558 ps
CPU time 116.8 seconds
Started Jun 04 02:02:47 PM PDT 24
Finished Jun 04 02:04:45 PM PDT 24
Peak memory 249128 kb
Host smart-6cd85bfc-9236-41a3-94c8-1623afef50a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200831454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4200831454
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.833183633
Short name T66
Test name
Test status
Simulation time 153825252 ps
CPU time 0.96 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:01:23 PM PDT 24
Peak memory 235052 kb
Host smart-e6f63972-c2d6-4c29-8ae6-72cdaad52a98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833183633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.833183633
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.900725838
Short name T246
Test name
Test status
Simulation time 57886459651 ps
CPU time 157.72 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:06:02 PM PDT 24
Peak memory 273516 kb
Host smart-f0a47bf1-8c22-4cf4-8edc-0dc73c01f709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900725838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.900725838
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1930832738
Short name T47
Test name
Test status
Simulation time 157647390644 ps
CPU time 729.21 seconds
Started Jun 04 02:01:19 PM PDT 24
Finished Jun 04 02:13:30 PM PDT 24
Peak memory 268852 kb
Host smart-1ff569a2-d31b-47e9-a00b-895676db25b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930832738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1930832738
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3696063016
Short name T139
Test name
Test status
Simulation time 50432745717 ps
CPU time 155.91 seconds
Started Jun 04 02:02:01 PM PDT 24
Finished Jun 04 02:04:38 PM PDT 24
Peak memory 249124 kb
Host smart-ab55e074-52d9-4102-9c69-70d9384fd434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696063016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3696063016
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.890219848
Short name T247
Test name
Test status
Simulation time 49248323678 ps
CPU time 543.03 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:12:41 PM PDT 24
Peak memory 273436 kb
Host smart-f14b2935-1a11-4a88-833c-e50764ff45c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890219848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.890219848
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.456964638
Short name T185
Test name
Test status
Simulation time 111054862240 ps
CPU time 412.35 seconds
Started Jun 04 02:03:01 PM PDT 24
Finished Jun 04 02:09:54 PM PDT 24
Peak memory 266820 kb
Host smart-d15ad63b-5821-418e-bee5-d46ef5d25b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456964638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.456964638
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3014149122
Short name T1029
Test name
Test status
Simulation time 947458250 ps
CPU time 5.57 seconds
Started Jun 04 12:45:33 PM PDT 24
Finished Jun 04 12:45:40 PM PDT 24
Peak memory 215340 kb
Host smart-7ce0dd6e-1d75-4962-87a3-ab30d2177970
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014149122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3014149122
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1994022531
Short name T310
Test name
Test status
Simulation time 7305683609 ps
CPU time 81.84 seconds
Started Jun 04 02:04:22 PM PDT 24
Finished Jun 04 02:05:45 PM PDT 24
Peak memory 239428 kb
Host smart-c792d9a7-668d-4f64-8a0a-ddc7b23969bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994022531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1994022531
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1473228875
Short name T30
Test name
Test status
Simulation time 865781077920 ps
CPU time 483.38 seconds
Started Jun 04 02:03:08 PM PDT 24
Finished Jun 04 02:11:13 PM PDT 24
Peak memory 267584 kb
Host smart-8f82c890-54e9-4a16-867c-64ffbe162428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473228875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1473228875
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3533549958
Short name T286
Test name
Test status
Simulation time 1111142456 ps
CPU time 17.4 seconds
Started Jun 04 12:45:31 PM PDT 24
Finished Jun 04 12:45:49 PM PDT 24
Peak memory 215144 kb
Host smart-491dc8dd-6c0c-4735-ab36-60dcf40c733e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533549958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3533549958
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.750374723
Short name T604
Test name
Test status
Simulation time 44267566653 ps
CPU time 126.33 seconds
Started Jun 04 02:02:07 PM PDT 24
Finished Jun 04 02:04:14 PM PDT 24
Peak memory 251992 kb
Host smart-69a3769d-8674-4362-a8cd-503ebca601b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750374723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.750374723
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3926430747
Short name T5
Test name
Test status
Simulation time 323997855 ps
CPU time 7.52 seconds
Started Jun 04 02:02:44 PM PDT 24
Finished Jun 04 02:02:52 PM PDT 24
Peak memory 236600 kb
Host smart-d8db292d-c3b7-492e-91cd-edaf95a7c20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926430747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3926430747
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3899365366
Short name T281
Test name
Test status
Simulation time 405867728 ps
CPU time 7.06 seconds
Started Jun 04 12:45:33 PM PDT 24
Finished Jun 04 12:45:42 PM PDT 24
Peak memory 215516 kb
Host smart-c8d5f13e-d9c8-495d-bfb2-4b5f6ad3f6a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899365366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3899365366
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3517836257
Short name T175
Test name
Test status
Simulation time 3377048263 ps
CPU time 52.9 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:02:15 PM PDT 24
Peak memory 250496 kb
Host smart-7d60c976-88b8-4012-bb25-5973aecafe21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517836257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3517836257
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1636195250
Short name T368
Test name
Test status
Simulation time 87458594 ps
CPU time 0.89 seconds
Started Jun 04 02:01:18 PM PDT 24
Finished Jun 04 02:01:21 PM PDT 24
Peak memory 206000 kb
Host smart-8cde586e-4d84-4837-8d69-8cb02551980f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636195250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1636195250
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2131578396
Short name T250
Test name
Test status
Simulation time 14015223577 ps
CPU time 158.27 seconds
Started Jun 04 02:02:06 PM PDT 24
Finished Jun 04 02:04:45 PM PDT 24
Peak memory 249064 kb
Host smart-224c6850-92c4-45f4-9025-272a19f15b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131578396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2131578396
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1044639334
Short name T231
Test name
Test status
Simulation time 2928002780 ps
CPU time 55.72 seconds
Started Jun 04 02:02:04 PM PDT 24
Finished Jun 04 02:03:01 PM PDT 24
Peak memory 239788 kb
Host smart-301c6e10-c433-4ae9-82b1-4f8a8fcce4b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044639334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1044639334
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3464476559
Short name T163
Test name
Test status
Simulation time 1082369043816 ps
CPU time 963.13 seconds
Started Jun 04 02:02:09 PM PDT 24
Finished Jun 04 02:18:14 PM PDT 24
Peak memory 269576 kb
Host smart-59b12f52-685e-43e3-aabe-adb49b7232c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464476559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3464476559
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2959328352
Short name T346
Test name
Test status
Simulation time 19731348696 ps
CPU time 60.06 seconds
Started Jun 04 02:03:02 PM PDT 24
Finished Jun 04 02:04:03 PM PDT 24
Peak memory 249064 kb
Host smart-14bbaa36-c904-4d60-acbe-854ab8ea7a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959328352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2959328352
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1473090907
Short name T92
Test name
Test status
Simulation time 1064514654 ps
CPU time 9.73 seconds
Started Jun 04 02:01:17 PM PDT 24
Finished Jun 04 02:01:27 PM PDT 24
Peak memory 234464 kb
Host smart-ce8f00c8-da0f-4fee-9b8e-d7ece8ae6449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473090907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1473090907
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.216897897
Short name T287
Test name
Test status
Simulation time 944368189 ps
CPU time 13.24 seconds
Started Jun 04 12:45:33 PM PDT 24
Finished Jun 04 12:45:48 PM PDT 24
Peak memory 215596 kb
Host smart-0186ea88-adbe-40fd-b262-d29706543641
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216897897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.216897897
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3704824241
Short name T267
Test name
Test status
Simulation time 332617053965 ps
CPU time 865.91 seconds
Started Jun 04 02:01:57 PM PDT 24
Finished Jun 04 02:16:24 PM PDT 24
Peak memory 254880 kb
Host smart-55731cc6-b5e8-4eb7-9032-ca054346b72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704824241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3704824241
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.652550070
Short name T355
Test name
Test status
Simulation time 1712611827 ps
CPU time 9.22 seconds
Started Jun 04 02:01:53 PM PDT 24
Finished Jun 04 02:02:03 PM PDT 24
Peak memory 216260 kb
Host smart-98627a49-b851-4ee9-b1b1-7d9c63b1e5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652550070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.652550070
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3668247250
Short name T913
Test name
Test status
Simulation time 491761601 ps
CPU time 9.66 seconds
Started Jun 04 02:02:02 PM PDT 24
Finished Jun 04 02:02:13 PM PDT 24
Peak memory 233564 kb
Host smart-09625e93-f8a0-4e2c-9e4f-451f423da22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668247250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3668247250
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.607605646
Short name T241
Test name
Test status
Simulation time 27116528170 ps
CPU time 176.54 seconds
Started Jun 04 02:02:08 PM PDT 24
Finished Jun 04 02:05:06 PM PDT 24
Peak memory 257164 kb
Host smart-dcb16005-acf7-485d-8bf1-6147196c8c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607605646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.607605646
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2810517393
Short name T161
Test name
Test status
Simulation time 3182885794 ps
CPU time 59.28 seconds
Started Jun 04 02:02:19 PM PDT 24
Finished Jun 04 02:03:20 PM PDT 24
Peak memory 250620 kb
Host smart-858770fc-d729-4bae-b02c-9f79356f6298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810517393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2810517393
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.870652096
Short name T278
Test name
Test status
Simulation time 8172318634 ps
CPU time 129.99 seconds
Started Jun 04 02:02:34 PM PDT 24
Finished Jun 04 02:04:46 PM PDT 24
Peak memory 249244 kb
Host smart-2481389b-329d-4369-ad17-1df42cf0c79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870652096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.870652096
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1337380251
Short name T263
Test name
Test status
Simulation time 29147390436 ps
CPU time 118.73 seconds
Started Jun 04 02:02:30 PM PDT 24
Finished Jun 04 02:04:29 PM PDT 24
Peak memory 254340 kb
Host smart-33fe3f57-b99c-4441-85df-8cc863f16fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337380251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1337380251
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3611215235
Short name T276
Test name
Test status
Simulation time 6169920094 ps
CPU time 80.64 seconds
Started Jun 04 02:02:41 PM PDT 24
Finished Jun 04 02:04:02 PM PDT 24
Peak memory 249052 kb
Host smart-812d2e5a-128e-49a2-b115-bbf7dc1dace3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611215235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3611215235
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3512749787
Short name T354
Test name
Test status
Simulation time 2038068464 ps
CPU time 9.26 seconds
Started Jun 04 02:03:08 PM PDT 24
Finished Jun 04 02:03:18 PM PDT 24
Peak memory 232972 kb
Host smart-d06569c2-26c7-4343-959f-b4bd4f895462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512749787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3512749787
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.634301129
Short name T34
Test name
Test status
Simulation time 2831706346 ps
CPU time 6.61 seconds
Started Jun 04 02:03:30 PM PDT 24
Finished Jun 04 02:03:38 PM PDT 24
Peak memory 238280 kb
Host smart-6efaec14-1be1-4662-98d2-e3a77aad47cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634301129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.634301129
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3968178143
Short name T269
Test name
Test status
Simulation time 90296167376 ps
CPU time 142.56 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:06:01 PM PDT 24
Peak memory 250416 kb
Host smart-9509d8f2-dc76-4c4a-aba9-5ee863b29363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968178143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3968178143
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3706833409
Short name T97
Test name
Test status
Simulation time 56072479 ps
CPU time 1.83 seconds
Started Jun 04 12:45:32 PM PDT 24
Finished Jun 04 12:45:35 PM PDT 24
Peak memory 215348 kb
Host smart-312c6394-193b-4d4a-95ce-358983e039d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706833409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3706833409
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2754029277
Short name T217
Test name
Test status
Simulation time 3821343301 ps
CPU time 12.88 seconds
Started Jun 04 02:02:31 PM PDT 24
Finished Jun 04 02:02:44 PM PDT 24
Peak memory 224420 kb
Host smart-efbe29ee-a2bb-4d11-98dc-3bf2b579f4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754029277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2754029277
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.801046949
Short name T86
Test name
Test status
Simulation time 31247765 ps
CPU time 1.14 seconds
Started Jun 04 12:45:25 PM PDT 24
Finished Jun 04 12:45:30 PM PDT 24
Peak memory 206884 kb
Host smart-f9f9eeb2-03d3-4364-a685-e4a36201d715
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801046949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.801046949
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.516645867
Short name T22
Test name
Test status
Simulation time 51564326854 ps
CPU time 154.55 seconds
Started Jun 04 02:02:08 PM PDT 24
Finished Jun 04 02:04:43 PM PDT 24
Peak memory 249208 kb
Host smart-c64e8af6-fbe0-4731-8dff-719ad9eef0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516645867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.516645867
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2943077939
Short name T124
Test name
Test status
Simulation time 4638599276 ps
CPU time 24.06 seconds
Started Jun 04 12:45:24 PM PDT 24
Finished Jun 04 12:45:50 PM PDT 24
Peak memory 215196 kb
Host smart-105a6ab7-d7e2-43c2-87ae-5514b2786e80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943077939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2943077939
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.696305159
Short name T133
Test name
Test status
Simulation time 2739289971 ps
CPU time 32.24 seconds
Started Jun 04 12:45:15 PM PDT 24
Finished Jun 04 12:45:49 PM PDT 24
Peak memory 206984 kb
Host smart-d4dc0fb5-967c-49d0-9cb6-a70dd0298090
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696305159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.696305159
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2045822655
Short name T1076
Test name
Test status
Simulation time 65271288 ps
CPU time 1.12 seconds
Started Jun 04 12:45:16 PM PDT 24
Finished Jun 04 12:45:18 PM PDT 24
Peak memory 216052 kb
Host smart-02f7bf51-9985-4cb9-a6ec-41770dd7480a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045822655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2045822655
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2387370624
Short name T1026
Test name
Test status
Simulation time 60043920 ps
CPU time 1.83 seconds
Started Jun 04 12:45:26 PM PDT 24
Finished Jun 04 12:45:31 PM PDT 24
Peak memory 215144 kb
Host smart-99dc8364-22e2-488c-9da0-e1a574c26464
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387370624 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2387370624
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3180594646
Short name T1003
Test name
Test status
Simulation time 21173618 ps
CPU time 1.31 seconds
Started Jun 04 12:45:16 PM PDT 24
Finished Jun 04 12:45:18 PM PDT 24
Peak memory 215116 kb
Host smart-451fba7a-e4a0-4116-bdb3-f2d392953e98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180594646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
180594646
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1624298312
Short name T1004
Test name
Test status
Simulation time 14861517 ps
CPU time 0.8 seconds
Started Jun 04 12:45:15 PM PDT 24
Finished Jun 04 12:45:17 PM PDT 24
Peak memory 203548 kb
Host smart-f82d684c-b2df-42c6-bb34-6f4a232be19d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624298312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
624298312
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.563785785
Short name T1055
Test name
Test status
Simulation time 133942801 ps
CPU time 1.34 seconds
Started Jun 04 12:45:16 PM PDT 24
Finished Jun 04 12:45:18 PM PDT 24
Peak memory 215188 kb
Host smart-999066ac-8fe2-408e-a675-b520ad732ffb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563785785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.563785785
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3778696790
Short name T986
Test name
Test status
Simulation time 34444119 ps
CPU time 0.67 seconds
Started Jun 04 12:45:12 PM PDT 24
Finished Jun 04 12:45:14 PM PDT 24
Peak memory 203440 kb
Host smart-3de79a3c-227a-4d78-ad3a-d4c712ad4fac
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778696790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3778696790
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1803312295
Short name T152
Test name
Test status
Simulation time 79333926 ps
CPU time 1.92 seconds
Started Jun 04 12:45:26 PM PDT 24
Finished Jun 04 12:45:31 PM PDT 24
Peak memory 215068 kb
Host smart-68e69e33-c017-4254-9464-e43c8af12b03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803312295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1803312295
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3277294758
Short name T1047
Test name
Test status
Simulation time 44325666 ps
CPU time 1.4 seconds
Started Jun 04 12:45:11 PM PDT 24
Finished Jun 04 12:45:14 PM PDT 24
Peak memory 206936 kb
Host smart-5982ecd4-122a-4e0c-bebd-4537b26d82c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277294758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
277294758
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.983581080
Short name T285
Test name
Test status
Simulation time 4244738272 ps
CPU time 23.16 seconds
Started Jun 04 12:45:14 PM PDT 24
Finished Jun 04 12:45:38 PM PDT 24
Peak memory 216100 kb
Host smart-8294a6bc-a48d-4452-ab7f-9d775f6714d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983581080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.983581080
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.583353214
Short name T130
Test name
Test status
Simulation time 1943404149 ps
CPU time 20.12 seconds
Started Jun 04 12:45:23 PM PDT 24
Finished Jun 04 12:45:44 PM PDT 24
Peak memory 206828 kb
Host smart-49d53d19-1cc9-441d-8733-a61c85cc06d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583353214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.583353214
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1520517403
Short name T1034
Test name
Test status
Simulation time 2432037517 ps
CPU time 12.87 seconds
Started Jun 04 12:45:24 PM PDT 24
Finished Jun 04 12:45:39 PM PDT 24
Peak memory 207000 kb
Host smart-58a398c3-3432-4e67-a759-4e47c28d3fed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520517403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1520517403
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2998594117
Short name T1015
Test name
Test status
Simulation time 25075334 ps
CPU time 0.98 seconds
Started Jun 04 12:45:22 PM PDT 24
Finished Jun 04 12:45:24 PM PDT 24
Peak memory 206724 kb
Host smart-b224c7b3-973c-4095-90f9-0e0c7c40c8a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998594117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2998594117
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.146215762
Short name T100
Test name
Test status
Simulation time 54104726 ps
CPU time 3.78 seconds
Started Jun 04 12:45:26 PM PDT 24
Finished Jun 04 12:45:33 PM PDT 24
Peak memory 217004 kb
Host smart-392e3abb-7455-42f3-9270-6a36342f5b5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146215762 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.146215762
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3060526510
Short name T1052
Test name
Test status
Simulation time 263416280 ps
CPU time 1.91 seconds
Started Jun 04 12:45:26 PM PDT 24
Finished Jun 04 12:45:31 PM PDT 24
Peak memory 215048 kb
Host smart-8a37a99d-01e9-492e-bcce-99c0d101f619
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060526510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
060526510
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3357087893
Short name T995
Test name
Test status
Simulation time 26825744 ps
CPU time 0.67 seconds
Started Jun 04 12:45:24 PM PDT 24
Finished Jun 04 12:45:28 PM PDT 24
Peak memory 203512 kb
Host smart-4de90f82-e94d-4ccb-b396-b54fa046815a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357087893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
357087893
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.451005983
Short name T127
Test name
Test status
Simulation time 57492811 ps
CPU time 1.29 seconds
Started Jun 04 12:45:24 PM PDT 24
Finished Jun 04 12:45:27 PM PDT 24
Peak memory 215108 kb
Host smart-4e5a806e-2cb3-4304-9967-0c84483f0cd9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451005983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.451005983
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2515113292
Short name T993
Test name
Test status
Simulation time 34148527 ps
CPU time 0.68 seconds
Started Jun 04 12:45:23 PM PDT 24
Finished Jun 04 12:45:25 PM PDT 24
Peak memory 203500 kb
Host smart-24b22096-d957-41b1-9fb5-ced45b7b5a33
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515113292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2515113292
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.270551783
Short name T1009
Test name
Test status
Simulation time 1083246777 ps
CPU time 3.14 seconds
Started Jun 04 12:45:27 PM PDT 24
Finished Jun 04 12:45:32 PM PDT 24
Peak memory 215448 kb
Host smart-0030c995-c7b9-4046-b926-17035c40c90e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270551783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.270551783
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1190229309
Short name T94
Test name
Test status
Simulation time 125638608 ps
CPU time 3.55 seconds
Started Jun 04 12:45:22 PM PDT 24
Finished Jun 04 12:45:27 PM PDT 24
Peak memory 215272 kb
Host smart-7fb19a66-4d8f-4aab-8714-6a3c96b2bfef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190229309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
190229309
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3204995958
Short name T283
Test name
Test status
Simulation time 557859047 ps
CPU time 13.08 seconds
Started Jun 04 12:45:23 PM PDT 24
Finished Jun 04 12:45:38 PM PDT 24
Peak memory 215084 kb
Host smart-7a54d922-f5fc-4d79-8c32-4abc9f7904eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204995958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3204995958
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.251760598
Short name T1073
Test name
Test status
Simulation time 55130563 ps
CPU time 4.05 seconds
Started Jun 04 12:45:33 PM PDT 24
Finished Jun 04 12:45:39 PM PDT 24
Peak memory 216972 kb
Host smart-a031f113-8f78-48ff-b53f-0ec7fc1b2d09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251760598 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.251760598
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3543051413
Short name T997
Test name
Test status
Simulation time 58430000 ps
CPU time 1.99 seconds
Started Jun 04 12:45:33 PM PDT 24
Finished Jun 04 12:45:36 PM PDT 24
Peak memory 215088 kb
Host smart-85ddc083-142a-458e-814c-7f94dd997996
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543051413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3543051413
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2465488394
Short name T1039
Test name
Test status
Simulation time 41647331 ps
CPU time 0.73 seconds
Started Jun 04 12:46:06 PM PDT 24
Finished Jun 04 12:46:08 PM PDT 24
Peak memory 203512 kb
Host smart-4d6d2b14-9074-4da3-91bf-95f7883cdeec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465488394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2465488394
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.806598104
Short name T1030
Test name
Test status
Simulation time 249693093 ps
CPU time 1.95 seconds
Started Jun 04 12:45:36 PM PDT 24
Finished Jun 04 12:45:39 PM PDT 24
Peak memory 215048 kb
Host smart-623252a0-bad1-485c-b43d-dfb3f2e49304
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806598104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.806598104
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2594320098
Short name T64
Test name
Test status
Simulation time 371184689 ps
CPU time 1.92 seconds
Started Jun 04 12:45:33 PM PDT 24
Finished Jun 04 12:45:37 PM PDT 24
Peak memory 216132 kb
Host smart-7f03bd51-4286-4a64-8fdb-955154a9144b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594320098 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2594320098
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2400066693
Short name T132
Test name
Test status
Simulation time 346797922 ps
CPU time 2.77 seconds
Started Jun 04 12:45:35 PM PDT 24
Finished Jun 04 12:45:40 PM PDT 24
Peak memory 215056 kb
Host smart-0d645433-bcb5-477d-84e6-af15b395561b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400066693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2400066693
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3336821212
Short name T974
Test name
Test status
Simulation time 11484742 ps
CPU time 0.7 seconds
Started Jun 04 12:45:34 PM PDT 24
Finished Jun 04 12:45:36 PM PDT 24
Peak memory 203844 kb
Host smart-8d9379f6-5546-445c-9e8a-6e250666fd69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336821212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3336821212
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3198726763
Short name T1011
Test name
Test status
Simulation time 971479985 ps
CPU time 4.41 seconds
Started Jun 04 12:45:33 PM PDT 24
Finished Jun 04 12:45:38 PM PDT 24
Peak memory 215104 kb
Host smart-7ec0ed73-cd00-413a-beb3-fa277030f15b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198726763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3198726763
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.603578306
Short name T103
Test name
Test status
Simulation time 112243994 ps
CPU time 3.21 seconds
Started Jun 04 12:45:35 PM PDT 24
Finished Jun 04 12:45:40 PM PDT 24
Peak memory 215208 kb
Host smart-6bfb24d5-6913-457a-ade2-c0e7b335468c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603578306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.603578306
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1724256229
Short name T1064
Test name
Test status
Simulation time 3077456288 ps
CPU time 4.03 seconds
Started Jun 04 12:45:36 PM PDT 24
Finished Jun 04 12:45:41 PM PDT 24
Peak memory 216724 kb
Host smart-3b8ccfa0-6bef-4130-85dd-2065718ae184
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724256229 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1724256229
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.732853967
Short name T1002
Test name
Test status
Simulation time 158184231 ps
CPU time 1.28 seconds
Started Jun 04 12:46:06 PM PDT 24
Finished Jun 04 12:46:09 PM PDT 24
Peak memory 206860 kb
Host smart-7ff3cc85-6d98-4168-8810-d91f87cdee1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732853967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.732853967
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1907667580
Short name T1058
Test name
Test status
Simulation time 14397489 ps
CPU time 0.71 seconds
Started Jun 04 12:45:39 PM PDT 24
Finished Jun 04 12:45:41 PM PDT 24
Peak memory 203576 kb
Host smart-61a28d4d-d9ab-4397-b969-e3481422ab6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907667580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1907667580
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2189939450
Short name T1012
Test name
Test status
Simulation time 162650079 ps
CPU time 1.96 seconds
Started Jun 04 12:45:33 PM PDT 24
Finished Jun 04 12:45:36 PM PDT 24
Peak memory 215172 kb
Host smart-1e4b043f-22ac-45d1-91f7-9c23f3dd0dd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189939450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2189939450
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3714342532
Short name T108
Test name
Test status
Simulation time 132724935 ps
CPU time 2.41 seconds
Started Jun 04 12:45:35 PM PDT 24
Finished Jun 04 12:45:38 PM PDT 24
Peak memory 215380 kb
Host smart-4acd18b8-238d-4756-b80e-7d4804cb41be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714342532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3714342532
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2060963798
Short name T290
Test name
Test status
Simulation time 138363979 ps
CPU time 6.45 seconds
Started Jun 04 12:45:34 PM PDT 24
Finished Jun 04 12:45:41 PM PDT 24
Peak memory 215144 kb
Host smart-a33ce113-ad21-47a5-88ea-e31671e90e97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060963798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2060963798
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2851715066
Short name T111
Test name
Test status
Simulation time 24285316 ps
CPU time 1.6 seconds
Started Jun 04 12:45:35 PM PDT 24
Finished Jun 04 12:45:38 PM PDT 24
Peak memory 215228 kb
Host smart-3fb438d1-0e9f-4404-a926-08e2112f8092
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851715066 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2851715066
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1012235254
Short name T1051
Test name
Test status
Simulation time 184850475 ps
CPU time 1.41 seconds
Started Jun 04 12:45:33 PM PDT 24
Finished Jun 04 12:45:36 PM PDT 24
Peak memory 206528 kb
Host smart-9e3be0c1-3e16-4d4c-9b87-b891982e0f8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012235254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1012235254
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3807185734
Short name T1020
Test name
Test status
Simulation time 25612731 ps
CPU time 0.71 seconds
Started Jun 04 12:45:35 PM PDT 24
Finished Jun 04 12:45:37 PM PDT 24
Peak memory 203652 kb
Host smart-e9fd2f54-753c-4149-a016-7007244192d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807185734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3807185734
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1311222279
Short name T1065
Test name
Test status
Simulation time 64130883 ps
CPU time 3.03 seconds
Started Jun 04 12:46:06 PM PDT 24
Finished Jun 04 12:46:10 PM PDT 24
Peak memory 215060 kb
Host smart-8a62e183-e1f4-4f89-a95e-2578b95f4b81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311222279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1311222279
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3680814763
Short name T1046
Test name
Test status
Simulation time 88366327 ps
CPU time 1.6 seconds
Started Jun 04 12:45:34 PM PDT 24
Finished Jun 04 12:45:37 PM PDT 24
Peak memory 215252 kb
Host smart-a1e0632d-f899-4204-be97-71cd5f6f3b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680814763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3680814763
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1105813947
Short name T1044
Test name
Test status
Simulation time 211906357 ps
CPU time 3.88 seconds
Started Jun 04 12:45:36 PM PDT 24
Finished Jun 04 12:45:41 PM PDT 24
Peak memory 216916 kb
Host smart-a2b87660-6489-4775-a841-d6963974755e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105813947 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1105813947
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3309128854
Short name T1013
Test name
Test status
Simulation time 13296579 ps
CPU time 0.68 seconds
Started Jun 04 12:45:36 PM PDT 24
Finished Jun 04 12:45:38 PM PDT 24
Peak memory 203860 kb
Host smart-87e7f699-5522-40fa-af0f-119b373a7a6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309128854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3309128854
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3711572885
Short name T973
Test name
Test status
Simulation time 50373293 ps
CPU time 1.74 seconds
Started Jun 04 12:45:36 PM PDT 24
Finished Jun 04 12:45:39 PM PDT 24
Peak memory 206892 kb
Host smart-82823460-cf9d-429e-8469-87900514d438
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711572885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3711572885
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1000042569
Short name T117
Test name
Test status
Simulation time 4760137317 ps
CPU time 15.99 seconds
Started Jun 04 12:45:39 PM PDT 24
Finished Jun 04 12:45:56 PM PDT 24
Peak memory 215260 kb
Host smart-93358171-7bac-4d6f-b648-809aeb04ec92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000042569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1000042569
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1129811444
Short name T115
Test name
Test status
Simulation time 251132840 ps
CPU time 2.69 seconds
Started Jun 04 12:45:42 PM PDT 24
Finished Jun 04 12:45:46 PM PDT 24
Peak memory 217528 kb
Host smart-a32c2b33-fe19-4b64-919d-781041024a02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129811444 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1129811444
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3721180185
Short name T970
Test name
Test status
Simulation time 36040967 ps
CPU time 1.24 seconds
Started Jun 04 12:45:45 PM PDT 24
Finished Jun 04 12:45:47 PM PDT 24
Peak memory 215120 kb
Host smart-febc834b-ad7c-4c11-a375-3223886afaac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721180185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3721180185
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1825845105
Short name T971
Test name
Test status
Simulation time 53635337 ps
CPU time 0.73 seconds
Started Jun 04 12:45:44 PM PDT 24
Finished Jun 04 12:45:47 PM PDT 24
Peak memory 203580 kb
Host smart-4d117f56-7f88-4288-8a80-28a264680c73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825845105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1825845105
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2797454739
Short name T1066
Test name
Test status
Simulation time 71282216 ps
CPU time 4.09 seconds
Started Jun 04 12:45:45 PM PDT 24
Finished Jun 04 12:45:50 PM PDT 24
Peak memory 215384 kb
Host smart-3cea6f51-d387-4b6c-9d6f-931b1c65d7bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797454739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2797454739
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3392871528
Short name T1042
Test name
Test status
Simulation time 23138088 ps
CPU time 1.32 seconds
Started Jun 04 12:46:03 PM PDT 24
Finished Jun 04 12:46:05 PM PDT 24
Peak memory 215212 kb
Host smart-7d37e7c8-2dc1-410a-ab97-76fd84222ced
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392871528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3392871528
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3692827361
Short name T1024
Test name
Test status
Simulation time 3858819335 ps
CPU time 8.43 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:52 PM PDT 24
Peak memory 215216 kb
Host smart-f428d8a3-39ec-48e7-992b-89a90636d62e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692827361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3692827361
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1702637947
Short name T118
Test name
Test status
Simulation time 60658147 ps
CPU time 1.75 seconds
Started Jun 04 12:45:39 PM PDT 24
Finished Jun 04 12:45:42 PM PDT 24
Peak memory 215276 kb
Host smart-5ef966a1-faf2-4478-a9b0-85e7eabfe855
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702637947 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1702637947
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2768302043
Short name T1041
Test name
Test status
Simulation time 39931042 ps
CPU time 2.68 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:46 PM PDT 24
Peak memory 206832 kb
Host smart-88d74cd0-2679-46d9-88a3-217105b9388f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768302043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2768302043
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1786061476
Short name T1014
Test name
Test status
Simulation time 33272454 ps
CPU time 0.75 seconds
Started Jun 04 12:45:43 PM PDT 24
Finished Jun 04 12:45:46 PM PDT 24
Peak memory 203624 kb
Host smart-278b5b8e-3c73-4612-b58b-a1cdc67c626e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786061476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1786061476
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.877065420
Short name T145
Test name
Test status
Simulation time 89358644 ps
CPU time 1.78 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:45 PM PDT 24
Peak memory 215136 kb
Host smart-9e86ca82-216c-4434-9849-7f68bc914659
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877065420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.877065420
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1857676159
Short name T107
Test name
Test status
Simulation time 43812665 ps
CPU time 1.55 seconds
Started Jun 04 12:45:40 PM PDT 24
Finished Jun 04 12:45:43 PM PDT 24
Peak memory 215580 kb
Host smart-03d732cf-485f-4cbc-bcbe-547d9d29f525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857676159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1857676159
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.222718475
Short name T113
Test name
Test status
Simulation time 25479943 ps
CPU time 1.69 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:44 PM PDT 24
Peak memory 215192 kb
Host smart-fc68edef-7e65-4c6f-b4ea-28bf307722b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222718475 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.222718475
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2301817899
Short name T128
Test name
Test status
Simulation time 409209595 ps
CPU time 2.08 seconds
Started Jun 04 12:45:43 PM PDT 24
Finished Jun 04 12:45:46 PM PDT 24
Peak memory 215068 kb
Host smart-5b3cf00d-ed85-4287-b90e-7bf64452aa3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301817899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2301817899
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.27877361
Short name T984
Test name
Test status
Simulation time 14909704 ps
CPU time 0.79 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:43 PM PDT 24
Peak memory 203548 kb
Host smart-f6678f3d-b912-466e-a862-f1ad135d41f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27877361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.27877361
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1932241416
Short name T144
Test name
Test status
Simulation time 244662355 ps
CPU time 3.89 seconds
Started Jun 04 12:45:42 PM PDT 24
Finished Jun 04 12:45:48 PM PDT 24
Peak memory 215060 kb
Host smart-ab41092c-cf63-4726-bef1-e8bbedd085cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932241416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1932241416
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.161029498
Short name T102
Test name
Test status
Simulation time 551147384 ps
CPU time 3.65 seconds
Started Jun 04 12:45:39 PM PDT 24
Finished Jun 04 12:45:43 PM PDT 24
Peak memory 215340 kb
Host smart-bc7ba1af-8b42-4e31-85b1-d24b0568f3b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161029498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.161029498
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.334054669
Short name T284
Test name
Test status
Simulation time 197610089 ps
CPU time 12.49 seconds
Started Jun 04 12:45:40 PM PDT 24
Finished Jun 04 12:45:53 PM PDT 24
Peak memory 215068 kb
Host smart-01f5194a-1159-4d04-bfd1-ed5bbeefc3a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334054669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.334054669
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.453717014
Short name T1048
Test name
Test status
Simulation time 24743100 ps
CPU time 1.69 seconds
Started Jun 04 12:45:42 PM PDT 24
Finished Jun 04 12:45:46 PM PDT 24
Peak memory 215176 kb
Host smart-a0a4707c-d802-4d42-aeca-e5f2a6b88d3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453717014 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.453717014
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.795245210
Short name T129
Test name
Test status
Simulation time 149442611 ps
CPU time 2.56 seconds
Started Jun 04 12:45:38 PM PDT 24
Finished Jun 04 12:45:42 PM PDT 24
Peak memory 215132 kb
Host smart-379dec10-3e31-4442-afe8-b6a8e3a9d61c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795245210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.795245210
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4051168547
Short name T1062
Test name
Test status
Simulation time 22124352 ps
CPU time 0.69 seconds
Started Jun 04 12:45:42 PM PDT 24
Finished Jun 04 12:45:45 PM PDT 24
Peak memory 203504 kb
Host smart-76fb1071-ab18-41c1-ab48-e98e5ce4c132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051168547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
4051168547
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3872897338
Short name T1060
Test name
Test status
Simulation time 378503051 ps
CPU time 3.85 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:47 PM PDT 24
Peak memory 215120 kb
Host smart-f98d7d37-8573-4cad-9229-c0ee21cb8104
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872897338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3872897338
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.944013177
Short name T1033
Test name
Test status
Simulation time 119253047 ps
CPU time 1.93 seconds
Started Jun 04 12:45:42 PM PDT 24
Finished Jun 04 12:45:46 PM PDT 24
Peak memory 215196 kb
Host smart-d08db04f-c74f-415c-b8f1-636009fd3e74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944013177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.944013177
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.255328788
Short name T1057
Test name
Test status
Simulation time 104906492 ps
CPU time 6.84 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:49 PM PDT 24
Peak memory 215108 kb
Host smart-7fa40214-be1d-460a-9f63-3ee6cd48f6e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255328788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.255328788
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2559464212
Short name T1069
Test name
Test status
Simulation time 52924832 ps
CPU time 2.81 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:45 PM PDT 24
Peak memory 217404 kb
Host smart-309b8c3a-4f7f-4d27-862c-f79ca3b4c51d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559464212 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2559464212
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1963824016
Short name T988
Test name
Test status
Simulation time 124300828 ps
CPU time 1.43 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:44 PM PDT 24
Peak memory 206984 kb
Host smart-bdee6cc0-21b6-488d-a4c3-b46bf7fc8b7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963824016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1963824016
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1673999614
Short name T1001
Test name
Test status
Simulation time 24281303 ps
CPU time 0.74 seconds
Started Jun 04 12:45:38 PM PDT 24
Finished Jun 04 12:45:40 PM PDT 24
Peak memory 203564 kb
Host smart-80eaad64-1b82-4463-849e-d74f7f2674b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673999614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1673999614
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2179627476
Short name T1022
Test name
Test status
Simulation time 31196560 ps
CPU time 1.94 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:45 PM PDT 24
Peak memory 214996 kb
Host smart-627dffd0-f4bd-4d6e-9b07-02db58a4df86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179627476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2179627476
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4289777150
Short name T104
Test name
Test status
Simulation time 145432016 ps
CPU time 3.5 seconds
Started Jun 04 12:45:42 PM PDT 24
Finished Jun 04 12:45:47 PM PDT 24
Peak memory 215200 kb
Host smart-c7a59853-ff85-4c65-8cc9-c4cd3f287206
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289777150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4289777150
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1430204010
Short name T1081
Test name
Test status
Simulation time 1920387903 ps
CPU time 13.85 seconds
Started Jun 04 12:45:42 PM PDT 24
Finished Jun 04 12:45:58 PM PDT 24
Peak memory 215108 kb
Host smart-4bddf188-e398-432b-887e-55f804298ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430204010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1430204010
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2569430802
Short name T151
Test name
Test status
Simulation time 420904676 ps
CPU time 8.71 seconds
Started Jun 04 12:45:23 PM PDT 24
Finished Jun 04 12:45:33 PM PDT 24
Peak memory 215096 kb
Host smart-30f034f4-a7dd-4ee9-8610-bd28337c844c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569430802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2569430802
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1593095214
Short name T981
Test name
Test status
Simulation time 1276328073 ps
CPU time 23.41 seconds
Started Jun 04 12:45:22 PM PDT 24
Finished Jun 04 12:45:47 PM PDT 24
Peak memory 206924 kb
Host smart-09dfdaec-4c8d-446d-9f9b-b15c9661e5e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593095214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1593095214
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2958682087
Short name T84
Test name
Test status
Simulation time 16882586 ps
CPU time 0.97 seconds
Started Jun 04 12:45:25 PM PDT 24
Finished Jun 04 12:45:29 PM PDT 24
Peak memory 206820 kb
Host smart-677b1db6-0117-4b24-8368-abbb0357bd58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958682087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2958682087
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3642691259
Short name T112
Test name
Test status
Simulation time 53179755 ps
CPU time 2.46 seconds
Started Jun 04 12:45:24 PM PDT 24
Finished Jun 04 12:45:29 PM PDT 24
Peak memory 217380 kb
Host smart-e8790e5f-86dc-4a53-bc34-2506046e8868
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642691259 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3642691259
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3441500305
Short name T1043
Test name
Test status
Simulation time 258798845 ps
CPU time 1.94 seconds
Started Jun 04 12:45:24 PM PDT 24
Finished Jun 04 12:45:29 PM PDT 24
Peak memory 206952 kb
Host smart-8174f60b-3cdd-48a1-acb4-09b5d8cd3d93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441500305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
441500305
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.534423268
Short name T1050
Test name
Test status
Simulation time 33904260 ps
CPU time 0.83 seconds
Started Jun 04 12:45:24 PM PDT 24
Finished Jun 04 12:45:27 PM PDT 24
Peak memory 203488 kb
Host smart-740a8e02-0bd7-4788-a2c3-96151f818048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534423268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.534423268
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.840826514
Short name T123
Test name
Test status
Simulation time 140836786 ps
CPU time 1.35 seconds
Started Jun 04 12:45:22 PM PDT 24
Finished Jun 04 12:45:25 PM PDT 24
Peak memory 215128 kb
Host smart-201bf5c8-eb27-4a95-a32d-12f33013822c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840826514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.840826514
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2187132517
Short name T998
Test name
Test status
Simulation time 15386648 ps
CPU time 0.68 seconds
Started Jun 04 12:45:25 PM PDT 24
Finished Jun 04 12:45:29 PM PDT 24
Peak memory 203828 kb
Host smart-16b62e58-aad5-40b5-bea5-e644b5dcac6c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187132517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2187132517
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4178223042
Short name T996
Test name
Test status
Simulation time 410573919 ps
CPU time 2.93 seconds
Started Jun 04 12:45:23 PM PDT 24
Finished Jun 04 12:45:29 PM PDT 24
Peak memory 215136 kb
Host smart-1b9e2a64-da69-4195-972a-c356109bac19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178223042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.4178223042
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3213972525
Short name T110
Test name
Test status
Simulation time 56021941 ps
CPU time 2.12 seconds
Started Jun 04 12:45:22 PM PDT 24
Finished Jun 04 12:45:26 PM PDT 24
Peak memory 215268 kb
Host smart-6f696165-e93b-49b5-8a1b-d9fa49a108a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213972525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
213972525
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1498628321
Short name T282
Test name
Test status
Simulation time 575418119 ps
CPU time 13.64 seconds
Started Jun 04 12:45:24 PM PDT 24
Finished Jun 04 12:45:40 PM PDT 24
Peak memory 215064 kb
Host smart-1dabe748-8713-44ab-860d-c525e424ba79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498628321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1498628321
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2001789404
Short name T1027
Test name
Test status
Simulation time 11564711 ps
CPU time 0.73 seconds
Started Jun 04 12:45:42 PM PDT 24
Finished Jun 04 12:45:45 PM PDT 24
Peak memory 203572 kb
Host smart-74408b71-644d-49d1-935f-45178000b2dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001789404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2001789404
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3317206842
Short name T1018
Test name
Test status
Simulation time 32186549 ps
CPU time 0.69 seconds
Started Jun 04 12:45:49 PM PDT 24
Finished Jun 04 12:45:51 PM PDT 24
Peak memory 203888 kb
Host smart-ce9d8bb2-d47d-4bcb-b89d-7ca8ea701b59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317206842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3317206842
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3139293838
Short name T992
Test name
Test status
Simulation time 146121217 ps
CPU time 0.7 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:44 PM PDT 24
Peak memory 203580 kb
Host smart-e2d913cd-2be5-4a96-910c-963f7df1c039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139293838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3139293838
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.946898394
Short name T985
Test name
Test status
Simulation time 59614505 ps
CPU time 0.75 seconds
Started Jun 04 12:45:40 PM PDT 24
Finished Jun 04 12:45:43 PM PDT 24
Peak memory 203640 kb
Host smart-31660106-355e-4618-abd4-61fc95c2a96c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946898394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.946898394
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4288493757
Short name T1040
Test name
Test status
Simulation time 31732712 ps
CPU time 0.79 seconds
Started Jun 04 12:45:40 PM PDT 24
Finished Jun 04 12:45:43 PM PDT 24
Peak memory 203544 kb
Host smart-9057b256-c776-46a2-a715-092c32f68519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288493757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4288493757
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3993716985
Short name T1017
Test name
Test status
Simulation time 101502037 ps
CPU time 0.77 seconds
Started Jun 04 12:45:42 PM PDT 24
Finished Jun 04 12:45:45 PM PDT 24
Peak memory 203608 kb
Host smart-a2c801a1-09f4-4ef4-8922-de4c2bb2104a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993716985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3993716985
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.403081618
Short name T978
Test name
Test status
Simulation time 77952995 ps
CPU time 0.77 seconds
Started Jun 04 12:45:40 PM PDT 24
Finished Jun 04 12:45:43 PM PDT 24
Peak memory 203644 kb
Host smart-08482d8a-69ae-4f37-aeb8-c74084eca63d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403081618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.403081618
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1445723338
Short name T1056
Test name
Test status
Simulation time 17694117 ps
CPU time 0.72 seconds
Started Jun 04 12:45:43 PM PDT 24
Finished Jun 04 12:45:46 PM PDT 24
Peak memory 203892 kb
Host smart-08b128bc-9c93-4f04-819b-7f84258dfdd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445723338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1445723338
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.205421853
Short name T1036
Test name
Test status
Simulation time 24480021 ps
CPU time 0.76 seconds
Started Jun 04 12:45:38 PM PDT 24
Finished Jun 04 12:45:40 PM PDT 24
Peak memory 203820 kb
Host smart-3f46c242-d0d0-4b4d-add6-e1f416006e56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205421853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.205421853
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.945090620
Short name T1028
Test name
Test status
Simulation time 15402110 ps
CPU time 0.72 seconds
Started Jun 04 12:45:45 PM PDT 24
Finished Jun 04 12:45:48 PM PDT 24
Peak memory 203540 kb
Host smart-f5b8f4d3-b0d2-425c-b167-155f08d6e3cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945090620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.945090620
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.362393124
Short name T966
Test name
Test status
Simulation time 316389384 ps
CPU time 8.35 seconds
Started Jun 04 12:45:25 PM PDT 24
Finished Jun 04 12:45:37 PM PDT 24
Peak memory 215036 kb
Host smart-8deeddc2-d559-4c58-ac9f-dfae92f9d437
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362393124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.362393124
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2203754550
Short name T131
Test name
Test status
Simulation time 8229166772 ps
CPU time 13.64 seconds
Started Jun 04 12:45:25 PM PDT 24
Finished Jun 04 12:45:41 PM PDT 24
Peak memory 207156 kb
Host smart-5ca6768c-b320-48a1-ae74-1efdeea4ae4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203754550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2203754550
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2352741711
Short name T114
Test name
Test status
Simulation time 157692361 ps
CPU time 3.79 seconds
Started Jun 04 12:45:22 PM PDT 24
Finished Jun 04 12:45:27 PM PDT 24
Peak memory 216964 kb
Host smart-0edfe946-5478-425c-9be8-b3d45c6ec8cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352741711 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2352741711
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3769765432
Short name T1038
Test name
Test status
Simulation time 69355333 ps
CPU time 2.33 seconds
Started Jun 04 12:45:24 PM PDT 24
Finished Jun 04 12:45:29 PM PDT 24
Peak memory 206788 kb
Host smart-f3b1f40d-eb8a-43ed-8222-b04093aa8d93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769765432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
769765432
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3260823296
Short name T994
Test name
Test status
Simulation time 11550097 ps
CPU time 0.73 seconds
Started Jun 04 12:45:24 PM PDT 24
Finished Jun 04 12:45:27 PM PDT 24
Peak memory 203900 kb
Host smart-abea86f0-2e35-4168-a9ca-478116e55b5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260823296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
260823296
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2275335308
Short name T1006
Test name
Test status
Simulation time 280422338 ps
CPU time 2.21 seconds
Started Jun 04 12:45:24 PM PDT 24
Finished Jun 04 12:45:29 PM PDT 24
Peak memory 215132 kb
Host smart-4fce9e05-6a05-4d08-be32-a2ed0cb4a7ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275335308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2275335308
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1494901208
Short name T965
Test name
Test status
Simulation time 11575593 ps
CPU time 0.67 seconds
Started Jun 04 12:45:29 PM PDT 24
Finished Jun 04 12:45:31 PM PDT 24
Peak memory 203456 kb
Host smart-107cb9d5-fb30-4208-b140-0031bd209674
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494901208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1494901208
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2825540650
Short name T1049
Test name
Test status
Simulation time 252196946 ps
CPU time 3.71 seconds
Started Jun 04 12:45:24 PM PDT 24
Finished Jun 04 12:45:30 PM PDT 24
Peak memory 215088 kb
Host smart-93acfa26-47ae-41a1-87da-21f7a9925412
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825540650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2825540650
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.240470806
Short name T106
Test name
Test status
Simulation time 546340420 ps
CPU time 3.73 seconds
Started Jun 04 12:45:23 PM PDT 24
Finished Jun 04 12:45:28 PM PDT 24
Peak memory 216256 kb
Host smart-05fa4820-74b8-4acf-abe8-be0275970685
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240470806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.240470806
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1743565156
Short name T1071
Test name
Test status
Simulation time 317027345 ps
CPU time 7.12 seconds
Started Jun 04 12:45:19 PM PDT 24
Finished Jun 04 12:45:27 PM PDT 24
Peak memory 215408 kb
Host smart-570e62dd-4c24-4e33-b615-7a1fb612df85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743565156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1743565156
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3503780957
Short name T1080
Test name
Test status
Simulation time 62147140 ps
CPU time 0.76 seconds
Started Jun 04 12:45:38 PM PDT 24
Finished Jun 04 12:45:39 PM PDT 24
Peak memory 203548 kb
Host smart-7ff58df5-6662-41f3-bec5-d684f44f2c25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503780957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3503780957
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3806334923
Short name T1035
Test name
Test status
Simulation time 11746289 ps
CPU time 0.75 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:43 PM PDT 24
Peak memory 203528 kb
Host smart-e9c24f6e-52f7-47bf-b836-7bfe237ae0ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806334923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3806334923
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1326556519
Short name T1010
Test name
Test status
Simulation time 23404927 ps
CPU time 0.7 seconds
Started Jun 04 12:45:38 PM PDT 24
Finished Jun 04 12:45:40 PM PDT 24
Peak memory 203932 kb
Host smart-e45dff25-9a72-4504-869f-1c54ffec731b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326556519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1326556519
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2839144577
Short name T1037
Test name
Test status
Simulation time 58811382 ps
CPU time 0.75 seconds
Started Jun 04 12:45:39 PM PDT 24
Finished Jun 04 12:45:41 PM PDT 24
Peak memory 203872 kb
Host smart-fe06be3c-6676-4a2e-a802-44cee27765d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839144577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2839144577
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3844336515
Short name T991
Test name
Test status
Simulation time 29166075 ps
CPU time 0.75 seconds
Started Jun 04 12:45:40 PM PDT 24
Finished Jun 04 12:45:43 PM PDT 24
Peak memory 203624 kb
Host smart-ee4138c0-6652-4709-aa98-a9691277fe33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844336515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3844336515
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1584430856
Short name T1021
Test name
Test status
Simulation time 12399041 ps
CPU time 0.77 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:43 PM PDT 24
Peak memory 203576 kb
Host smart-18822fd1-ffef-4767-8c8d-cbfe52e3ebbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584430856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1584430856
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.383001326
Short name T1053
Test name
Test status
Simulation time 20829851 ps
CPU time 0.8 seconds
Started Jun 04 12:45:39 PM PDT 24
Finished Jun 04 12:45:41 PM PDT 24
Peak memory 203632 kb
Host smart-490bef8b-e599-488e-b34d-65b0195b61c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383001326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.383001326
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4074068731
Short name T982
Test name
Test status
Simulation time 29734306 ps
CPU time 0.75 seconds
Started Jun 04 12:45:44 PM PDT 24
Finished Jun 04 12:45:47 PM PDT 24
Peak memory 203556 kb
Host smart-2dc12d23-2ab1-4997-a3ef-31d79c969f78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074068731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4074068731
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4272101266
Short name T989
Test name
Test status
Simulation time 39864217 ps
CPU time 0.7 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:44 PM PDT 24
Peak memory 203864 kb
Host smart-f888eef3-a43f-4ae7-af1b-6c1d857a0546
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272101266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
4272101266
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1490138948
Short name T1045
Test name
Test status
Simulation time 49187049 ps
CPU time 0.69 seconds
Started Jun 04 12:45:42 PM PDT 24
Finished Jun 04 12:45:44 PM PDT 24
Peak memory 203624 kb
Host smart-4d71e7a4-db7c-4cc9-9209-17340aa6e5ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490138948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1490138948
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3003341739
Short name T153
Test name
Test status
Simulation time 1880055606 ps
CPU time 25.88 seconds
Started Jun 04 12:45:23 PM PDT 24
Finished Jun 04 12:45:51 PM PDT 24
Peak memory 215116 kb
Host smart-a9dc5c74-3306-404c-beb7-5958b6c6dba9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003341739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3003341739
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2324971213
Short name T122
Test name
Test status
Simulation time 2706786160 ps
CPU time 39.32 seconds
Started Jun 04 12:45:24 PM PDT 24
Finished Jun 04 12:46:05 PM PDT 24
Peak memory 215240 kb
Host smart-c3fea12e-7bbe-4316-b365-6d9da86d9fdc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324971213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2324971213
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2783852118
Short name T85
Test name
Test status
Simulation time 75387645 ps
CPU time 0.96 seconds
Started Jun 04 12:45:21 PM PDT 24
Finished Jun 04 12:45:23 PM PDT 24
Peak memory 206740 kb
Host smart-74698f10-76aa-4da0-b7d1-f924429fc4ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783852118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2783852118
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2847128935
Short name T1031
Test name
Test status
Simulation time 520533025 ps
CPU time 3.92 seconds
Started Jun 04 12:45:23 PM PDT 24
Finished Jun 04 12:45:30 PM PDT 24
Peak memory 217500 kb
Host smart-cf313f69-e81e-406a-9ea3-430c12956c95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847128935 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2847128935
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2954175742
Short name T120
Test name
Test status
Simulation time 254653179 ps
CPU time 1.84 seconds
Started Jun 04 12:45:25 PM PDT 24
Finished Jun 04 12:45:30 PM PDT 24
Peak memory 215052 kb
Host smart-c5af6cec-bf06-477a-a2e7-f0597f11e4b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954175742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
954175742
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.296879415
Short name T987
Test name
Test status
Simulation time 56956621 ps
CPU time 0.76 seconds
Started Jun 04 12:45:29 PM PDT 24
Finished Jun 04 12:45:31 PM PDT 24
Peak memory 203560 kb
Host smart-89577b4c-4142-4308-a266-71c0e5613479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296879415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.296879415
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1124263846
Short name T1068
Test name
Test status
Simulation time 135647412 ps
CPU time 2.22 seconds
Started Jun 04 12:45:25 PM PDT 24
Finished Jun 04 12:45:29 PM PDT 24
Peak memory 215256 kb
Host smart-876c0dfd-7313-49f5-885e-8c381a39bf22
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124263846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1124263846
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1706330130
Short name T1019
Test name
Test status
Simulation time 18292318 ps
CPU time 0.7 seconds
Started Jun 04 12:45:26 PM PDT 24
Finished Jun 04 12:45:30 PM PDT 24
Peak memory 203452 kb
Host smart-32d53971-3842-49e2-9fa0-538679f3a7a4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706330130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1706330130
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2077605671
Short name T968
Test name
Test status
Simulation time 459340988 ps
CPU time 3 seconds
Started Jun 04 12:45:29 PM PDT 24
Finished Jun 04 12:45:33 PM PDT 24
Peak memory 215124 kb
Host smart-09432eea-0239-45a8-b52c-6cc0f32e6f28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077605671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2077605671
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2445610054
Short name T1067
Test name
Test status
Simulation time 2374881600 ps
CPU time 4.86 seconds
Started Jun 04 12:45:25 PM PDT 24
Finished Jun 04 12:45:33 PM PDT 24
Peak memory 216384 kb
Host smart-9d4550d5-dc28-4ac0-a356-7ceead5a8bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445610054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
445610054
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.670915857
Short name T62
Test name
Test status
Simulation time 3275693213 ps
CPU time 12.57 seconds
Started Jun 04 12:45:25 PM PDT 24
Finished Jun 04 12:45:41 PM PDT 24
Peak memory 215396 kb
Host smart-b0aeee83-aa21-46af-be95-431e3c3803e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670915857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.670915857
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2723393056
Short name T1025
Test name
Test status
Simulation time 171199722 ps
CPU time 0.73 seconds
Started Jun 04 12:45:44 PM PDT 24
Finished Jun 04 12:45:46 PM PDT 24
Peak memory 203832 kb
Host smart-1c629551-e793-4c48-aac9-e06165f3eedc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723393056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2723393056
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1329641349
Short name T977
Test name
Test status
Simulation time 34823871 ps
CPU time 0.73 seconds
Started Jun 04 12:45:38 PM PDT 24
Finished Jun 04 12:45:40 PM PDT 24
Peak memory 203652 kb
Host smart-33ca631c-ea32-4ed0-8276-0c704706487c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329641349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1329641349
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.855357393
Short name T967
Test name
Test status
Simulation time 12497617 ps
CPU time 0.71 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:44 PM PDT 24
Peak memory 203628 kb
Host smart-2db94339-7e79-4a31-b689-c332f9a032ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855357393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.855357393
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4135360525
Short name T972
Test name
Test status
Simulation time 37120676 ps
CPU time 0.71 seconds
Started Jun 04 12:45:39 PM PDT 24
Finished Jun 04 12:45:41 PM PDT 24
Peak memory 203884 kb
Host smart-95703a08-e21c-4845-a97b-3ad2997d7d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135360525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4135360525
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1734176202
Short name T1000
Test name
Test status
Simulation time 12408944 ps
CPU time 0.74 seconds
Started Jun 04 12:45:42 PM PDT 24
Finished Jun 04 12:45:45 PM PDT 24
Peak memory 203640 kb
Host smart-a2d8fdef-8720-4ce8-bbe0-dfad4edb5ec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734176202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1734176202
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.20273191
Short name T1077
Test name
Test status
Simulation time 75150996 ps
CPU time 0.7 seconds
Started Jun 04 12:45:49 PM PDT 24
Finished Jun 04 12:45:51 PM PDT 24
Peak memory 203872 kb
Host smart-8eb5e752-bd96-4b36-8bce-d58eca3e4b17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20273191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.20273191
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3971533430
Short name T1007
Test name
Test status
Simulation time 16375195 ps
CPU time 0.75 seconds
Started Jun 04 12:45:44 PM PDT 24
Finished Jun 04 12:45:46 PM PDT 24
Peak memory 203540 kb
Host smart-5208923e-9066-45e6-8c0e-3819953d6313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971533430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3971533430
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1822066013
Short name T1072
Test name
Test status
Simulation time 60249043 ps
CPU time 0.74 seconds
Started Jun 04 12:45:45 PM PDT 24
Finished Jun 04 12:45:47 PM PDT 24
Peak memory 203548 kb
Host smart-6188d867-025d-46dd-aad1-6fa5d85194ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822066013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1822066013
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2128042014
Short name T1005
Test name
Test status
Simulation time 13395272 ps
CPU time 0.72 seconds
Started Jun 04 12:45:48 PM PDT 24
Finished Jun 04 12:45:50 PM PDT 24
Peak memory 203564 kb
Host smart-08e6ac78-28ac-4ec3-83ec-84c9b9ccbc25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128042014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2128042014
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.326356038
Short name T1008
Test name
Test status
Simulation time 31510339 ps
CPU time 0.69 seconds
Started Jun 04 12:45:44 PM PDT 24
Finished Jun 04 12:45:46 PM PDT 24
Peak memory 203536 kb
Host smart-03dd0a90-6a85-4d7d-a86b-8ea7661cdad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326356038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.326356038
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2813190207
Short name T1059
Test name
Test status
Simulation time 175100121 ps
CPU time 4.1 seconds
Started Jun 04 12:45:32 PM PDT 24
Finished Jun 04 12:45:37 PM PDT 24
Peak memory 217200 kb
Host smart-55842035-9b0a-4f67-96cd-baa6a037b5c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813190207 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2813190207
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.294353014
Short name T1075
Test name
Test status
Simulation time 171069522 ps
CPU time 2.68 seconds
Started Jun 04 12:45:32 PM PDT 24
Finished Jun 04 12:45:36 PM PDT 24
Peak memory 215172 kb
Host smart-9c716add-2783-4ee3-98be-fec8fc63a696
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294353014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.294353014
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3266913523
Short name T999
Test name
Test status
Simulation time 19666306 ps
CPU time 0.79 seconds
Started Jun 04 12:45:24 PM PDT 24
Finished Jun 04 12:45:28 PM PDT 24
Peak memory 203552 kb
Host smart-625ed9ac-c3a4-41a6-a377-d78877e1d9ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266913523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
266913523
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.545242033
Short name T969
Test name
Test status
Simulation time 218981389 ps
CPU time 2.7 seconds
Started Jun 04 12:45:32 PM PDT 24
Finished Jun 04 12:45:36 PM PDT 24
Peak memory 215028 kb
Host smart-8c65b392-5c08-48ec-8a85-165a145709e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545242033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.545242033
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.678749198
Short name T101
Test name
Test status
Simulation time 117925757 ps
CPU time 2.92 seconds
Started Jun 04 12:45:27 PM PDT 24
Finished Jun 04 12:45:32 PM PDT 24
Peak memory 215208 kb
Host smart-f7fc3a1c-ce7f-4913-b19b-13ee6b4268c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678749198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.678749198
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4161243171
Short name T96
Test name
Test status
Simulation time 829328614 ps
CPU time 22.68 seconds
Started Jun 04 12:45:22 PM PDT 24
Finished Jun 04 12:45:47 PM PDT 24
Peak memory 215120 kb
Host smart-f264b4e2-71cf-418d-bdd9-cb1d51452bfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161243171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.4161243171
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3693474198
Short name T1016
Test name
Test status
Simulation time 183928356 ps
CPU time 1.62 seconds
Started Jun 04 12:45:30 PM PDT 24
Finished Jun 04 12:45:33 PM PDT 24
Peak memory 215188 kb
Host smart-1e49d819-f735-4653-98f4-b24be0dbaf73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693474198 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3693474198
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3376404072
Short name T121
Test name
Test status
Simulation time 155425936 ps
CPU time 1.37 seconds
Started Jun 04 12:45:33 PM PDT 24
Finished Jun 04 12:45:35 PM PDT 24
Peak memory 206880 kb
Host smart-8fcddd80-6178-465d-8f4a-4d148905ef3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376404072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
376404072
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2912699319
Short name T1070
Test name
Test status
Simulation time 24792906 ps
CPU time 0.75 seconds
Started Jun 04 12:45:32 PM PDT 24
Finished Jun 04 12:45:34 PM PDT 24
Peak memory 203540 kb
Host smart-66a9e51e-2e14-4318-8e6b-04c022136138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912699319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
912699319
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3495729772
Short name T975
Test name
Test status
Simulation time 47996250 ps
CPU time 2.84 seconds
Started Jun 04 12:45:40 PM PDT 24
Finished Jun 04 12:45:44 PM PDT 24
Peak memory 215060 kb
Host smart-ab500e09-cd58-419b-8c37-305938d44485
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495729772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3495729772
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.93664298
Short name T95
Test name
Test status
Simulation time 1232682862 ps
CPU time 17.46 seconds
Started Jun 04 12:45:30 PM PDT 24
Finished Jun 04 12:45:48 PM PDT 24
Peak memory 215092 kb
Host smart-b9ba1f98-1fb2-4437-a8e0-00b3223c677d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93664298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_t
l_intg_err.93664298
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.681210423
Short name T1023
Test name
Test status
Simulation time 118314386 ps
CPU time 2.35 seconds
Started Jun 04 12:45:41 PM PDT 24
Finished Jun 04 12:45:45 PM PDT 24
Peak memory 217880 kb
Host smart-6bc4ac39-4536-4eba-8046-8f7ca8f14c1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681210423 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.681210423
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2044222842
Short name T979
Test name
Test status
Simulation time 82270232 ps
CPU time 1.46 seconds
Started Jun 04 12:45:30 PM PDT 24
Finished Jun 04 12:45:32 PM PDT 24
Peak memory 215108 kb
Host smart-2fbd43a6-108e-478b-931a-10e01b4d89e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044222842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
044222842
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2442714429
Short name T976
Test name
Test status
Simulation time 18258911 ps
CPU time 0.75 seconds
Started Jun 04 12:45:33 PM PDT 24
Finished Jun 04 12:45:35 PM PDT 24
Peak memory 203424 kb
Host smart-afb57282-c630-40f3-931e-6a4b98fb8e0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442714429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
442714429
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1751321137
Short name T983
Test name
Test status
Simulation time 150794161 ps
CPU time 3.76 seconds
Started Jun 04 12:45:32 PM PDT 24
Finished Jun 04 12:45:37 PM PDT 24
Peak memory 215112 kb
Host smart-2af89cea-3801-4205-ba3c-dadff347f4cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751321137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1751321137
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3363652857
Short name T109
Test name
Test status
Simulation time 237677913 ps
CPU time 3.93 seconds
Started Jun 04 12:45:39 PM PDT 24
Finished Jun 04 12:45:44 PM PDT 24
Peak memory 216300 kb
Host smart-b5d2ff41-9fef-424c-9bb6-011303c36418
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363652857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
363652857
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4049020832
Short name T289
Test name
Test status
Simulation time 4133814059 ps
CPU time 16.64 seconds
Started Jun 04 12:45:31 PM PDT 24
Finished Jun 04 12:45:49 PM PDT 24
Peak memory 215152 kb
Host smart-ed466fd7-6c59-42ec-a885-10e9d7b0f105
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049020832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4049020832
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3055644071
Short name T1063
Test name
Test status
Simulation time 74767625 ps
CPU time 2.8 seconds
Started Jun 04 12:45:36 PM PDT 24
Finished Jun 04 12:45:40 PM PDT 24
Peak memory 217640 kb
Host smart-c60adf86-5ba2-4772-a2d3-11ccb2fb5ba0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055644071 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3055644071
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4087603711
Short name T980
Test name
Test status
Simulation time 118902161 ps
CPU time 2.34 seconds
Started Jun 04 12:45:32 PM PDT 24
Finished Jun 04 12:45:35 PM PDT 24
Peak memory 215140 kb
Host smart-aa07b795-faa7-4a64-8687-00580e06039a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087603711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
087603711
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1478661307
Short name T1079
Test name
Test status
Simulation time 15404063 ps
CPU time 0.71 seconds
Started Jun 04 12:45:34 PM PDT 24
Finished Jun 04 12:45:36 PM PDT 24
Peak memory 203956 kb
Host smart-7a5d6c2e-c81d-42e0-b1f9-fa37b32ba5fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478661307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
478661307
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3148616981
Short name T1061
Test name
Test status
Simulation time 374726898 ps
CPU time 3.88 seconds
Started Jun 04 12:45:31 PM PDT 24
Finished Jun 04 12:45:36 PM PDT 24
Peak memory 215088 kb
Host smart-52d46b62-a7f5-43bc-b6c8-571e78c871de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148616981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3148616981
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1912584587
Short name T105
Test name
Test status
Simulation time 198784183 ps
CPU time 1.5 seconds
Started Jun 04 12:45:39 PM PDT 24
Finished Jun 04 12:45:42 PM PDT 24
Peak memory 215328 kb
Host smart-ddd31509-ee1f-4833-87c6-0a5fa23baefa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912584587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
912584587
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3484864827
Short name T288
Test name
Test status
Simulation time 2742934603 ps
CPU time 12.42 seconds
Started Jun 04 12:45:31 PM PDT 24
Finished Jun 04 12:45:44 PM PDT 24
Peak memory 215664 kb
Host smart-453116af-bdf4-40f0-b1a6-4244a63e3c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484864827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3484864827
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1606879846
Short name T1074
Test name
Test status
Simulation time 50761993 ps
CPU time 1.72 seconds
Started Jun 04 12:45:32 PM PDT 24
Finished Jun 04 12:45:35 PM PDT 24
Peak memory 216096 kb
Host smart-b05cce7c-8fee-4edc-b4d1-29f21f966334
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606879846 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1606879846
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3507307534
Short name T126
Test name
Test status
Simulation time 176112275 ps
CPU time 1.22 seconds
Started Jun 04 12:45:32 PM PDT 24
Finished Jun 04 12:45:34 PM PDT 24
Peak memory 206936 kb
Host smart-a5dc651a-b79e-4954-82bb-c3e4c2390658
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507307534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
507307534
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2282318126
Short name T1032
Test name
Test status
Simulation time 18333637 ps
CPU time 0.74 seconds
Started Jun 04 12:45:33 PM PDT 24
Finished Jun 04 12:45:35 PM PDT 24
Peak memory 203584 kb
Host smart-7f0b6fe0-ad1e-4bb5-a08a-7ca10a06fb7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282318126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
282318126
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2694939265
Short name T1078
Test name
Test status
Simulation time 784358920 ps
CPU time 2.69 seconds
Started Jun 04 12:45:31 PM PDT 24
Finished Jun 04 12:45:35 PM PDT 24
Peak memory 215136 kb
Host smart-305c93b6-12e8-4a91-b8cc-9e633b38ef7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694939265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2694939265
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1887737386
Short name T1054
Test name
Test status
Simulation time 88556651 ps
CPU time 2.25 seconds
Started Jun 04 12:45:33 PM PDT 24
Finished Jun 04 12:45:37 PM PDT 24
Peak memory 215272 kb
Host smart-e3a3a13e-55cf-45f1-b0b1-6383db3d93c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887737386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
887737386
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.733893865
Short name T990
Test name
Test status
Simulation time 106915938 ps
CPU time 6.95 seconds
Started Jun 04 12:45:34 PM PDT 24
Finished Jun 04 12:45:42 PM PDT 24
Peak memory 215040 kb
Host smart-596b9f6c-355e-4c7d-afac-badf4174ed48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733893865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.733893865
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2157180393
Short name T583
Test name
Test status
Simulation time 33152659 ps
CPU time 0.71 seconds
Started Jun 04 02:01:23 PM PDT 24
Finished Jun 04 02:01:24 PM PDT 24
Peak memory 205384 kb
Host smart-54679eae-548f-4b19-a100-f1ef8bd66578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157180393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
157180393
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3297319021
Short name T15
Test name
Test status
Simulation time 7310551996 ps
CPU time 8.52 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:01:30 PM PDT 24
Peak memory 220336 kb
Host smart-f38e66b9-011f-4234-8570-d208af55aae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297319021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3297319021
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2781437450
Short name T575
Test name
Test status
Simulation time 19566496 ps
CPU time 0.81 seconds
Started Jun 04 02:01:17 PM PDT 24
Finished Jun 04 02:01:19 PM PDT 24
Peak memory 206348 kb
Host smart-f7ab54d0-d5d0-4e87-8434-c65346c63ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781437450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2781437450
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.188887625
Short name T89
Test name
Test status
Simulation time 28127492223 ps
CPU time 216.32 seconds
Started Jun 04 02:01:18 PM PDT 24
Finished Jun 04 02:04:55 PM PDT 24
Peak memory 254456 kb
Host smart-f07b0a89-d63d-4fb0-8597-a0c296a9c2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188887625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.188887625
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1838210721
Short name T319
Test name
Test status
Simulation time 26703397433 ps
CPU time 232.79 seconds
Started Jun 04 02:01:22 PM PDT 24
Finished Jun 04 02:05:16 PM PDT 24
Peak memory 232532 kb
Host smart-0b378855-25f0-4f1e-92fc-1ce789abb24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838210721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1838210721
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3443215637
Short name T42
Test name
Test status
Simulation time 15543005632 ps
CPU time 57.91 seconds
Started Jun 04 02:01:19 PM PDT 24
Finished Jun 04 02:02:19 PM PDT 24
Peak memory 237656 kb
Host smart-f7d45824-f174-410d-a1fd-09ae4d6cdba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443215637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3443215637
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2805277066
Short name T726
Test name
Test status
Simulation time 374436049 ps
CPU time 9.36 seconds
Started Jun 04 02:01:23 PM PDT 24
Finished Jun 04 02:01:33 PM PDT 24
Peak memory 239580 kb
Host smart-9ca83849-3ed5-4bee-b66a-90dd072794b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805277066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2805277066
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.659109678
Short name T93
Test name
Test status
Simulation time 3056681870 ps
CPU time 17.03 seconds
Started Jun 04 02:01:15 PM PDT 24
Finished Jun 04 02:01:33 PM PDT 24
Peak memory 234688 kb
Host smart-6895242b-095c-4185-9e7e-6942154ed6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659109678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.659109678
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3901310176
Short name T761
Test name
Test status
Simulation time 7116918124 ps
CPU time 22.41 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:01:44 PM PDT 24
Peak memory 233292 kb
Host smart-a4687975-596b-466f-b1af-bdc8f7eaee59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901310176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3901310176
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3631113854
Short name T851
Test name
Test status
Simulation time 1536851089 ps
CPU time 11.58 seconds
Started Jun 04 02:01:19 PM PDT 24
Finished Jun 04 02:01:32 PM PDT 24
Peak memory 240744 kb
Host smart-18ac256b-0dff-471b-81e9-243397913327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631113854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3631113854
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2639841865
Short name T625
Test name
Test status
Simulation time 313462353 ps
CPU time 5.24 seconds
Started Jun 04 02:01:21 PM PDT 24
Finished Jun 04 02:01:28 PM PDT 24
Peak memory 220008 kb
Host smart-0fdebfbd-e51a-404d-903a-31e6a45d6f35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2639841865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2639841865
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3862071867
Short name T780
Test name
Test status
Simulation time 13450336 ps
CPU time 0.72 seconds
Started Jun 04 02:01:16 PM PDT 24
Finished Jun 04 02:01:18 PM PDT 24
Peak memory 205540 kb
Host smart-72ccb493-768f-4587-b1b7-17a8ad571c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862071867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3862071867
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2100021392
Short name T612
Test name
Test status
Simulation time 10541249073 ps
CPU time 9.01 seconds
Started Jun 04 02:01:17 PM PDT 24
Finished Jun 04 02:01:27 PM PDT 24
Peak memory 216192 kb
Host smart-40fb5ce6-0783-44cd-871b-c12c9dac1bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100021392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2100021392
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2511689317
Short name T389
Test name
Test status
Simulation time 120333432 ps
CPU time 0.94 seconds
Started Jun 04 02:01:15 PM PDT 24
Finished Jun 04 02:01:17 PM PDT 24
Peak memory 206692 kb
Host smart-059c9c26-b7a0-49ba-89e8-efb5d5359278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511689317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2511689317
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.130789607
Short name T577
Test name
Test status
Simulation time 28119352 ps
CPU time 0.76 seconds
Started Jun 04 02:01:18 PM PDT 24
Finished Jun 04 02:01:20 PM PDT 24
Peak memory 205684 kb
Host smart-109a2894-0511-4dad-b888-62f598ba5eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130789607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.130789607
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.906867732
Short name T723
Test name
Test status
Simulation time 3679767799 ps
CPU time 6.68 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:01:28 PM PDT 24
Peak memory 237856 kb
Host smart-88487b5c-f4a3-4629-9430-8b9c0da69eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906867732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.906867732
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2591620719
Short name T418
Test name
Test status
Simulation time 14078961 ps
CPU time 0.74 seconds
Started Jun 04 02:01:22 PM PDT 24
Finished Jun 04 02:01:24 PM PDT 24
Peak memory 204680 kb
Host smart-314cbd47-b38b-4dcd-9271-2d007dacd19c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591620719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
591620719
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3889528389
Short name T685
Test name
Test status
Simulation time 684650391 ps
CPU time 5 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:01:27 PM PDT 24
Peak memory 235044 kb
Host smart-15bcc700-26ae-4de1-b9d2-dbb1fae98087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889528389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3889528389
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4181557471
Short name T744
Test name
Test status
Simulation time 57469060 ps
CPU time 0.77 seconds
Started Jun 04 02:01:19 PM PDT 24
Finished Jun 04 02:01:21 PM PDT 24
Peak memory 206372 kb
Host smart-f73a50d3-533c-4d80-b9f8-ffef4c1108d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181557471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4181557471
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2658009669
Short name T235
Test name
Test status
Simulation time 7782200955 ps
CPU time 49.19 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:02:11 PM PDT 24
Peak memory 224504 kb
Host smart-fc215a99-b888-46c7-bf17-befae0bffe62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658009669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2658009669
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1427399853
Short name T897
Test name
Test status
Simulation time 16733847009 ps
CPU time 138.92 seconds
Started Jun 04 02:01:19 PM PDT 24
Finished Jun 04 02:03:40 PM PDT 24
Peak memory 249416 kb
Host smart-a29160c0-ee02-48a8-8edb-d92817532ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427399853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1427399853
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3265725111
Short name T249
Test name
Test status
Simulation time 23688589857 ps
CPU time 218.87 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:05:01 PM PDT 24
Peak memory 264672 kb
Host smart-a43c1370-ac45-40a8-89a1-09e7b94d5acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265725111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3265725111
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3483837756
Short name T474
Test name
Test status
Simulation time 1212664899 ps
CPU time 10.3 seconds
Started Jun 04 02:01:22 PM PDT 24
Finished Jun 04 02:01:34 PM PDT 24
Peak memory 232604 kb
Host smart-cc63e597-ba16-4367-9b42-fa9f84c11ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483837756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3483837756
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2512749422
Short name T635
Test name
Test status
Simulation time 2670676859 ps
CPU time 22.47 seconds
Started Jun 04 02:01:21 PM PDT 24
Finished Jun 04 02:01:45 PM PDT 24
Peak memory 233428 kb
Host smart-a0c1561a-476c-487a-92f3-0474544ab242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512749422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2512749422
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3346771487
Short name T291
Test name
Test status
Simulation time 16001631365 ps
CPU time 31.86 seconds
Started Jun 04 02:01:23 PM PDT 24
Finished Jun 04 02:01:56 PM PDT 24
Peak memory 219952 kb
Host smart-e1512967-a968-484e-8b07-9f2324a6877a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346771487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3346771487
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.423743711
Short name T750
Test name
Test status
Simulation time 32194104 ps
CPU time 2.32 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:01:24 PM PDT 24
Peak memory 221388 kb
Host smart-51802a55-4be5-4384-bde3-9a887aced24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423743711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
423743711
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2872496460
Short name T331
Test name
Test status
Simulation time 14584739176 ps
CPU time 14.58 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:01:37 PM PDT 24
Peak memory 231196 kb
Host smart-579fb6bc-9819-4341-a4cc-ecfb07a805eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872496460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2872496460
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2186343853
Short name T147
Test name
Test status
Simulation time 243789531 ps
CPU time 4.68 seconds
Started Jun 04 02:01:19 PM PDT 24
Finished Jun 04 02:01:25 PM PDT 24
Peak memory 222504 kb
Host smart-64b02cc8-b1e3-4299-8aaa-9dd1009294e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2186343853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2186343853
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4000545192
Short name T67
Test name
Test status
Simulation time 472008106 ps
CPU time 1.08 seconds
Started Jun 04 02:01:19 PM PDT 24
Finished Jun 04 02:01:22 PM PDT 24
Peak memory 235032 kb
Host smart-a0c4a3ea-5c1a-4fa9-a4d7-5e5a84e12a4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000545192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4000545192
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3999034427
Short name T496
Test name
Test status
Simulation time 6261686941 ps
CPU time 16.54 seconds
Started Jun 04 02:01:33 PM PDT 24
Finished Jun 04 02:01:50 PM PDT 24
Peak memory 216464 kb
Host smart-bb2373a1-dfbc-437b-a56e-f029f2cc7325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999034427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3999034427
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2032755705
Short name T87
Test name
Test status
Simulation time 854953988 ps
CPU time 1.41 seconds
Started Jun 04 02:01:21 PM PDT 24
Finished Jun 04 02:01:24 PM PDT 24
Peak memory 207540 kb
Host smart-31f6a948-9d44-4918-9a24-22a66fb23494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032755705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2032755705
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1313206837
Short name T553
Test name
Test status
Simulation time 52316320 ps
CPU time 1.11 seconds
Started Jun 04 02:01:33 PM PDT 24
Finished Jun 04 02:01:35 PM PDT 24
Peak memory 207764 kb
Host smart-52af7a11-ccfd-46ff-b634-63fb3f09828b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313206837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1313206837
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_upload.2674010411
Short name T233
Test name
Test status
Simulation time 954011742 ps
CPU time 9.38 seconds
Started Jun 04 02:01:21 PM PDT 24
Finished Jun 04 02:01:32 PM PDT 24
Peak memory 233868 kb
Host smart-c2c2a61f-cbff-4281-ab42-de32e0db2359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674010411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2674010411
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3781023319
Short name T784
Test name
Test status
Simulation time 18344314 ps
CPU time 0.69 seconds
Started Jun 04 02:01:48 PM PDT 24
Finished Jun 04 02:01:50 PM PDT 24
Peak memory 204704 kb
Host smart-73fb5a9c-afef-4330-8218-2855eceb6bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781023319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3781023319
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3624321785
Short name T90
Test name
Test status
Simulation time 439786456 ps
CPU time 6.59 seconds
Started Jun 04 02:01:48 PM PDT 24
Finished Jun 04 02:01:56 PM PDT 24
Peak memory 234164 kb
Host smart-c60c3a0f-caf4-4758-b2c1-8723de2312f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624321785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3624321785
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.138870474
Short name T732
Test name
Test status
Simulation time 69221648 ps
CPU time 0.79 seconds
Started Jun 04 02:01:48 PM PDT 24
Finished Jun 04 02:01:50 PM PDT 24
Peak memory 206696 kb
Host smart-fce3e554-1885-4226-b661-c6b5ceca12d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138870474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.138870474
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2632096364
Short name T884
Test name
Test status
Simulation time 51546746801 ps
CPU time 332.02 seconds
Started Jun 04 02:01:52 PM PDT 24
Finished Jun 04 02:07:26 PM PDT 24
Peak memory 249036 kb
Host smart-1db94481-3612-4141-b008-a294aa1a4259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632096364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2632096364
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1811918781
Short name T314
Test name
Test status
Simulation time 6395989643 ps
CPU time 93.01 seconds
Started Jun 04 02:01:50 PM PDT 24
Finished Jun 04 02:03:24 PM PDT 24
Peak memory 251464 kb
Host smart-43eb5b0a-3dd8-49c6-8a2d-ee8dcaedd3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811918781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1811918781
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.867135735
Short name T57
Test name
Test status
Simulation time 229882695913 ps
CPU time 558.38 seconds
Started Jun 04 02:01:47 PM PDT 24
Finished Jun 04 02:11:07 PM PDT 24
Peak memory 257224 kb
Host smart-820bd8ab-db1a-4ddc-a22c-b1afa0111776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867135735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.867135735
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1586688608
Short name T679
Test name
Test status
Simulation time 1136551692 ps
CPU time 8.83 seconds
Started Jun 04 02:01:46 PM PDT 24
Finished Jun 04 02:01:56 PM PDT 24
Peak memory 240736 kb
Host smart-6a369009-6001-4de8-8be8-17e5e93af340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586688608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1586688608
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3142343880
Short name T594
Test name
Test status
Simulation time 1865831019 ps
CPU time 12.83 seconds
Started Jun 04 02:01:47 PM PDT 24
Finished Jun 04 02:02:02 PM PDT 24
Peak memory 227100 kb
Host smart-f8b6e3fb-95ca-4e5c-a6a6-1c177eadecd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142343880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3142343880
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2762518711
Short name T218
Test name
Test status
Simulation time 20712119265 ps
CPU time 15.73 seconds
Started Jun 04 02:01:47 PM PDT 24
Finished Jun 04 02:02:05 PM PDT 24
Peak memory 218416 kb
Host smart-55fcc054-be06-431f-9011-2ab14d9bc6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762518711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2762518711
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.209240393
Short name T648
Test name
Test status
Simulation time 87213777 ps
CPU time 2.32 seconds
Started Jun 04 02:01:49 PM PDT 24
Finished Jun 04 02:01:53 PM PDT 24
Peak memory 218704 kb
Host smart-0cc98aeb-31c9-4690-9d81-ef34e7c7c56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209240393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.209240393
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1372789015
Short name T556
Test name
Test status
Simulation time 2348744946 ps
CPU time 11.77 seconds
Started Jun 04 02:01:49 PM PDT 24
Finished Jun 04 02:02:02 PM PDT 24
Peak memory 223064 kb
Host smart-de937df3-87fb-421e-9ddf-5734862772f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1372789015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1372789015
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.689958117
Short name T198
Test name
Test status
Simulation time 31843993565 ps
CPU time 118.2 seconds
Started Jun 04 02:01:48 PM PDT 24
Finished Jun 04 02:03:48 PM PDT 24
Peak memory 248996 kb
Host smart-254c721d-d7d8-4ccb-95b7-2945623ce57e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689958117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.689958117
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.985677126
Short name T462
Test name
Test status
Simulation time 4236692931 ps
CPU time 11.53 seconds
Started Jun 04 02:01:48 PM PDT 24
Finished Jun 04 02:02:01 PM PDT 24
Peak memory 216292 kb
Host smart-2227bd5e-96c4-42cd-8432-6c71dfcc83c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985677126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.985677126
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.4193729094
Short name T20
Test name
Test status
Simulation time 12610964 ps
CPU time 0.71 seconds
Started Jun 04 02:01:47 PM PDT 24
Finished Jun 04 02:01:50 PM PDT 24
Peak memory 205456 kb
Host smart-254d6153-3f14-4cc6-b610-408ed935e613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193729094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.4193729094
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2494033954
Short name T505
Test name
Test status
Simulation time 48968675 ps
CPU time 1.25 seconds
Started Jun 04 02:01:46 PM PDT 24
Finished Jun 04 02:01:48 PM PDT 24
Peak memory 207988 kb
Host smart-2c7f86d8-f35f-41f2-9e88-43de489ce22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494033954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2494033954
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2525687494
Short name T365
Test name
Test status
Simulation time 10958809 ps
CPU time 0.69 seconds
Started Jun 04 02:01:46 PM PDT 24
Finished Jun 04 02:01:48 PM PDT 24
Peak memory 205368 kb
Host smart-2fad4b94-1284-451b-92af-9df4768331ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525687494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2525687494
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.231025999
Short name T818
Test name
Test status
Simulation time 5138253322 ps
CPU time 10.26 seconds
Started Jun 04 02:01:45 PM PDT 24
Finished Jun 04 02:01:56 PM PDT 24
Peak memory 229324 kb
Host smart-4025ef89-d2f6-4e00-abac-6fd4f99c058f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231025999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.231025999
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.92160117
Short name T812
Test name
Test status
Simulation time 17016472 ps
CPU time 0.69 seconds
Started Jun 04 02:01:56 PM PDT 24
Finished Jun 04 02:01:57 PM PDT 24
Peak memory 205704 kb
Host smart-e1bb8dbf-8b5c-40a3-9814-b89bb8821f4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92160117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.92160117
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.203725001
Short name T558
Test name
Test status
Simulation time 1159486972 ps
CPU time 10.46 seconds
Started Jun 04 02:01:52 PM PDT 24
Finished Jun 04 02:02:04 PM PDT 24
Peak memory 219620 kb
Host smart-68e374e6-1546-4ec3-bc12-7dd8a8fb0dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203725001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.203725001
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1343883554
Short name T420
Test name
Test status
Simulation time 20008736 ps
CPU time 0.78 seconds
Started Jun 04 02:01:47 PM PDT 24
Finished Jun 04 02:01:49 PM PDT 24
Peak memory 205348 kb
Host smart-334eccaa-0c16-4d3b-8062-3e15a9e2d4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343883554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1343883554
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2727894437
Short name T26
Test name
Test status
Simulation time 5232020006 ps
CPU time 22.47 seconds
Started Jun 04 02:01:56 PM PDT 24
Finished Jun 04 02:02:19 PM PDT 24
Peak memory 249000 kb
Host smart-0a78cb3a-cdf6-499b-b4e6-cd5c7799e6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727894437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2727894437
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.118458006
Short name T840
Test name
Test status
Simulation time 33407084301 ps
CPU time 78.23 seconds
Started Jun 04 02:01:53 PM PDT 24
Finished Jun 04 02:03:13 PM PDT 24
Peak memory 240560 kb
Host smart-ca196f99-f0b5-4349-9af7-613734e1b5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118458006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.118458006
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3529625192
Short name T755
Test name
Test status
Simulation time 20264647508 ps
CPU time 185.42 seconds
Started Jun 04 02:01:55 PM PDT 24
Finished Jun 04 02:05:01 PM PDT 24
Peak memory 233696 kb
Host smart-112df8ed-83d9-4a2c-b2cd-f27376dfb1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529625192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3529625192
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2056531346
Short name T672
Test name
Test status
Simulation time 41195977 ps
CPU time 2.36 seconds
Started Jun 04 02:01:48 PM PDT 24
Finished Jun 04 02:01:52 PM PDT 24
Peak memory 224412 kb
Host smart-52daac2f-abad-480c-b125-c43e6ae3cdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056531346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2056531346
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2801375601
Short name T229
Test name
Test status
Simulation time 55303915 ps
CPU time 2.65 seconds
Started Jun 04 02:01:45 PM PDT 24
Finished Jun 04 02:01:48 PM PDT 24
Peak memory 234052 kb
Host smart-375e3211-f4fd-4016-ba97-e879477ab09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801375601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2801375601
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.4018074204
Short name T916
Test name
Test status
Simulation time 3115014945 ps
CPU time 12.57 seconds
Started Jun 04 02:01:45 PM PDT 24
Finished Jun 04 02:01:59 PM PDT 24
Peak memory 234200 kb
Host smart-f1b6e284-3851-424e-82a8-4becae5ce352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018074204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4018074204
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2608112832
Short name T194
Test name
Test status
Simulation time 474682653 ps
CPU time 5.47 seconds
Started Jun 04 02:01:48 PM PDT 24
Finished Jun 04 02:01:55 PM PDT 24
Peak memory 235136 kb
Host smart-965ee77c-4bad-4acf-894a-67fcf28d6249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608112832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2608112832
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.663885233
Short name T172
Test name
Test status
Simulation time 20218837798 ps
CPU time 12.05 seconds
Started Jun 04 02:01:48 PM PDT 24
Finished Jun 04 02:02:01 PM PDT 24
Peak memory 218824 kb
Host smart-af4f654d-32ed-4b24-949b-662d4c11eba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663885233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.663885233
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1154139498
Short name T885
Test name
Test status
Simulation time 241195186 ps
CPU time 4.1 seconds
Started Jun 04 02:01:47 PM PDT 24
Finished Jun 04 02:01:53 PM PDT 24
Peak memory 218928 kb
Host smart-fe0ce710-1006-442e-b093-f6e146cbb456
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1154139498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1154139498
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2457430219
Short name T519
Test name
Test status
Simulation time 66365991 ps
CPU time 1.12 seconds
Started Jun 04 02:01:53 PM PDT 24
Finished Jun 04 02:01:55 PM PDT 24
Peak memory 207024 kb
Host smart-edae0bf5-c8e8-495b-be43-7866b93d3cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457430219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2457430219
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3570352971
Short name T535
Test name
Test status
Simulation time 1236936993 ps
CPU time 18.63 seconds
Started Jun 04 02:01:46 PM PDT 24
Finished Jun 04 02:02:05 PM PDT 24
Peak memory 216500 kb
Host smart-e66a550b-a5b8-4370-9faf-f5172302e983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570352971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3570352971
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1975821259
Short name T360
Test name
Test status
Simulation time 2493790837 ps
CPU time 4.02 seconds
Started Jun 04 02:01:48 PM PDT 24
Finished Jun 04 02:01:53 PM PDT 24
Peak memory 216180 kb
Host smart-11b352c8-56c5-4ebf-b890-4999d9a90d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975821259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1975821259
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3267343340
Short name T728
Test name
Test status
Simulation time 46221010 ps
CPU time 1.29 seconds
Started Jun 04 02:01:48 PM PDT 24
Finished Jun 04 02:01:51 PM PDT 24
Peak memory 216216 kb
Host smart-5fc38888-b366-4309-ae9d-a4b3b532ab54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267343340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3267343340
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3504968561
Short name T861
Test name
Test status
Simulation time 46455055 ps
CPU time 0.87 seconds
Started Jun 04 02:01:46 PM PDT 24
Finished Jun 04 02:01:47 PM PDT 24
Peak memory 205576 kb
Host smart-e46c9f0c-e5f4-4a2b-8f0c-711111147792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504968561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3504968561
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.757645109
Short name T819
Test name
Test status
Simulation time 26647568465 ps
CPU time 13.34 seconds
Started Jun 04 02:01:46 PM PDT 24
Finished Jun 04 02:02:01 PM PDT 24
Peak memory 219020 kb
Host smart-5f69ff9b-cba6-4d5e-a4ed-fffe0ef541d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757645109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.757645109
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4078308990
Short name T461
Test name
Test status
Simulation time 31053809 ps
CPU time 0.7 seconds
Started Jun 04 02:01:52 PM PDT 24
Finished Jun 04 02:01:53 PM PDT 24
Peak memory 205688 kb
Host smart-6fe4aebd-d2fe-4fcb-8da7-bf1dabc17672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078308990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4078308990
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1886289866
Short name T164
Test name
Test status
Simulation time 1285921680 ps
CPU time 13.64 seconds
Started Jun 04 02:01:54 PM PDT 24
Finished Jun 04 02:02:09 PM PDT 24
Peak memory 218548 kb
Host smart-36ab1389-fcc2-4386-a5c0-ab18bc4ef064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886289866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1886289866
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1567151087
Short name T455
Test name
Test status
Simulation time 99475769 ps
CPU time 0.75 seconds
Started Jun 04 02:01:54 PM PDT 24
Finished Jun 04 02:01:56 PM PDT 24
Peak memory 206396 kb
Host smart-d8f69138-302f-4431-8838-f84e49874f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567151087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1567151087
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3810001960
Short name T165
Test name
Test status
Simulation time 4371433247 ps
CPU time 66.75 seconds
Started Jun 04 02:01:53 PM PDT 24
Finished Jun 04 02:03:01 PM PDT 24
Peak memory 249432 kb
Host smart-7dd6978a-83b1-4228-a307-631dea8572c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810001960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3810001960
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3701416545
Short name T643
Test name
Test status
Simulation time 21074286821 ps
CPU time 90.77 seconds
Started Jun 04 02:01:53 PM PDT 24
Finished Jun 04 02:03:25 PM PDT 24
Peak memory 251976 kb
Host smart-0c4f50e9-e31d-430a-8eb9-559aa50b197b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701416545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3701416545
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1444406304
Short name T835
Test name
Test status
Simulation time 2113413897 ps
CPU time 30.26 seconds
Started Jun 04 02:01:54 PM PDT 24
Finished Jun 04 02:02:26 PM PDT 24
Peak memory 248988 kb
Host smart-109574c3-58dd-4b3b-bcae-3e42e1e235dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444406304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1444406304
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2890275223
Short name T72
Test name
Test status
Simulation time 4501744578 ps
CPU time 35.8 seconds
Started Jun 04 02:01:53 PM PDT 24
Finished Jun 04 02:02:30 PM PDT 24
Peak memory 233696 kb
Host smart-194ac11b-169a-4b6a-aa77-1530379f60a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890275223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2890275223
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1430632673
Short name T841
Test name
Test status
Simulation time 490631999 ps
CPU time 7.52 seconds
Started Jun 04 02:01:54 PM PDT 24
Finished Jun 04 02:02:03 PM PDT 24
Peak memory 218452 kb
Host smart-193e494e-b9c4-431b-ab50-937ff9440ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430632673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1430632673
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1435811403
Short name T785
Test name
Test status
Simulation time 1016955429 ps
CPU time 6.08 seconds
Started Jun 04 02:01:52 PM PDT 24
Finished Jun 04 02:01:59 PM PDT 24
Peak memory 236220 kb
Host smart-bce14250-ddec-4187-a165-0c75bdf8eae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435811403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1435811403
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2923571258
Short name T947
Test name
Test status
Simulation time 10135159923 ps
CPU time 8.76 seconds
Started Jun 04 02:01:53 PM PDT 24
Finished Jun 04 02:02:03 PM PDT 24
Peak memory 233984 kb
Host smart-931f665d-dfff-457c-ab3d-46ba627605e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923571258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2923571258
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1236572599
Short name T598
Test name
Test status
Simulation time 140149661 ps
CPU time 3.4 seconds
Started Jun 04 02:01:53 PM PDT 24
Finished Jun 04 02:01:57 PM PDT 24
Peak memory 222864 kb
Host smart-ca89ed33-22bf-4099-8872-d853bb8ad252
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1236572599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1236572599
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3790418376
Short name T220
Test name
Test status
Simulation time 1696459074 ps
CPU time 32.14 seconds
Started Jun 04 02:01:55 PM PDT 24
Finished Jun 04 02:02:28 PM PDT 24
Peak memory 224416 kb
Host smart-8158217a-5d19-488b-b360-b65e772c7277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790418376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3790418376
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3597564169
Short name T361
Test name
Test status
Simulation time 8650326820 ps
CPU time 23.65 seconds
Started Jun 04 02:01:54 PM PDT 24
Finished Jun 04 02:02:19 PM PDT 24
Peak memory 216152 kb
Host smart-eb5d3efc-f61d-48aa-b8d8-bb53c04fa917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597564169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3597564169
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.490334527
Short name T509
Test name
Test status
Simulation time 82269380 ps
CPU time 1.33 seconds
Started Jun 04 02:01:53 PM PDT 24
Finished Jun 04 02:01:56 PM PDT 24
Peak memory 216188 kb
Host smart-9efaa77a-8313-48d8-80bd-6ca94c57461d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490334527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.490334527
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1296882709
Short name T924
Test name
Test status
Simulation time 56631764 ps
CPU time 0.76 seconds
Started Jun 04 02:01:53 PM PDT 24
Finished Jun 04 02:01:55 PM PDT 24
Peak memory 205676 kb
Host smart-374a425a-2961-410a-b101-75681e8e56ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296882709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1296882709
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1696056020
Short name T617
Test name
Test status
Simulation time 1390833077 ps
CPU time 8.6 seconds
Started Jun 04 02:01:52 PM PDT 24
Finished Jun 04 02:02:01 PM PDT 24
Peak memory 231472 kb
Host smart-1d8b52f9-ca99-4fd8-a845-8400f2498735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696056020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1696056020
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3362293117
Short name T573
Test name
Test status
Simulation time 25002359 ps
CPU time 0.71 seconds
Started Jun 04 02:02:02 PM PDT 24
Finished Jun 04 02:02:04 PM PDT 24
Peak memory 204760 kb
Host smart-461b78d6-8b8d-49f1-9560-0a222b0c2021
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362293117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3362293117
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3349717801
Short name T325
Test name
Test status
Simulation time 425382147 ps
CPU time 3.68 seconds
Started Jun 04 02:02:04 PM PDT 24
Finished Jun 04 02:02:09 PM PDT 24
Peak memory 236412 kb
Host smart-1b900ee7-836b-4649-bb58-3fb7741513ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349717801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3349717801
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3009279511
Short name T938
Test name
Test status
Simulation time 20561861 ps
CPU time 0.77 seconds
Started Jun 04 02:01:56 PM PDT 24
Finished Jun 04 02:01:58 PM PDT 24
Peak memory 206716 kb
Host smart-3c5382a3-1e71-41c5-8100-a6c5c18e7479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009279511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3009279511
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3468272930
Short name T21
Test name
Test status
Simulation time 22835505855 ps
CPU time 163.2 seconds
Started Jun 04 02:02:01 PM PDT 24
Finished Jun 04 02:04:45 PM PDT 24
Peak memory 250016 kb
Host smart-e7169e2f-398e-4a02-bf7e-1538fac94192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468272930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3468272930
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3565067729
Short name T950
Test name
Test status
Simulation time 6433556015 ps
CPU time 40.13 seconds
Started Jun 04 02:02:00 PM PDT 24
Finished Jun 04 02:02:41 PM PDT 24
Peak memory 240876 kb
Host smart-a02075f3-89b0-4dab-80c7-0d93f0227758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565067729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3565067729
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3515256265
Short name T866
Test name
Test status
Simulation time 4793303243 ps
CPU time 26.35 seconds
Started Jun 04 02:02:02 PM PDT 24
Finished Jun 04 02:02:30 PM PDT 24
Peak memory 237548 kb
Host smart-c02d052a-6575-422d-93e9-efc74d3719f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515256265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3515256265
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1655696780
Short name T236
Test name
Test status
Simulation time 2012417512 ps
CPU time 21.23 seconds
Started Jun 04 02:01:53 PM PDT 24
Finished Jun 04 02:02:16 PM PDT 24
Peak memory 233524 kb
Host smart-67765a9d-b492-405e-8175-2d745561f06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655696780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1655696780
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1783746242
Short name T868
Test name
Test status
Simulation time 712808591 ps
CPU time 3.88 seconds
Started Jun 04 02:02:01 PM PDT 24
Finished Jun 04 02:02:06 PM PDT 24
Peak memory 224340 kb
Host smart-a7ed07f3-3549-459a-be3c-f24a5e9d89a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783746242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1783746242
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1513680312
Short name T33
Test name
Test status
Simulation time 1329166388 ps
CPU time 9.92 seconds
Started Jun 04 02:01:53 PM PDT 24
Finished Jun 04 02:02:04 PM PDT 24
Peak memory 233812 kb
Host smart-082c7823-cf29-4642-b034-ffcb90506a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513680312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1513680312
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2287491790
Short name T230
Test name
Test status
Simulation time 720467537 ps
CPU time 5.69 seconds
Started Jun 04 02:01:57 PM PDT 24
Finished Jun 04 02:02:04 PM PDT 24
Peak memory 218476 kb
Host smart-be3a82fe-e57a-47c0-8687-8b55051031ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287491790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2287491790
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3356569427
Short name T404
Test name
Test status
Simulation time 9445128095 ps
CPU time 20.42 seconds
Started Jun 04 02:02:02 PM PDT 24
Finished Jun 04 02:02:23 PM PDT 24
Peak memory 218788 kb
Host smart-7eb03c2d-b5cf-4996-9ac0-d2997f379eb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3356569427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3356569427
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2413247838
Short name T258
Test name
Test status
Simulation time 28135957382 ps
CPU time 176.97 seconds
Started Jun 04 02:01:59 PM PDT 24
Finished Jun 04 02:04:56 PM PDT 24
Peak memory 265492 kb
Host smart-0edc34c3-706e-4213-9081-75748f1ec49c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413247838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2413247838
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.380424590
Short name T507
Test name
Test status
Simulation time 135546037 ps
CPU time 0.71 seconds
Started Jun 04 02:01:53 PM PDT 24
Finished Jun 04 02:01:55 PM PDT 24
Peak memory 205560 kb
Host smart-f33b1f42-ed1b-49e9-ab68-d90a468aa5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380424590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.380424590
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3794275623
Short name T435
Test name
Test status
Simulation time 30543688 ps
CPU time 0.68 seconds
Started Jun 04 02:01:53 PM PDT 24
Finished Jun 04 02:01:54 PM PDT 24
Peak memory 205492 kb
Host smart-2735899e-38af-49bc-a741-a062245042d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794275623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3794275623
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2017127482
Short name T707
Test name
Test status
Simulation time 52143428 ps
CPU time 0.85 seconds
Started Jun 04 02:01:56 PM PDT 24
Finished Jun 04 02:01:57 PM PDT 24
Peak memory 206488 kb
Host smart-56568757-9482-4ef7-9c4a-26bc18f05774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017127482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2017127482
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2577364547
Short name T821
Test name
Test status
Simulation time 68417392 ps
CPU time 0.92 seconds
Started Jun 04 02:01:57 PM PDT 24
Finished Jun 04 02:01:59 PM PDT 24
Peak memory 205540 kb
Host smart-970f4606-666c-46aa-9e93-1c3ce90162f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577364547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2577364547
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.660157687
Short name T190
Test name
Test status
Simulation time 12928033042 ps
CPU time 6.31 seconds
Started Jun 04 02:02:04 PM PDT 24
Finished Jun 04 02:02:11 PM PDT 24
Peak memory 224432 kb
Host smart-d3f6eff6-b845-4d0c-a069-06ae21fe162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660157687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.660157687
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1343947146
Short name T615
Test name
Test status
Simulation time 12063533 ps
CPU time 0.77 seconds
Started Jun 04 02:02:01 PM PDT 24
Finished Jun 04 02:02:03 PM PDT 24
Peak memory 205436 kb
Host smart-e212753a-c990-4ea6-ba47-a26680084e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343947146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1343947146
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1454962581
Short name T602
Test name
Test status
Simulation time 751426572 ps
CPU time 6.42 seconds
Started Jun 04 02:02:06 PM PDT 24
Finished Jun 04 02:02:13 PM PDT 24
Peak memory 218300 kb
Host smart-f35f48b2-6376-4071-ab34-8a5c988eb17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454962581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1454962581
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1256317041
Short name T844
Test name
Test status
Simulation time 19051007 ps
CPU time 0.76 seconds
Started Jun 04 02:02:06 PM PDT 24
Finished Jun 04 02:02:08 PM PDT 24
Peak memory 206728 kb
Host smart-577876cc-305d-43de-97ba-4390a1914716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256317041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1256317041
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.347534384
Short name T518
Test name
Test status
Simulation time 20265713 ps
CPU time 0.78 seconds
Started Jun 04 02:02:03 PM PDT 24
Finished Jun 04 02:02:05 PM PDT 24
Peak memory 215680 kb
Host smart-ebdb3c92-023c-47b3-a920-f1860667d234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347534384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.347534384
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1560496370
Short name T955
Test name
Test status
Simulation time 16594550546 ps
CPU time 187.83 seconds
Started Jun 04 02:02:03 PM PDT 24
Finished Jun 04 02:05:12 PM PDT 24
Peak memory 256164 kb
Host smart-0c4905a4-12de-4efa-98a7-cbb9a67d4117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560496370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1560496370
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1091385826
Short name T527
Test name
Test status
Simulation time 19315720789 ps
CPU time 144.89 seconds
Started Jun 04 02:02:06 PM PDT 24
Finished Jun 04 02:04:31 PM PDT 24
Peak memory 240824 kb
Host smart-8fd1e3b2-9176-4f1a-8be3-7209880fe9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091385826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1091385826
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1848585381
Short name T734
Test name
Test status
Simulation time 1060851996 ps
CPU time 12.11 seconds
Started Jun 04 02:02:03 PM PDT 24
Finished Jun 04 02:02:17 PM PDT 24
Peak memory 224304 kb
Host smart-66d9330c-04da-4877-bbde-9b416d120c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848585381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1848585381
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3083940796
Short name T774
Test name
Test status
Simulation time 28415211 ps
CPU time 2.02 seconds
Started Jun 04 02:02:02 PM PDT 24
Finished Jun 04 02:02:05 PM PDT 24
Peak memory 215952 kb
Host smart-b0cb4c0e-89bb-4641-ab60-f045ad962bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083940796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3083940796
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.4008231096
Short name T239
Test name
Test status
Simulation time 2916108387 ps
CPU time 35.77 seconds
Started Jun 04 02:02:00 PM PDT 24
Finished Jun 04 02:02:36 PM PDT 24
Peak memory 219480 kb
Host smart-60c02f49-7f46-4cc7-98b9-6597ba326244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008231096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.4008231096
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3720701393
Short name T223
Test name
Test status
Simulation time 3496155043 ps
CPU time 12.4 seconds
Started Jun 04 02:02:03 PM PDT 24
Finished Jun 04 02:02:17 PM PDT 24
Peak memory 218544 kb
Host smart-d8d7cd32-e2a1-4940-a689-30f814b2fda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720701393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3720701393
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1630955354
Short name T468
Test name
Test status
Simulation time 4243142957 ps
CPU time 14.05 seconds
Started Jun 04 02:02:02 PM PDT 24
Finished Jun 04 02:02:17 PM PDT 24
Peak memory 240636 kb
Host smart-9187908d-8d7d-471e-b579-c560985aed23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630955354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1630955354
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.451075283
Short name T663
Test name
Test status
Simulation time 578911619 ps
CPU time 3.81 seconds
Started Jun 04 02:02:02 PM PDT 24
Finished Jun 04 02:02:07 PM PDT 24
Peak memory 220144 kb
Host smart-a49deaed-6da1-46aa-98be-5921c5305a4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=451075283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.451075283
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1870707747
Short name T946
Test name
Test status
Simulation time 23463524240 ps
CPU time 39.79 seconds
Started Jun 04 02:02:02 PM PDT 24
Finished Jun 04 02:02:42 PM PDT 24
Peak memory 216112 kb
Host smart-2b73b7e4-b0b5-4e02-8872-349972b8b4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870707747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1870707747
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2111657377
Short name T501
Test name
Test status
Simulation time 293769402 ps
CPU time 1.83 seconds
Started Jun 04 02:02:00 PM PDT 24
Finished Jun 04 02:02:03 PM PDT 24
Peak memory 206864 kb
Host smart-1e51e8a3-a116-4021-ac43-f4dca9bfe59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111657377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2111657377
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1392638352
Short name T892
Test name
Test status
Simulation time 186495472 ps
CPU time 5.79 seconds
Started Jun 04 02:02:03 PM PDT 24
Finished Jun 04 02:02:10 PM PDT 24
Peak memory 216192 kb
Host smart-3029742b-ab4f-405a-99da-6fe45d484ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392638352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1392638352
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3756088747
Short name T548
Test name
Test status
Simulation time 193465024 ps
CPU time 0.88 seconds
Started Jun 04 02:02:03 PM PDT 24
Finished Jun 04 02:02:05 PM PDT 24
Peak memory 205548 kb
Host smart-61ab0952-a7cc-4889-b5cf-7c4a4593060d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756088747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3756088747
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3793694588
Short name T306
Test name
Test status
Simulation time 701913497 ps
CPU time 6.25 seconds
Started Jun 04 02:02:01 PM PDT 24
Finished Jun 04 02:02:08 PM PDT 24
Peak memory 240712 kb
Host smart-8465797e-344b-494f-9209-41ce924ddd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793694588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3793694588
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2244761981
Short name T50
Test name
Test status
Simulation time 19603869 ps
CPU time 0.7 seconds
Started Jun 04 02:02:03 PM PDT 24
Finished Jun 04 02:02:05 PM PDT 24
Peak memory 205348 kb
Host smart-f6d5faa3-67b0-464c-bb86-e32947fe5991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244761981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2244761981
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.9393807
Short name T941
Test name
Test status
Simulation time 341990822 ps
CPU time 5.45 seconds
Started Jun 04 02:02:04 PM PDT 24
Finished Jun 04 02:02:11 PM PDT 24
Peak memory 218608 kb
Host smart-949dfaf0-535e-4e8a-8ac0-d436610c99a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9393807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.9393807
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.847897985
Short name T479
Test name
Test status
Simulation time 25464921 ps
CPU time 0.76 seconds
Started Jun 04 02:02:01 PM PDT 24
Finished Jun 04 02:02:03 PM PDT 24
Peak memory 205436 kb
Host smart-06f8d753-138b-4eae-9cb5-da3cfbe3392e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847897985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.847897985
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.253412866
Short name T166
Test name
Test status
Simulation time 64434081 ps
CPU time 0.78 seconds
Started Jun 04 02:02:03 PM PDT 24
Finished Jun 04 02:02:05 PM PDT 24
Peak memory 215720 kb
Host smart-e2aa0fc1-e9ea-4a88-8489-422fbc32b560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253412866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.253412866
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2290112716
Short name T690
Test name
Test status
Simulation time 9607457692 ps
CPU time 63.52 seconds
Started Jun 04 02:02:00 PM PDT 24
Finished Jun 04 02:03:04 PM PDT 24
Peak memory 265428 kb
Host smart-08d8f378-2af7-4057-9fd5-f146d963dd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290112716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2290112716
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_intercept.4081099982
Short name T960
Test name
Test status
Simulation time 53616412 ps
CPU time 3.27 seconds
Started Jun 04 02:02:00 PM PDT 24
Finished Jun 04 02:02:03 PM PDT 24
Peak memory 232584 kb
Host smart-b41e6599-4f5f-4025-979a-453d197a3234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081099982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.4081099982
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.581179168
Short name T345
Test name
Test status
Simulation time 38967986980 ps
CPU time 115.55 seconds
Started Jun 04 02:02:03 PM PDT 24
Finished Jun 04 02:04:00 PM PDT 24
Peak memory 240180 kb
Host smart-b3f854b3-be27-4c7d-b7eb-0ecfc9e7500c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581179168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.581179168
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2869701506
Short name T279
Test name
Test status
Simulation time 5412164272 ps
CPU time 18.25 seconds
Started Jun 04 02:02:00 PM PDT 24
Finished Jun 04 02:02:20 PM PDT 24
Peak memory 233916 kb
Host smart-979ac5ad-b88e-4c93-948c-b9f8f1af6b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869701506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2869701506
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2276113980
Short name T939
Test name
Test status
Simulation time 5012452523 ps
CPU time 15.86 seconds
Started Jun 04 02:02:03 PM PDT 24
Finished Jun 04 02:02:20 PM PDT 24
Peak memory 233176 kb
Host smart-e8725659-80cb-43d8-835b-74e896ed6620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276113980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2276113980
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.918065821
Short name T422
Test name
Test status
Simulation time 822230292 ps
CPU time 7.03 seconds
Started Jun 04 02:02:01 PM PDT 24
Finished Jun 04 02:02:09 PM PDT 24
Peak memory 222132 kb
Host smart-f72337e1-45bb-4be3-aefa-59e58ab29a79
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=918065821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.918065821
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3923484574
Short name T158
Test name
Test status
Simulation time 113253140 ps
CPU time 1.02 seconds
Started Jun 04 02:02:03 PM PDT 24
Finished Jun 04 02:02:05 PM PDT 24
Peak memory 206720 kb
Host smart-55aed827-6cbe-474f-849d-4d106eaabae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923484574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3923484574
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3982930381
Short name T760
Test name
Test status
Simulation time 930251902 ps
CPU time 4.32 seconds
Started Jun 04 02:02:00 PM PDT 24
Finished Jun 04 02:02:05 PM PDT 24
Peak memory 216392 kb
Host smart-afb925dd-44a7-45ae-b596-0cac541f4e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982930381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3982930381
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3427747253
Short name T13
Test name
Test status
Simulation time 1002006588 ps
CPU time 4.01 seconds
Started Jun 04 02:02:00 PM PDT 24
Finished Jun 04 02:02:05 PM PDT 24
Peak memory 216140 kb
Host smart-3f1e4773-5078-4ff8-a3fa-39801127be72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427747253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3427747253
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1821125169
Short name T498
Test name
Test status
Simulation time 63144093 ps
CPU time 1.2 seconds
Started Jun 04 02:02:00 PM PDT 24
Finished Jun 04 02:02:02 PM PDT 24
Peak memory 207748 kb
Host smart-e6421a50-7d9a-4534-b0a5-b96dfd334288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821125169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1821125169
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.102960938
Short name T710
Test name
Test status
Simulation time 100861407 ps
CPU time 0.68 seconds
Started Jun 04 02:02:03 PM PDT 24
Finished Jun 04 02:02:04 PM PDT 24
Peak memory 205436 kb
Host smart-c65fbbfb-b449-44ec-a142-da204315d4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102960938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.102960938
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1836919288
Short name T689
Test name
Test status
Simulation time 15001800641 ps
CPU time 12.59 seconds
Started Jun 04 02:02:02 PM PDT 24
Finished Jun 04 02:02:16 PM PDT 24
Peak memory 218876 kb
Host smart-d671ce07-791e-4b2a-8693-ebafab87bf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836919288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1836919288
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2476693635
Short name T381
Test name
Test status
Simulation time 12989257 ps
CPU time 0.71 seconds
Started Jun 04 02:02:11 PM PDT 24
Finished Jun 04 02:02:13 PM PDT 24
Peak memory 204800 kb
Host smart-b3cf1b57-de6d-4faa-bd11-46a114c410ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476693635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2476693635
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.276643927
Short name T202
Test name
Test status
Simulation time 1263577833 ps
CPU time 11.77 seconds
Started Jun 04 02:02:11 PM PDT 24
Finished Jun 04 02:02:23 PM PDT 24
Peak memory 233560 kb
Host smart-50b40d47-572c-4fad-9652-897b3ee98dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276643927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.276643927
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1436315165
Short name T779
Test name
Test status
Simulation time 15316473 ps
CPU time 0.72 seconds
Started Jun 04 02:02:00 PM PDT 24
Finished Jun 04 02:02:02 PM PDT 24
Peak memory 205676 kb
Host smart-65af4381-8fd5-4ea0-bc08-dc538eed1adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436315165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1436315165
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3001069949
Short name T436
Test name
Test status
Simulation time 10324282831 ps
CPU time 90.93 seconds
Started Jun 04 02:02:07 PM PDT 24
Finished Jun 04 02:03:39 PM PDT 24
Peak memory 249056 kb
Host smart-9c687345-2e72-48c6-a4d7-b2a4ec2772a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001069949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3001069949
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2688629017
Short name T141
Test name
Test status
Simulation time 16653966852 ps
CPU time 96.01 seconds
Started Jun 04 02:02:12 PM PDT 24
Finished Jun 04 02:03:48 PM PDT 24
Peak memory 252572 kb
Host smart-34b30603-9d71-4c2c-9678-372f51769840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688629017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2688629017
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.966809494
Short name T388
Test name
Test status
Simulation time 314166399 ps
CPU time 6.91 seconds
Started Jun 04 02:02:07 PM PDT 24
Finished Jun 04 02:02:14 PM PDT 24
Peak memory 224316 kb
Host smart-3685784e-864b-4269-b3cf-236cf3babdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966809494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.966809494
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.563446714
Short name T210
Test name
Test status
Simulation time 166125008 ps
CPU time 3.43 seconds
Started Jun 04 02:02:06 PM PDT 24
Finished Jun 04 02:02:10 PM PDT 24
Peak memory 216428 kb
Host smart-b1b4bda1-2173-4576-9642-bf996d286460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563446714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.563446714
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.325589410
Short name T806
Test name
Test status
Simulation time 441736972 ps
CPU time 4.31 seconds
Started Jun 04 02:02:08 PM PDT 24
Finished Jun 04 02:02:14 PM PDT 24
Peak memory 218580 kb
Host smart-50617a2d-d0bd-45d0-8edb-53b1b8e173a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325589410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.325589410
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4258145959
Short name T638
Test name
Test status
Simulation time 89693015596 ps
CPU time 27.58 seconds
Started Jun 04 02:02:07 PM PDT 24
Finished Jun 04 02:02:36 PM PDT 24
Peak memory 240812 kb
Host smart-fdc2b586-9e73-418c-9fad-e36b6ea86078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258145959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4258145959
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1371838349
Short name T811
Test name
Test status
Simulation time 21332660634 ps
CPU time 24.28 seconds
Started Jun 04 02:02:06 PM PDT 24
Finished Jun 04 02:02:31 PM PDT 24
Peak memory 218860 kb
Host smart-fe6c818b-2419-4304-8b71-b79e6f9cd321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371838349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1371838349
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1212606067
Short name T457
Test name
Test status
Simulation time 3687837636 ps
CPU time 8.26 seconds
Started Jun 04 02:02:06 PM PDT 24
Finished Jun 04 02:02:15 PM PDT 24
Peak memory 222900 kb
Host smart-0e7f66bb-ff26-4347-91d6-bbb0573a573c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1212606067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1212606067
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3531504538
Short name T159
Test name
Test status
Simulation time 91033487628 ps
CPU time 826.98 seconds
Started Jun 04 02:02:08 PM PDT 24
Finished Jun 04 02:15:56 PM PDT 24
Peak memory 266516 kb
Host smart-a6f0227d-ca2a-4b50-bb15-a345fed2c72a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531504538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3531504538
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.547022722
Short name T646
Test name
Test status
Simulation time 9359317650 ps
CPU time 26.12 seconds
Started Jun 04 02:02:09 PM PDT 24
Finished Jun 04 02:02:37 PM PDT 24
Peak memory 216304 kb
Host smart-a1f69f91-0c43-48c1-8143-4e6e7756a798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547022722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.547022722
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.203922080
Short name T408
Test name
Test status
Simulation time 4792624272 ps
CPU time 3.88 seconds
Started Jun 04 02:02:03 PM PDT 24
Finished Jun 04 02:02:08 PM PDT 24
Peak memory 216164 kb
Host smart-43c447d3-8e8e-4a5c-a3c9-528ddc78a02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203922080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.203922080
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1673138168
Short name T429
Test name
Test status
Simulation time 68770006 ps
CPU time 0.77 seconds
Started Jun 04 02:02:08 PM PDT 24
Finished Jun 04 02:02:10 PM PDT 24
Peak memory 205724 kb
Host smart-95f9a59f-f43b-4c56-9a57-f9a9caa8f945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673138168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1673138168
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.687940450
Short name T787
Test name
Test status
Simulation time 61277249 ps
CPU time 0.87 seconds
Started Jun 04 02:02:07 PM PDT 24
Finished Jun 04 02:02:09 PM PDT 24
Peak memory 205632 kb
Host smart-4f3f71cd-0a11-4254-81c0-beb4adc8697b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687940450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.687940450
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3411972365
Short name T783
Test name
Test status
Simulation time 817160548 ps
CPU time 8.6 seconds
Started Jun 04 02:02:10 PM PDT 24
Finished Jun 04 02:02:19 PM PDT 24
Peak memory 235428 kb
Host smart-e5751d13-eac5-4d06-96b3-2204cae8ca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411972365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3411972365
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1963557646
Short name T762
Test name
Test status
Simulation time 59905588 ps
CPU time 0.7 seconds
Started Jun 04 02:02:09 PM PDT 24
Finished Jun 04 02:02:11 PM PDT 24
Peak memory 205396 kb
Host smart-dd30c3d3-0e81-411f-8b4e-b67f187fa2d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963557646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1963557646
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3710959606
Short name T684
Test name
Test status
Simulation time 65333913 ps
CPU time 2.12 seconds
Started Jun 04 02:02:09 PM PDT 24
Finished Jun 04 02:02:12 PM PDT 24
Peak memory 218724 kb
Host smart-c34fae0f-92d4-4056-8719-34a257498360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710959606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3710959606
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.285538505
Short name T79
Test name
Test status
Simulation time 16191441 ps
CPU time 0.78 seconds
Started Jun 04 02:02:07 PM PDT 24
Finished Jun 04 02:02:09 PM PDT 24
Peak memory 206456 kb
Host smart-13d25264-6989-43d9-8280-d09994e434b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285538505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.285538505
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.731367165
Short name T320
Test name
Test status
Simulation time 28795782489 ps
CPU time 107.16 seconds
Started Jun 04 02:02:09 PM PDT 24
Finished Jun 04 02:03:57 PM PDT 24
Peak memory 239420 kb
Host smart-9e1f22d2-929b-48eb-96d8-a4a5780e23c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731367165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.731367165
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1592961162
Short name T351
Test name
Test status
Simulation time 356024265 ps
CPU time 5.98 seconds
Started Jun 04 02:02:10 PM PDT 24
Finished Jun 04 02:02:17 PM PDT 24
Peak memory 240760 kb
Host smart-33775a28-ddf2-405f-8e83-084eb932c7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592961162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1592961162
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2630933346
Short name T221
Test name
Test status
Simulation time 1281955475 ps
CPU time 3.79 seconds
Started Jun 04 02:02:08 PM PDT 24
Finished Jun 04 02:02:13 PM PDT 24
Peak memory 233988 kb
Host smart-0a6ce94f-981f-4581-bd13-56783d769ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630933346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2630933346
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1226384957
Short name T702
Test name
Test status
Simulation time 399571892 ps
CPU time 6.67 seconds
Started Jun 04 02:02:09 PM PDT 24
Finished Jun 04 02:02:17 PM PDT 24
Peak memory 226660 kb
Host smart-07d54b0e-152f-43d0-9215-4582d51715e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226384957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1226384957
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2814308418
Short name T692
Test name
Test status
Simulation time 427218819 ps
CPU time 2.15 seconds
Started Jun 04 02:02:07 PM PDT 24
Finished Jun 04 02:02:10 PM PDT 24
Peak memory 216068 kb
Host smart-98235506-3998-4d25-80ee-044067b0a380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814308418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2814308418
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1391441702
Short name T309
Test name
Test status
Simulation time 1610916749 ps
CPU time 7.15 seconds
Started Jun 04 02:02:08 PM PDT 24
Finished Jun 04 02:02:16 PM PDT 24
Peak memory 233668 kb
Host smart-4cf8281e-d42b-4252-be52-5200a464cb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391441702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1391441702
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1087358489
Short name T517
Test name
Test status
Simulation time 5014882283 ps
CPU time 7.97 seconds
Started Jun 04 02:02:09 PM PDT 24
Finished Jun 04 02:02:18 PM PDT 24
Peak memory 222936 kb
Host smart-4609c4ec-4a34-4e0b-868d-33a49d2c3074
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1087358489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1087358489
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.589634569
Short name T623
Test name
Test status
Simulation time 21302644002 ps
CPU time 31.67 seconds
Started Jun 04 02:02:08 PM PDT 24
Finished Jun 04 02:02:41 PM PDT 24
Peak memory 216300 kb
Host smart-0b508845-b6ed-413d-8137-dd22cc891ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589634569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.589634569
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2244807923
Short name T370
Test name
Test status
Simulation time 2474850328 ps
CPU time 11.71 seconds
Started Jun 04 02:02:07 PM PDT 24
Finished Jun 04 02:02:20 PM PDT 24
Peak memory 216164 kb
Host smart-92fc1050-f58b-4152-8a5d-113681ec003a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244807923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2244807923
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.883169741
Short name T928
Test name
Test status
Simulation time 120577540 ps
CPU time 1.6 seconds
Started Jun 04 02:02:06 PM PDT 24
Finished Jun 04 02:02:09 PM PDT 24
Peak memory 216152 kb
Host smart-7a5522b7-cab9-4fde-bc6e-ff6bb0df30df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883169741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.883169741
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3532896083
Short name T636
Test name
Test status
Simulation time 37862175 ps
CPU time 0.85 seconds
Started Jun 04 02:02:09 PM PDT 24
Finished Jun 04 02:02:11 PM PDT 24
Peak memory 205960 kb
Host smart-d866b4b9-4f46-4fdc-9247-2d7418726e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532896083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3532896083
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.303093610
Short name T842
Test name
Test status
Simulation time 35229158377 ps
CPU time 30.96 seconds
Started Jun 04 02:02:07 PM PDT 24
Finished Jun 04 02:02:39 PM PDT 24
Peak memory 245476 kb
Host smart-cc15bb31-950d-40d2-a146-42a7bb5a767e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303093610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.303093610
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1683325307
Short name T627
Test name
Test status
Simulation time 39175438 ps
CPU time 0.7 seconds
Started Jun 04 02:02:21 PM PDT 24
Finished Jun 04 02:02:22 PM PDT 24
Peak memory 204796 kb
Host smart-90a3d95b-8fdd-4196-8e39-dbb6fc2aff7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683325307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1683325307
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1108556936
Short name T647
Test name
Test status
Simulation time 192343016 ps
CPU time 3.45 seconds
Started Jun 04 02:02:19 PM PDT 24
Finished Jun 04 02:02:24 PM PDT 24
Peak memory 233948 kb
Host smart-03ce3877-d327-4e07-8eac-2995e8db7ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108556936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1108556936
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3972229817
Short name T559
Test name
Test status
Simulation time 18582188 ps
CPU time 0.79 seconds
Started Jun 04 02:02:08 PM PDT 24
Finished Jun 04 02:02:10 PM PDT 24
Peak memory 205400 kb
Host smart-e5f7317f-e3ae-41e7-8be3-4f946b8bd275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972229817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3972229817
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2079969984
Short name T366
Test name
Test status
Simulation time 59176539 ps
CPU time 0.94 seconds
Started Jun 04 02:02:20 PM PDT 24
Finished Jun 04 02:02:22 PM PDT 24
Peak memory 215892 kb
Host smart-2f659d5f-6f15-4c14-bd6a-2e02737abf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079969984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2079969984
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1424972940
Short name T933
Test name
Test status
Simulation time 8159178976 ps
CPU time 38.91 seconds
Started Jun 04 02:02:19 PM PDT 24
Finished Jun 04 02:02:59 PM PDT 24
Peak memory 240940 kb
Host smart-34fbe12e-1419-499a-9fbc-88081bc8431e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424972940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1424972940
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2633499374
Short name T211
Test name
Test status
Simulation time 5833686693 ps
CPU time 52.67 seconds
Started Jun 04 02:02:18 PM PDT 24
Finished Jun 04 02:03:12 PM PDT 24
Peak memory 251748 kb
Host smart-d466b1bf-e7ac-4d68-900b-59d3d9bd33e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633499374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2633499374
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3729291929
Short name T537
Test name
Test status
Simulation time 1276083886 ps
CPU time 5.21 seconds
Started Jun 04 02:02:19 PM PDT 24
Finished Jun 04 02:02:25 PM PDT 24
Peak memory 232540 kb
Host smart-b23713dc-0c2b-4b6b-8615-22bf0c446b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729291929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3729291929
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1483987934
Short name T860
Test name
Test status
Simulation time 2393836187 ps
CPU time 13.44 seconds
Started Jun 04 02:02:20 PM PDT 24
Finished Jun 04 02:02:35 PM PDT 24
Peak memory 219456 kb
Host smart-ab6330e8-c6c6-455c-a729-d050a6955c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483987934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1483987934
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2812562213
Short name T506
Test name
Test status
Simulation time 15753317132 ps
CPU time 34.97 seconds
Started Jun 04 02:02:18 PM PDT 24
Finished Jun 04 02:02:54 PM PDT 24
Peak memory 233676 kb
Host smart-d0c79c70-3a82-47f1-be85-7ea1c5cace90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812562213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2812562213
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2957604837
Short name T724
Test name
Test status
Simulation time 502194657 ps
CPU time 3.34 seconds
Started Jun 04 02:02:18 PM PDT 24
Finished Jun 04 02:02:23 PM PDT 24
Peak memory 218768 kb
Host smart-e0b0602e-36af-4d0b-9e8f-ce865da6d185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957604837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2957604837
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.611210871
Short name T807
Test name
Test status
Simulation time 1843143220 ps
CPU time 8.13 seconds
Started Jun 04 02:02:21 PM PDT 24
Finished Jun 04 02:02:30 PM PDT 24
Peak memory 221076 kb
Host smart-41eb5020-7562-4273-aed6-f6b546e41efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611210871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.611210871
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3489432126
Short name T777
Test name
Test status
Simulation time 3448638599 ps
CPU time 5.28 seconds
Started Jun 04 02:02:21 PM PDT 24
Finished Jun 04 02:02:27 PM PDT 24
Peak memory 222976 kb
Host smart-952965e7-86c3-4a59-b9d4-c46714ba4a79
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3489432126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3489432126
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2977728653
Short name T721
Test name
Test status
Simulation time 57118964 ps
CPU time 0.7 seconds
Started Jun 04 02:02:09 PM PDT 24
Finished Jun 04 02:02:11 PM PDT 24
Peak memory 205528 kb
Host smart-48a4a802-693c-4aa4-82ab-65a83541c7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977728653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2977728653
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.469129858
Short name T748
Test name
Test status
Simulation time 2392635144 ps
CPU time 6.97 seconds
Started Jun 04 02:02:11 PM PDT 24
Finished Jun 04 02:02:19 PM PDT 24
Peak memory 216180 kb
Host smart-1f9f1059-af33-4fe6-bed9-703bd0013291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469129858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.469129858
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2215174697
Short name T961
Test name
Test status
Simulation time 80960687 ps
CPU time 0.87 seconds
Started Jun 04 02:02:18 PM PDT 24
Finished Jun 04 02:02:20 PM PDT 24
Peak memory 206436 kb
Host smart-bbf9375b-f463-437b-a3c3-bc5e74fef383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215174697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2215174697
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2583431889
Short name T80
Test name
Test status
Simulation time 94294010 ps
CPU time 0.7 seconds
Started Jun 04 02:02:08 PM PDT 24
Finished Jun 04 02:02:10 PM PDT 24
Peak memory 205480 kb
Host smart-93d7ac80-ca02-4575-9828-36a44d3c7f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583431889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2583431889
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1739879463
Short name T550
Test name
Test status
Simulation time 19224010669 ps
CPU time 18.93 seconds
Started Jun 04 02:02:20 PM PDT 24
Finished Jun 04 02:02:40 PM PDT 24
Peak memory 243080 kb
Host smart-2e4a1141-6f7d-4d49-a596-620423183e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739879463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1739879463
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1950291226
Short name T698
Test name
Test status
Simulation time 55698178 ps
CPU time 0.71 seconds
Started Jun 04 02:02:18 PM PDT 24
Finished Jun 04 02:02:19 PM PDT 24
Peak memory 205344 kb
Host smart-b043a45c-441d-4f78-88e2-fa41fddaf23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950291226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1950291226
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2493586155
Short name T893
Test name
Test status
Simulation time 656257785 ps
CPU time 8.77 seconds
Started Jun 04 02:02:18 PM PDT 24
Finished Jun 04 02:02:27 PM PDT 24
Peak memory 234372 kb
Host smart-f4dbc4cf-ae4b-44a0-931b-fba86b2dc650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493586155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2493586155
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3429984953
Short name T800
Test name
Test status
Simulation time 26958705 ps
CPU time 0.82 seconds
Started Jun 04 02:02:18 PM PDT 24
Finished Jun 04 02:02:20 PM PDT 24
Peak memory 205380 kb
Host smart-4b1d45f3-d913-410d-af74-efb9e66fe82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429984953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3429984953
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1029973184
Short name T477
Test name
Test status
Simulation time 34000309427 ps
CPU time 149.51 seconds
Started Jun 04 02:02:21 PM PDT 24
Finished Jun 04 02:04:52 PM PDT 24
Peak memory 249076 kb
Host smart-7ebb1837-a262-4c1f-8d0c-d0f3ca00c898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029973184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1029973184
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3907826272
Short name T670
Test name
Test status
Simulation time 9495871378 ps
CPU time 59.73 seconds
Started Jun 04 02:02:19 PM PDT 24
Finished Jun 04 02:03:20 PM PDT 24
Peak memory 249116 kb
Host smart-004d1c46-2600-4544-946b-00992f6f5086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907826272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3907826272
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.438699539
Short name T423
Test name
Test status
Simulation time 41867416578 ps
CPU time 24.69 seconds
Started Jun 04 02:02:20 PM PDT 24
Finished Jun 04 02:02:46 PM PDT 24
Peak memory 217084 kb
Host smart-fb079c08-4da1-42c9-9aa6-91573b2b463c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438699539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.438699539
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.694681490
Short name T610
Test name
Test status
Simulation time 2772365269 ps
CPU time 30.94 seconds
Started Jun 04 02:02:19 PM PDT 24
Finished Jun 04 02:02:52 PM PDT 24
Peak memory 232592 kb
Host smart-7a56dce2-5e47-4d75-a229-6d6ea9320c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694681490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.694681490
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1550038914
Short name T410
Test name
Test status
Simulation time 32905529977 ps
CPU time 27.36 seconds
Started Jun 04 02:02:21 PM PDT 24
Finished Jun 04 02:02:49 PM PDT 24
Peak memory 220612 kb
Host smart-1378488f-e193-42d0-8630-b75ce146c56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550038914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1550038914
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.60137820
Short name T900
Test name
Test status
Simulation time 24877875587 ps
CPU time 55.39 seconds
Started Jun 04 02:02:20 PM PDT 24
Finished Jun 04 02:03:17 PM PDT 24
Peak memory 235384 kb
Host smart-6047b7c7-f9eb-4083-bba7-13638620660c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60137820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.60137820
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3719550263
Short name T192
Test name
Test status
Simulation time 3617711491 ps
CPU time 13.4 seconds
Started Jun 04 02:02:19 PM PDT 24
Finished Jun 04 02:02:33 PM PDT 24
Peak memory 233564 kb
Host smart-3e7dcb40-49db-46fe-9be2-7e6253a315e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719550263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3719550263
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3522603393
Short name T397
Test name
Test status
Simulation time 103457997 ps
CPU time 2.34 seconds
Started Jun 04 02:02:19 PM PDT 24
Finished Jun 04 02:02:23 PM PDT 24
Peak memory 215876 kb
Host smart-23741d50-3b66-4fbe-9c26-96993aacf139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522603393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3522603393
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3758447456
Short name T607
Test name
Test status
Simulation time 335641212 ps
CPU time 4 seconds
Started Jun 04 02:02:20 PM PDT 24
Finished Jun 04 02:02:25 PM PDT 24
Peak memory 222844 kb
Host smart-c5660863-9ddf-451b-bd85-abe7e8669b6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3758447456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3758447456
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1191251964
Short name T894
Test name
Test status
Simulation time 34148413003 ps
CPU time 232.61 seconds
Started Jun 04 02:02:19 PM PDT 24
Finished Jun 04 02:06:13 PM PDT 24
Peak memory 248952 kb
Host smart-87326bab-650f-4e2f-b3db-e81b17a84294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191251964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1191251964
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2349348504
Short name T776
Test name
Test status
Simulation time 27719951210 ps
CPU time 40.04 seconds
Started Jun 04 02:02:22 PM PDT 24
Finished Jun 04 02:03:03 PM PDT 24
Peak memory 216208 kb
Host smart-7fe62120-3e9d-44ee-b0bd-e44c28f312f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349348504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2349348504
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2305363260
Short name T589
Test name
Test status
Simulation time 7530535314 ps
CPU time 19.27 seconds
Started Jun 04 02:02:20 PM PDT 24
Finished Jun 04 02:02:40 PM PDT 24
Peak memory 216064 kb
Host smart-7e91fc6a-c9f3-48e3-b39c-9d01a16f26bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305363260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2305363260
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.131264709
Short name T745
Test name
Test status
Simulation time 47041734 ps
CPU time 1.2 seconds
Started Jun 04 02:02:19 PM PDT 24
Finished Jun 04 02:02:22 PM PDT 24
Peak memory 207968 kb
Host smart-f8e38864-9147-4726-b317-22dc7593ce85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131264709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.131264709
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4203714489
Short name T775
Test name
Test status
Simulation time 47049242 ps
CPU time 0.81 seconds
Started Jun 04 02:02:22 PM PDT 24
Finished Jun 04 02:02:24 PM PDT 24
Peak memory 205584 kb
Host smart-407ed5f8-2213-40cd-a4e5-d0763020fe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203714489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4203714489
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2373417370
Short name T135
Test name
Test status
Simulation time 393301175 ps
CPU time 2.5 seconds
Started Jun 04 02:02:20 PM PDT 24
Finished Jun 04 02:02:24 PM PDT 24
Peak memory 218564 kb
Host smart-5954aac5-a83f-49ed-a7c1-9af206c7eec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373417370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2373417370
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3959424866
Short name T510
Test name
Test status
Simulation time 14711521 ps
CPU time 0.7 seconds
Started Jun 04 02:01:27 PM PDT 24
Finished Jun 04 02:01:29 PM PDT 24
Peak memory 204840 kb
Host smart-b02e547c-869d-4c82-bd34-88798a52db7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959424866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
959424866
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2947155686
Short name T322
Test name
Test status
Simulation time 121636402 ps
CPU time 2.38 seconds
Started Jun 04 02:01:21 PM PDT 24
Finished Jun 04 02:01:25 PM PDT 24
Peak memory 233588 kb
Host smart-35617278-945a-4ab9-9f20-319ad490d864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947155686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2947155686
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.319173449
Short name T908
Test name
Test status
Simulation time 13246686 ps
CPU time 0.77 seconds
Started Jun 04 02:01:34 PM PDT 24
Finished Jun 04 02:01:36 PM PDT 24
Peak memory 206388 kb
Host smart-14abd6a5-9ddc-4e0b-bd70-3178e1fa10ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319173449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.319173449
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1305930488
Short name T754
Test name
Test status
Simulation time 44549993705 ps
CPU time 357.73 seconds
Started Jun 04 02:01:24 PM PDT 24
Finished Jun 04 02:07:22 PM PDT 24
Peak memory 259800 kb
Host smart-5c6f6bf2-a09c-4e96-96a5-50aa7f92c1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305930488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1305930488
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3330291406
Short name T311
Test name
Test status
Simulation time 3705167665 ps
CPU time 58.54 seconds
Started Jun 04 02:01:21 PM PDT 24
Finished Jun 04 02:02:21 PM PDT 24
Peak memory 249920 kb
Host smart-21b978de-67b4-405d-b827-7fb7b71e582e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330291406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3330291406
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1722351686
Short name T567
Test name
Test status
Simulation time 144228777 ps
CPU time 2.46 seconds
Started Jun 04 02:01:19 PM PDT 24
Finished Jun 04 02:01:23 PM PDT 24
Peak memory 232532 kb
Host smart-2c3d03c2-f4fb-42cf-866b-3e683abaf4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722351686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1722351686
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1039556182
Short name T232
Test name
Test status
Simulation time 2710469068 ps
CPU time 13.23 seconds
Started Jun 04 02:01:23 PM PDT 24
Finished Jun 04 02:01:37 PM PDT 24
Peak memory 218268 kb
Host smart-ecc67184-9cb7-4736-85d4-119108b55d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039556182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1039556182
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2341151738
Short name T37
Test name
Test status
Simulation time 1653497270 ps
CPU time 15.87 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:01:38 PM PDT 24
Peak memory 234224 kb
Host smart-880a9f60-3b61-431e-b15d-c6572775a4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341151738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2341151738
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1391801747
Short name T257
Test name
Test status
Simulation time 14583631089 ps
CPU time 7.08 seconds
Started Jun 04 02:01:21 PM PDT 24
Finished Jun 04 02:01:30 PM PDT 24
Peak memory 218460 kb
Host smart-e2b59e56-0837-4a76-804c-e0f7dad3fd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391801747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1391801747
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2861223101
Short name T729
Test name
Test status
Simulation time 483124002 ps
CPU time 2.39 seconds
Started Jun 04 02:01:23 PM PDT 24
Finished Jun 04 02:01:26 PM PDT 24
Peak memory 224308 kb
Host smart-3aa043bb-6b9d-43ad-b41c-03eee8536588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861223101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2861223101
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.293376018
Short name T626
Test name
Test status
Simulation time 1357509578 ps
CPU time 15.81 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:01:38 PM PDT 24
Peak memory 219896 kb
Host smart-4af94ee4-f14b-4bfb-9959-df155587b879
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=293376018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.293376018
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1000307629
Short name T68
Test name
Test status
Simulation time 96804209 ps
CPU time 1.2 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:01:23 PM PDT 24
Peak memory 236728 kb
Host smart-abe23fad-ac69-4341-9cea-6e23e12d0aa3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000307629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1000307629
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2591769450
Short name T43
Test name
Test status
Simulation time 14819064586 ps
CPU time 31.1 seconds
Started Jun 04 02:01:21 PM PDT 24
Finished Jun 04 02:01:53 PM PDT 24
Peak memory 216472 kb
Host smart-e1624521-6df3-4c51-a497-d202718990c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591769450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2591769450
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4178922238
Short name T378
Test name
Test status
Simulation time 2956308864 ps
CPU time 8.75 seconds
Started Jun 04 02:01:33 PM PDT 24
Finished Jun 04 02:01:42 PM PDT 24
Peak memory 216120 kb
Host smart-bec4db07-8d91-45d2-9943-c1ca3fa4ddf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178922238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4178922238
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2036929157
Short name T870
Test name
Test status
Simulation time 192718795 ps
CPU time 6.06 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:01:28 PM PDT 24
Peak memory 216132 kb
Host smart-a325630a-960d-4aa4-bd24-1f1f428ea9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036929157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2036929157
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4208923144
Short name T687
Test name
Test status
Simulation time 43138637 ps
CPU time 0.68 seconds
Started Jun 04 02:01:20 PM PDT 24
Finished Jun 04 02:01:23 PM PDT 24
Peak memory 205620 kb
Host smart-c8ccd14e-1109-4301-96fa-da29bc63f62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208923144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4208923144
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3972520629
Short name T336
Test name
Test status
Simulation time 17569391615 ps
CPU time 15.01 seconds
Started Jun 04 02:01:22 PM PDT 24
Finished Jun 04 02:01:38 PM PDT 24
Peak memory 234592 kb
Host smart-49d47d84-329f-4f9b-a9e1-d416e3b0c0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972520629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3972520629
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3342478461
Short name T882
Test name
Test status
Simulation time 19640960 ps
CPU time 0.69 seconds
Started Jun 04 02:02:34 PM PDT 24
Finished Jun 04 02:02:36 PM PDT 24
Peak memory 205396 kb
Host smart-76c5b764-e75f-4338-b451-8ffd744435d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342478461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3342478461
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3723196431
Short name T364
Test name
Test status
Simulation time 1319363272 ps
CPU time 13.19 seconds
Started Jun 04 02:02:21 PM PDT 24
Finished Jun 04 02:02:35 PM PDT 24
Peak memory 234316 kb
Host smart-e616f805-6c77-44b7-a60b-f3578eed6d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723196431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3723196431
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.801267632
Short name T375
Test name
Test status
Simulation time 19274381 ps
CPU time 0.94 seconds
Started Jun 04 02:02:22 PM PDT 24
Finished Jun 04 02:02:24 PM PDT 24
Peak memory 206676 kb
Host smart-c17e1523-0d87-4a80-a06b-e16bb0dc1281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801267632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.801267632
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.400277374
Short name T308
Test name
Test status
Simulation time 42086348403 ps
CPU time 144.75 seconds
Started Jun 04 02:02:31 PM PDT 24
Finished Jun 04 02:04:56 PM PDT 24
Peak memory 249068 kb
Host smart-ea3a785b-8f76-4d4b-8614-e9d7cac6bd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400277374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.400277374
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2104256976
Short name T736
Test name
Test status
Simulation time 18527864423 ps
CPU time 167.62 seconds
Started Jun 04 02:02:35 PM PDT 24
Finished Jun 04 02:05:25 PM PDT 24
Peak memory 249092 kb
Host smart-0533bae5-9c28-40ce-af92-1c6e59ad57c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104256976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2104256976
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2092650664
Short name T534
Test name
Test status
Simulation time 81574149 ps
CPU time 3.01 seconds
Started Jun 04 02:02:34 PM PDT 24
Finished Jun 04 02:02:39 PM PDT 24
Peak memory 232592 kb
Host smart-978b1543-0277-467c-be9f-99f4c1655468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092650664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2092650664
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1976240554
Short name T678
Test name
Test status
Simulation time 138553454 ps
CPU time 2.28 seconds
Started Jun 04 02:02:18 PM PDT 24
Finished Jun 04 02:02:21 PM PDT 24
Peak memory 220720 kb
Host smart-71c83b6f-af11-4f60-a1c3-ee72734ebf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976240554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1976240554
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.580337348
Short name T673
Test name
Test status
Simulation time 12809349895 ps
CPU time 46.44 seconds
Started Jun 04 02:02:20 PM PDT 24
Finished Jun 04 02:03:07 PM PDT 24
Peak memory 222372 kb
Host smart-d392720e-4a76-479e-ba9a-500013a9c7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580337348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.580337348
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1192803962
Short name T398
Test name
Test status
Simulation time 55268299 ps
CPU time 2.1 seconds
Started Jun 04 02:02:19 PM PDT 24
Finished Jun 04 02:02:22 PM PDT 24
Peak memory 218584 kb
Host smart-1ebc1d0d-97e9-4a00-bd55-e5afb4fbf5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192803962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1192803962
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1961127112
Short name T817
Test name
Test status
Simulation time 143572414 ps
CPU time 3.62 seconds
Started Jun 04 02:02:20 PM PDT 24
Finished Jun 04 02:02:25 PM PDT 24
Peak memory 234656 kb
Host smart-985b9ac2-0865-417d-aad3-6b30aa4503cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961127112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1961127112
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.798613068
Short name T400
Test name
Test status
Simulation time 1190041020 ps
CPU time 12.37 seconds
Started Jun 04 02:02:32 PM PDT 24
Finished Jun 04 02:02:45 PM PDT 24
Peak memory 222792 kb
Host smart-094b5769-9a4f-4ff6-84a0-94a452a34ba1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=798613068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.798613068
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.4075200816
Short name T693
Test name
Test status
Simulation time 89965320 ps
CPU time 1.02 seconds
Started Jun 04 02:02:34 PM PDT 24
Finished Jun 04 02:02:37 PM PDT 24
Peak memory 207056 kb
Host smart-0365b4c2-63a0-4e39-8e71-dda5fd26b81b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075200816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.4075200816
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.852799084
Short name T382
Test name
Test status
Simulation time 621770634 ps
CPU time 3.99 seconds
Started Jun 04 02:02:19 PM PDT 24
Finished Jun 04 02:02:24 PM PDT 24
Peak memory 216200 kb
Host smart-1c0f779a-b944-4544-9c60-0a9012ea132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852799084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.852799084
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1248846552
Short name T444
Test name
Test status
Simulation time 4518838296 ps
CPU time 13.24 seconds
Started Jun 04 02:02:20 PM PDT 24
Finished Jun 04 02:02:35 PM PDT 24
Peak memory 216228 kb
Host smart-07cf24f9-bd01-4b07-9411-d54540503a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248846552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1248846552
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.233321634
Short name T914
Test name
Test status
Simulation time 108222380 ps
CPU time 0.84 seconds
Started Jun 04 02:02:20 PM PDT 24
Finished Jun 04 02:02:22 PM PDT 24
Peak memory 205732 kb
Host smart-653d0f01-1e41-4c91-a2d0-4414c9ea7caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233321634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.233321634
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1264878835
Short name T802
Test name
Test status
Simulation time 431826261 ps
CPU time 1.02 seconds
Started Jun 04 02:02:18 PM PDT 24
Finished Jun 04 02:02:19 PM PDT 24
Peak memory 206700 kb
Host smart-11eb2742-216c-4bc6-8a8e-f7b27a05f467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264878835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1264878835
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3521018881
Short name T838
Test name
Test status
Simulation time 4416250951 ps
CPU time 8.63 seconds
Started Jun 04 02:02:17 PM PDT 24
Finished Jun 04 02:02:26 PM PDT 24
Peak memory 216312 kb
Host smart-b665e8e3-3144-45f9-a716-e8648ff576de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521018881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3521018881
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2195782273
Short name T873
Test name
Test status
Simulation time 13147544 ps
CPU time 0.7 seconds
Started Jun 04 02:02:32 PM PDT 24
Finished Jun 04 02:02:33 PM PDT 24
Peak memory 204724 kb
Host smart-5d0b983b-f498-483c-a7ab-739d017a058e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195782273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2195782273
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2376661681
Short name T511
Test name
Test status
Simulation time 159305110 ps
CPU time 2.49 seconds
Started Jun 04 02:02:34 PM PDT 24
Finished Jun 04 02:02:38 PM PDT 24
Peak memory 218360 kb
Host smart-dfeb245a-ce2b-4961-96f1-807fe3e95e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376661681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2376661681
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3790313967
Short name T719
Test name
Test status
Simulation time 37205612 ps
CPU time 0.78 seconds
Started Jun 04 02:02:32 PM PDT 24
Finished Jun 04 02:02:34 PM PDT 24
Peak memory 206364 kb
Host smart-99c9e9a0-41f8-4739-ba76-0b55c92d0e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790313967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3790313967
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3289547691
Short name T191
Test name
Test status
Simulation time 167133693260 ps
CPU time 248.38 seconds
Started Jun 04 02:02:32 PM PDT 24
Finished Jun 04 02:06:42 PM PDT 24
Peak memory 251116 kb
Host smart-958487e8-af9f-42d9-bbfd-15af96751c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289547691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3289547691
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1420836380
Short name T725
Test name
Test status
Simulation time 10442710500 ps
CPU time 61.3 seconds
Started Jun 04 02:02:30 PM PDT 24
Finished Jun 04 02:03:32 PM PDT 24
Peak memory 250420 kb
Host smart-eb2ccbc4-2b67-4b30-bf29-622c4818ba40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420836380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1420836380
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2572006799
Short name T369
Test name
Test status
Simulation time 258809810 ps
CPU time 6.09 seconds
Started Jun 04 02:02:35 PM PDT 24
Finished Jun 04 02:02:43 PM PDT 24
Peak memory 224340 kb
Host smart-a1f59f47-1edd-4854-bb7f-054380121fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572006799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2572006799
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2894576539
Short name T831
Test name
Test status
Simulation time 2571671706 ps
CPU time 4.27 seconds
Started Jun 04 02:02:37 PM PDT 24
Finished Jun 04 02:02:43 PM PDT 24
Peak memory 216320 kb
Host smart-788a0f57-1b5b-4f90-a56d-6846f424ab00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894576539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2894576539
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3071358939
Short name T302
Test name
Test status
Simulation time 1852428572 ps
CPU time 16.35 seconds
Started Jun 04 02:02:31 PM PDT 24
Finished Jun 04 02:02:48 PM PDT 24
Peak memory 232156 kb
Host smart-8c866fc9-0bf1-4081-8dab-2bcaa49f68b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071358939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3071358939
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1962415142
Short name T611
Test name
Test status
Simulation time 3564929944 ps
CPU time 5.82 seconds
Started Jun 04 02:02:32 PM PDT 24
Finished Jun 04 02:02:39 PM PDT 24
Peak memory 221860 kb
Host smart-01726263-4e47-4f78-aa49-9863d2037a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962415142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1962415142
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.83003110
Short name T475
Test name
Test status
Simulation time 4305247415 ps
CPU time 13.63 seconds
Started Jun 04 02:02:34 PM PDT 24
Finished Jun 04 02:02:49 PM PDT 24
Peak memory 220404 kb
Host smart-4ef9d4c2-96b3-475f-a9a7-4aa8e012aa04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=83003110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direc
t.83003110
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.4145813394
Short name T23
Test name
Test status
Simulation time 81785655768 ps
CPU time 189.67 seconds
Started Jun 04 02:02:32 PM PDT 24
Finished Jun 04 02:05:43 PM PDT 24
Peak memory 249124 kb
Host smart-1deb7399-63a7-498c-81fa-e4b61c1a3a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145813394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.4145813394
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2731429097
Short name T651
Test name
Test status
Simulation time 490800630 ps
CPU time 3.46 seconds
Started Jun 04 02:02:36 PM PDT 24
Finished Jun 04 02:02:42 PM PDT 24
Peak memory 216108 kb
Host smart-9b7ed799-a342-47f9-9275-ea32bf9fe072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731429097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2731429097
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.80015454
Short name T593
Test name
Test status
Simulation time 19128917 ps
CPU time 0.68 seconds
Started Jun 04 02:02:35 PM PDT 24
Finished Jun 04 02:02:38 PM PDT 24
Peak memory 205492 kb
Host smart-8a7c919d-5f82-4113-9bb3-7cd0660372ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80015454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.80015454
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3887444655
Short name T804
Test name
Test status
Simulation time 415505730 ps
CPU time 4.71 seconds
Started Jun 04 02:02:34 PM PDT 24
Finished Jun 04 02:02:40 PM PDT 24
Peak memory 216192 kb
Host smart-45aa47fe-a14d-461c-9c2b-88d654bf9f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887444655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3887444655
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.326296760
Short name T585
Test name
Test status
Simulation time 87780954 ps
CPU time 0.93 seconds
Started Jun 04 02:02:33 PM PDT 24
Finished Jun 04 02:02:35 PM PDT 24
Peak memory 206072 kb
Host smart-a797ca39-5209-4860-a36d-8b4840b4893d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326296760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.326296760
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1506580302
Short name T619
Test name
Test status
Simulation time 29632233851 ps
CPU time 17.36 seconds
Started Jun 04 02:02:32 PM PDT 24
Finished Jun 04 02:02:51 PM PDT 24
Peak memory 217624 kb
Host smart-caf20a6d-d9c9-43ce-8981-91bda615b966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506580302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1506580302
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3639958335
Short name T898
Test name
Test status
Simulation time 11776024 ps
CPU time 0.71 seconds
Started Jun 04 02:02:31 PM PDT 24
Finished Jun 04 02:02:32 PM PDT 24
Peak memory 205652 kb
Host smart-4baa1d36-237f-477b-bf45-84ccb16c411d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639958335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3639958335
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.496466165
Short name T682
Test name
Test status
Simulation time 430204784 ps
CPU time 3.3 seconds
Started Jun 04 02:02:33 PM PDT 24
Finished Jun 04 02:02:37 PM PDT 24
Peak memory 234884 kb
Host smart-5e628130-0e4e-4774-9dfd-7165cd306bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496466165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.496466165
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.448301055
Short name T549
Test name
Test status
Simulation time 36910194 ps
CPU time 0.75 seconds
Started Jun 04 02:02:33 PM PDT 24
Finished Jun 04 02:02:35 PM PDT 24
Peak memory 205336 kb
Host smart-564d2f67-cf32-476d-a698-1943e0524ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448301055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.448301055
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1613488049
Short name T786
Test name
Test status
Simulation time 9242194753 ps
CPU time 42.6 seconds
Started Jun 04 02:02:35 PM PDT 24
Finished Jun 04 02:03:19 PM PDT 24
Peak memory 249016 kb
Host smart-2a8e946f-024b-4fb7-baab-fd27ffcda7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613488049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1613488049
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.273529376
Short name T767
Test name
Test status
Simulation time 44306896890 ps
CPU time 412.66 seconds
Started Jun 04 02:02:33 PM PDT 24
Finished Jun 04 02:09:27 PM PDT 24
Peak memory 253260 kb
Host smart-384d3336-2a43-4f57-9baa-b64e92fa5a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273529376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.273529376
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3387358341
Short name T347
Test name
Test status
Simulation time 1913973813 ps
CPU time 11.99 seconds
Started Jun 04 02:02:31 PM PDT 24
Finished Jun 04 02:02:44 PM PDT 24
Peak memory 232504 kb
Host smart-56ec303e-00c0-4786-b6f4-f3cb10a35cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387358341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3387358341
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.636012061
Short name T40
Test name
Test status
Simulation time 110663374 ps
CPU time 2.1 seconds
Started Jun 04 02:02:33 PM PDT 24
Finished Jun 04 02:02:37 PM PDT 24
Peak memory 217580 kb
Host smart-b1091ca9-e89d-46c9-8fbd-9df999758d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636012061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.636012061
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4097153197
Short name T570
Test name
Test status
Simulation time 160210980 ps
CPU time 3.71 seconds
Started Jun 04 02:02:32 PM PDT 24
Finished Jun 04 02:02:37 PM PDT 24
Peak memory 224408 kb
Host smart-2b42d7f7-f959-41fa-be7b-819d492bb6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097153197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4097153197
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2083134501
Short name T629
Test name
Test status
Simulation time 3174598275 ps
CPU time 6.98 seconds
Started Jun 04 02:02:31 PM PDT 24
Finished Jun 04 02:02:38 PM PDT 24
Peak memory 235496 kb
Host smart-bcd9fab1-e042-4e94-838a-da940cd1db8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083134501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2083134501
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3039332471
Short name T740
Test name
Test status
Simulation time 18232797309 ps
CPU time 17.22 seconds
Started Jun 04 02:02:33 PM PDT 24
Finished Jun 04 02:02:51 PM PDT 24
Peak memory 249796 kb
Host smart-2be3b154-3fe0-4e0d-8f30-26989b8956ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039332471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3039332471
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2971765652
Short name T445
Test name
Test status
Simulation time 456021700 ps
CPU time 5.56 seconds
Started Jun 04 02:02:32 PM PDT 24
Finished Jun 04 02:02:39 PM PDT 24
Peak memory 218940 kb
Host smart-3cda969e-c4f5-4f0f-9598-ed50c9347884
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2971765652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2971765652
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.180442653
Short name T879
Test name
Test status
Simulation time 18873232168 ps
CPU time 45.31 seconds
Started Jun 04 02:02:33 PM PDT 24
Finished Jun 04 02:03:20 PM PDT 24
Peak memory 239296 kb
Host smart-97fc1677-52ef-4775-8e65-aec3b6bafa8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180442653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.180442653
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4086828837
Short name T409
Test name
Test status
Simulation time 10572501173 ps
CPU time 17.23 seconds
Started Jun 04 02:02:33 PM PDT 24
Finished Jun 04 02:02:51 PM PDT 24
Peak memory 216288 kb
Host smart-2c49efef-b507-4bb7-9aff-5251518feca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086828837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4086828837
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2161747333
Short name T640
Test name
Test status
Simulation time 727305930 ps
CPU time 4.29 seconds
Started Jun 04 02:02:36 PM PDT 24
Finished Jun 04 02:02:42 PM PDT 24
Peak memory 216160 kb
Host smart-b7a922f6-1c25-4a98-ba0e-a67b3c56a189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161747333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2161747333
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3217154816
Short name T480
Test name
Test status
Simulation time 83615347 ps
CPU time 0.99 seconds
Started Jun 04 02:02:29 PM PDT 24
Finished Jun 04 02:02:31 PM PDT 24
Peak memory 207316 kb
Host smart-82b075fb-572d-4544-91e3-9e9f2b73bb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217154816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3217154816
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2409282806
Short name T488
Test name
Test status
Simulation time 14978272 ps
CPU time 0.74 seconds
Started Jun 04 02:02:36 PM PDT 24
Finished Jun 04 02:02:39 PM PDT 24
Peak memory 205556 kb
Host smart-20c57279-7a2f-4430-b469-0bc00b8d3b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409282806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2409282806
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1154222855
Short name T188
Test name
Test status
Simulation time 9966338735 ps
CPU time 19.66 seconds
Started Jun 04 02:02:36 PM PDT 24
Finished Jun 04 02:02:57 PM PDT 24
Peak memory 240764 kb
Host smart-d94adfa9-d8c9-4b67-92e0-8f0cb1c960fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154222855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1154222855
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4041247577
Short name T386
Test name
Test status
Simulation time 17680511 ps
CPU time 0.74 seconds
Started Jun 04 02:02:35 PM PDT 24
Finished Jun 04 02:02:38 PM PDT 24
Peak memory 205344 kb
Host smart-1ec74151-8ffa-4635-bef0-a808a8ebed77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041247577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4041247577
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3531183418
Short name T606
Test name
Test status
Simulation time 5895120592 ps
CPU time 16.33 seconds
Started Jun 04 02:02:40 PM PDT 24
Finished Jun 04 02:02:58 PM PDT 24
Peak memory 234100 kb
Host smart-c45734a7-243e-496d-a650-3cfe7e0391af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531183418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3531183418
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2086443339
Short name T405
Test name
Test status
Simulation time 31879027 ps
CPU time 0.78 seconds
Started Jun 04 02:02:35 PM PDT 24
Finished Jun 04 02:02:38 PM PDT 24
Peak memory 206420 kb
Host smart-c2085f16-a5d9-44e8-a90a-7327fb1dee39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086443339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2086443339
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.373327041
Short name T442
Test name
Test status
Simulation time 15276911277 ps
CPU time 61.46 seconds
Started Jun 04 02:02:41 PM PDT 24
Finished Jun 04 02:03:44 PM PDT 24
Peak memory 248800 kb
Host smart-a93ecc9d-41c1-4236-94a9-711680b12e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373327041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.373327041
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1179543090
Short name T261
Test name
Test status
Simulation time 88196796723 ps
CPU time 146.91 seconds
Started Jun 04 02:02:39 PM PDT 24
Finished Jun 04 02:05:07 PM PDT 24
Peak memory 224552 kb
Host smart-fb82ace9-dfe6-442b-b948-f55a2b2658f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179543090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1179543090
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1470821386
Short name T312
Test name
Test status
Simulation time 3785015947 ps
CPU time 34 seconds
Started Jun 04 02:02:38 PM PDT 24
Finished Jun 04 02:03:13 PM PDT 24
Peak memory 249016 kb
Host smart-6a5b9792-7617-494d-95c6-44bc9844c1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470821386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1470821386
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2509303063
Short name T401
Test name
Test status
Simulation time 854237814 ps
CPU time 6.6 seconds
Started Jun 04 02:02:41 PM PDT 24
Finished Jun 04 02:02:49 PM PDT 24
Peak memory 232612 kb
Host smart-af539545-bf25-4c79-aea8-017800966e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509303063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2509303063
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3514196933
Short name T38
Test name
Test status
Simulation time 655147662 ps
CPU time 4.37 seconds
Started Jun 04 02:02:33 PM PDT 24
Finished Jun 04 02:02:39 PM PDT 24
Peak memory 233448 kb
Host smart-809ee70c-6ad6-439c-bf16-5dcd09a37beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514196933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3514196933
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.449270265
Short name T792
Test name
Test status
Simulation time 942565133 ps
CPU time 8.43 seconds
Started Jun 04 02:02:33 PM PDT 24
Finished Jun 04 02:02:43 PM PDT 24
Peak memory 233404 kb
Host smart-b49f5e6f-6866-4c0e-b48e-89570be0598a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449270265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.449270265
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2690229568
Short name T906
Test name
Test status
Simulation time 175156574 ps
CPU time 3.56 seconds
Started Jun 04 02:02:32 PM PDT 24
Finished Jun 04 02:02:36 PM PDT 24
Peak memory 218456 kb
Host smart-fdee3fce-ff5c-4dd5-a818-e208fd800845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690229568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2690229568
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.401721935
Short name T902
Test name
Test status
Simulation time 30900641 ps
CPU time 1.83 seconds
Started Jun 04 02:02:36 PM PDT 24
Finished Jun 04 02:02:40 PM PDT 24
Peak memory 215980 kb
Host smart-040c1fc7-cda5-4b9c-a7c6-577d84e4ce5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401721935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.401721935
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2092866826
Short name T149
Test name
Test status
Simulation time 15579336653 ps
CPU time 18.27 seconds
Started Jun 04 02:02:34 PM PDT 24
Finished Jun 04 02:02:53 PM PDT 24
Peak memory 218916 kb
Host smart-38dfc7ab-126c-40cc-97a3-50cb256c1658
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2092866826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2092866826
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1649260460
Short name T216
Test name
Test status
Simulation time 131614026945 ps
CPU time 283.02 seconds
Started Jun 04 02:02:39 PM PDT 24
Finished Jun 04 02:07:24 PM PDT 24
Peak memory 256128 kb
Host smart-efb2175b-5fe1-4d38-8f58-67dc47772711
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649260460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1649260460
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1063713681
Short name T770
Test name
Test status
Simulation time 3016731761 ps
CPU time 29.05 seconds
Started Jun 04 02:02:35 PM PDT 24
Finished Jun 04 02:03:06 PM PDT 24
Peak memory 216216 kb
Host smart-87729a55-627c-412e-94b6-8e2f5ee67bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063713681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1063713681
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.702952582
Short name T714
Test name
Test status
Simulation time 1901427673 ps
CPU time 6.88 seconds
Started Jun 04 02:02:35 PM PDT 24
Finished Jun 04 02:02:44 PM PDT 24
Peak memory 216072 kb
Host smart-30f231c9-4f35-4a97-9d5e-6981eb3da09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702952582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.702952582
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3411875031
Short name T394
Test name
Test status
Simulation time 839215352 ps
CPU time 6.53 seconds
Started Jun 04 02:02:33 PM PDT 24
Finished Jun 04 02:02:41 PM PDT 24
Peak memory 216160 kb
Host smart-936c6856-d134-4ea6-be75-882589b0702c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411875031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3411875031
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.4128586999
Short name T555
Test name
Test status
Simulation time 86411247 ps
CPU time 0.96 seconds
Started Jun 04 02:02:34 PM PDT 24
Finished Jun 04 02:02:37 PM PDT 24
Peak memory 205628 kb
Host smart-1ec6d60c-29bd-4a1b-965b-272dd7a8e9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128586999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.4128586999
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.366783018
Short name T584
Test name
Test status
Simulation time 317136135 ps
CPU time 5.62 seconds
Started Jun 04 02:02:33 PM PDT 24
Finished Jun 04 02:02:40 PM PDT 24
Peak memory 234492 kb
Host smart-614e2205-05b2-416e-9382-0f481ea876da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366783018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.366783018
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2566651263
Short name T53
Test name
Test status
Simulation time 14308528 ps
CPU time 0.72 seconds
Started Jun 04 02:02:37 PM PDT 24
Finished Jun 04 02:02:40 PM PDT 24
Peak memory 205776 kb
Host smart-07c701fe-9eac-4d76-ba44-a4d7fc816548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566651263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2566651263
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1310825698
Short name T75
Test name
Test status
Simulation time 619098859 ps
CPU time 3.25 seconds
Started Jun 04 02:02:37 PM PDT 24
Finished Jun 04 02:02:42 PM PDT 24
Peak memory 219368 kb
Host smart-5ba72bba-9f81-473e-bfa5-a88b31f2e1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310825698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1310825698
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2053693489
Short name T917
Test name
Test status
Simulation time 19057797 ps
CPU time 0.77 seconds
Started Jun 04 02:02:34 PM PDT 24
Finished Jun 04 02:02:36 PM PDT 24
Peak memory 206392 kb
Host smart-3eef5bfe-c0ad-42d1-8037-a783412c1f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053693489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2053693489
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1827758749
Short name T255
Test name
Test status
Simulation time 7719616695 ps
CPU time 93.82 seconds
Started Jun 04 02:02:38 PM PDT 24
Finished Jun 04 02:04:14 PM PDT 24
Peak memory 257324 kb
Host smart-c86e35bc-7d09-48f2-88f7-37d9501bcd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827758749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1827758749
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4242640506
Short name T16
Test name
Test status
Simulation time 98264791569 ps
CPU time 74.06 seconds
Started Jun 04 02:02:37 PM PDT 24
Finished Jun 04 02:03:53 PM PDT 24
Peak memory 238920 kb
Host smart-d641f3f8-6343-491e-b50d-78fbda4b8325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242640506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4242640506
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3857189361
Short name T460
Test name
Test status
Simulation time 385430766 ps
CPU time 7.98 seconds
Started Jun 04 02:02:38 PM PDT 24
Finished Jun 04 02:02:48 PM PDT 24
Peak memory 224432 kb
Host smart-628b7a7b-646a-426d-91db-8e9e262a6476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857189361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3857189361
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2825570738
Short name T848
Test name
Test status
Simulation time 527056756 ps
CPU time 5.48 seconds
Started Jun 04 02:02:36 PM PDT 24
Finished Jun 04 02:02:43 PM PDT 24
Peak memory 218284 kb
Host smart-57d9d2f4-3c5f-481a-a6d1-0832d3f60e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825570738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2825570738
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.926138460
Short name T301
Test name
Test status
Simulation time 33350384083 ps
CPU time 79.5 seconds
Started Jun 04 02:02:35 PM PDT 24
Finished Jun 04 02:03:57 PM PDT 24
Peak memory 240828 kb
Host smart-87586e22-1894-4f6f-9654-6896cfe50e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926138460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.926138460
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1957225390
Short name T451
Test name
Test status
Simulation time 149298143607 ps
CPU time 32.46 seconds
Started Jun 04 02:02:37 PM PDT 24
Finished Jun 04 02:03:11 PM PDT 24
Peak memory 226028 kb
Host smart-5204e9b3-b347-4603-b583-78dc7d81e22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957225390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1957225390
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3592397857
Short name T591
Test name
Test status
Simulation time 5949731922 ps
CPU time 9.22 seconds
Started Jun 04 02:02:35 PM PDT 24
Finished Jun 04 02:02:46 PM PDT 24
Peak memory 245100 kb
Host smart-8a12d083-3c23-40e1-b23a-a9f17c4cf7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592397857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3592397857
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1395538551
Short name T490
Test name
Test status
Simulation time 451127394 ps
CPU time 4.77 seconds
Started Jun 04 02:02:41 PM PDT 24
Finished Jun 04 02:02:47 PM PDT 24
Peak memory 222148 kb
Host smart-37393698-9f68-4522-9b76-a7439cbda0da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1395538551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1395538551
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.24528149
Short name T45
Test name
Test status
Simulation time 35745698624 ps
CPU time 91.72 seconds
Started Jun 04 02:02:39 PM PDT 24
Finished Jun 04 02:04:12 PM PDT 24
Peak memory 238308 kb
Host smart-c8672bfe-7308-4f7e-b953-2915d1d90dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24528149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress
_all.24528149
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3679274893
Short name T512
Test name
Test status
Simulation time 4913236939 ps
CPU time 27.86 seconds
Started Jun 04 02:02:37 PM PDT 24
Finished Jun 04 02:03:06 PM PDT 24
Peak memory 216216 kb
Host smart-62b5c76c-c8fb-4b99-bb1a-7ea62d951da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679274893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3679274893
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2599855701
Short name T595
Test name
Test status
Simulation time 7904365580 ps
CPU time 13.79 seconds
Started Jun 04 02:02:36 PM PDT 24
Finished Jun 04 02:02:52 PM PDT 24
Peak memory 216164 kb
Host smart-38ec4da9-c721-4047-9183-8b596a5b7242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599855701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2599855701
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.602476584
Short name T911
Test name
Test status
Simulation time 548162779 ps
CPU time 8.7 seconds
Started Jun 04 02:02:36 PM PDT 24
Finished Jun 04 02:02:47 PM PDT 24
Peak memory 216148 kb
Host smart-d88ebda2-b3fd-44e6-be55-39b8c817ebf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602476584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.602476584
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1819001181
Short name T628
Test name
Test status
Simulation time 90475962 ps
CPU time 0.84 seconds
Started Jun 04 02:02:40 PM PDT 24
Finished Jun 04 02:02:42 PM PDT 24
Peak memory 205584 kb
Host smart-334169e6-9a44-45ad-9ead-200c69de80f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819001181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1819001181
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3076403484
Short name T733
Test name
Test status
Simulation time 1028028263 ps
CPU time 2.91 seconds
Started Jun 04 02:02:35 PM PDT 24
Finished Jun 04 02:02:40 PM PDT 24
Peak memory 216188 kb
Host smart-02d6ce09-58ee-46fc-9c49-2c0b260f9019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076403484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3076403484
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3430343279
Short name T896
Test name
Test status
Simulation time 53297091 ps
CPU time 0.7 seconds
Started Jun 04 02:02:39 PM PDT 24
Finished Jun 04 02:02:41 PM PDT 24
Peak memory 205672 kb
Host smart-20a6e961-34f4-484c-a46a-bf5d6dee2307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430343279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3430343279
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3831699408
Short name T516
Test name
Test status
Simulation time 408783011 ps
CPU time 2.31 seconds
Started Jun 04 02:02:40 PM PDT 24
Finished Jun 04 02:02:44 PM PDT 24
Peak memory 218532 kb
Host smart-14843765-d6dd-40fd-aea4-b36ccd59fd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831699408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3831699408
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3108210324
Short name T660
Test name
Test status
Simulation time 14057921 ps
CPU time 0.85 seconds
Started Jun 04 02:02:36 PM PDT 24
Finished Jun 04 02:02:39 PM PDT 24
Peak memory 206400 kb
Host smart-f6f563c8-3fcc-4954-9985-ad4c925b5665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108210324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3108210324
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1529721024
Short name T478
Test name
Test status
Simulation time 54365940 ps
CPU time 0.95 seconds
Started Jun 04 02:02:40 PM PDT 24
Finished Jun 04 02:02:42 PM PDT 24
Peak memory 215808 kb
Host smart-2f245bbd-6eb1-4d47-8daf-af2121423904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529721024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1529721024
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.4180080844
Short name T694
Test name
Test status
Simulation time 6657947593 ps
CPU time 45.04 seconds
Started Jun 04 02:02:35 PM PDT 24
Finished Jun 04 02:03:22 PM PDT 24
Peak memory 249080 kb
Host smart-8832d021-40c4-449b-b16d-8dcf737e9894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180080844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.4180080844
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.579182791
Short name T303
Test name
Test status
Simulation time 3419255726 ps
CPU time 17.17 seconds
Started Jun 04 02:02:40 PM PDT 24
Finished Jun 04 02:02:59 PM PDT 24
Peak memory 232516 kb
Host smart-b0b112db-927d-4acb-84d5-46d940dbf3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579182791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.579182791
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2655087261
Short name T655
Test name
Test status
Simulation time 1658694338 ps
CPU time 5.18 seconds
Started Jun 04 02:02:39 PM PDT 24
Finished Jun 04 02:02:46 PM PDT 24
Peak memory 234592 kb
Host smart-1422e0a8-b7dc-4f9a-ac33-7b465a583f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655087261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2655087261
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1874903943
Short name T227
Test name
Test status
Simulation time 177973936 ps
CPU time 2.61 seconds
Started Jun 04 02:02:39 PM PDT 24
Finished Jun 04 02:02:44 PM PDT 24
Peak memory 233712 kb
Host smart-901f1f44-7624-4c23-be25-fd1fc8d2029f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874903943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1874903943
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2650395712
Short name T504
Test name
Test status
Simulation time 1030319584 ps
CPU time 9.54 seconds
Started Jun 04 02:02:39 PM PDT 24
Finished Jun 04 02:02:50 PM PDT 24
Peak memory 237904 kb
Host smart-0dd2ecde-3bdd-4a55-aa4d-3b4352c02ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650395712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2650395712
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3578156346
Short name T855
Test name
Test status
Simulation time 233958803 ps
CPU time 2.71 seconds
Started Jun 04 02:02:41 PM PDT 24
Finished Jun 04 02:02:44 PM PDT 24
Peak memory 218568 kb
Host smart-f66a386b-d3b6-4e63-9a12-6145d0f0d2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578156346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3578156346
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3008763047
Short name T424
Test name
Test status
Simulation time 1702990442 ps
CPU time 11.21 seconds
Started Jun 04 02:02:43 PM PDT 24
Finished Jun 04 02:02:55 PM PDT 24
Peak memory 218720 kb
Host smart-3720fe6d-fdec-4ac4-a405-f32ab88e11d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3008763047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3008763047
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3528306683
Short name T440
Test name
Test status
Simulation time 80982392 ps
CPU time 1.15 seconds
Started Jun 04 02:02:38 PM PDT 24
Finished Jun 04 02:02:41 PM PDT 24
Peak memory 207212 kb
Host smart-9c86940b-5b16-4ac3-933a-02220b1d3450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528306683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3528306683
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4061681016
Short name T578
Test name
Test status
Simulation time 25737457852 ps
CPU time 21.47 seconds
Started Jun 04 02:02:36 PM PDT 24
Finished Jun 04 02:03:00 PM PDT 24
Peak memory 216228 kb
Host smart-f266d327-315d-4c74-8408-584505fd8ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061681016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4061681016
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1721308457
Short name T484
Test name
Test status
Simulation time 2070242027 ps
CPU time 2.4 seconds
Started Jun 04 02:02:36 PM PDT 24
Finished Jun 04 02:02:40 PM PDT 24
Peak memory 216144 kb
Host smart-ec5c35ca-43a7-4ee7-8078-eb131370f8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721308457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1721308457
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.242582343
Short name T384
Test name
Test status
Simulation time 747952898 ps
CPU time 13.43 seconds
Started Jun 04 02:02:36 PM PDT 24
Finished Jun 04 02:02:51 PM PDT 24
Peak memory 216216 kb
Host smart-ebe94659-5914-4d05-908b-cb60ecff7575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242582343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.242582343
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3167254420
Short name T487
Test name
Test status
Simulation time 21135801 ps
CPU time 0.78 seconds
Started Jun 04 02:02:39 PM PDT 24
Finished Jun 04 02:02:41 PM PDT 24
Peak memory 205588 kb
Host smart-fda15c79-4d12-4e1b-bc24-d306f547e793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167254420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3167254420
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3367516623
Short name T329
Test name
Test status
Simulation time 205077245 ps
CPU time 2.94 seconds
Started Jun 04 02:02:38 PM PDT 24
Finished Jun 04 02:02:42 PM PDT 24
Peak memory 235272 kb
Host smart-3025dda1-fe7b-4205-b85d-44dc2f684738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367516623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3367516623
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3686721295
Short name T609
Test name
Test status
Simulation time 12586697 ps
CPU time 0.71 seconds
Started Jun 04 02:02:51 PM PDT 24
Finished Jun 04 02:02:52 PM PDT 24
Peak memory 205716 kb
Host smart-d3f82c08-f425-4148-b338-521ac7759fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686721295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3686721295
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.94835627
Short name T778
Test name
Test status
Simulation time 1263414103 ps
CPU time 10.25 seconds
Started Jun 04 02:02:43 PM PDT 24
Finished Jun 04 02:02:54 PM PDT 24
Peak memory 233308 kb
Host smart-eb5b9695-60b2-4f2b-aa14-07fbb7f9e508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94835627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.94835627
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3527270134
Short name T416
Test name
Test status
Simulation time 38010026 ps
CPU time 0.74 seconds
Started Jun 04 02:02:45 PM PDT 24
Finished Jun 04 02:02:47 PM PDT 24
Peak memory 205328 kb
Host smart-b83539ec-54ab-4cf5-966c-6cad9d8abdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527270134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3527270134
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3738159279
Short name T432
Test name
Test status
Simulation time 521207485 ps
CPU time 5.8 seconds
Started Jun 04 02:02:43 PM PDT 24
Finished Jun 04 02:02:49 PM PDT 24
Peak memory 224300 kb
Host smart-7435f876-ad55-470c-922e-780df82ff629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738159279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3738159279
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2605894942
Short name T816
Test name
Test status
Simulation time 13727406773 ps
CPU time 70.54 seconds
Started Jun 04 02:02:48 PM PDT 24
Finished Jun 04 02:04:00 PM PDT 24
Peak memory 251160 kb
Host smart-41a06cd4-b9b9-4e8b-9821-eca8030ee550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605894942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2605894942
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.327943376
Short name T350
Test name
Test status
Simulation time 7943418384 ps
CPU time 59.18 seconds
Started Jun 04 02:02:49 PM PDT 24
Finished Jun 04 02:03:50 PM PDT 24
Peak memory 238816 kb
Host smart-f1b14107-2cad-4c24-bc74-cc1efcf5c156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327943376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.327943376
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2103286158
Short name T522
Test name
Test status
Simulation time 1441932714 ps
CPU time 11.77 seconds
Started Jun 04 02:02:49 PM PDT 24
Finished Jun 04 02:03:02 PM PDT 24
Peak memory 233796 kb
Host smart-5807b7a2-9322-4088-bee9-5ac7f677eecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103286158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2103286158
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2069848931
Short name T201
Test name
Test status
Simulation time 4754870747 ps
CPU time 46.94 seconds
Started Jun 04 02:02:44 PM PDT 24
Finished Jun 04 02:03:31 PM PDT 24
Peak memory 230840 kb
Host smart-708e5cbc-05e3-4273-bebf-7639c1b2646a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069848931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2069848931
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1111486276
Short name T853
Test name
Test status
Simulation time 31385818974 ps
CPU time 25.07 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:03:19 PM PDT 24
Peak memory 238248 kb
Host smart-dbdc40ac-961e-4a36-9e09-140f333e1999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111486276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1111486276
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1305300306
Short name T533
Test name
Test status
Simulation time 3675309064 ps
CPU time 14.48 seconds
Started Jun 04 02:02:43 PM PDT 24
Finished Jun 04 02:02:58 PM PDT 24
Peak memory 233668 kb
Host smart-7c08b094-25b3-40f1-9ad6-24815e0572d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305300306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1305300306
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.738739138
Short name T757
Test name
Test status
Simulation time 2386581986 ps
CPU time 8.01 seconds
Started Jun 04 02:02:42 PM PDT 24
Finished Jun 04 02:02:51 PM PDT 24
Peak memory 222888 kb
Host smart-896a03a6-2de2-4759-bdab-e75a8010da25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=738739138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.738739138
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1009031197
Short name T61
Test name
Test status
Simulation time 40165301 ps
CPU time 0.96 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:02:55 PM PDT 24
Peak memory 206608 kb
Host smart-ae2a7d50-7adb-41e3-9acf-ebf39a99a4dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009031197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1009031197
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.881847879
Short name T753
Test name
Test status
Simulation time 11458127 ps
CPU time 0.73 seconds
Started Jun 04 02:02:45 PM PDT 24
Finished Jun 04 02:02:46 PM PDT 24
Peak memory 205464 kb
Host smart-26bbe25c-f5db-4d93-83ca-45fc9272c677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881847879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.881847879
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1905936670
Short name T752
Test name
Test status
Simulation time 4639172616 ps
CPU time 6.12 seconds
Started Jun 04 02:02:40 PM PDT 24
Finished Jun 04 02:02:47 PM PDT 24
Peak memory 216092 kb
Host smart-d9f5bc0e-1526-4c9b-b3a1-8e990a39ffea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905936670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1905936670
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3466784579
Short name T599
Test name
Test status
Simulation time 74701410 ps
CPU time 1.43 seconds
Started Jun 04 02:02:49 PM PDT 24
Finished Jun 04 02:02:52 PM PDT 24
Peak memory 208032 kb
Host smart-d2714b31-f880-41f3-b38b-10e3a6412c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466784579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3466784579
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.960387636
Short name T450
Test name
Test status
Simulation time 44738848 ps
CPU time 0.78 seconds
Started Jun 04 02:02:46 PM PDT 24
Finished Jun 04 02:02:47 PM PDT 24
Peak memory 205576 kb
Host smart-a4cb0349-f812-454f-80c7-81673f3b18aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960387636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.960387636
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.4266799068
Short name T297
Test name
Test status
Simulation time 1452435692 ps
CPU time 3.26 seconds
Started Jun 04 02:02:51 PM PDT 24
Finished Jun 04 02:02:55 PM PDT 24
Peak memory 217208 kb
Host smart-f6edb2c6-6e72-4759-8e5d-dfc54225c887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266799068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4266799068
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.295910073
Short name T747
Test name
Test status
Simulation time 11910107 ps
CPU time 0.71 seconds
Started Jun 04 02:02:43 PM PDT 24
Finished Jun 04 02:02:44 PM PDT 24
Peak memory 205396 kb
Host smart-53cde006-8138-498d-8793-b1d862fc017a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295910073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.295910073
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1202088588
Short name T891
Test name
Test status
Simulation time 79484535 ps
CPU time 2.39 seconds
Started Jun 04 02:02:47 PM PDT 24
Finished Jun 04 02:02:50 PM PDT 24
Peak memory 218748 kb
Host smart-ea7173fc-1ae6-4f94-811f-619313f8e80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202088588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1202088588
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2817463652
Short name T58
Test name
Test status
Simulation time 228656601 ps
CPU time 0.74 seconds
Started Jun 04 02:02:43 PM PDT 24
Finished Jun 04 02:02:44 PM PDT 24
Peak memory 206304 kb
Host smart-2d6202d2-6eb8-4539-b3fd-f8ccabfd2e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817463652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2817463652
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3618580243
Short name T248
Test name
Test status
Simulation time 36965096634 ps
CPU time 293.06 seconds
Started Jun 04 02:02:44 PM PDT 24
Finished Jun 04 02:07:38 PM PDT 24
Peak memory 253780 kb
Host smart-4e05d884-0541-42a1-833e-e3901705073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618580243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3618580243
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.73080411
Short name T862
Test name
Test status
Simulation time 339953584 ps
CPU time 6.21 seconds
Started Jun 04 02:02:44 PM PDT 24
Finished Jun 04 02:02:51 PM PDT 24
Peak memory 224244 kb
Host smart-9816bdc4-dc2a-4700-aa14-ab540d2dae55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73080411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.73080411
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2409493637
Short name T219
Test name
Test status
Simulation time 1249528535 ps
CPU time 5.55 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:03:00 PM PDT 24
Peak memory 234320 kb
Host smart-4e23fc96-610a-4fb0-969f-a606f865f2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409493637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2409493637
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.392175686
Short name T74
Test name
Test status
Simulation time 44425087 ps
CPU time 2.66 seconds
Started Jun 04 02:02:42 PM PDT 24
Finished Jun 04 02:02:46 PM PDT 24
Peak memory 224360 kb
Host smart-e53af508-b2bb-44f7-917d-aa3d47fb1369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392175686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.392175686
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3016333371
Short name T590
Test name
Test status
Simulation time 120620327 ps
CPU time 2.56 seconds
Started Jun 04 02:02:52 PM PDT 24
Finished Jun 04 02:02:55 PM PDT 24
Peak memory 232648 kb
Host smart-5d197a1c-a23a-4956-a185-5aabf4823849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016333371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3016333371
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1348764769
Short name T540
Test name
Test status
Simulation time 32807264486 ps
CPU time 22.89 seconds
Started Jun 04 02:02:46 PM PDT 24
Finished Jun 04 02:03:09 PM PDT 24
Peak memory 234196 kb
Host smart-70888d0c-daa6-4d2e-a2c2-2b1aa2536ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348764769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1348764769
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1792971506
Short name T12
Test name
Test status
Simulation time 654243398 ps
CPU time 5.22 seconds
Started Jun 04 02:02:45 PM PDT 24
Finished Jun 04 02:02:50 PM PDT 24
Peak memory 220444 kb
Host smart-26585435-f4ad-4c76-94a4-a7fee4a7571e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1792971506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1792971506
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3562215796
Short name T699
Test name
Test status
Simulation time 85391996 ps
CPU time 0.97 seconds
Started Jun 04 02:02:42 PM PDT 24
Finished Jun 04 02:02:44 PM PDT 24
Peak memory 206632 kb
Host smart-ca5cabb9-354f-4b4a-9112-997f2638c79e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562215796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3562215796
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1198566707
Short name T426
Test name
Test status
Simulation time 1319021386 ps
CPU time 7.63 seconds
Started Jun 04 02:02:50 PM PDT 24
Finished Jun 04 02:02:58 PM PDT 24
Peak memory 216164 kb
Host smart-5b456aca-cd4e-4471-81c5-14061fed0d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198566707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1198566707
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2027393099
Short name T417
Test name
Test status
Simulation time 118182005 ps
CPU time 0.76 seconds
Started Jun 04 02:02:42 PM PDT 24
Finished Jun 04 02:02:43 PM PDT 24
Peak memory 205524 kb
Host smart-a7032d3b-7bad-4171-b63f-863e3bda3280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027393099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2027393099
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3065211261
Short name T17
Test name
Test status
Simulation time 837058250 ps
CPU time 1.34 seconds
Started Jun 04 02:02:45 PM PDT 24
Finished Jun 04 02:02:47 PM PDT 24
Peak memory 216184 kb
Host smart-e09d65e0-fa2e-4f10-a717-2ea372583afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065211261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3065211261
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.558630269
Short name T727
Test name
Test status
Simulation time 112383047 ps
CPU time 0.79 seconds
Started Jun 04 02:02:46 PM PDT 24
Finished Jun 04 02:02:48 PM PDT 24
Peak memory 205628 kb
Host smart-5c99c009-1048-45b3-9f0a-d3675d646222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558630269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.558630269
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2148034551
Short name T330
Test name
Test status
Simulation time 207751633 ps
CPU time 3.19 seconds
Started Jun 04 02:02:44 PM PDT 24
Finished Jun 04 02:02:48 PM PDT 24
Peak memory 224376 kb
Host smart-295b97e2-f90b-4e3f-bbe6-64808c0e9fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148034551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2148034551
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3068610644
Short name T391
Test name
Test status
Simulation time 13495204 ps
CPU time 0.75 seconds
Started Jun 04 02:02:55 PM PDT 24
Finished Jun 04 02:02:57 PM PDT 24
Peak memory 205540 kb
Host smart-5e92817b-a34e-4b11-910d-c0b86b5d97b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068610644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3068610644
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3657692710
Short name T525
Test name
Test status
Simulation time 150209923 ps
CPU time 3.02 seconds
Started Jun 04 02:02:46 PM PDT 24
Finished Jun 04 02:02:50 PM PDT 24
Peak memory 218520 kb
Host smart-f488c891-4388-464d-bf41-c766fc74b6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657692710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3657692710
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2399630769
Short name T396
Test name
Test status
Simulation time 20246921 ps
CPU time 0.78 seconds
Started Jun 04 02:02:44 PM PDT 24
Finished Jun 04 02:02:46 PM PDT 24
Peak memory 206684 kb
Host smart-284152c1-3637-43ef-8c44-79ae6c663837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399630769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2399630769
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1267321075
Short name T668
Test name
Test status
Simulation time 182418038029 ps
CPU time 96.5 seconds
Started Jun 04 02:02:48 PM PDT 24
Finished Jun 04 02:04:25 PM PDT 24
Peak memory 249012 kb
Host smart-32243ce8-c972-41cc-8b6d-c44078ece9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267321075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1267321075
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3432380539
Short name T49
Test name
Test status
Simulation time 239429349269 ps
CPU time 230.8 seconds
Started Jun 04 02:02:48 PM PDT 24
Finished Jun 04 02:06:40 PM PDT 24
Peak memory 249348 kb
Host smart-6feebe26-9255-4f42-a67e-21e489571d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432380539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3432380539
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.587659793
Short name T196
Test name
Test status
Simulation time 24112506238 ps
CPU time 179.51 seconds
Started Jun 04 02:02:45 PM PDT 24
Finished Jun 04 02:05:46 PM PDT 24
Peak memory 272588 kb
Host smart-2565455b-42d3-458a-a5b3-86605ae0de17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587659793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.587659793
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.601773181
Short name T942
Test name
Test status
Simulation time 1257033714 ps
CPU time 20.6 seconds
Started Jun 04 02:02:47 PM PDT 24
Finished Jun 04 02:03:09 PM PDT 24
Peak memory 240784 kb
Host smart-13dfad5b-e7d9-41fd-ab42-cfbb23938559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601773181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.601773181
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2490891862
Short name T197
Test name
Test status
Simulation time 309537738 ps
CPU time 4.99 seconds
Started Jun 04 02:02:47 PM PDT 24
Finished Jun 04 02:02:53 PM PDT 24
Peak memory 233160 kb
Host smart-edae3e3b-07f9-4ac0-8b74-4d82ae9788f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490891862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2490891862
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1541255443
Short name T878
Test name
Test status
Simulation time 669955289 ps
CPU time 6.12 seconds
Started Jun 04 02:02:49 PM PDT 24
Finished Jun 04 02:02:56 PM PDT 24
Peak memory 218432 kb
Host smart-ff814dfe-bb23-4bea-be45-17010fb1e78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541255443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1541255443
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3181693846
Short name T340
Test name
Test status
Simulation time 2437321608 ps
CPU time 6.08 seconds
Started Jun 04 02:02:46 PM PDT 24
Finished Jun 04 02:02:53 PM PDT 24
Peak memory 233564 kb
Host smart-5be79831-7a98-4f15-b202-6c294c5ff20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181693846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3181693846
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3594656665
Short name T805
Test name
Test status
Simulation time 624372357 ps
CPU time 2.74 seconds
Started Jun 04 02:02:55 PM PDT 24
Finished Jun 04 02:03:00 PM PDT 24
Peak memory 224500 kb
Host smart-996f1f70-6ec8-4148-818c-d1263ab584d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594656665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3594656665
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.955123709
Short name T937
Test name
Test status
Simulation time 4005484970 ps
CPU time 5.51 seconds
Started Jun 04 02:02:46 PM PDT 24
Finished Jun 04 02:02:53 PM PDT 24
Peak memory 220332 kb
Host smart-71a8d3c6-8b3f-4f61-afae-363a8da82c8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=955123709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.955123709
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2564418443
Short name T162
Test name
Test status
Simulation time 29544642525 ps
CPU time 313.53 seconds
Started Jun 04 02:02:47 PM PDT 24
Finished Jun 04 02:08:02 PM PDT 24
Peak memory 273720 kb
Host smart-06708200-7e81-4a12-a171-4b2154f62fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564418443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2564418443
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.686147965
Short name T497
Test name
Test status
Simulation time 3126760820 ps
CPU time 21.41 seconds
Started Jun 04 02:02:44 PM PDT 24
Finished Jun 04 02:03:06 PM PDT 24
Peak memory 216268 kb
Host smart-e67e470f-3a8d-49ef-a872-a81b82c54e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686147965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.686147965
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1218215056
Short name T448
Test name
Test status
Simulation time 11793336353 ps
CPU time 11.98 seconds
Started Jun 04 02:02:51 PM PDT 24
Finished Jun 04 02:03:04 PM PDT 24
Peak memory 216048 kb
Host smart-6839da2e-1a99-432f-bd5d-0d17a77ba2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218215056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1218215056
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3058409304
Short name T438
Test name
Test status
Simulation time 436317503 ps
CPU time 0.97 seconds
Started Jun 04 02:02:47 PM PDT 24
Finished Jun 04 02:02:49 PM PDT 24
Peak memory 207724 kb
Host smart-2147d95b-9bad-4271-83fd-eb05adb69842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058409304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3058409304
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.712010105
Short name T676
Test name
Test status
Simulation time 312863700 ps
CPU time 1.07 seconds
Started Jun 04 02:02:44 PM PDT 24
Finished Jun 04 02:02:46 PM PDT 24
Peak memory 205608 kb
Host smart-e28d610b-eb0e-4da7-9adb-5bec8bd8d7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712010105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.712010105
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2028372886
Short name T661
Test name
Test status
Simulation time 975528940 ps
CPU time 9.28 seconds
Started Jun 04 02:02:48 PM PDT 24
Finished Jun 04 02:02:58 PM PDT 24
Peak memory 235324 kb
Host smart-2b5fc7ff-4527-4f9c-b339-26bfcbf96661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028372886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2028372886
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3465504382
Short name T60
Test name
Test status
Simulation time 12423894 ps
CPU time 0.71 seconds
Started Jun 04 02:02:51 PM PDT 24
Finished Jun 04 02:02:53 PM PDT 24
Peak memory 205336 kb
Host smart-eebebc68-5875-4a5f-a69b-91eced76cde7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465504382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3465504382
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.4049237792
Short name T413
Test name
Test status
Simulation time 88892053 ps
CPU time 1.96 seconds
Started Jun 04 02:02:47 PM PDT 24
Finished Jun 04 02:02:50 PM PDT 24
Peak memory 215912 kb
Host smart-f9bdb0df-ce13-4004-8a97-db21bbdee92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049237792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.4049237792
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1978933992
Short name T959
Test name
Test status
Simulation time 22692713 ps
CPU time 0.8 seconds
Started Jun 04 02:02:45 PM PDT 24
Finished Jun 04 02:02:47 PM PDT 24
Peak memory 206336 kb
Host smart-7089714a-d8c3-4429-9c1e-5bb7ebbfb247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978933992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1978933992
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1669746601
Short name T696
Test name
Test status
Simulation time 73587243 ps
CPU time 0.73 seconds
Started Jun 04 02:02:55 PM PDT 24
Finished Jun 04 02:02:57 PM PDT 24
Peak memory 215752 kb
Host smart-15234443-11c9-41c3-9389-20449d02d956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669746601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1669746601
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1118680266
Short name T252
Test name
Test status
Simulation time 16920651163 ps
CPU time 139 seconds
Started Jun 04 02:02:55 PM PDT 24
Finished Jun 04 02:05:16 PM PDT 24
Peak memory 249128 kb
Host smart-9d417f9d-b2f4-4630-8b27-035a2ce4b1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118680266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1118680266
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.496218267
Short name T277
Test name
Test status
Simulation time 7432306185 ps
CPU time 41.98 seconds
Started Jun 04 02:02:55 PM PDT 24
Finished Jun 04 02:03:38 PM PDT 24
Peak memory 255152 kb
Host smart-99ee8489-7310-4448-8f50-070cee468491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496218267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.496218267
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2388856255
Short name T447
Test name
Test status
Simulation time 89537894 ps
CPU time 4.05 seconds
Started Jun 04 02:02:45 PM PDT 24
Finished Jun 04 02:02:50 PM PDT 24
Peak memory 232568 kb
Host smart-416a5ec6-4912-4eb4-b94d-d144a44a4fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388856255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2388856255
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1876848504
Short name T318
Test name
Test status
Simulation time 223735265 ps
CPU time 2.8 seconds
Started Jun 04 02:02:47 PM PDT 24
Finished Jun 04 02:02:51 PM PDT 24
Peak memory 218468 kb
Host smart-cf13360b-2b0d-478f-b6d6-3a17ac3cccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876848504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1876848504
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2954653742
Short name T500
Test name
Test status
Simulation time 8145787628 ps
CPU time 18.99 seconds
Started Jun 04 02:02:55 PM PDT 24
Finished Jun 04 02:03:16 PM PDT 24
Peak memory 248744 kb
Host smart-3d1eadda-7ef5-4a6d-8e88-9f265143bb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954653742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2954653742
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1397765135
Short name T828
Test name
Test status
Simulation time 20503163273 ps
CPU time 16.08 seconds
Started Jun 04 02:02:49 PM PDT 24
Finished Jun 04 02:03:07 PM PDT 24
Peak memory 235268 kb
Host smart-6b463c58-a030-42f1-8d50-d2c4bada539d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397765135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1397765135
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1321046492
Short name T51
Test name
Test status
Simulation time 1289560968 ps
CPU time 8.88 seconds
Started Jun 04 02:02:47 PM PDT 24
Finished Jun 04 02:02:57 PM PDT 24
Peak memory 220452 kb
Host smart-5ed8b4d1-69a7-4e39-865c-9bd7bf5199a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1321046492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1321046492
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.37110723
Short name T922
Test name
Test status
Simulation time 15195572314 ps
CPU time 105.23 seconds
Started Jun 04 02:02:49 PM PDT 24
Finished Jun 04 02:04:35 PM PDT 24
Peak memory 254848 kb
Host smart-24ef2bda-dc46-4428-a842-43092f5bb008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37110723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress
_all.37110723
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2573501726
Short name T944
Test name
Test status
Simulation time 8403479073 ps
CPU time 41.72 seconds
Started Jun 04 02:02:49 PM PDT 24
Finished Jun 04 02:03:32 PM PDT 24
Peak memory 216212 kb
Host smart-7039c013-93aa-4ed9-aa13-a747f67cc932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573501726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2573501726
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.953125899
Short name T76
Test name
Test status
Simulation time 38508309237 ps
CPU time 19.19 seconds
Started Jun 04 02:02:48 PM PDT 24
Finished Jun 04 02:03:08 PM PDT 24
Peak memory 216156 kb
Host smart-5e42fad6-7d6e-4d7a-b93b-63f0ca7ade6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953125899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.953125899
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2653159590
Short name T601
Test name
Test status
Simulation time 37626620 ps
CPU time 0.89 seconds
Started Jun 04 02:02:55 PM PDT 24
Finished Jun 04 02:02:58 PM PDT 24
Peak memory 206504 kb
Host smart-94f3b05a-a8eb-4fb2-96bc-7235748b2944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653159590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2653159590
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3170707807
Short name T543
Test name
Test status
Simulation time 55922234 ps
CPU time 0.8 seconds
Started Jun 04 02:02:47 PM PDT 24
Finished Jun 04 02:02:49 PM PDT 24
Peak memory 205628 kb
Host smart-313cf2c9-8b0d-4bb9-a7fb-aabaf89debed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170707807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3170707807
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.617316686
Short name T964
Test name
Test status
Simulation time 81143339 ps
CPU time 2.51 seconds
Started Jun 04 02:02:49 PM PDT 24
Finished Jun 04 02:02:53 PM PDT 24
Peak memory 220816 kb
Host smart-456c65ff-b1ea-4ffb-ba86-25cffcdd83b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617316686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.617316686
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3965124994
Short name T929
Test name
Test status
Simulation time 11600354 ps
CPU time 0.74 seconds
Started Jun 04 02:01:25 PM PDT 24
Finished Jun 04 02:01:27 PM PDT 24
Peak memory 205752 kb
Host smart-dffe1249-af11-497a-bc9d-4d5036dc1a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965124994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
965124994
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1280486504
Short name T167
Test name
Test status
Simulation time 344325569 ps
CPU time 3.31 seconds
Started Jun 04 02:01:26 PM PDT 24
Finished Jun 04 02:01:31 PM PDT 24
Peak memory 234300 kb
Host smart-bb4a7c30-6051-4f53-bb07-02069677bd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280486504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1280486504
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.217196269
Short name T551
Test name
Test status
Simulation time 29541919 ps
CPU time 0.8 seconds
Started Jun 04 02:01:29 PM PDT 24
Finished Jun 04 02:01:31 PM PDT 24
Peak memory 206408 kb
Host smart-b8affa51-1203-4a25-8286-3b5b0e319da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217196269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.217196269
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1304762552
Short name T940
Test name
Test status
Simulation time 18744589822 ps
CPU time 81.78 seconds
Started Jun 04 02:01:25 PM PDT 24
Finished Jun 04 02:02:48 PM PDT 24
Peak memory 250496 kb
Host smart-242aa6d6-83eb-4201-b624-977a62e5d10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304762552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1304762552
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1990220284
Short name T943
Test name
Test status
Simulation time 3704445721 ps
CPU time 63.12 seconds
Started Jun 04 02:01:28 PM PDT 24
Finished Jun 04 02:02:32 PM PDT 24
Peak memory 249124 kb
Host smart-e187b574-e60e-4b12-a2c4-5a43a52c30d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990220284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1990220284
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2673978362
Short name T730
Test name
Test status
Simulation time 2782283245 ps
CPU time 71.66 seconds
Started Jun 04 02:01:26 PM PDT 24
Finished Jun 04 02:02:39 PM PDT 24
Peak memory 249256 kb
Host smart-ce8da115-6f70-4c76-a32d-07df6dcaae72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673978362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2673978362
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3709817339
Short name T562
Test name
Test status
Simulation time 80290729 ps
CPU time 2.66 seconds
Started Jun 04 02:01:28 PM PDT 24
Finished Jun 04 02:01:32 PM PDT 24
Peak memory 224312 kb
Host smart-f5abfff9-0b51-446d-85f4-5d48bd832094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709817339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3709817339
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1123066363
Short name T99
Test name
Test status
Simulation time 8157184971 ps
CPU time 15.94 seconds
Started Jun 04 02:01:24 PM PDT 24
Finished Jun 04 02:01:41 PM PDT 24
Peak memory 234880 kb
Host smart-444c0b38-561f-42f7-8157-47abd5c28629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123066363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1123066363
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3880973041
Short name T849
Test name
Test status
Simulation time 3464202326 ps
CPU time 29.76 seconds
Started Jun 04 02:01:24 PM PDT 24
Finished Jun 04 02:01:55 PM PDT 24
Peak memory 235988 kb
Host smart-471ef2be-9a67-446f-a07a-c1a1686ba956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880973041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3880973041
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2222342016
Short name T2
Test name
Test status
Simulation time 2441646674 ps
CPU time 4.84 seconds
Started Jun 04 02:01:30 PM PDT 24
Finished Jun 04 02:01:35 PM PDT 24
Peak memory 218472 kb
Host smart-0a1f45c6-a3f9-4c5b-952a-c80853556e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222342016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2222342016
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1550614323
Short name T713
Test name
Test status
Simulation time 159880298 ps
CPU time 2.22 seconds
Started Jun 04 02:01:24 PM PDT 24
Finished Jun 04 02:01:27 PM PDT 24
Peak memory 218464 kb
Host smart-17751615-bfda-4457-ada1-379e1ad173fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550614323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1550614323
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1230063751
Short name T520
Test name
Test status
Simulation time 1161004778 ps
CPU time 4.16 seconds
Started Jun 04 02:01:27 PM PDT 24
Finished Jun 04 02:01:33 PM PDT 24
Peak memory 220616 kb
Host smart-2a95e398-98ee-4896-84c6-39a887c2f162
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1230063751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1230063751
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2285718990
Short name T69
Test name
Test status
Simulation time 431147998 ps
CPU time 1.07 seconds
Started Jun 04 02:01:25 PM PDT 24
Finished Jun 04 02:01:27 PM PDT 24
Peak memory 235020 kb
Host smart-21ebbefb-3e5f-4ad4-a960-92f7d3fa0588
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285718990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2285718990
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1677668040
Short name T357
Test name
Test status
Simulation time 7321745695 ps
CPU time 34.16 seconds
Started Jun 04 02:01:26 PM PDT 24
Finished Jun 04 02:02:02 PM PDT 24
Peak memory 216564 kb
Host smart-ea43e83a-e7b4-46cd-9fe0-a38da544a6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677668040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1677668040
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2715822544
Short name T741
Test name
Test status
Simulation time 1492210688 ps
CPU time 3.91 seconds
Started Jun 04 02:01:38 PM PDT 24
Finished Jun 04 02:01:43 PM PDT 24
Peak memory 216008 kb
Host smart-6053b70e-ac32-4e0d-892a-969f3607a69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715822544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2715822544
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.4291334921
Short name T934
Test name
Test status
Simulation time 40883625 ps
CPU time 0.71 seconds
Started Jun 04 02:01:26 PM PDT 24
Finished Jun 04 02:01:29 PM PDT 24
Peak memory 205456 kb
Host smart-e975ffab-eeb5-4c08-b33d-59e4e8a3794f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291334921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.4291334921
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1823002757
Short name T541
Test name
Test status
Simulation time 120011002 ps
CPU time 0.84 seconds
Started Jun 04 02:01:27 PM PDT 24
Finished Jun 04 02:01:30 PM PDT 24
Peak memory 205540 kb
Host smart-2cccd723-dab8-477f-8077-5089cfe62025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823002757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1823002757
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.249919261
Short name T328
Test name
Test status
Simulation time 2124461089 ps
CPU time 7.01 seconds
Started Jun 04 02:01:29 PM PDT 24
Finished Jun 04 02:01:37 PM PDT 24
Peak memory 240644 kb
Host smart-e2cd953f-260d-4138-8b97-d28ade4129c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249919261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.249919261
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2552087834
Short name T52
Test name
Test status
Simulation time 62690872 ps
CPU time 0.75 seconds
Started Jun 04 02:02:54 PM PDT 24
Finished Jun 04 02:02:57 PM PDT 24
Peak memory 205356 kb
Host smart-e893a3b9-3a7c-484a-87cf-e4f68b1f1c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552087834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2552087834
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2395119785
Short name T936
Test name
Test status
Simulation time 827782360 ps
CPU time 4.24 seconds
Started Jun 04 02:02:55 PM PDT 24
Finished Jun 04 02:03:01 PM PDT 24
Peak memory 233972 kb
Host smart-67939f33-3d84-480a-890d-0e46d0906590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395119785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2395119785
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2979770924
Short name T539
Test name
Test status
Simulation time 17903871 ps
CPU time 0.73 seconds
Started Jun 04 02:02:46 PM PDT 24
Finished Jun 04 02:02:47 PM PDT 24
Peak memory 205380 kb
Host smart-75e5f8f7-c7b2-4f56-a82f-9dcb527ddd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979770924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2979770924
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.280301998
Short name T226
Test name
Test status
Simulation time 416228278685 ps
CPU time 149.91 seconds
Started Jun 04 02:02:54 PM PDT 24
Finished Jun 04 02:05:26 PM PDT 24
Peak memory 249076 kb
Host smart-f3be1bcd-3e62-40f6-9420-99adc9452bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280301998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.280301998
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.693391887
Short name T772
Test name
Test status
Simulation time 8596494102 ps
CPU time 53.16 seconds
Started Jun 04 02:02:57 PM PDT 24
Finished Jun 04 02:03:51 PM PDT 24
Peak memory 250084 kb
Host smart-d5fdc916-f488-4832-8055-d91d87b6e249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693391887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.693391887
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1910157662
Short name T945
Test name
Test status
Simulation time 82136344517 ps
CPU time 175.44 seconds
Started Jun 04 02:02:54 PM PDT 24
Finished Jun 04 02:05:51 PM PDT 24
Peak memory 256256 kb
Host smart-dc502c61-e70d-4904-822c-380187269d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910157662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1910157662
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4271050865
Short name T546
Test name
Test status
Simulation time 8693189777 ps
CPU time 12.2 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:03:08 PM PDT 24
Peak memory 236116 kb
Host smart-d2c6b7af-9f5a-405b-aa4d-921078712b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271050865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4271050865
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.4155366206
Short name T563
Test name
Test status
Simulation time 1495809664 ps
CPU time 15.7 seconds
Started Jun 04 02:02:52 PM PDT 24
Finished Jun 04 02:03:09 PM PDT 24
Peak memory 219368 kb
Host smart-78bd6a16-17cb-42c6-925d-cd3a0298aa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155366206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.4155366206
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1689688694
Short name T829
Test name
Test status
Simulation time 5723290655 ps
CPU time 53.23 seconds
Started Jun 04 02:02:55 PM PDT 24
Finished Jun 04 02:03:50 PM PDT 24
Peak memory 234012 kb
Host smart-33a5eda5-848b-460e-bfda-c9a0cd62cba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689688694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1689688694
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3749308800
Short name T41
Test name
Test status
Simulation time 1360825728 ps
CPU time 4.1 seconds
Started Jun 04 02:02:54 PM PDT 24
Finished Jun 04 02:03:00 PM PDT 24
Peak memory 218628 kb
Host smart-f485a6b8-c4b3-45d0-9311-4d31567184f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749308800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3749308800
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1644338028
Short name T771
Test name
Test status
Simulation time 5993096858 ps
CPU time 6.92 seconds
Started Jun 04 02:02:52 PM PDT 24
Finished Jun 04 02:03:00 PM PDT 24
Peak memory 218660 kb
Host smart-e6e8bb79-333f-4d05-8796-0f0552869706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644338028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1644338028
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.385087557
Short name T431
Test name
Test status
Simulation time 1599151168 ps
CPU time 7.18 seconds
Started Jun 04 02:02:57 PM PDT 24
Finished Jun 04 02:03:05 PM PDT 24
Peak memory 222704 kb
Host smart-2cad7afb-889b-4bea-bbfa-b38e580bc7a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=385087557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.385087557
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2035950210
Short name T958
Test name
Test status
Simulation time 42680935 ps
CPU time 0.96 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:02:56 PM PDT 24
Peak memory 206804 kb
Host smart-d51bbbec-a57b-45f6-9c18-d8769fdd142a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035950210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2035950210
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2801985007
Short name T14
Test name
Test status
Simulation time 2833667279 ps
CPU time 24.55 seconds
Started Jun 04 02:02:51 PM PDT 24
Finished Jun 04 02:03:16 PM PDT 24
Peak memory 216196 kb
Host smart-4ec507d7-f7f8-4a41-b508-b5b5f334b505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801985007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2801985007
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1149883715
Short name T645
Test name
Test status
Simulation time 595462186 ps
CPU time 3.9 seconds
Started Jun 04 02:02:51 PM PDT 24
Finished Jun 04 02:02:56 PM PDT 24
Peak memory 216064 kb
Host smart-7766f930-4e49-4907-9159-e15212904468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149883715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1149883715
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3077401862
Short name T399
Test name
Test status
Simulation time 17754060 ps
CPU time 0.93 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:02:56 PM PDT 24
Peak memory 207212 kb
Host smart-11c4f760-9c1c-4a50-ade0-1b151d5d9f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077401862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3077401862
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3314408821
Short name T463
Test name
Test status
Simulation time 153557318 ps
CPU time 0.83 seconds
Started Jun 04 02:02:52 PM PDT 24
Finished Jun 04 02:02:54 PM PDT 24
Peak memory 205524 kb
Host smart-aebc1029-7b97-465b-8798-03a21d434584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314408821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3314408821
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.602379752
Short name T709
Test name
Test status
Simulation time 231134954 ps
CPU time 3.38 seconds
Started Jun 04 02:02:54 PM PDT 24
Finished Jun 04 02:02:59 PM PDT 24
Peak memory 219596 kb
Host smart-bccfb76f-0f1b-4aa2-9234-036c42502558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602379752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.602379752
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1298798272
Short name T763
Test name
Test status
Simulation time 24061690 ps
CPU time 0.74 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:02:55 PM PDT 24
Peak memory 205300 kb
Host smart-3b86c9c2-717b-44c8-ad52-618df63d2596
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298798272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1298798272
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2197850800
Short name T327
Test name
Test status
Simulation time 6726168341 ps
CPU time 11.82 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:03:07 PM PDT 24
Peak memory 234324 kb
Host smart-6de9986f-42c9-4777-9ebc-0b032927fea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197850800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2197850800
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2554058141
Short name T492
Test name
Test status
Simulation time 41871068 ps
CPU time 0.78 seconds
Started Jun 04 02:02:54 PM PDT 24
Finished Jun 04 02:02:57 PM PDT 24
Peak memory 206400 kb
Host smart-853002b7-be7a-4aa7-aa4c-d9589ab55c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554058141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2554058141
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3393506476
Short name T813
Test name
Test status
Simulation time 10000523501 ps
CPU time 68.57 seconds
Started Jun 04 02:02:52 PM PDT 24
Finished Jun 04 02:04:02 PM PDT 24
Peak memory 250632 kb
Host smart-2da67cfd-ce0d-4932-bfc4-b52a8862c21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393506476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3393506476
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1594744542
Short name T669
Test name
Test status
Simulation time 12405323579 ps
CPU time 115.23 seconds
Started Jun 04 02:02:55 PM PDT 24
Finished Jun 04 02:04:52 PM PDT 24
Peak memory 251384 kb
Host smart-a01e1e4c-fb04-40e2-9d22-c42e556c8afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594744542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1594744542
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.488964174
Short name T536
Test name
Test status
Simulation time 19833380526 ps
CPU time 71.33 seconds
Started Jun 04 02:02:55 PM PDT 24
Finished Jun 04 02:04:08 PM PDT 24
Peak memory 256392 kb
Host smart-9b63ddcf-f30f-433e-9b15-d3e699902a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488964174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.488964174
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.98454876
Short name T349
Test name
Test status
Simulation time 244590255 ps
CPU time 3.5 seconds
Started Jun 04 02:02:55 PM PDT 24
Finished Jun 04 02:03:00 PM PDT 24
Peak memory 224328 kb
Host smart-6d2a2e9e-3b0b-4898-9da0-4cb4217b0183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98454876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.98454876
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2546008419
Short name T695
Test name
Test status
Simulation time 281366515 ps
CPU time 2.2 seconds
Started Jun 04 02:02:54 PM PDT 24
Finished Jun 04 02:02:58 PM PDT 24
Peak memory 216516 kb
Host smart-e9ccb2c4-048d-4775-bea5-0187f12a07bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546008419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2546008419
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3996012481
Short name T54
Test name
Test status
Simulation time 12594778808 ps
CPU time 28.16 seconds
Started Jun 04 02:02:52 PM PDT 24
Finished Jun 04 02:03:21 PM PDT 24
Peak memory 238884 kb
Host smart-0ab2fd22-0247-4b5d-bd0a-5e2aace86d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996012481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3996012481
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1712097904
Short name T224
Test name
Test status
Simulation time 533890558 ps
CPU time 4.74 seconds
Started Jun 04 02:02:54 PM PDT 24
Finished Jun 04 02:03:00 PM PDT 24
Peak memory 226924 kb
Host smart-162e3e97-5103-4094-ae9c-9a3373a67f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712097904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1712097904
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2579244709
Short name T295
Test name
Test status
Simulation time 270261239 ps
CPU time 2.5 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:02:57 PM PDT 24
Peak memory 216620 kb
Host smart-0209b782-8bcb-4853-96d6-1ed9d8d72841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579244709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2579244709
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.829607945
Short name T809
Test name
Test status
Simulation time 256686819 ps
CPU time 4.15 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:02:59 PM PDT 24
Peak memory 222888 kb
Host smart-fb470573-1a60-4d0c-838c-e714d88857ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=829607945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.829607945
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.949244581
Short name T268
Test name
Test status
Simulation time 5334315063 ps
CPU time 65.11 seconds
Started Jun 04 02:02:57 PM PDT 24
Finished Jun 04 02:04:03 PM PDT 24
Peak memory 251508 kb
Host smart-8017de38-deef-4b2e-a4ad-b90d423e860d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949244581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.949244581
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3233631540
Short name T706
Test name
Test status
Simulation time 4546446389 ps
CPU time 24.51 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:03:19 PM PDT 24
Peak memory 216300 kb
Host smart-656bc715-9b1e-4f27-bc72-d70847f034ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233631540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3233631540
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.101468035
Short name T437
Test name
Test status
Simulation time 1066076857 ps
CPU time 5.25 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:03:01 PM PDT 24
Peak memory 216032 kb
Host smart-50c1a4ff-2656-48dd-85b4-49cbe94014b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101468035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.101468035
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3959895670
Short name T469
Test name
Test status
Simulation time 164480071 ps
CPU time 1.72 seconds
Started Jun 04 02:02:57 PM PDT 24
Finished Jun 04 02:02:59 PM PDT 24
Peak memory 216232 kb
Host smart-ff1fd9b0-4dfc-400a-bd21-6c0e2afdac96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959895670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3959895670
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3374315938
Short name T634
Test name
Test status
Simulation time 36613115 ps
CPU time 0.71 seconds
Started Jun 04 02:02:52 PM PDT 24
Finished Jun 04 02:02:54 PM PDT 24
Peak memory 205640 kb
Host smart-e4c75dd2-e4f9-43b5-abae-19b98f38e0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374315938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3374315938
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.640562517
Short name T711
Test name
Test status
Simulation time 104467097 ps
CPU time 2.83 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:02:58 PM PDT 24
Peak memory 234028 kb
Host smart-d35fd78d-58bf-4877-b9f9-23164a39e646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640562517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.640562517
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2889628
Short name T923
Test name
Test status
Simulation time 14744092 ps
CPU time 0.7 seconds
Started Jun 04 02:03:01 PM PDT 24
Finished Jun 04 02:03:03 PM PDT 24
Peak memory 204776 kb
Host smart-0423da85-afdc-47d2-a143-74aaf08ba15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.2889628
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2129985155
Short name T791
Test name
Test status
Simulation time 144163504 ps
CPU time 2.5 seconds
Started Jun 04 02:03:00 PM PDT 24
Finished Jun 04 02:03:03 PM PDT 24
Peak memory 233304 kb
Host smart-9c5beee0-f028-498d-9502-4498da4eb8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129985155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2129985155
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1383958082
Short name T798
Test name
Test status
Simulation time 40694346 ps
CPU time 0.85 seconds
Started Jun 04 02:02:55 PM PDT 24
Finished Jun 04 02:02:57 PM PDT 24
Peak memory 206324 kb
Host smart-43a53946-1122-4d67-b18d-2164e5fcf0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383958082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1383958082
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3944776733
Short name T683
Test name
Test status
Simulation time 12220268361 ps
CPU time 92.28 seconds
Started Jun 04 02:03:03 PM PDT 24
Finished Jun 04 02:04:36 PM PDT 24
Peak memory 237044 kb
Host smart-b32679a9-ff87-40c2-afb0-4f16c7ee3c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944776733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3944776733
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.881376217
Short name T169
Test name
Test status
Simulation time 7411131714 ps
CPU time 29.9 seconds
Started Jun 04 02:03:00 PM PDT 24
Finished Jun 04 02:03:31 PM PDT 24
Peak memory 238080 kb
Host smart-272c65b1-fea1-4a26-8353-b1e8d2459c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881376217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.881376217
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1927554614
Short name T737
Test name
Test status
Simulation time 7006640427 ps
CPU time 27.17 seconds
Started Jun 04 02:03:01 PM PDT 24
Finished Jun 04 02:03:29 PM PDT 24
Peak memory 224524 kb
Host smart-cac8bf6c-6a3d-4dee-acb8-b673c23828e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927554614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1927554614
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2687243416
Short name T874
Test name
Test status
Simulation time 11828247784 ps
CPU time 42.7 seconds
Started Jun 04 02:03:01 PM PDT 24
Finished Jun 04 02:03:45 PM PDT 24
Peak memory 234932 kb
Host smart-9f8add28-566f-4510-b649-e251b11470ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687243416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2687243416
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3028871743
Short name T920
Test name
Test status
Simulation time 3502698217 ps
CPU time 15.95 seconds
Started Jun 04 02:03:02 PM PDT 24
Finished Jun 04 02:03:19 PM PDT 24
Peak memory 233492 kb
Host smart-5618625d-b0a3-4388-9244-9706add0a286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028871743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3028871743
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3466799450
Short name T305
Test name
Test status
Simulation time 1686707862 ps
CPU time 7.26 seconds
Started Jun 04 02:03:00 PM PDT 24
Finished Jun 04 02:03:08 PM PDT 24
Peak memory 218724 kb
Host smart-637e8c39-2f4b-422e-8b34-9c2684860182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466799450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3466799450
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2580999673
Short name T618
Test name
Test status
Simulation time 445644067 ps
CPU time 3 seconds
Started Jun 04 02:03:01 PM PDT 24
Finished Jun 04 02:03:05 PM PDT 24
Peak memory 233608 kb
Host smart-c3b45ae7-c635-437b-85a4-aa3a98a0731b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580999673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2580999673
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1797397940
Short name T907
Test name
Test status
Simulation time 9270227498 ps
CPU time 12.65 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:03:07 PM PDT 24
Peak memory 233412 kb
Host smart-bd4c1bad-5099-4cce-895f-16757c0089be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797397940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1797397940
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.716746391
Short name T863
Test name
Test status
Simulation time 72974882 ps
CPU time 3.36 seconds
Started Jun 04 02:03:03 PM PDT 24
Finished Jun 04 02:03:07 PM PDT 24
Peak memory 222804 kb
Host smart-061cb761-145f-4d6f-81d9-920ba871ffe4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=716746391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.716746391
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2783882030
Short name T260
Test name
Test status
Simulation time 57969702563 ps
CPU time 137.56 seconds
Started Jun 04 02:03:04 PM PDT 24
Finished Jun 04 02:05:23 PM PDT 24
Peak memory 236844 kb
Host smart-989699b3-1ee0-41d1-ad33-d305e9977a75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783882030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2783882030
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1421842101
Short name T963
Test name
Test status
Simulation time 9371470993 ps
CPU time 13.19 seconds
Started Jun 04 02:02:52 PM PDT 24
Finished Jun 04 02:03:07 PM PDT 24
Peak memory 216224 kb
Host smart-8c784a8f-ca1d-49ad-877f-1dbac8bcce55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421842101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1421842101
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3254543471
Short name T962
Test name
Test status
Simulation time 19984901021 ps
CPU time 15.21 seconds
Started Jun 04 02:02:56 PM PDT 24
Finished Jun 04 02:03:12 PM PDT 24
Peak memory 216172 kb
Host smart-c9f3aa7a-42c8-4c13-9758-7f2e2bbab704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254543471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3254543471
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2247792403
Short name T419
Test name
Test status
Simulation time 248078252 ps
CPU time 1.68 seconds
Started Jun 04 02:02:57 PM PDT 24
Finished Jun 04 02:03:00 PM PDT 24
Peak memory 216180 kb
Host smart-ba8b86f5-64a6-4884-a421-61fecf69315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247792403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2247792403
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2432507885
Short name T367
Test name
Test status
Simulation time 137329945 ps
CPU time 1.12 seconds
Started Jun 04 02:02:53 PM PDT 24
Finished Jun 04 02:02:56 PM PDT 24
Peak memory 206068 kb
Host smart-04cd9804-0447-408a-9adb-ef8e6cd4420e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432507885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2432507885
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.876774411
Short name T824
Test name
Test status
Simulation time 993540439 ps
CPU time 5.66 seconds
Started Jun 04 02:03:01 PM PDT 24
Finished Jun 04 02:03:08 PM PDT 24
Peak memory 217616 kb
Host smart-57ce6055-1dee-4fad-ae32-f1ba0c42f5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876774411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.876774411
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1030676031
Short name T392
Test name
Test status
Simulation time 14645833 ps
CPU time 0.74 seconds
Started Jun 04 02:03:03 PM PDT 24
Finished Jun 04 02:03:05 PM PDT 24
Peak memory 205336 kb
Host smart-a03bdfb6-aad1-4bb8-8848-c97c7e171056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030676031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1030676031
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1271957374
Short name T324
Test name
Test status
Simulation time 831487418 ps
CPU time 4.24 seconds
Started Jun 04 02:03:00 PM PDT 24
Finished Jun 04 02:03:06 PM PDT 24
Peak memory 218536 kb
Host smart-79dbba8e-f118-4baa-8b38-e84bca7f19f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271957374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1271957374
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1269575719
Short name T380
Test name
Test status
Simulation time 28221882 ps
CPU time 0.75 seconds
Started Jun 04 02:03:02 PM PDT 24
Finished Jun 04 02:03:04 PM PDT 24
Peak memory 205724 kb
Host smart-68afc849-f996-4ba9-b192-36257c0288d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269575719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1269575719
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3964100481
Short name T215
Test name
Test status
Simulation time 15470939011 ps
CPU time 118.81 seconds
Started Jun 04 02:03:02 PM PDT 24
Finished Jun 04 02:05:02 PM PDT 24
Peak memory 249052 kb
Host smart-f1981d84-32a7-43f0-8e46-af2d33669a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964100481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3964100481
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3157112451
Short name T656
Test name
Test status
Simulation time 4152887041 ps
CPU time 52.55 seconds
Started Jun 04 02:03:00 PM PDT 24
Finished Jun 04 02:03:53 PM PDT 24
Peak memory 253240 kb
Host smart-bab6673f-323f-4f21-ae30-cbb74250589f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157112451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3157112451
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1782768296
Short name T659
Test name
Test status
Simulation time 2403009190 ps
CPU time 7.1 seconds
Started Jun 04 02:03:02 PM PDT 24
Finished Jun 04 02:03:11 PM PDT 24
Peak memory 234376 kb
Host smart-d1ffbbc7-3d22-4e48-a8e8-2a5fe4dfce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782768296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1782768296
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2352523447
Short name T481
Test name
Test status
Simulation time 1138011015 ps
CPU time 18.43 seconds
Started Jun 04 02:03:01 PM PDT 24
Finished Jun 04 02:03:21 PM PDT 24
Peak memory 218676 kb
Host smart-83fb65bc-74af-4929-8002-930d1630514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352523447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2352523447
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.968464336
Short name T376
Test name
Test status
Simulation time 972903614 ps
CPU time 4.82 seconds
Started Jun 04 02:03:00 PM PDT 24
Finished Jun 04 02:03:05 PM PDT 24
Peak memory 218500 kb
Host smart-acc72c1a-6d82-468e-9b96-d961a083b23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968464336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.968464336
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.802577262
Short name T168
Test name
Test status
Simulation time 85351839 ps
CPU time 2.68 seconds
Started Jun 04 02:03:00 PM PDT 24
Finished Jun 04 02:03:04 PM PDT 24
Peak memory 233864 kb
Host smart-2ae31e25-a28d-48ae-9c65-9dff6f887e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802577262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.802577262
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3426181664
Short name T6
Test name
Test status
Simulation time 1066308085 ps
CPU time 9.64 seconds
Started Jun 04 02:03:02 PM PDT 24
Finished Jun 04 02:03:12 PM PDT 24
Peak memory 218880 kb
Host smart-a10694e0-6c92-49f0-ad2e-3f494a0d344b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3426181664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3426181664
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.593649810
Short name T280
Test name
Test status
Simulation time 10460184636 ps
CPU time 34.46 seconds
Started Jun 04 02:03:02 PM PDT 24
Finished Jun 04 02:03:38 PM PDT 24
Peak memory 232752 kb
Host smart-301dbef4-d403-4800-bb42-c695ac09186d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593649810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.593649810
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3538719967
Short name T421
Test name
Test status
Simulation time 5295846687 ps
CPU time 32.51 seconds
Started Jun 04 02:03:00 PM PDT 24
Finished Jun 04 02:03:33 PM PDT 24
Peak memory 216216 kb
Host smart-5b533d58-d791-409b-8e73-0ef94773fb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538719967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3538719967
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2629890468
Short name T605
Test name
Test status
Simulation time 1587322569 ps
CPU time 7.18 seconds
Started Jun 04 02:03:00 PM PDT 24
Finished Jun 04 02:03:08 PM PDT 24
Peak memory 215968 kb
Host smart-0c4bb834-f8be-437f-9cc6-973500d0b03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629890468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2629890468
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1489694455
Short name T374
Test name
Test status
Simulation time 110814413 ps
CPU time 0.87 seconds
Started Jun 04 02:03:02 PM PDT 24
Finished Jun 04 02:03:04 PM PDT 24
Peak memory 207764 kb
Host smart-8e726a8c-19f0-40d2-b387-996d89bbae33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489694455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1489694455
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2313886851
Short name T865
Test name
Test status
Simulation time 20402847 ps
CPU time 0.75 seconds
Started Jun 04 02:03:01 PM PDT 24
Finished Jun 04 02:03:03 PM PDT 24
Peak memory 205612 kb
Host smart-1edfc15b-5189-451c-b7ac-5db5ad35c403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313886851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2313886851
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1346676437
Short name T810
Test name
Test status
Simulation time 8161645405 ps
CPU time 14.88 seconds
Started Jun 04 02:03:03 PM PDT 24
Finished Jun 04 02:03:19 PM PDT 24
Peak memory 222012 kb
Host smart-436b13ae-2a8c-4766-880b-b8de6e99519f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346676437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1346676437
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1572947928
Short name T769
Test name
Test status
Simulation time 40952809 ps
CPU time 0.74 seconds
Started Jun 04 02:03:08 PM PDT 24
Finished Jun 04 02:03:11 PM PDT 24
Peak memory 205540 kb
Host smart-c51c919f-087c-4378-8960-9cc61a440de7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572947928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1572947928
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.824719564
Short name T71
Test name
Test status
Simulation time 573397131 ps
CPU time 5.36 seconds
Started Jun 04 02:03:08 PM PDT 24
Finished Jun 04 02:03:15 PM PDT 24
Peak memory 234116 kb
Host smart-ee397d82-6003-4c4f-8001-2bdae83a6c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824719564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.824719564
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3342055073
Short name T8
Test name
Test status
Simulation time 25459171 ps
CPU time 0.77 seconds
Started Jun 04 02:03:01 PM PDT 24
Finished Jun 04 02:03:03 PM PDT 24
Peak memory 206688 kb
Host smart-aac431fa-3939-45e5-81b9-758519a8b067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342055073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3342055073
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.914042235
Short name T142
Test name
Test status
Simulation time 42144648517 ps
CPU time 460.39 seconds
Started Jun 04 02:03:10 PM PDT 24
Finished Jun 04 02:10:51 PM PDT 24
Peak memory 262636 kb
Host smart-6da5be51-aafa-4180-aab7-ee24f17edfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914042235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.914042235
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.4190948054
Short name T179
Test name
Test status
Simulation time 10396707921 ps
CPU time 52.73 seconds
Started Jun 04 02:03:07 PM PDT 24
Finished Jun 04 02:04:01 PM PDT 24
Peak memory 249820 kb
Host smart-4bcc0044-ebfc-4de8-96e4-11b0661c89e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190948054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.4190948054
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3945022842
Short name T918
Test name
Test status
Simulation time 7327304566 ps
CPU time 30.53 seconds
Started Jun 04 02:03:11 PM PDT 24
Finished Jun 04 02:03:42 PM PDT 24
Peak memory 240080 kb
Host smart-6f7809ff-3670-4543-96b1-6551c5342b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945022842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3945022842
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.813825913
Short name T630
Test name
Test status
Simulation time 3738276493 ps
CPU time 9.39 seconds
Started Jun 04 02:03:07 PM PDT 24
Finished Jun 04 02:03:19 PM PDT 24
Peak memory 218444 kb
Host smart-57bc223d-55dd-4b79-a6c5-9f455413b245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813825913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.813825913
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.833024194
Short name T832
Test name
Test status
Simulation time 11309127570 ps
CPU time 21.5 seconds
Started Jun 04 02:03:06 PM PDT 24
Finished Jun 04 02:03:29 PM PDT 24
Peak memory 240076 kb
Host smart-4147a26c-e1d2-4fdb-a9e3-a4797bbc10da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833024194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.833024194
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1524465958
Short name T136
Test name
Test status
Simulation time 2418090148 ps
CPU time 3.44 seconds
Started Jun 04 02:03:07 PM PDT 24
Finished Jun 04 02:03:12 PM PDT 24
Peak memory 224356 kb
Host smart-9124df19-722c-40d8-8172-228972ebe12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524465958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1524465958
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2276605297
Short name T644
Test name
Test status
Simulation time 34334337380 ps
CPU time 9.15 seconds
Started Jun 04 02:03:08 PM PDT 24
Finished Jun 04 02:03:19 PM PDT 24
Peak memory 221288 kb
Host smart-3b77429f-0da2-47d3-9fea-05ba1e10ad31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276605297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2276605297
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3009996553
Short name T561
Test name
Test status
Simulation time 191009453 ps
CPU time 4.96 seconds
Started Jun 04 02:03:09 PM PDT 24
Finished Jun 04 02:03:15 PM PDT 24
Peak memory 222848 kb
Host smart-e1630a87-ceba-4710-9e4c-6e48b0f1404c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3009996553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3009996553
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.4162236231
Short name T867
Test name
Test status
Simulation time 11726263582 ps
CPU time 28.91 seconds
Started Jun 04 02:03:02 PM PDT 24
Finished Jun 04 02:03:32 PM PDT 24
Peak memory 216184 kb
Host smart-e064ee71-a9e6-461b-8023-7889d9688a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162236231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4162236231
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2847306551
Short name T703
Test name
Test status
Simulation time 2555150722 ps
CPU time 6.1 seconds
Started Jun 04 02:03:01 PM PDT 24
Finished Jun 04 02:03:08 PM PDT 24
Peak memory 216200 kb
Host smart-67e0a50d-d37a-4881-ab4a-b5fa6d7a1494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847306551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2847306551
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1237184026
Short name T134
Test name
Test status
Simulation time 12757651 ps
CPU time 0.73 seconds
Started Jun 04 02:03:07 PM PDT 24
Finished Jun 04 02:03:09 PM PDT 24
Peak memory 205476 kb
Host smart-e1bcdf5b-541c-4656-8766-15120445c91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237184026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1237184026
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2190646455
Short name T371
Test name
Test status
Simulation time 96232252 ps
CPU time 0.76 seconds
Started Jun 04 02:03:11 PM PDT 24
Finished Jun 04 02:03:13 PM PDT 24
Peak memory 205636 kb
Host smart-49103eef-21a1-4043-8089-a035dc53dac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190646455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2190646455
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1646255351
Short name T632
Test name
Test status
Simulation time 55590684 ps
CPU time 2.25 seconds
Started Jun 04 02:03:07 PM PDT 24
Finished Jun 04 02:03:11 PM PDT 24
Peak memory 212856 kb
Host smart-e902658a-a777-48b2-8e96-f8de7bab5a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646255351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1646255351
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2556661181
Short name T743
Test name
Test status
Simulation time 41319264 ps
CPU time 0.74 seconds
Started Jun 04 02:03:15 PM PDT 24
Finished Jun 04 02:03:17 PM PDT 24
Peak memory 205352 kb
Host smart-780b8c44-0242-4029-b6b7-6f7c315b3d7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556661181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2556661181
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2807962866
Short name T718
Test name
Test status
Simulation time 59056293 ps
CPU time 2.85 seconds
Started Jun 04 02:03:09 PM PDT 24
Finished Jun 04 02:03:13 PM PDT 24
Peak memory 232652 kb
Host smart-08c63580-56d5-4540-a67e-92c8c45ae4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807962866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2807962866
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3009559334
Short name T825
Test name
Test status
Simulation time 17834533 ps
CPU time 0.79 seconds
Started Jun 04 02:03:08 PM PDT 24
Finished Jun 04 02:03:10 PM PDT 24
Peak memory 206416 kb
Host smart-0a5a4ba2-e7d7-4ed9-ace7-a054a5b5f7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009559334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3009559334
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.991868263
Short name T514
Test name
Test status
Simulation time 52080401255 ps
CPU time 180.25 seconds
Started Jun 04 02:03:07 PM PDT 24
Finished Jun 04 02:06:09 PM PDT 24
Peak memory 252200 kb
Host smart-c4a5d30f-1342-4c15-bf86-97fa4f7e0eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991868263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.991868263
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.574960699
Short name T954
Test name
Test status
Simulation time 14427144142 ps
CPU time 167.89 seconds
Started Jun 04 02:03:13 PM PDT 24
Finished Jun 04 02:06:01 PM PDT 24
Peak memory 252452 kb
Host smart-71497cda-5f0a-42f3-bc94-e3bb91cda5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574960699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.574960699
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3606910367
Short name T746
Test name
Test status
Simulation time 1845297407 ps
CPU time 20.04 seconds
Started Jun 04 02:03:17 PM PDT 24
Finished Jun 04 02:03:38 PM PDT 24
Peak memory 224340 kb
Host smart-832bb823-42ef-45de-8ffd-3cbbb0f600b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606910367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3606910367
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3224008480
Short name T467
Test name
Test status
Simulation time 738953352 ps
CPU time 10.17 seconds
Started Jun 04 02:03:07 PM PDT 24
Finished Jun 04 02:03:19 PM PDT 24
Peak memory 219724 kb
Host smart-bf8d4c8c-2d6d-4f58-8d51-e716f5a7d219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224008480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3224008480
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.568081967
Short name T343
Test name
Test status
Simulation time 5848165903 ps
CPU time 18.28 seconds
Started Jun 04 02:03:09 PM PDT 24
Finished Jun 04 02:03:28 PM PDT 24
Peak memory 232512 kb
Host smart-eee0223c-018d-41f1-87fc-87f4b58d55ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568081967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.568081967
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1017925589
Short name T571
Test name
Test status
Simulation time 754770005 ps
CPU time 5.57 seconds
Started Jun 04 02:03:09 PM PDT 24
Finished Jun 04 02:03:16 PM PDT 24
Peak memory 223712 kb
Host smart-5045e3f3-d38b-4f9a-8157-961d4ea2e72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017925589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1017925589
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2495723484
Short name T596
Test name
Test status
Simulation time 35236828670 ps
CPU time 27.07 seconds
Started Jun 04 02:03:09 PM PDT 24
Finished Jun 04 02:03:37 PM PDT 24
Peak memory 248648 kb
Host smart-caf87c24-d314-4a13-8ace-5d0f3d6402bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495723484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2495723484
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.589730256
Short name T441
Test name
Test status
Simulation time 1598826797 ps
CPU time 18.84 seconds
Started Jun 04 02:03:08 PM PDT 24
Finished Jun 04 02:03:28 PM PDT 24
Peak memory 218976 kb
Host smart-c94aee7f-9b0b-4e59-b6cc-0fe3cb76d584
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=589730256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.589730256
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2391814699
Short name T154
Test name
Test status
Simulation time 5069093012 ps
CPU time 27.03 seconds
Started Jun 04 02:03:15 PM PDT 24
Finished Jun 04 02:03:43 PM PDT 24
Peak memory 224424 kb
Host smart-0aeaada7-2a08-4187-a497-9f87df62b5db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391814699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2391814699
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.347854668
Short name T765
Test name
Test status
Simulation time 7223352497 ps
CPU time 19.5 seconds
Started Jun 04 02:03:08 PM PDT 24
Finished Jun 04 02:03:29 PM PDT 24
Peak memory 216512 kb
Host smart-3346d817-9dcc-4d3a-bd12-0da6e6063b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347854668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.347854668
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3675199987
Short name T433
Test name
Test status
Simulation time 4615538555 ps
CPU time 13.37 seconds
Started Jun 04 02:03:07 PM PDT 24
Finished Jun 04 02:03:22 PM PDT 24
Peak memory 216108 kb
Host smart-8515f21e-63c6-4ae3-b47d-6659154e3142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675199987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3675199987
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2773447072
Short name T453
Test name
Test status
Simulation time 82367676 ps
CPU time 1.38 seconds
Started Jun 04 02:03:08 PM PDT 24
Finished Jun 04 02:03:11 PM PDT 24
Peak memory 216276 kb
Host smart-04cb0ece-84b3-4f6c-91b9-103b94984833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773447072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2773447072
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2477018791
Short name T485
Test name
Test status
Simulation time 12842972 ps
CPU time 0.74 seconds
Started Jun 04 02:03:07 PM PDT 24
Finished Jun 04 02:03:09 PM PDT 24
Peak memory 205616 kb
Host smart-ed3f3f9b-b435-4747-9433-39b1876c97cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477018791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2477018791
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1219429788
Short name T576
Test name
Test status
Simulation time 5655089994 ps
CPU time 18.01 seconds
Started Jun 04 02:03:07 PM PDT 24
Finished Jun 04 02:03:27 PM PDT 24
Peak memory 230084 kb
Host smart-ab80729e-2b2a-4759-9b02-cbc7e6266d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219429788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1219429788
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.351803181
Short name T912
Test name
Test status
Simulation time 27005123 ps
CPU time 0.71 seconds
Started Jun 04 02:03:17 PM PDT 24
Finished Jun 04 02:03:19 PM PDT 24
Peak memory 205420 kb
Host smart-357df000-d45a-42d6-9c08-f480c9209bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351803181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.351803181
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1226516788
Short name T228
Test name
Test status
Simulation time 1106398958 ps
CPU time 9.88 seconds
Started Jun 04 02:03:12 PM PDT 24
Finished Jun 04 02:03:22 PM PDT 24
Peak memory 234204 kb
Host smart-82dbce86-ec0f-4866-a3eb-81720a169016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226516788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1226516788
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2493852131
Short name T808
Test name
Test status
Simulation time 17443577 ps
CPU time 0.74 seconds
Started Jun 04 02:03:17 PM PDT 24
Finished Jun 04 02:03:18 PM PDT 24
Peak memory 205652 kb
Host smart-d1de592c-8f10-4fb7-9b06-1c274bd15f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493852131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2493852131
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4123684094
Short name T199
Test name
Test status
Simulation time 2745193756 ps
CPU time 50.54 seconds
Started Jun 04 02:03:15 PM PDT 24
Finished Jun 04 02:04:06 PM PDT 24
Peak memory 249012 kb
Host smart-3a589641-b4ad-46ca-9c4a-186f9d19c696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123684094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4123684094
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3681775592
Short name T46
Test name
Test status
Simulation time 15795330564 ps
CPU time 161.61 seconds
Started Jun 04 02:03:17 PM PDT 24
Finished Jun 04 02:05:59 PM PDT 24
Peak memory 251584 kb
Host smart-c4faeadf-55ef-46e7-a9c8-a86eafde5224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681775592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3681775592
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3378018476
Short name T544
Test name
Test status
Simulation time 16005099968 ps
CPU time 54.86 seconds
Started Jun 04 02:03:12 PM PDT 24
Finished Jun 04 02:04:08 PM PDT 24
Peak memory 235608 kb
Host smart-d169d67c-123e-484f-86df-8dd001d280c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378018476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3378018476
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.855922400
Short name T637
Test name
Test status
Simulation time 131205817 ps
CPU time 3.13 seconds
Started Jun 04 02:03:18 PM PDT 24
Finished Jun 04 02:03:22 PM PDT 24
Peak memory 232604 kb
Host smart-86344932-baca-40a9-994b-bdf124b62747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855922400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.855922400
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2175729014
Short name T293
Test name
Test status
Simulation time 10549869700 ps
CPU time 18.12 seconds
Started Jun 04 02:03:17 PM PDT 24
Finished Jun 04 02:03:36 PM PDT 24
Peak memory 220940 kb
Host smart-c8c57e72-40a1-4b48-9dda-305913494155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175729014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2175729014
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.615819256
Short name T183
Test name
Test status
Simulation time 2735307719 ps
CPU time 13.99 seconds
Started Jun 04 02:03:15 PM PDT 24
Finished Jun 04 02:03:30 PM PDT 24
Peak memory 232608 kb
Host smart-1c61a656-5614-416e-8fbe-43764c557c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615819256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.615819256
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.143055247
Short name T193
Test name
Test status
Simulation time 81379249372 ps
CPU time 31.39 seconds
Started Jun 04 02:03:15 PM PDT 24
Finished Jun 04 02:03:47 PM PDT 24
Peak memory 233380 kb
Host smart-ebe091a9-8d7d-43b2-89d3-6b21c4196fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143055247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.143055247
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1268342597
Short name T200
Test name
Test status
Simulation time 4593345200 ps
CPU time 6.48 seconds
Started Jun 04 02:03:14 PM PDT 24
Finished Jun 04 02:03:22 PM PDT 24
Peak memory 220200 kb
Host smart-364c6739-5f6d-4ffa-8647-ef046f5e3287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268342597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1268342597
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1380379434
Short name T579
Test name
Test status
Simulation time 251966549 ps
CPU time 5.68 seconds
Started Jun 04 02:03:15 PM PDT 24
Finished Jun 04 02:03:22 PM PDT 24
Peak memory 220180 kb
Host smart-ef6f06a2-ba36-43e2-aedb-f7f7b9d078f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1380379434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1380379434
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1577569033
Short name T452
Test name
Test status
Simulation time 484806762 ps
CPU time 9.97 seconds
Started Jun 04 02:03:16 PM PDT 24
Finished Jun 04 02:03:27 PM PDT 24
Peak memory 234584 kb
Host smart-512107e1-6222-4c34-a0a9-110996aac42e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577569033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1577569033
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.492010270
Short name T402
Test name
Test status
Simulation time 271730880 ps
CPU time 4.24 seconds
Started Jun 04 02:03:15 PM PDT 24
Finished Jun 04 02:03:20 PM PDT 24
Peak memory 216516 kb
Host smart-09e97c55-af84-4f2c-bd8e-b98b5bc9d130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492010270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.492010270
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2595730277
Short name T10
Test name
Test status
Simulation time 11674008823 ps
CPU time 15.93 seconds
Started Jun 04 02:03:16 PM PDT 24
Finished Jun 04 02:03:33 PM PDT 24
Peak memory 216052 kb
Host smart-643ee8b9-b223-434c-b5f7-091e358a6e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595730277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2595730277
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1693058977
Short name T766
Test name
Test status
Simulation time 206750732 ps
CPU time 1.1 seconds
Started Jun 04 02:03:13 PM PDT 24
Finished Jun 04 02:03:15 PM PDT 24
Peak memory 206916 kb
Host smart-03e16dec-30b3-4771-af7a-a59db4f0719c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693058977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1693058977
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3233379831
Short name T790
Test name
Test status
Simulation time 103475931 ps
CPU time 0.79 seconds
Started Jun 04 02:03:17 PM PDT 24
Finished Jun 04 02:03:19 PM PDT 24
Peak memory 205672 kb
Host smart-bc308b39-de5b-4899-99b6-c3233db3a5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233379831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3233379831
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.152941453
Short name T237
Test name
Test status
Simulation time 4954564043 ps
CPU time 6.24 seconds
Started Jun 04 02:03:15 PM PDT 24
Finished Jun 04 02:03:22 PM PDT 24
Peak memory 234440 kb
Host smart-7827e686-a101-4ade-98f8-249e924cdd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152941453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.152941453
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2613643350
Short name T953
Test name
Test status
Simulation time 13162941 ps
CPU time 0.71 seconds
Started Jun 04 02:03:20 PM PDT 24
Finished Jun 04 02:03:21 PM PDT 24
Peak memory 205348 kb
Host smart-e24df2b5-daba-4a38-9fcc-317a531878cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613643350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2613643350
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3811229984
Short name T466
Test name
Test status
Simulation time 122940201 ps
CPU time 2.43 seconds
Started Jun 04 02:03:19 PM PDT 24
Finished Jun 04 02:03:22 PM PDT 24
Peak memory 218452 kb
Host smart-cddd3119-6cdc-4578-9205-c7c23fc3e4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811229984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3811229984
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2693071940
Short name T759
Test name
Test status
Simulation time 68345974 ps
CPU time 0.73 seconds
Started Jun 04 02:03:14 PM PDT 24
Finished Jun 04 02:03:15 PM PDT 24
Peak memory 205428 kb
Host smart-b61236cb-a70b-4d12-9cbb-7eeb26925493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693071940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2693071940
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2931871604
Short name T332
Test name
Test status
Simulation time 1112898553 ps
CPU time 8.35 seconds
Started Jun 04 02:03:24 PM PDT 24
Finished Jun 04 02:03:34 PM PDT 24
Peak memory 233952 kb
Host smart-bda7b3c8-6ee2-4474-aa4b-8a14806ea71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931871604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2931871604
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3419162316
Short name T871
Test name
Test status
Simulation time 59650904980 ps
CPU time 298.92 seconds
Started Jun 04 02:03:26 PM PDT 24
Finished Jun 04 02:08:26 PM PDT 24
Peak memory 252484 kb
Host smart-24f7da3f-4e5f-46a5-a51f-bb6e5e24cc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419162316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3419162316
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.99090444
Short name T664
Test name
Test status
Simulation time 91152749214 ps
CPU time 176.56 seconds
Started Jun 04 02:03:22 PM PDT 24
Finished Jun 04 02:06:20 PM PDT 24
Peak memory 254996 kb
Host smart-d7b40d2d-a3ed-40e9-970f-b5747a73370d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99090444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.99090444
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.4075853034
Short name T39
Test name
Test status
Simulation time 386635724 ps
CPU time 6.16 seconds
Started Jun 04 02:03:21 PM PDT 24
Finished Jun 04 02:03:29 PM PDT 24
Peak memory 224356 kb
Host smart-67073ed4-e312-43cf-8ae6-41cc2577fb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075853034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.4075853034
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1427722091
Short name T919
Test name
Test status
Simulation time 83936979 ps
CPU time 3.48 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:03:28 PM PDT 24
Peak memory 218464 kb
Host smart-258d8732-768b-4d5d-b71f-848da7e21ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427722091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1427722091
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2436610570
Short name T323
Test name
Test status
Simulation time 7480538794 ps
CPU time 40.83 seconds
Started Jun 04 02:03:20 PM PDT 24
Finished Jun 04 02:04:02 PM PDT 24
Peak memory 238072 kb
Host smart-b21f11dc-7fb4-435d-8769-20b6785fd988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436610570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2436610570
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2244878239
Short name T823
Test name
Test status
Simulation time 4130323946 ps
CPU time 11.08 seconds
Started Jun 04 02:03:21 PM PDT 24
Finished Jun 04 02:03:34 PM PDT 24
Peak memory 232796 kb
Host smart-44eb0f66-de7f-4d07-a8c2-23f9602b6e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244878239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2244878239
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.4192982672
Short name T697
Test name
Test status
Simulation time 33018539 ps
CPU time 2.33 seconds
Started Jun 04 02:03:22 PM PDT 24
Finished Jun 04 02:03:26 PM PDT 24
Peak memory 220836 kb
Host smart-85c0c922-b808-43d6-b390-0c9e4f5d6c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192982672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.4192982672
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2822311620
Short name T586
Test name
Test status
Simulation time 1764132484 ps
CPU time 10.78 seconds
Started Jun 04 02:03:26 PM PDT 24
Finished Jun 04 02:03:38 PM PDT 24
Peak memory 222760 kb
Host smart-0a9cc5d8-03d4-4c8e-a9a9-2c1790c959ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2822311620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2822311620
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.349979628
Short name T160
Test name
Test status
Simulation time 14802409931 ps
CPU time 162.24 seconds
Started Jun 04 02:03:25 PM PDT 24
Finished Jun 04 02:06:08 PM PDT 24
Peak memory 249212 kb
Host smart-53acf673-9c87-40ce-81f7-07f22953b817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349979628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.349979628
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2455503487
Short name T722
Test name
Test status
Simulation time 8836711206 ps
CPU time 43.64 seconds
Started Jun 04 02:03:13 PM PDT 24
Finished Jun 04 02:03:57 PM PDT 24
Peak memory 216116 kb
Host smart-5f989943-7909-4d9a-89a9-c2cbabc79ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455503487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2455503487
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1035891849
Short name T529
Test name
Test status
Simulation time 640659333 ps
CPU time 1.57 seconds
Started Jun 04 02:03:13 PM PDT 24
Finished Jun 04 02:03:15 PM PDT 24
Peak memory 207516 kb
Host smart-0f6b45ed-febc-48bf-adeb-e4b88264c2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035891849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1035891849
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1610691158
Short name T425
Test name
Test status
Simulation time 49579737 ps
CPU time 0.86 seconds
Started Jun 04 02:03:22 PM PDT 24
Finished Jun 04 02:03:25 PM PDT 24
Peak memory 205776 kb
Host smart-53773cb1-7fce-4ca1-b616-7c5d2a71b2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610691158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1610691158
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3342142112
Short name T758
Test name
Test status
Simulation time 80699824 ps
CPU time 0.83 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:03:26 PM PDT 24
Peak memory 206648 kb
Host smart-8cb1ea27-0df7-4090-900b-163a7f0ed3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342142112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3342142112
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.797457231
Short name T456
Test name
Test status
Simulation time 9779948491 ps
CPU time 33.04 seconds
Started Jun 04 02:03:24 PM PDT 24
Finished Jun 04 02:03:58 PM PDT 24
Peak memory 238596 kb
Host smart-72a2821c-84d4-40f8-b561-45da13a2637a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797457231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.797457231
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4124757911
Short name T739
Test name
Test status
Simulation time 15756629 ps
CPU time 0.7 seconds
Started Jun 04 02:03:19 PM PDT 24
Finished Jun 04 02:03:21 PM PDT 24
Peak memory 204804 kb
Host smart-641eb7f2-17da-4a5a-8026-6d900189bba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124757911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4124757911
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4277792669
Short name T212
Test name
Test status
Simulation time 50342445 ps
CPU time 2.64 seconds
Started Jun 04 02:03:24 PM PDT 24
Finished Jun 04 02:03:28 PM PDT 24
Peak memory 236480 kb
Host smart-bd0b71df-8186-48df-88c3-b71b5774bf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277792669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4277792669
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2111210189
Short name T796
Test name
Test status
Simulation time 39949279 ps
CPU time 0.74 seconds
Started Jun 04 02:03:22 PM PDT 24
Finished Jun 04 02:03:24 PM PDT 24
Peak memory 206404 kb
Host smart-c117e6d4-901f-4495-8270-5fae6ed9749f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111210189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2111210189
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3255852205
Short name T572
Test name
Test status
Simulation time 7832118178 ps
CPU time 82.79 seconds
Started Jun 04 02:03:26 PM PDT 24
Finished Jun 04 02:04:50 PM PDT 24
Peak memory 249196 kb
Host smart-b4912624-0cfe-4146-99c2-dbe7d75a0daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255852205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3255852205
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1379719717
Short name T184
Test name
Test status
Simulation time 5498620488 ps
CPU time 57.09 seconds
Started Jun 04 02:03:24 PM PDT 24
Finished Jun 04 02:04:22 PM PDT 24
Peak memory 240732 kb
Host smart-fef8df2b-2d3d-461f-b32e-628ad226d190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379719717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1379719717
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1220835426
Short name T801
Test name
Test status
Simulation time 4561500275 ps
CPU time 7.99 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:03:32 PM PDT 24
Peak memory 219416 kb
Host smart-5ab3c511-8338-40cf-a5a1-c4dd3abc25ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220835426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1220835426
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2593586023
Short name T569
Test name
Test status
Simulation time 906204098 ps
CPU time 5.78 seconds
Started Jun 04 02:03:21 PM PDT 24
Finished Jun 04 02:03:27 PM PDT 24
Peak memory 220844 kb
Host smart-ad960220-4c0c-49ba-84aa-a38678e27f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593586023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2593586023
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2772831130
Short name T271
Test name
Test status
Simulation time 59081831 ps
CPU time 2.42 seconds
Started Jun 04 02:03:22 PM PDT 24
Finished Jun 04 02:03:26 PM PDT 24
Peak memory 233376 kb
Host smart-f49fdd1e-67a8-433f-9dab-256d5b4299ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772831130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2772831130
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1806038718
Short name T3
Test name
Test status
Simulation time 1101707903 ps
CPU time 6.76 seconds
Started Jun 04 02:03:21 PM PDT 24
Finished Jun 04 02:03:29 PM PDT 24
Peak memory 243824 kb
Host smart-ca3e5b8e-8a7e-4656-bde3-7f3ce76252e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806038718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1806038718
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2962359260
Short name T91
Test name
Test status
Simulation time 142795706 ps
CPU time 3.96 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:03:29 PM PDT 24
Peak memory 222328 kb
Host smart-a16d2c8e-6627-4b1a-95ce-57b03026f450
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2962359260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2962359260
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.461087653
Short name T156
Test name
Test status
Simulation time 17231159673 ps
CPU time 66.64 seconds
Started Jun 04 02:03:21 PM PDT 24
Finished Jun 04 02:04:29 PM PDT 24
Peak memory 256524 kb
Host smart-0afadfbb-f16d-482d-8a65-2a1a06adadde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461087653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.461087653
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2798519846
Short name T359
Test name
Test status
Simulation time 149064575 ps
CPU time 0.69 seconds
Started Jun 04 02:03:21 PM PDT 24
Finished Jun 04 02:03:22 PM PDT 24
Peak memory 205520 kb
Host smart-26bab38b-f8c9-4f1b-97fb-7bcf3a0a2694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798519846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2798519846
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3173337971
Short name T88
Test name
Test status
Simulation time 28602801958 ps
CPU time 21.11 seconds
Started Jun 04 02:03:22 PM PDT 24
Finished Jun 04 02:03:44 PM PDT 24
Peak memory 216156 kb
Host smart-488d65ce-0e5d-4f5b-bdb7-83851054d693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173337971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3173337971
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3619779103
Short name T412
Test name
Test status
Simulation time 174088022 ps
CPU time 0.93 seconds
Started Jun 04 02:03:22 PM PDT 24
Finished Jun 04 02:03:25 PM PDT 24
Peak memory 206764 kb
Host smart-fbfd8311-6351-449b-83f6-c43eabbcbfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619779103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3619779103
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3698533012
Short name T671
Test name
Test status
Simulation time 157577452 ps
CPU time 0.81 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:03:25 PM PDT 24
Peak memory 205636 kb
Host smart-da7531f5-ac0e-463b-a554-5ab0dbd7638b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698533012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3698533012
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3357272879
Short name T326
Test name
Test status
Simulation time 1381466257 ps
CPU time 4.4 seconds
Started Jun 04 02:03:22 PM PDT 24
Finished Jun 04 02:03:28 PM PDT 24
Peak memory 236592 kb
Host smart-1d832b46-12b9-49a5-8d18-6f019fd2b01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357272879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3357272879
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.804848320
Short name T952
Test name
Test status
Simulation time 11403460 ps
CPU time 0.73 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:03:26 PM PDT 24
Peak memory 205672 kb
Host smart-dd8efbc7-eaf3-47a2-bd6f-9eb8b2e5231d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804848320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.804848320
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1073458810
Short name T701
Test name
Test status
Simulation time 9002083041 ps
CPU time 25.19 seconds
Started Jun 04 02:03:25 PM PDT 24
Finished Jun 04 02:03:51 PM PDT 24
Peak memory 234104 kb
Host smart-3081f8dd-c47a-4402-9e1c-0ed32e24dc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073458810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1073458810
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.629380121
Short name T795
Test name
Test status
Simulation time 29894921 ps
CPU time 0.77 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:03:25 PM PDT 24
Peak memory 206356 kb
Host smart-6b936aa6-865f-4774-918a-0771914b952f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629380121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.629380121
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.565246917
Short name T298
Test name
Test status
Simulation time 15593501307 ps
CPU time 74.27 seconds
Started Jun 04 02:03:25 PM PDT 24
Finished Jun 04 02:04:40 PM PDT 24
Peak memory 262516 kb
Host smart-13a5f404-a59f-4122-ab3a-c1518ceb6a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565246917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.565246917
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1658041967
Short name T294
Test name
Test status
Simulation time 2006414320 ps
CPU time 30.09 seconds
Started Jun 04 02:03:26 PM PDT 24
Finished Jun 04 02:03:57 PM PDT 24
Peak memory 240544 kb
Host smart-47d05960-b93e-4608-9f83-6e8dd76e2f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658041967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1658041967
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3948891869
Short name T321
Test name
Test status
Simulation time 1861862920 ps
CPU time 42.67 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:04:07 PM PDT 24
Peak memory 253820 kb
Host smart-deceedd6-d460-469e-92bf-1e427e7d4f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948891869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3948891869
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2029504179
Short name T434
Test name
Test status
Simulation time 177359192 ps
CPU time 2.84 seconds
Started Jun 04 02:03:20 PM PDT 24
Finished Jun 04 02:03:23 PM PDT 24
Peak memory 232560 kb
Host smart-44638066-76e3-4bf9-bea1-6970c6028307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029504179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2029504179
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.605883277
Short name T335
Test name
Test status
Simulation time 454497909 ps
CPU time 5.04 seconds
Started Jun 04 02:03:20 PM PDT 24
Finished Jun 04 02:03:26 PM PDT 24
Peak memory 219272 kb
Host smart-55d6a4fe-81ba-4a7c-aac8-eea638b82992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605883277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.605883277
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1540171013
Short name T316
Test name
Test status
Simulation time 4394497889 ps
CPU time 8.93 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:03:33 PM PDT 24
Peak memory 237880 kb
Host smart-e208c83b-392e-4230-b95b-328f6754196d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540171013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1540171013
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1957920038
Short name T592
Test name
Test status
Simulation time 115623109 ps
CPU time 2.56 seconds
Started Jun 04 02:03:21 PM PDT 24
Finished Jun 04 02:03:24 PM PDT 24
Peak memory 221408 kb
Host smart-77c2078e-1620-49da-8e19-20699016b0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957920038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1957920038
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3001212443
Short name T930
Test name
Test status
Simulation time 201317505 ps
CPU time 2.41 seconds
Started Jun 04 02:03:22 PM PDT 24
Finished Jun 04 02:03:26 PM PDT 24
Peak memory 233128 kb
Host smart-a1b635ed-eb2e-43ab-8637-ed815b04ed30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001212443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3001212443
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.792387903
Short name T875
Test name
Test status
Simulation time 334432654 ps
CPU time 3.32 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:03:27 PM PDT 24
Peak memory 219224 kb
Host smart-bd9951b3-a59e-42d9-9d55-e940401cb53f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=792387903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.792387903
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1190339918
Short name T797
Test name
Test status
Simulation time 62557780 ps
CPU time 0.95 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:03:25 PM PDT 24
Peak memory 207136 kb
Host smart-8a73fbe7-5c46-48f5-b826-07f4c40a58b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190339918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1190339918
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.358148799
Short name T957
Test name
Test status
Simulation time 3120309486 ps
CPU time 19.21 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:03:44 PM PDT 24
Peak memory 216252 kb
Host smart-721f1566-5dc8-4098-bb30-de3d86143601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358148799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.358148799
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.746696235
Short name T876
Test name
Test status
Simulation time 2220929691 ps
CPU time 4.85 seconds
Started Jun 04 02:03:22 PM PDT 24
Finished Jun 04 02:03:28 PM PDT 24
Peak memory 216204 kb
Host smart-946d5532-59c3-4ef8-ae0e-54df08af8846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746696235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.746696235
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2475711829
Short name T616
Test name
Test status
Simulation time 51275127 ps
CPU time 0.68 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:03:25 PM PDT 24
Peak memory 205412 kb
Host smart-c4d3f975-941c-4174-8146-a03462468213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475711829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2475711829
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1634329073
Short name T657
Test name
Test status
Simulation time 60411595 ps
CPU time 0.85 seconds
Started Jun 04 02:03:24 PM PDT 24
Finished Jun 04 02:03:26 PM PDT 24
Peak memory 205620 kb
Host smart-da361738-0e45-4e11-9d43-0ad9b504815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634329073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1634329073
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1091358152
Short name T528
Test name
Test status
Simulation time 473135168 ps
CPU time 3.8 seconds
Started Jun 04 02:03:22 PM PDT 24
Finished Jun 04 02:03:28 PM PDT 24
Peak memory 235904 kb
Host smart-50d4d092-66de-45e4-9d05-631335a831a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091358152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1091358152
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3067492729
Short name T700
Test name
Test status
Simulation time 15088088 ps
CPU time 0.71 seconds
Started Jun 04 02:01:28 PM PDT 24
Finished Jun 04 02:01:30 PM PDT 24
Peak memory 205432 kb
Host smart-ff8cec56-4caa-48ac-a094-cce95c85bc92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067492729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
067492729
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2168240723
Short name T587
Test name
Test status
Simulation time 205370167 ps
CPU time 3.39 seconds
Started Jun 04 02:01:26 PM PDT 24
Finished Jun 04 02:01:31 PM PDT 24
Peak memory 219872 kb
Host smart-ad3e6620-e932-4a95-ad54-e9d22a31de92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168240723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2168240723
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.242478452
Short name T19
Test name
Test status
Simulation time 14703550 ps
CPU time 0.76 seconds
Started Jun 04 02:01:29 PM PDT 24
Finished Jun 04 02:01:31 PM PDT 24
Peak memory 205336 kb
Host smart-ece225f6-8607-44f1-9c3f-e67f2bf4ab33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242478452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.242478452
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.68424007
Short name T560
Test name
Test status
Simulation time 189633404277 ps
CPU time 163.35 seconds
Started Jun 04 02:01:29 PM PDT 24
Finished Jun 04 02:04:13 PM PDT 24
Peak memory 249068 kb
Host smart-1aab246a-7bb9-4251-affb-cd395080d6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68424007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.68424007
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.832620097
Short name T25
Test name
Test status
Simulation time 60361463796 ps
CPU time 304.35 seconds
Started Jun 04 02:01:32 PM PDT 24
Finished Jun 04 02:06:37 PM PDT 24
Peak memory 253104 kb
Host smart-c6098590-75f2-4fdf-a025-9f3c74b8192d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832620097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.832620097
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2196589447
Short name T180
Test name
Test status
Simulation time 8026379079 ps
CPU time 57.89 seconds
Started Jun 04 02:01:28 PM PDT 24
Finished Jun 04 02:02:27 PM PDT 24
Peak memory 253388 kb
Host smart-58925d4f-f954-44cb-9c01-04029171d07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196589447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2196589447
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.101606680
Short name T353
Test name
Test status
Simulation time 635280066 ps
CPU time 3.72 seconds
Started Jun 04 02:01:28 PM PDT 24
Finished Jun 04 02:01:33 PM PDT 24
Peak memory 224272 kb
Host smart-61c26e61-06dd-4866-bddf-211d2440bb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101606680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.101606680
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.124442044
Short name T300
Test name
Test status
Simulation time 124068111 ps
CPU time 3.39 seconds
Started Jun 04 02:01:26 PM PDT 24
Finished Jun 04 02:01:31 PM PDT 24
Peak memory 219608 kb
Host smart-feb1b856-1e73-44ba-8b8d-514f0ef5616a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124442044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.124442044
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2036939617
Short name T799
Test name
Test status
Simulation time 472063111 ps
CPU time 2.18 seconds
Started Jun 04 02:01:25 PM PDT 24
Finished Jun 04 02:01:28 PM PDT 24
Peak memory 232664 kb
Host smart-86f04e5c-a6ec-42f0-b159-fd414d3ed8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036939617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2036939617
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3415985147
Short name T859
Test name
Test status
Simulation time 3341739834 ps
CPU time 11.98 seconds
Started Jun 04 02:01:27 PM PDT 24
Finished Jun 04 02:01:40 PM PDT 24
Peak memory 218340 kb
Host smart-2494142d-e803-4c53-b494-3f376f6fb50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415985147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3415985147
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2386454746
Short name T688
Test name
Test status
Simulation time 484516391 ps
CPU time 4.35 seconds
Started Jun 04 02:01:27 PM PDT 24
Finished Jun 04 02:01:33 PM PDT 24
Peak memory 218008 kb
Host smart-61664164-077a-4235-bfc5-9522f96cd52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386454746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2386454746
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1545997729
Short name T674
Test name
Test status
Simulation time 932952514 ps
CPU time 9.45 seconds
Started Jun 04 02:01:32 PM PDT 24
Finished Jun 04 02:01:42 PM PDT 24
Peak memory 220104 kb
Host smart-954702b2-f4b6-4862-8d66-de90dc589f17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1545997729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1545997729
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.434403815
Short name T70
Test name
Test status
Simulation time 343751292 ps
CPU time 1.13 seconds
Started Jun 04 02:01:28 PM PDT 24
Finished Jun 04 02:01:31 PM PDT 24
Peak memory 235212 kb
Host smart-183f51fb-47e9-4841-9863-21ddd0196bdf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434403815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.434403815
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1452111126
Short name T574
Test name
Test status
Simulation time 2655615200 ps
CPU time 11.01 seconds
Started Jun 04 02:01:27 PM PDT 24
Finished Jun 04 02:01:40 PM PDT 24
Peak memory 216200 kb
Host smart-b5f948fb-1bd9-4243-81e9-f492770b7faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452111126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1452111126
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2059150651
Short name T379
Test name
Test status
Simulation time 599713703 ps
CPU time 3.05 seconds
Started Jun 04 02:01:27 PM PDT 24
Finished Jun 04 02:01:32 PM PDT 24
Peak memory 216144 kb
Host smart-ebcbdfa8-1cc5-4181-9416-bbd22790c050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059150651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2059150651
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3099397292
Short name T373
Test name
Test status
Simulation time 96272087 ps
CPU time 1.86 seconds
Started Jun 04 02:01:25 PM PDT 24
Finished Jun 04 02:01:28 PM PDT 24
Peak memory 216188 kb
Host smart-5a0524a8-162b-44b0-bfcb-2cd27c2ee19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099397292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3099397292
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2879941866
Short name T665
Test name
Test status
Simulation time 241071626 ps
CPU time 0.78 seconds
Started Jun 04 02:01:24 PM PDT 24
Finished Jun 04 02:01:25 PM PDT 24
Peak memory 205560 kb
Host smart-7109a27b-0a46-4d26-9039-8a5af7214249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879941866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2879941866
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4003468124
Short name T473
Test name
Test status
Simulation time 476542518 ps
CPU time 2.88 seconds
Started Jun 04 02:01:38 PM PDT 24
Finished Jun 04 02:01:42 PM PDT 24
Peak memory 235968 kb
Host smart-2e3c9f67-4077-4a0e-a21a-d263f58a51d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003468124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4003468124
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3912241367
Short name T372
Test name
Test status
Simulation time 12201860 ps
CPU time 0.72 seconds
Started Jun 04 02:03:31 PM PDT 24
Finished Jun 04 02:03:32 PM PDT 24
Peak memory 205308 kb
Host smart-7e37f2d7-ac9f-4113-ab2b-a426f63a805f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912241367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3912241367
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.791810802
Short name T240
Test name
Test status
Simulation time 1546442494 ps
CPU time 17.49 seconds
Started Jun 04 02:03:29 PM PDT 24
Finished Jun 04 02:03:47 PM PDT 24
Peak memory 234592 kb
Host smart-104bbbd8-b958-4568-99d6-270b7b2613a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791810802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.791810802
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.906859486
Short name T427
Test name
Test status
Simulation time 15662121 ps
CPU time 0.76 seconds
Started Jun 04 02:03:21 PM PDT 24
Finished Jun 04 02:03:23 PM PDT 24
Peak memory 205312 kb
Host smart-a408d46f-0167-4cd9-9070-b762ac1d92ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906859486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.906859486
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2598347586
Short name T304
Test name
Test status
Simulation time 104228099398 ps
CPU time 179.65 seconds
Started Jun 04 02:03:32 PM PDT 24
Finished Jun 04 02:06:33 PM PDT 24
Peak memory 249280 kb
Host smart-6a377599-9219-4b92-ac84-b3138f14ab43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598347586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2598347586
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.942429444
Short name T245
Test name
Test status
Simulation time 127308448173 ps
CPU time 162.02 seconds
Started Jun 04 02:03:34 PM PDT 24
Finished Jun 04 02:06:16 PM PDT 24
Peak memory 264968 kb
Host smart-8314b1c4-8454-4688-95c6-86bc6c494e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942429444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.942429444
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.181311474
Short name T582
Test name
Test status
Simulation time 32817835511 ps
CPU time 65.47 seconds
Started Jun 04 02:03:28 PM PDT 24
Finished Jun 04 02:04:35 PM PDT 24
Peak memory 224488 kb
Host smart-2473a6c8-e8b9-49c6-914c-6d7b1a467436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181311474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.181311474
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.263200994
Short name T524
Test name
Test status
Simulation time 180707747 ps
CPU time 4.81 seconds
Started Jun 04 02:03:28 PM PDT 24
Finished Jun 04 02:03:34 PM PDT 24
Peak memory 224344 kb
Host smart-a9a8230a-6698-4063-bffa-e0bc6564449c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263200994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.263200994
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4104214945
Short name T470
Test name
Test status
Simulation time 605511745 ps
CPU time 4.46 seconds
Started Jun 04 02:03:30 PM PDT 24
Finished Jun 04 02:03:36 PM PDT 24
Peak memory 232928 kb
Host smart-323e292e-9591-451a-8f96-fd9e2d1b3da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104214945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4104214945
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3018294608
Short name T414
Test name
Test status
Simulation time 778009078 ps
CPU time 4.7 seconds
Started Jun 04 02:03:30 PM PDT 24
Finished Jun 04 02:03:36 PM PDT 24
Peak memory 224384 kb
Host smart-0fcb4cf6-d767-49f2-b001-83554903a496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018294608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3018294608
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2134461558
Short name T521
Test name
Test status
Simulation time 4167704963 ps
CPU time 14.67 seconds
Started Jun 04 02:03:28 PM PDT 24
Finished Jun 04 02:03:44 PM PDT 24
Peak memory 220028 kb
Host smart-61d2dbcb-509a-4f6c-b466-65df829bc2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134461558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2134461558
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2658033635
Short name T742
Test name
Test status
Simulation time 8573317664 ps
CPU time 24.83 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:03:49 PM PDT 24
Peak memory 240328 kb
Host smart-e97d2ef0-710e-49e4-8318-f63e1d936ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658033635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2658033635
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.494355331
Short name T493
Test name
Test status
Simulation time 2068813930 ps
CPU time 7.69 seconds
Started Jun 04 02:03:30 PM PDT 24
Finished Jun 04 02:03:38 PM PDT 24
Peak memory 221200 kb
Host smart-2ddc5b62-e791-40df-a8f9-32d5472d72d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=494355331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.494355331
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3519236046
Short name T846
Test name
Test status
Simulation time 60841441840 ps
CPU time 603.13 seconds
Started Jun 04 02:03:31 PM PDT 24
Finished Jun 04 02:13:36 PM PDT 24
Peak memory 266964 kb
Host smart-d6de27b1-d3ea-407c-b7b4-3be14f72b1a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519236046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3519236046
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1990574240
Short name T887
Test name
Test status
Simulation time 1340448777 ps
CPU time 17.58 seconds
Started Jun 04 02:03:25 PM PDT 24
Finished Jun 04 02:03:43 PM PDT 24
Peak memory 216264 kb
Host smart-d5f88845-1adc-4a2f-89f1-cb71ff4253dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990574240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1990574240
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3939196139
Short name T449
Test name
Test status
Simulation time 16386905738 ps
CPU time 9.34 seconds
Started Jun 04 02:03:22 PM PDT 24
Finished Jun 04 02:03:32 PM PDT 24
Peak memory 216220 kb
Host smart-8f5009d4-64d3-4103-b2d8-17c341e66afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939196139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3939196139
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2618993095
Short name T503
Test name
Test status
Simulation time 166519885 ps
CPU time 6.53 seconds
Started Jun 04 02:03:23 PM PDT 24
Finished Jun 04 02:03:31 PM PDT 24
Peak memory 216344 kb
Host smart-e25a7d23-286c-41f9-9a96-8debe7db47c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618993095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2618993095
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.177211262
Short name T557
Test name
Test status
Simulation time 129009703 ps
CPU time 0.93 seconds
Started Jun 04 02:03:25 PM PDT 24
Finished Jun 04 02:03:27 PM PDT 24
Peak memory 205984 kb
Host smart-e1341653-28b0-4fd9-961d-006ce362eb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177211262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.177211262
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.810042758
Short name T411
Test name
Test status
Simulation time 160181488 ps
CPU time 2.46 seconds
Started Jun 04 02:03:29 PM PDT 24
Finished Jun 04 02:03:33 PM PDT 24
Peak memory 232588 kb
Host smart-0edcd4c6-f353-42b8-be52-ff97ce72d122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810042758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.810042758
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1122384342
Short name T927
Test name
Test status
Simulation time 17857857 ps
CPU time 0.77 seconds
Started Jun 04 02:03:30 PM PDT 24
Finished Jun 04 02:03:31 PM PDT 24
Peak memory 205368 kb
Host smart-d0387867-6470-4ea5-89ea-9eae63eec2e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122384342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1122384342
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.282436143
Short name T773
Test name
Test status
Simulation time 660960393 ps
CPU time 8.79 seconds
Started Jun 04 02:03:28 PM PDT 24
Finished Jun 04 02:03:38 PM PDT 24
Peak memory 233592 kb
Host smart-a392369d-9ce0-45e8-bab6-37b5cb69712b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282436143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.282436143
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3502002596
Short name T921
Test name
Test status
Simulation time 25925523 ps
CPU time 0.77 seconds
Started Jun 04 02:03:32 PM PDT 24
Finished Jun 04 02:03:34 PM PDT 24
Peak memory 205356 kb
Host smart-63538955-ed06-4ce5-a7c2-18ff2503e518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502002596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3502002596
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3441198711
Short name T273
Test name
Test status
Simulation time 30522244256 ps
CPU time 199.57 seconds
Started Jun 04 02:03:28 PM PDT 24
Finished Jun 04 02:06:49 PM PDT 24
Peak memory 240792 kb
Host smart-32b53476-3fff-49a4-a4a1-a78154279afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441198711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3441198711
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2209343008
Short name T532
Test name
Test status
Simulation time 6934499333 ps
CPU time 57.22 seconds
Started Jun 04 02:03:31 PM PDT 24
Finished Jun 04 02:04:30 PM PDT 24
Peak memory 255464 kb
Host smart-172aafc8-8625-41ec-8acf-85f5ec891e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209343008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2209343008
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1902607989
Short name T633
Test name
Test status
Simulation time 5231432055 ps
CPU time 71.37 seconds
Started Jun 04 02:03:32 PM PDT 24
Finished Jun 04 02:04:45 PM PDT 24
Peak memory 240872 kb
Host smart-43f33386-b942-4727-86aa-cea06c94f51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902607989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1902607989
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.548809673
Short name T1
Test name
Test status
Simulation time 3794409748 ps
CPU time 15.57 seconds
Started Jun 04 02:03:28 PM PDT 24
Finished Jun 04 02:03:45 PM PDT 24
Peak memory 232548 kb
Host smart-d5520bf7-7cdf-4325-b777-64a57ecfa888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548809673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.548809673
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4103868448
Short name T296
Test name
Test status
Simulation time 1608246441 ps
CPU time 7.13 seconds
Started Jun 04 02:03:27 PM PDT 24
Finished Jun 04 02:03:36 PM PDT 24
Peak memory 233336 kb
Host smart-d1e44585-f7f0-4ca9-a14d-61e02a6baeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103868448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4103868448
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2368222399
Short name T171
Test name
Test status
Simulation time 9085200962 ps
CPU time 31.38 seconds
Started Jun 04 02:03:32 PM PDT 24
Finished Jun 04 02:04:04 PM PDT 24
Peak memory 225924 kb
Host smart-c3375358-e013-4152-9de6-48bda22cbb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368222399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2368222399
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3662940402
Short name T499
Test name
Test status
Simulation time 2586358917 ps
CPU time 8.54 seconds
Started Jun 04 02:03:29 PM PDT 24
Finished Jun 04 02:03:38 PM PDT 24
Peak memory 233508 kb
Host smart-1d733789-5f60-4736-93c6-2aff0e5808a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662940402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3662940402
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.395686192
Short name T877
Test name
Test status
Simulation time 457413171 ps
CPU time 3.61 seconds
Started Jun 04 02:03:33 PM PDT 24
Finished Jun 04 02:03:38 PM PDT 24
Peak memory 222468 kb
Host smart-db67afc6-45ae-4791-883f-8984e646970b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=395686192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.395686192
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2387913345
Short name T949
Test name
Test status
Simulation time 7401631824 ps
CPU time 73.04 seconds
Started Jun 04 02:03:32 PM PDT 24
Finished Jun 04 02:04:46 PM PDT 24
Peak memory 249180 kb
Host smart-533e78a7-5e18-4060-bf50-8d3ee7ef2284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387913345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2387913345
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1748673049
Short name T406
Test name
Test status
Simulation time 3814816913 ps
CPU time 5.25 seconds
Started Jun 04 02:03:28 PM PDT 24
Finished Jun 04 02:03:34 PM PDT 24
Peak memory 216376 kb
Host smart-3bfa3617-033a-477d-8b96-4d5284e10f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748673049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1748673049
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2222266454
Short name T428
Test name
Test status
Simulation time 1666192416 ps
CPU time 4.04 seconds
Started Jun 04 02:03:30 PM PDT 24
Finished Jun 04 02:03:34 PM PDT 24
Peak memory 215992 kb
Host smart-c8d69a88-38d2-4c27-b14d-32473c5402fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222266454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2222266454
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1120930590
Short name T545
Test name
Test status
Simulation time 1037757680 ps
CPU time 1.1 seconds
Started Jun 04 02:03:32 PM PDT 24
Finished Jun 04 02:03:34 PM PDT 24
Peak memory 206712 kb
Host smart-c67627f1-87ef-4f9b-b93a-72e809de6ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120930590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1120930590
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.551909551
Short name T515
Test name
Test status
Simulation time 87777844 ps
CPU time 0.72 seconds
Started Jun 04 02:03:28 PM PDT 24
Finished Jun 04 02:03:30 PM PDT 24
Peak memory 205600 kb
Host smart-fdced299-3ff7-40dc-8566-3925bed99a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551909551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.551909551
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2696309689
Short name T465
Test name
Test status
Simulation time 15099675785 ps
CPU time 7.89 seconds
Started Jun 04 02:03:29 PM PDT 24
Finished Jun 04 02:03:38 PM PDT 24
Peak memory 222060 kb
Host smart-22bf6f99-b684-4108-8700-d536ec306019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696309689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2696309689
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1213424547
Short name T935
Test name
Test status
Simulation time 39661159 ps
CPU time 0.7 seconds
Started Jun 04 02:03:32 PM PDT 24
Finished Jun 04 02:03:34 PM PDT 24
Peak memory 204840 kb
Host smart-44888764-eb6a-4e7d-a5fe-e8b1edb36054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213424547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1213424547
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1429663220
Short name T895
Test name
Test status
Simulation time 420344205 ps
CPU time 2.19 seconds
Started Jun 04 02:03:31 PM PDT 24
Finished Jun 04 02:03:34 PM PDT 24
Peak memory 215988 kb
Host smart-63eddf2f-a91a-4bb2-b8a2-c317ae9aa6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429663220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1429663220
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.44738321
Short name T708
Test name
Test status
Simulation time 107104127 ps
CPU time 0.75 seconds
Started Jun 04 02:03:31 PM PDT 24
Finished Jun 04 02:03:33 PM PDT 24
Peak memory 206668 kb
Host smart-4e917c67-eae1-4cf3-8f9d-bdbd672de302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44738321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.44738321
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3761279640
Short name T407
Test name
Test status
Simulation time 992245264 ps
CPU time 4.08 seconds
Started Jun 04 02:03:28 PM PDT 24
Finished Jun 04 02:03:33 PM PDT 24
Peak memory 240784 kb
Host smart-ab6a53fb-da7c-472b-80f8-58af82b492b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761279640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3761279640
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4068043371
Short name T837
Test name
Test status
Simulation time 38024894117 ps
CPU time 64.18 seconds
Started Jun 04 02:03:33 PM PDT 24
Finished Jun 04 02:04:38 PM PDT 24
Peak memory 249136 kb
Host smart-347aa41a-637d-455a-b48f-46a8effcbd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068043371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4068043371
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2143256633
Short name T681
Test name
Test status
Simulation time 8879766621 ps
CPU time 60.14 seconds
Started Jun 04 02:03:35 PM PDT 24
Finished Jun 04 02:04:35 PM PDT 24
Peak memory 239668 kb
Host smart-9559c1a2-617f-4ad0-b4e3-5ac96abc37db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143256633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2143256633
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1267191675
Short name T446
Test name
Test status
Simulation time 973071438 ps
CPU time 6.52 seconds
Started Jun 04 02:03:34 PM PDT 24
Finished Jun 04 02:03:41 PM PDT 24
Peak memory 232624 kb
Host smart-09d9debd-1776-4cef-8ef8-15971e6cc33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267191675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1267191675
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.862692026
Short name T377
Test name
Test status
Simulation time 867156277 ps
CPU time 5.76 seconds
Started Jun 04 02:03:29 PM PDT 24
Finished Jun 04 02:03:35 PM PDT 24
Peak memory 233468 kb
Host smart-e14e39bf-5ed9-4641-b425-51b7f9a85858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862692026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.862692026
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1754579773
Short name T794
Test name
Test status
Simulation time 647915050 ps
CPU time 8.8 seconds
Started Jun 04 02:03:33 PM PDT 24
Finished Jun 04 02:03:43 PM PDT 24
Peak memory 232392 kb
Host smart-c48cc3cd-710c-4aa0-ae74-3f0eb187dfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754579773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1754579773
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1145012186
Short name T182
Test name
Test status
Simulation time 2155356990 ps
CPU time 4.24 seconds
Started Jun 04 02:03:27 PM PDT 24
Finished Jun 04 02:03:31 PM PDT 24
Peak memory 218420 kb
Host smart-26491903-ec96-44b0-86fe-20f53393b912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145012186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1145012186
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1277713609
Short name T649
Test name
Test status
Simulation time 355679964 ps
CPU time 2.13 seconds
Started Jun 04 02:03:30 PM PDT 24
Finished Jun 04 02:03:34 PM PDT 24
Peak memory 215984 kb
Host smart-0c5bd9b9-5f0e-47af-82b8-2165979b35fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277713609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1277713609
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3325128198
Short name T749
Test name
Test status
Simulation time 952642770 ps
CPU time 4.62 seconds
Started Jun 04 02:03:30 PM PDT 24
Finished Jun 04 02:03:35 PM PDT 24
Peak memory 222020 kb
Host smart-b9f7daa0-92ab-480d-ab03-1b3f0d7f47ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3325128198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3325128198
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.214454759
Short name T415
Test name
Test status
Simulation time 14003809096 ps
CPU time 134.6 seconds
Started Jun 04 02:03:29 PM PDT 24
Finished Jun 04 02:05:45 PM PDT 24
Peak memory 249072 kb
Host smart-cf4fae09-ea5a-4a1b-9b26-b0c58c40aa58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214454759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.214454759
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2787026704
Short name T717
Test name
Test status
Simulation time 4897639561 ps
CPU time 32.18 seconds
Started Jun 04 02:03:31 PM PDT 24
Finished Jun 04 02:04:04 PM PDT 24
Peak memory 216224 kb
Host smart-a877e60c-d77e-4da0-bcfe-215dd1f8c43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787026704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2787026704
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.486919671
Short name T650
Test name
Test status
Simulation time 1352085606 ps
CPU time 4.75 seconds
Started Jun 04 02:03:28 PM PDT 24
Finished Jun 04 02:03:33 PM PDT 24
Peak memory 216092 kb
Host smart-9ad0e9c8-5602-4ecf-af39-af8d3b64606d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486919671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.486919671
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3957907900
Short name T547
Test name
Test status
Simulation time 154714694 ps
CPU time 8.06 seconds
Started Jun 04 02:03:30 PM PDT 24
Finished Jun 04 02:03:39 PM PDT 24
Peak memory 216200 kb
Host smart-049d3346-6a83-4a37-bdcb-a10b22669a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957907900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3957907900
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3393667307
Short name T523
Test name
Test status
Simulation time 193993113 ps
CPU time 0.79 seconds
Started Jun 04 02:03:28 PM PDT 24
Finished Jun 04 02:03:29 PM PDT 24
Peak memory 205640 kb
Host smart-8808600d-5fa5-4c18-9f4c-344bdfc07328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393667307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3393667307
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2563726414
Short name T213
Test name
Test status
Simulation time 2760879893 ps
CPU time 12.14 seconds
Started Jun 04 02:03:29 PM PDT 24
Finished Jun 04 02:03:42 PM PDT 24
Peak memory 235800 kb
Host smart-f005653b-73a8-463a-b4d7-2df9130e1baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563726414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2563726414
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.160823878
Short name T641
Test name
Test status
Simulation time 30681741 ps
CPU time 0.68 seconds
Started Jun 04 02:03:38 PM PDT 24
Finished Jun 04 02:03:40 PM PDT 24
Peak memory 205536 kb
Host smart-e40cb650-41dc-4adc-a383-f225b6560226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160823878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.160823878
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3784474535
Short name T203
Test name
Test status
Simulation time 1033726115 ps
CPU time 5.04 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:03:43 PM PDT 24
Peak memory 218732 kb
Host smart-a802994d-fa22-4fa1-bb8f-a509f9005f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784474535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3784474535
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.440448335
Short name T833
Test name
Test status
Simulation time 19926876 ps
CPU time 0.74 seconds
Started Jun 04 02:03:38 PM PDT 24
Finished Jun 04 02:03:40 PM PDT 24
Peak memory 206452 kb
Host smart-74cc66d3-3e01-4253-b8ed-171fc7e0f471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440448335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.440448335
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1050379472
Short name T262
Test name
Test status
Simulation time 5489721301 ps
CPU time 102.31 seconds
Started Jun 04 02:03:36 PM PDT 24
Finished Jun 04 02:05:20 PM PDT 24
Peak memory 256720 kb
Host smart-96e59100-d02c-4220-999b-c6069c3b3a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050379472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1050379472
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3696363685
Short name T44
Test name
Test status
Simulation time 45303027436 ps
CPU time 110.64 seconds
Started Jun 04 02:03:34 PM PDT 24
Finished Jun 04 02:05:26 PM PDT 24
Peak memory 251852 kb
Host smart-67833420-45ab-4a30-8000-d67dcc95e520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696363685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3696363685
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.905608407
Short name T344
Test name
Test status
Simulation time 619439546139 ps
CPU time 334.99 seconds
Started Jun 04 02:03:36 PM PDT 24
Finished Jun 04 02:09:12 PM PDT 24
Peak memory 249172 kb
Host smart-cb051760-3d07-41ed-a22d-455b3a21374b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905608407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.905608407
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1449460965
Short name T383
Test name
Test status
Simulation time 14527548861 ps
CPU time 22.07 seconds
Started Jun 04 02:03:38 PM PDT 24
Finished Jun 04 02:04:01 PM PDT 24
Peak memory 224388 kb
Host smart-776bf987-2e48-4733-a0dc-e5bb389daf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449460965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1449460965
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3314521553
Short name T847
Test name
Test status
Simulation time 585622323 ps
CPU time 6.39 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:03:45 PM PDT 24
Peak memory 234124 kb
Host smart-b1ca6552-b70c-4354-8879-9b3b67430970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314521553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3314521553
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1717159125
Short name T225
Test name
Test status
Simulation time 23748496129 ps
CPU time 40.86 seconds
Started Jun 04 02:03:36 PM PDT 24
Finished Jun 04 02:04:17 PM PDT 24
Peak memory 222680 kb
Host smart-c5593ce7-6864-492f-9132-0fe897532d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717159125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1717159125
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1274681020
Short name T531
Test name
Test status
Simulation time 12500901113 ps
CPU time 9.08 seconds
Started Jun 04 02:03:35 PM PDT 24
Finished Jun 04 02:03:45 PM PDT 24
Peak memory 218676 kb
Host smart-31fb81c7-5bf7-4218-b444-394209972748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274681020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1274681020
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2508135842
Short name T36
Test name
Test status
Simulation time 115765215 ps
CPU time 3.39 seconds
Started Jun 04 02:03:36 PM PDT 24
Finished Jun 04 02:03:41 PM PDT 24
Peak memory 233816 kb
Host smart-209fb660-4e1d-4fd2-990b-4037239b3027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508135842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2508135842
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4199068293
Short name T764
Test name
Test status
Simulation time 1848345676 ps
CPU time 4.73 seconds
Started Jun 04 02:03:36 PM PDT 24
Finished Jun 04 02:03:41 PM PDT 24
Peak memory 222944 kb
Host smart-10be9ea9-c16a-4adb-aafc-618e6ab93a9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4199068293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4199068293
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2603479484
Short name T356
Test name
Test status
Simulation time 1499271786 ps
CPU time 18.12 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:03:57 PM PDT 24
Peak memory 216256 kb
Host smart-beb5fb4a-9077-4ea2-8d3b-522ad87b833d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603479484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2603479484
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3174523032
Short name T472
Test name
Test status
Simulation time 5121166547 ps
CPU time 7.27 seconds
Started Jun 04 02:03:36 PM PDT 24
Finished Jun 04 02:03:45 PM PDT 24
Peak memory 216132 kb
Host smart-c85b0200-af97-47ec-ace6-20da121ce54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174523032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3174523032
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.447136526
Short name T662
Test name
Test status
Simulation time 579222511 ps
CPU time 6.64 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:03:45 PM PDT 24
Peak memory 216232 kb
Host smart-6e8f25b8-382b-44cc-b96f-3b1baa35993c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447136526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.447136526
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3392300336
Short name T363
Test name
Test status
Simulation time 90897831 ps
CPU time 0.92 seconds
Started Jun 04 02:03:35 PM PDT 24
Finished Jun 04 02:03:37 PM PDT 24
Peak memory 205932 kb
Host smart-7c550499-f2d4-4d29-b20a-d9b13fd0e7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392300336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3392300336
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3390349779
Short name T850
Test name
Test status
Simulation time 7487548393 ps
CPU time 9.43 seconds
Started Jun 04 02:03:36 PM PDT 24
Finished Jun 04 02:03:47 PM PDT 24
Peak memory 220816 kb
Host smart-8e9b5062-8e47-467c-8416-8418edfef149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390349779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3390349779
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3587300998
Short name T209
Test name
Test status
Simulation time 164344065 ps
CPU time 3.77 seconds
Started Jun 04 02:03:36 PM PDT 24
Finished Jun 04 02:03:42 PM PDT 24
Peak memory 234452 kb
Host smart-0e263b5a-9e34-4c4b-94da-7bba09a75cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587300998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3587300998
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.695243417
Short name T459
Test name
Test status
Simulation time 21668987 ps
CPU time 0.8 seconds
Started Jun 04 02:03:36 PM PDT 24
Finished Jun 04 02:03:37 PM PDT 24
Peak memory 206484 kb
Host smart-a18fa21a-a8c6-4e97-86d5-94489538ebe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695243417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.695243417
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.350812621
Short name T272
Test name
Test status
Simulation time 4393966644 ps
CPU time 55.28 seconds
Started Jun 04 02:03:35 PM PDT 24
Finished Jun 04 02:04:31 PM PDT 24
Peak memory 240920 kb
Host smart-59587acd-db45-4f3b-8feb-252d02ca1599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350812621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.350812621
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1063664198
Short name T494
Test name
Test status
Simulation time 25811486528 ps
CPU time 106.93 seconds
Started Jun 04 02:03:36 PM PDT 24
Finished Jun 04 02:05:24 PM PDT 24
Peak memory 250104 kb
Host smart-c6d25624-fe72-48ef-8600-4f3b85be397f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063664198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1063664198
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1259786984
Short name T48
Test name
Test status
Simulation time 3238359409 ps
CPU time 14.34 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:03:53 PM PDT 24
Peak memory 224344 kb
Host smart-e66b8f1c-76d1-4f82-a4d7-4648d842b21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259786984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1259786984
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.4148949597
Short name T403
Test name
Test status
Simulation time 3475541039 ps
CPU time 9.54 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:03:48 PM PDT 24
Peak memory 233920 kb
Host smart-fb93f3cb-d2ee-40f6-a245-8b24a886bbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148949597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4148949597
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3842069443
Short name T845
Test name
Test status
Simulation time 4450908998 ps
CPU time 35.87 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:04:14 PM PDT 24
Peak memory 218800 kb
Host smart-1f4d125a-0513-4ead-aa4d-769be8d7a6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842069443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3842069443
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3552322633
Short name T852
Test name
Test status
Simulation time 2509833388 ps
CPU time 6.15 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:03:45 PM PDT 24
Peak memory 219732 kb
Host smart-90152663-b823-4a1b-83dc-6ba855d86b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552322633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3552322633
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3050285388
Short name T888
Test name
Test status
Simulation time 1179862739 ps
CPU time 8.84 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:03:47 PM PDT 24
Peak memory 233584 kb
Host smart-1e233c03-ea87-40f6-9111-e5e840618f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050285388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3050285388
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3097193350
Short name T150
Test name
Test status
Simulation time 984244560 ps
CPU time 7.38 seconds
Started Jun 04 02:03:38 PM PDT 24
Finished Jun 04 02:03:46 PM PDT 24
Peak memory 218476 kb
Host smart-b55a62f3-4dc8-4a36-80a0-b7c109654180
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3097193350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3097193350
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2805364299
Short name T173
Test name
Test status
Simulation time 9022844477 ps
CPU time 42.55 seconds
Started Jun 04 02:03:39 PM PDT 24
Finished Jun 04 02:04:22 PM PDT 24
Peak memory 217296 kb
Host smart-9720f5d8-ebee-4ba5-935b-6e6d3c467b8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805364299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2805364299
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3495239983
Short name T603
Test name
Test status
Simulation time 8422332241 ps
CPU time 21.58 seconds
Started Jun 04 02:03:35 PM PDT 24
Finished Jun 04 02:03:58 PM PDT 24
Peak memory 216260 kb
Host smart-da62cee6-4f72-4462-995f-74866d425b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495239983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3495239983
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.928645472
Short name T856
Test name
Test status
Simulation time 1085157977 ps
CPU time 5.11 seconds
Started Jun 04 02:03:38 PM PDT 24
Finished Jun 04 02:03:44 PM PDT 24
Peak memory 215960 kb
Host smart-631cac80-24d0-41c9-a3b1-4b2e23e29958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928645472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.928645472
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.4133654988
Short name T803
Test name
Test status
Simulation time 371458045 ps
CPU time 5.81 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:03:45 PM PDT 24
Peak memory 216152 kb
Host smart-a16fc769-c0cf-4ee7-9afb-fac26998c410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133654988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4133654988
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.737668200
Short name T486
Test name
Test status
Simulation time 207864647 ps
CPU time 0.89 seconds
Started Jun 04 02:03:38 PM PDT 24
Finished Jun 04 02:03:40 PM PDT 24
Peak memory 206660 kb
Host smart-b21b47be-dd5f-4746-98c5-e9af9f1aa8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737668200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.737668200
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2567185820
Short name T204
Test name
Test status
Simulation time 708235401 ps
CPU time 5.19 seconds
Started Jun 04 02:03:38 PM PDT 24
Finished Jun 04 02:03:44 PM PDT 24
Peak memory 217156 kb
Host smart-484dec20-3145-4aa7-99e5-e334aeb3e429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567185820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2567185820
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.232647048
Short name T751
Test name
Test status
Simulation time 42150778 ps
CPU time 0.71 seconds
Started Jun 04 02:04:09 PM PDT 24
Finished Jun 04 02:04:10 PM PDT 24
Peak memory 204712 kb
Host smart-434dd083-3e44-48ee-bdde-be004304b817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232647048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.232647048
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2918327629
Short name T843
Test name
Test status
Simulation time 555671140 ps
CPU time 3.08 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:03:41 PM PDT 24
Peak memory 233448 kb
Host smart-838d99b2-747e-44e7-bd13-af689520bed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918327629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2918327629
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2995020723
Short name T886
Test name
Test status
Simulation time 54549295 ps
CPU time 0.76 seconds
Started Jun 04 02:03:38 PM PDT 24
Finished Jun 04 02:03:40 PM PDT 24
Peak memory 205380 kb
Host smart-04a49eeb-4c11-4bca-8f0f-dd91261de86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995020723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2995020723
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2672824853
Short name T653
Test name
Test status
Simulation time 1629607522 ps
CPU time 29.58 seconds
Started Jun 04 02:04:11 PM PDT 24
Finished Jun 04 02:04:42 PM PDT 24
Peak memory 240772 kb
Host smart-aaa1fe2e-ddee-4d40-8678-50f489a2c61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672824853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2672824853
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4126180104
Short name T259
Test name
Test status
Simulation time 61430460830 ps
CPU time 556.29 seconds
Started Jun 04 02:04:12 PM PDT 24
Finished Jun 04 02:13:29 PM PDT 24
Peak memory 257292 kb
Host smart-10d78091-ee76-457f-86a3-e23c049ae10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126180104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4126180104
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2550570488
Short name T675
Test name
Test status
Simulation time 807360987 ps
CPU time 9.99 seconds
Started Jun 04 02:03:38 PM PDT 24
Finished Jun 04 02:03:49 PM PDT 24
Peak memory 248964 kb
Host smart-3a20d440-8a1b-4f84-ac71-2806bffaeb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550570488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2550570488
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1611165698
Short name T9
Test name
Test status
Simulation time 594275291 ps
CPU time 4.78 seconds
Started Jun 04 02:03:35 PM PDT 24
Finished Jun 04 02:03:40 PM PDT 24
Peak memory 233692 kb
Host smart-ee90471c-a729-4813-8e09-5bf32a529e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611165698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1611165698
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1997285258
Short name T186
Test name
Test status
Simulation time 2179617064 ps
CPU time 10.53 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:03:49 PM PDT 24
Peak memory 232460 kb
Host smart-e2b86528-d92b-4d3a-83b7-1a62fc972eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997285258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1997285258
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.509036543
Short name T251
Test name
Test status
Simulation time 1408492367 ps
CPU time 9.03 seconds
Started Jun 04 02:03:36 PM PDT 24
Finished Jun 04 02:03:46 PM PDT 24
Peak memory 234544 kb
Host smart-d55383ed-8f2a-489b-81cc-840e6beba20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509036543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.509036543
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3219941802
Short name T931
Test name
Test status
Simulation time 32444218 ps
CPU time 2.31 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:03:41 PM PDT 24
Peak memory 232676 kb
Host smart-ea246cd9-f5db-4db8-af87-0cd63555e8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219941802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3219941802
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2358441842
Short name T639
Test name
Test status
Simulation time 1479261197 ps
CPU time 15.8 seconds
Started Jun 04 02:04:13 PM PDT 24
Finished Jun 04 02:04:30 PM PDT 24
Peak memory 219916 kb
Host smart-d5aae4c7-3700-40d9-850f-26edcaa49711
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2358441842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2358441842
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.191422664
Short name T275
Test name
Test status
Simulation time 2124802097 ps
CPU time 37.53 seconds
Started Jun 04 02:04:14 PM PDT 24
Finished Jun 04 02:04:52 PM PDT 24
Peak memory 249044 kb
Host smart-f375c30b-3ff9-47e1-997a-f05861b31aa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191422664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.191422664
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.53566079
Short name T358
Test name
Test status
Simulation time 4523542862 ps
CPU time 12.8 seconds
Started Jun 04 02:03:37 PM PDT 24
Finished Jun 04 02:03:51 PM PDT 24
Peak memory 216152 kb
Host smart-407d3258-42b3-4598-b280-2a85e57db451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53566079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.53566079
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2925707324
Short name T495
Test name
Test status
Simulation time 5545448128 ps
CPU time 10.61 seconds
Started Jun 04 02:03:36 PM PDT 24
Finished Jun 04 02:03:48 PM PDT 24
Peak memory 216140 kb
Host smart-6cda1138-f89c-4e61-8bc7-d205e6982a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925707324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2925707324
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3510373081
Short name T857
Test name
Test status
Simulation time 74788761 ps
CPU time 1.3 seconds
Started Jun 04 02:03:36 PM PDT 24
Finished Jun 04 02:03:38 PM PDT 24
Peak memory 216176 kb
Host smart-520ffe16-1d4d-4225-8059-7e65d973cb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510373081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3510373081
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3690180430
Short name T667
Test name
Test status
Simulation time 43731669 ps
CPU time 0.81 seconds
Started Jun 04 02:03:36 PM PDT 24
Finished Jun 04 02:03:38 PM PDT 24
Peak memory 205560 kb
Host smart-a8b9be49-b72f-4f24-82e5-bf4b8e116ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690180430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3690180430
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.517431865
Short name T393
Test name
Test status
Simulation time 289704716 ps
CPU time 2.11 seconds
Started Jun 04 02:03:36 PM PDT 24
Finished Jun 04 02:03:39 PM PDT 24
Peak memory 207808 kb
Host smart-5f36edbe-9970-4cbc-82bb-da07a7ae5254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517431865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.517431865
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.4217516060
Short name T513
Test name
Test status
Simulation time 21392166 ps
CPU time 0.73 seconds
Started Jun 04 02:04:14 PM PDT 24
Finished Jun 04 02:04:16 PM PDT 24
Peak memory 205368 kb
Host smart-0159afbb-8c49-41a0-91b5-e3ad475abc94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217516060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
4217516060
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3675646187
Short name T905
Test name
Test status
Simulation time 3314567581 ps
CPU time 4.87 seconds
Started Jun 04 02:04:14 PM PDT 24
Finished Jun 04 02:04:20 PM PDT 24
Peak memory 233356 kb
Host smart-aff1f5e1-6679-4e1b-ac71-3e0f3f6b8e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675646187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3675646187
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3534789764
Short name T566
Test name
Test status
Simulation time 52858374 ps
CPU time 0.78 seconds
Started Jun 04 02:04:15 PM PDT 24
Finished Jun 04 02:04:17 PM PDT 24
Peak memory 206572 kb
Host smart-e9c36236-69da-4caf-bf70-ad82da9157ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534789764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3534789764
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1476356792
Short name T82
Test name
Test status
Simulation time 21714899581 ps
CPU time 92.37 seconds
Started Jun 04 02:04:12 PM PDT 24
Finished Jun 04 02:05:46 PM PDT 24
Peak memory 265880 kb
Host smart-94a09dae-9410-445c-8743-0b6185fef704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476356792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1476356792
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1653949959
Short name T143
Test name
Test status
Simulation time 7968412374 ps
CPU time 72.24 seconds
Started Jun 04 02:04:11 PM PDT 24
Finished Jun 04 02:05:24 PM PDT 24
Peak memory 255528 kb
Host smart-ce6da020-b8af-4860-9d1d-a1a42b98bda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653949959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1653949959
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.351961878
Short name T580
Test name
Test status
Simulation time 1934873372 ps
CPU time 15.38 seconds
Started Jun 04 02:04:13 PM PDT 24
Finished Jun 04 02:04:30 PM PDT 24
Peak memory 224288 kb
Host smart-85b2a50b-a861-49a9-bb0a-acbe4a4ff03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351961878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.351961878
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1807876957
Short name T170
Test name
Test status
Simulation time 752150598 ps
CPU time 9.5 seconds
Started Jun 04 02:04:11 PM PDT 24
Finished Jun 04 02:04:21 PM PDT 24
Peak memory 219688 kb
Host smart-68a5e8d2-9dfc-4600-baab-5eb630586eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807876957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1807876957
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2088190480
Short name T588
Test name
Test status
Simulation time 281230600 ps
CPU time 3.85 seconds
Started Jun 04 02:04:11 PM PDT 24
Finished Jun 04 02:04:16 PM PDT 24
Peak memory 218308 kb
Host smart-8d56f782-74dd-4117-b06e-d965412f3f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088190480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2088190480
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3803264715
Short name T600
Test name
Test status
Simulation time 164306009 ps
CPU time 2.71 seconds
Started Jun 04 02:04:11 PM PDT 24
Finished Jun 04 02:04:15 PM PDT 24
Peak memory 233056 kb
Host smart-9e78047d-0fcf-45d5-b4f3-9c6d9f094570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803264715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3803264715
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2768216993
Short name T738
Test name
Test status
Simulation time 1800827944 ps
CPU time 7.66 seconds
Started Jun 04 02:04:12 PM PDT 24
Finished Jun 04 02:04:21 PM PDT 24
Peak memory 233496 kb
Host smart-5fa6a686-77cc-4fc6-a21a-7ea4117a7908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768216993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2768216993
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3631532124
Short name T956
Test name
Test status
Simulation time 96205866 ps
CPU time 3.77 seconds
Started Jun 04 02:04:11 PM PDT 24
Finished Jun 04 02:04:16 PM PDT 24
Peak memory 222664 kb
Host smart-8b68a939-815a-4418-b5c2-d1f9d301024a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3631532124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3631532124
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4034841950
Short name T654
Test name
Test status
Simulation time 25443789627 ps
CPU time 223.8 seconds
Started Jun 04 02:04:10 PM PDT 24
Finished Jun 04 02:07:55 PM PDT 24
Peak memory 245592 kb
Host smart-d7f0ab0e-aa62-4c86-b46b-824da6e3c6c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034841950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4034841950
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1673020542
Short name T458
Test name
Test status
Simulation time 1690196229 ps
CPU time 11.98 seconds
Started Jun 04 02:04:13 PM PDT 24
Finished Jun 04 02:04:26 PM PDT 24
Peak memory 216096 kb
Host smart-f7c59a71-1bf1-4b52-8867-4d1fa2f9f390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673020542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1673020542
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.4016576743
Short name T454
Test name
Test status
Simulation time 266237210 ps
CPU time 1.53 seconds
Started Jun 04 02:04:13 PM PDT 24
Finished Jun 04 02:04:16 PM PDT 24
Peak memory 206656 kb
Host smart-e05ff23f-ce55-4d71-b421-b8b094c5db4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016576743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.4016576743
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2567373756
Short name T815
Test name
Test status
Simulation time 15195789 ps
CPU time 0.74 seconds
Started Jun 04 02:04:14 PM PDT 24
Finished Jun 04 02:04:16 PM PDT 24
Peak memory 205624 kb
Host smart-3de23adf-7ea9-4f88-ad50-6b50863ce716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567373756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2567373756
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.121401216
Short name T793
Test name
Test status
Simulation time 17402058 ps
CPU time 0.74 seconds
Started Jun 04 02:04:18 PM PDT 24
Finished Jun 04 02:04:20 PM PDT 24
Peak memory 205544 kb
Host smart-0fe49945-03b0-4d2d-bc2e-a4d4b6027659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121401216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.121401216
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3654687611
Short name T530
Test name
Test status
Simulation time 1226606121 ps
CPU time 6.38 seconds
Started Jun 04 02:04:12 PM PDT 24
Finished Jun 04 02:04:19 PM PDT 24
Peak memory 234404 kb
Host smart-5ae6193e-5b0f-464f-816a-0726f1586264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654687611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3654687611
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.4154776829
Short name T889
Test name
Test status
Simulation time 24633258 ps
CPU time 0.83 seconds
Started Jun 04 02:04:14 PM PDT 24
Finished Jun 04 02:04:16 PM PDT 24
Peak memory 204760 kb
Host smart-a48f3661-3c88-4001-9469-b17e9d87fcc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154776829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
4154776829
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2196729890
Short name T756
Test name
Test status
Simulation time 2209215291 ps
CPU time 7.49 seconds
Started Jun 04 02:04:13 PM PDT 24
Finished Jun 04 02:04:21 PM PDT 24
Peak memory 233692 kb
Host smart-daf9df35-355a-4a63-b70d-7ab5b131ed1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196729890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2196729890
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1372698231
Short name T782
Test name
Test status
Simulation time 107457901 ps
CPU time 0.8 seconds
Started Jun 04 02:04:10 PM PDT 24
Finished Jun 04 02:04:12 PM PDT 24
Peak memory 206436 kb
Host smart-2b8c9323-3584-4bb4-92e5-d1899b58afef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372698231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1372698231
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.392191295
Short name T265
Test name
Test status
Simulation time 5706610415 ps
CPU time 91.39 seconds
Started Jun 04 02:04:10 PM PDT 24
Finished Jun 04 02:05:42 PM PDT 24
Peak memory 258864 kb
Host smart-3137566e-a437-43e8-8ad2-0593101139b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392191295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.392191295
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1227271930
Short name T686
Test name
Test status
Simulation time 78491574092 ps
CPU time 351.99 seconds
Started Jun 04 02:04:11 PM PDT 24
Finished Jun 04 02:10:03 PM PDT 24
Peak memory 249132 kb
Host smart-e5889dda-d1ea-4b15-99ab-d99cce16ff7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227271930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1227271930
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1373124533
Short name T864
Test name
Test status
Simulation time 33386595854 ps
CPU time 80.1 seconds
Started Jun 04 02:04:17 PM PDT 24
Finished Jun 04 02:05:38 PM PDT 24
Peak memory 249484 kb
Host smart-f54de328-6ea5-417a-a492-99900569010f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373124533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1373124533
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3271295050
Short name T883
Test name
Test status
Simulation time 752035869 ps
CPU time 8.85 seconds
Started Jun 04 02:04:12 PM PDT 24
Finished Jun 04 02:04:21 PM PDT 24
Peak memory 250484 kb
Host smart-89f95343-1d3b-4ba3-a498-0d5f7ffb652b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271295050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3271295050
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1568548768
Short name T443
Test name
Test status
Simulation time 1132108807 ps
CPU time 9.81 seconds
Started Jun 04 02:04:12 PM PDT 24
Finished Jun 04 02:04:23 PM PDT 24
Peak memory 218372 kb
Host smart-2d0e0c2a-efa4-4391-ab8a-cfbe69d3560f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568548768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1568548768
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1038011769
Short name T680
Test name
Test status
Simulation time 3533460526 ps
CPU time 26.13 seconds
Started Jun 04 02:04:13 PM PDT 24
Finished Jun 04 02:04:40 PM PDT 24
Peak memory 238764 kb
Host smart-5350fc49-6361-4a64-90b2-249f07e17e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038011769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1038011769
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1875481682
Short name T137
Test name
Test status
Simulation time 13612122279 ps
CPU time 41.32 seconds
Started Jun 04 02:04:14 PM PDT 24
Finished Jun 04 02:04:57 PM PDT 24
Peak memory 233264 kb
Host smart-0725e8b6-eac6-402f-bd59-12642d58d32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875481682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1875481682
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3902738600
Short name T910
Test name
Test status
Simulation time 35175947253 ps
CPU time 22.81 seconds
Started Jun 04 02:04:12 PM PDT 24
Finished Jun 04 02:04:35 PM PDT 24
Peak memory 228552 kb
Host smart-3f6c34e0-6e55-4ba3-9aaa-ae2be7827ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902738600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3902738600
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3634075711
Short name T464
Test name
Test status
Simulation time 829144905 ps
CPU time 4.5 seconds
Started Jun 04 02:04:11 PM PDT 24
Finished Jun 04 02:04:16 PM PDT 24
Peak memory 219992 kb
Host smart-2464f18f-d856-4421-8f21-ed205b01f5a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3634075711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3634075711
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1382608286
Short name T333
Test name
Test status
Simulation time 3397292712 ps
CPU time 24.95 seconds
Started Jun 04 02:04:15 PM PDT 24
Finished Jun 04 02:04:42 PM PDT 24
Peak memory 237408 kb
Host smart-bbfd5bd7-89f1-4bdb-9e63-ccbf8a7a83d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382608286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1382608286
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3899561546
Short name T704
Test name
Test status
Simulation time 2712391517 ps
CPU time 9.14 seconds
Started Jun 04 02:04:12 PM PDT 24
Finished Jun 04 02:04:23 PM PDT 24
Peak memory 216400 kb
Host smart-901bc801-6ada-4abb-9816-166028d9d2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899561546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3899561546
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2637370677
Short name T390
Test name
Test status
Simulation time 1133145345 ps
CPU time 5.04 seconds
Started Jun 04 02:04:14 PM PDT 24
Finished Jun 04 02:04:20 PM PDT 24
Peak memory 216056 kb
Host smart-542a6d72-b7a8-47d1-b6c3-cd9091aa0f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637370677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2637370677
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1036222062
Short name T613
Test name
Test status
Simulation time 28546591 ps
CPU time 0.87 seconds
Started Jun 04 02:04:14 PM PDT 24
Finished Jun 04 02:04:16 PM PDT 24
Peak memory 205712 kb
Host smart-cad2b7be-6743-40dc-bb90-01443bda5ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036222062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1036222062
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1902240181
Short name T489
Test name
Test status
Simulation time 21607517 ps
CPU time 0.73 seconds
Started Jun 04 02:04:12 PM PDT 24
Finished Jun 04 02:04:14 PM PDT 24
Peak memory 205608 kb
Host smart-033df7f1-fb99-4a04-b15c-5d0e979de502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902240181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1902240181
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1357570761
Short name T620
Test name
Test status
Simulation time 1466390023 ps
CPU time 7.73 seconds
Started Jun 04 02:04:12 PM PDT 24
Finished Jun 04 02:04:20 PM PDT 24
Peak memory 217380 kb
Host smart-b26654c1-7950-465f-bde0-0a37a4043be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357570761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1357570761
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1377662392
Short name T385
Test name
Test status
Simulation time 48416665 ps
CPU time 0.68 seconds
Started Jun 04 02:04:13 PM PDT 24
Finished Jun 04 02:04:15 PM PDT 24
Peak memory 205716 kb
Host smart-fff12f07-c4fd-42d4-a447-0f89792120fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377662392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1377662392
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3016326725
Short name T565
Test name
Test status
Simulation time 1984877569 ps
CPU time 11.21 seconds
Started Jun 04 02:04:15 PM PDT 24
Finished Jun 04 02:04:27 PM PDT 24
Peak memory 219084 kb
Host smart-b983cdbc-198d-46c2-a4e2-9666f974c79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016326725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3016326725
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2077869327
Short name T731
Test name
Test status
Simulation time 18717538 ps
CPU time 0.74 seconds
Started Jun 04 02:04:13 PM PDT 24
Finished Jun 04 02:04:15 PM PDT 24
Peak memory 206676 kb
Host smart-144ecd50-26f2-4868-abb2-0e406b4cd26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077869327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2077869327
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3634497557
Short name T608
Test name
Test status
Simulation time 9284921697 ps
CPU time 42.57 seconds
Started Jun 04 02:04:15 PM PDT 24
Finished Jun 04 02:04:58 PM PDT 24
Peak memory 249484 kb
Host smart-e0f55e10-0dd1-4fca-9947-4a95b8d158eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634497557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3634497557
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.787851951
Short name T243
Test name
Test status
Simulation time 1631237568 ps
CPU time 40.89 seconds
Started Jun 04 02:04:20 PM PDT 24
Finished Jun 04 02:05:02 PM PDT 24
Peak memory 249068 kb
Host smart-0d198f69-001f-4b54-9129-65d5b97f1e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787851951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.787851951
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3175541594
Short name T254
Test name
Test status
Simulation time 45724204299 ps
CPU time 478.11 seconds
Started Jun 04 02:04:17 PM PDT 24
Finished Jun 04 02:12:16 PM PDT 24
Peak memory 256668 kb
Host smart-aa0de7d0-c181-4d0f-b0c0-11ad025132e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175541594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3175541594
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2140363414
Short name T834
Test name
Test status
Simulation time 1908426218 ps
CPU time 17.65 seconds
Started Jun 04 02:04:15 PM PDT 24
Finished Jun 04 02:04:34 PM PDT 24
Peak memory 232524 kb
Host smart-8cae2983-3546-45df-8bcd-d7fd097ee248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140363414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2140363414
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.860283093
Short name T234
Test name
Test status
Simulation time 610696070 ps
CPU time 7.7 seconds
Started Jun 04 02:04:17 PM PDT 24
Finished Jun 04 02:04:26 PM PDT 24
Peak memory 218672 kb
Host smart-e257fe9c-5f79-46a5-b8b4-4d849239ab29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860283093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.860283093
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1411384475
Short name T932
Test name
Test status
Simulation time 36763427390 ps
CPU time 86.8 seconds
Started Jun 04 02:04:12 PM PDT 24
Finished Jun 04 02:05:40 PM PDT 24
Peak memory 240748 kb
Host smart-b031524c-ead2-4e54-82a7-1beb23981052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411384475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1411384475
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3590012834
Short name T256
Test name
Test status
Simulation time 16904607257 ps
CPU time 22.43 seconds
Started Jun 04 02:04:15 PM PDT 24
Finished Jun 04 02:04:39 PM PDT 24
Peak memory 232664 kb
Host smart-688f6205-08ed-4fc5-875c-3f74c9292ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590012834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3590012834
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1276927964
Short name T138
Test name
Test status
Simulation time 12204623234 ps
CPU time 12.45 seconds
Started Jun 04 02:04:17 PM PDT 24
Finished Jun 04 02:04:31 PM PDT 24
Peak memory 233732 kb
Host smart-36127608-3db0-4c03-af2b-a1e325fb3195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276927964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1276927964
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2197668549
Short name T119
Test name
Test status
Simulation time 800767017 ps
CPU time 4.13 seconds
Started Jun 04 02:04:15 PM PDT 24
Finished Jun 04 02:04:20 PM PDT 24
Peak memory 222280 kb
Host smart-826db5d9-f6e1-43e1-8bc7-32444290d4f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2197668549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2197668549
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.175815324
Short name T839
Test name
Test status
Simulation time 53459728527 ps
CPU time 329.36 seconds
Started Jun 04 02:04:15 PM PDT 24
Finished Jun 04 02:09:46 PM PDT 24
Peak memory 253568 kb
Host smart-d89c32cd-f17d-45e6-861d-9a24fbfe3fe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175815324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.175815324
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1296823356
Short name T642
Test name
Test status
Simulation time 564253373 ps
CPU time 1.94 seconds
Started Jun 04 02:04:17 PM PDT 24
Finished Jun 04 02:04:20 PM PDT 24
Peak memory 216184 kb
Host smart-889ec029-8f75-45bb-adcd-9efffbcdf122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296823356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1296823356
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2598027885
Short name T483
Test name
Test status
Simulation time 18559048703 ps
CPU time 19.08 seconds
Started Jun 04 02:04:16 PM PDT 24
Finished Jun 04 02:04:37 PM PDT 24
Peak memory 216084 kb
Host smart-18ddaeac-8647-430b-a37d-568115b87ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598027885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2598027885
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3964546491
Short name T502
Test name
Test status
Simulation time 41468279 ps
CPU time 1.08 seconds
Started Jun 04 02:04:18 PM PDT 24
Finished Jun 04 02:04:20 PM PDT 24
Peak memory 207132 kb
Host smart-f5fe29c1-edfc-4b63-b2ee-10fab7c46fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964546491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3964546491
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2688459743
Short name T872
Test name
Test status
Simulation time 18858353 ps
CPU time 0.76 seconds
Started Jun 04 02:04:14 PM PDT 24
Finished Jun 04 02:04:16 PM PDT 24
Peak memory 205592 kb
Host smart-5c8f4b4b-204c-4851-8d37-f44b9e474761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688459743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2688459743
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1934230728
Short name T206
Test name
Test status
Simulation time 99069472 ps
CPU time 2.27 seconds
Started Jun 04 02:04:17 PM PDT 24
Finished Jun 04 02:04:20 PM PDT 24
Peak memory 218400 kb
Host smart-f2afcd07-761f-4701-953d-cd3e83faf36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934230728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1934230728
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2961035099
Short name T59
Test name
Test status
Simulation time 16366354 ps
CPU time 0.72 seconds
Started Jun 04 02:04:19 PM PDT 24
Finished Jun 04 02:04:21 PM PDT 24
Peak memory 204836 kb
Host smart-1dd499b6-6774-4427-be3f-2b1ea24efe7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961035099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2961035099
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1562976681
Short name T430
Test name
Test status
Simulation time 627835143 ps
CPU time 8.32 seconds
Started Jun 04 02:04:19 PM PDT 24
Finished Jun 04 02:04:29 PM PDT 24
Peak memory 233692 kb
Host smart-69ce9075-19a3-45d9-8896-5d04e79119d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562976681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1562976681
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1051177897
Short name T814
Test name
Test status
Simulation time 66929530 ps
CPU time 0.77 seconds
Started Jun 04 02:04:16 PM PDT 24
Finished Jun 04 02:04:18 PM PDT 24
Peak memory 206316 kb
Host smart-49d42247-b5fc-40a3-9d20-0720b41afb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051177897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1051177897
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.19904196
Short name T781
Test name
Test status
Simulation time 32217907882 ps
CPU time 70.4 seconds
Started Jun 04 02:04:15 PM PDT 24
Finished Jun 04 02:05:27 PM PDT 24
Peak memory 249032 kb
Host smart-43404636-1949-458b-90d5-3427af1f847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19904196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.19904196
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3419147713
Short name T554
Test name
Test status
Simulation time 7121945886 ps
CPU time 40.84 seconds
Started Jun 04 02:04:17 PM PDT 24
Finished Jun 04 02:04:59 PM PDT 24
Peak memory 254084 kb
Host smart-8a87a038-ba23-43f0-a367-e49fe9b5938d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419147713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3419147713
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3299278185
Short name T880
Test name
Test status
Simulation time 8346842489 ps
CPU time 25.09 seconds
Started Jun 04 02:04:17 PM PDT 24
Finished Jun 04 02:04:44 PM PDT 24
Peak memory 232668 kb
Host smart-170af323-ed7d-442d-9ac3-f9d857637670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299278185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3299278185
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2761776637
Short name T214
Test name
Test status
Simulation time 477067519 ps
CPU time 5.73 seconds
Started Jun 04 02:04:17 PM PDT 24
Finished Jun 04 02:04:24 PM PDT 24
Peak memory 218296 kb
Host smart-154bedd1-245e-4a6f-a08a-9b9af7d3a689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761776637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2761776637
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.741512515
Short name T925
Test name
Test status
Simulation time 1661264223 ps
CPU time 7.3 seconds
Started Jun 04 02:04:16 PM PDT 24
Finished Jun 04 02:04:25 PM PDT 24
Peak memory 218544 kb
Host smart-8666df66-3c76-433c-88cd-3d5d272c199e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741512515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.741512515
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1135846832
Short name T338
Test name
Test status
Simulation time 526654995 ps
CPU time 3.66 seconds
Started Jun 04 02:04:21 PM PDT 24
Finished Jun 04 02:04:25 PM PDT 24
Peak memory 232624 kb
Host smart-c141a8f0-39b5-479f-87ea-0b051930d229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135846832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1135846832
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1390500498
Short name T552
Test name
Test status
Simulation time 14857199763 ps
CPU time 26.37 seconds
Started Jun 04 02:04:17 PM PDT 24
Finished Jun 04 02:04:45 PM PDT 24
Peak memory 248792 kb
Host smart-fd2dedd6-380a-4444-a696-1f96f68a2506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390500498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1390500498
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.587405111
Short name T542
Test name
Test status
Simulation time 650248137 ps
CPU time 4.11 seconds
Started Jun 04 02:04:20 PM PDT 24
Finished Jun 04 02:04:25 PM PDT 24
Peak memory 220172 kb
Host smart-47e64711-a535-4f6b-8c6c-2667dd2e757e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=587405111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.587405111
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.430750661
Short name T915
Test name
Test status
Simulation time 3258001272 ps
CPU time 18.64 seconds
Started Jun 04 02:04:19 PM PDT 24
Finished Jun 04 02:04:38 PM PDT 24
Peak memory 216220 kb
Host smart-7eb0427e-b84e-4572-91d2-38ca860dedf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430750661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.430750661
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.888492667
Short name T712
Test name
Test status
Simulation time 2900076661 ps
CPU time 7.49 seconds
Started Jun 04 02:04:16 PM PDT 24
Finished Jun 04 02:04:25 PM PDT 24
Peak memory 216212 kb
Host smart-2337c223-6849-4b18-89ee-802f7005d348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888492667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.888492667
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2233707460
Short name T27
Test name
Test status
Simulation time 2000490149 ps
CPU time 1.93 seconds
Started Jun 04 02:04:16 PM PDT 24
Finished Jun 04 02:04:19 PM PDT 24
Peak memory 216172 kb
Host smart-b25e6507-dbf0-4afb-9f22-eadd1aae2a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233707460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2233707460
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3951193818
Short name T830
Test name
Test status
Simulation time 108352330 ps
CPU time 0.85 seconds
Started Jun 04 02:04:19 PM PDT 24
Finished Jun 04 02:04:21 PM PDT 24
Peak memory 205628 kb
Host smart-60da82b2-c230-468d-8e41-671d14518d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951193818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3951193818
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.619040247
Short name T691
Test name
Test status
Simulation time 941945186 ps
CPU time 8.26 seconds
Started Jun 04 02:04:19 PM PDT 24
Finished Jun 04 02:04:29 PM PDT 24
Peak memory 232588 kb
Host smart-ffb08293-9faa-483a-ab30-4a06ea9ca5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619040247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.619040247
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3298007515
Short name T836
Test name
Test status
Simulation time 14496735 ps
CPU time 0.73 seconds
Started Jun 04 02:01:33 PM PDT 24
Finished Jun 04 02:01:34 PM PDT 24
Peak memory 204768 kb
Host smart-4d1b28d7-3ef7-4d0c-b20d-8363bada6e94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298007515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
298007515
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1243310581
Short name T858
Test name
Test status
Simulation time 153582097 ps
CPU time 2.26 seconds
Started Jun 04 02:01:38 PM PDT 24
Finished Jun 04 02:01:41 PM PDT 24
Peak memory 217704 kb
Host smart-4a624a1f-f907-44d4-9391-a501fafa164b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243310581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1243310581
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4043965473
Short name T476
Test name
Test status
Simulation time 51054291 ps
CPU time 0.76 seconds
Started Jun 04 02:01:26 PM PDT 24
Finished Jun 04 02:01:29 PM PDT 24
Peak memory 205752 kb
Host smart-67c93266-1727-44ba-b14d-5ae9812e4d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043965473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4043965473
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.4087235638
Short name T439
Test name
Test status
Simulation time 3612536108 ps
CPU time 37.37 seconds
Started Jun 04 02:01:38 PM PDT 24
Finished Jun 04 02:02:17 PM PDT 24
Peak memory 253352 kb
Host smart-8a5309d6-0142-4e7f-9e99-adf8b07e2ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087235638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.4087235638
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2989261475
Short name T705
Test name
Test status
Simulation time 16036771682 ps
CPU time 51.45 seconds
Started Jun 04 02:01:36 PM PDT 24
Finished Jun 04 02:02:29 PM PDT 24
Peak memory 234816 kb
Host smart-d5556d6e-8ec6-4805-bab1-dbdc3137fab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989261475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2989261475
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1252170400
Short name T716
Test name
Test status
Simulation time 185345399 ps
CPU time 2.77 seconds
Started Jun 04 02:01:35 PM PDT 24
Finished Jun 04 02:01:39 PM PDT 24
Peak memory 224352 kb
Host smart-6e525ee0-660e-40a3-9a83-49613ad6fc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252170400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1252170400
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2292159410
Short name T299
Test name
Test status
Simulation time 982138497 ps
CPU time 12.41 seconds
Started Jun 04 02:01:26 PM PDT 24
Finished Jun 04 02:01:40 PM PDT 24
Peak memory 235188 kb
Host smart-590d6702-597f-459d-8fea-e1584fea4932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292159410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2292159410
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3606861180
Short name T341
Test name
Test status
Simulation time 44626593518 ps
CPU time 93.51 seconds
Started Jun 04 02:01:27 PM PDT 24
Finished Jun 04 02:03:02 PM PDT 24
Peak memory 240860 kb
Host smart-b58874f2-7cfe-4b51-895e-a3c3eba7af01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606861180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3606861180
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3464422822
Short name T56
Test name
Test status
Simulation time 269585891 ps
CPU time 4.23 seconds
Started Jun 04 02:01:24 PM PDT 24
Finished Jun 04 02:01:28 PM PDT 24
Peak memory 225628 kb
Host smart-42e1fdf7-2813-4b93-834f-1961bfecdf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464422822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3464422822
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1582636059
Short name T315
Test name
Test status
Simulation time 2626884714 ps
CPU time 5.94 seconds
Started Jun 04 02:01:28 PM PDT 24
Finished Jun 04 02:01:35 PM PDT 24
Peak memory 232928 kb
Host smart-3f4f1547-ff84-4143-9eff-0acda09f9215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582636059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1582636059
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4270982082
Short name T146
Test name
Test status
Simulation time 854617788 ps
CPU time 4.94 seconds
Started Jun 04 02:01:36 PM PDT 24
Finished Jun 04 02:01:42 PM PDT 24
Peak memory 222344 kb
Host smart-65321652-8129-43da-bb31-3690941307cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4270982082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4270982082
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1515940893
Short name T244
Test name
Test status
Simulation time 142736124791 ps
CPU time 318.75 seconds
Started Jun 04 02:01:33 PM PDT 24
Finished Jun 04 02:06:53 PM PDT 24
Peak memory 250568 kb
Host smart-85b6aa2c-8a7f-4058-8c4e-d1b528f56097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515940893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1515940893
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2438455412
Short name T827
Test name
Test status
Simulation time 34930249534 ps
CPU time 26.24 seconds
Started Jun 04 02:01:25 PM PDT 24
Finished Jun 04 02:01:52 PM PDT 24
Peak memory 216336 kb
Host smart-5c20fa15-8e3a-4968-becb-cbed5ce94d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438455412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2438455412
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.652099307
Short name T820
Test name
Test status
Simulation time 730254124 ps
CPU time 2.61 seconds
Started Jun 04 02:01:32 PM PDT 24
Finished Jun 04 02:01:35 PM PDT 24
Peak memory 216164 kb
Host smart-8a2ba3ee-5c6f-45b5-8c59-0b7586275678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652099307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.652099307
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1185453307
Short name T24
Test name
Test status
Simulation time 262043804 ps
CPU time 2.15 seconds
Started Jun 04 02:01:25 PM PDT 24
Finished Jun 04 02:01:28 PM PDT 24
Peak memory 216196 kb
Host smart-3653563f-3638-4c36-83dc-08f924e17f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185453307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1185453307
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.635606410
Short name T909
Test name
Test status
Simulation time 106941965 ps
CPU time 0.9 seconds
Started Jun 04 02:01:30 PM PDT 24
Finished Jun 04 02:01:31 PM PDT 24
Peak memory 205580 kb
Host smart-725f1d52-d837-4c3d-a01b-70c38220ad85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635606410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.635606410
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2791132824
Short name T899
Test name
Test status
Simulation time 52195675311 ps
CPU time 21.15 seconds
Started Jun 04 02:01:38 PM PDT 24
Finished Jun 04 02:02:00 PM PDT 24
Peak memory 219028 kb
Host smart-4833ec6a-c09d-4f79-815f-c7644c7f112e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791132824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2791132824
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2547803052
Short name T568
Test name
Test status
Simulation time 12693057 ps
CPU time 0.75 seconds
Started Jun 04 02:01:37 PM PDT 24
Finished Jun 04 02:01:39 PM PDT 24
Peak memory 205432 kb
Host smart-855f763c-d03d-433e-94e4-382c91d95542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547803052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
547803052
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3514019944
Short name T631
Test name
Test status
Simulation time 6639848095 ps
CPU time 12.43 seconds
Started Jun 04 02:01:34 PM PDT 24
Finished Jun 04 02:01:47 PM PDT 24
Peak memory 218472 kb
Host smart-ded0f0f3-a798-4456-8671-5082a37d19a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514019944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3514019944
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1421565158
Short name T362
Test name
Test status
Simulation time 49010553 ps
CPU time 0.73 seconds
Started Jun 04 02:01:35 PM PDT 24
Finished Jun 04 02:01:37 PM PDT 24
Peak memory 205312 kb
Host smart-b355a43a-27f8-4360-a5f5-f844e2f31713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421565158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1421565158
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.483821148
Short name T253
Test name
Test status
Simulation time 15652619074 ps
CPU time 27.95 seconds
Started Jun 04 02:01:37 PM PDT 24
Finished Jun 04 02:02:06 PM PDT 24
Peak memory 224364 kb
Host smart-fc0090f1-0d8e-4e50-87c1-9f0a2a1fa965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483821148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.483821148
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.238612305
Short name T313
Test name
Test status
Simulation time 10967535632 ps
CPU time 79.77 seconds
Started Jun 04 02:01:34 PM PDT 24
Finished Jun 04 02:02:54 PM PDT 24
Peak memory 249120 kb
Host smart-8aeef134-9483-4978-b3eb-ece14065ecbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238612305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.238612305
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3061826808
Short name T177
Test name
Test status
Simulation time 62235343979 ps
CPU time 162.34 seconds
Started Jun 04 02:01:35 PM PDT 24
Finished Jun 04 02:04:18 PM PDT 24
Peak memory 256684 kb
Host smart-c12b08d8-0845-4e28-a4cd-a74ef55e2799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061826808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3061826808
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1040630393
Short name T348
Test name
Test status
Simulation time 1847017760 ps
CPU time 33.04 seconds
Started Jun 04 02:01:36 PM PDT 24
Finished Jun 04 02:02:10 PM PDT 24
Peak memory 232492 kb
Host smart-d01a972c-c587-427b-880f-6fc4c7ea736b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040630393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1040630393
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.4214137875
Short name T720
Test name
Test status
Simulation time 606530379 ps
CPU time 3.91 seconds
Started Jun 04 02:01:36 PM PDT 24
Finished Jun 04 02:01:41 PM PDT 24
Peak memory 233268 kb
Host smart-0c8ce786-95fc-45db-807e-e9d47dceab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214137875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4214137875
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.346062088
Short name T98
Test name
Test status
Simulation time 12290317574 ps
CPU time 68.19 seconds
Started Jun 04 02:01:34 PM PDT 24
Finished Jun 04 02:02:44 PM PDT 24
Peak memory 235280 kb
Host smart-36bc8746-3f98-4b65-8421-cd4c63607969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346062088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.346062088
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2638728508
Short name T339
Test name
Test status
Simulation time 2529743399 ps
CPU time 4.01 seconds
Started Jun 04 02:01:43 PM PDT 24
Finished Jun 04 02:01:48 PM PDT 24
Peak memory 218732 kb
Host smart-319a582d-8c42-4e43-9b04-f0962b1b0baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638728508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2638728508
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.154882627
Short name T187
Test name
Test status
Simulation time 2040869402 ps
CPU time 13.65 seconds
Started Jun 04 02:01:36 PM PDT 24
Finished Jun 04 02:01:51 PM PDT 24
Peak memory 235328 kb
Host smart-f159c758-eaa6-4e44-82e3-36e33071cce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154882627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.154882627
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2775749491
Short name T395
Test name
Test status
Simulation time 5884527238 ps
CPU time 6.88 seconds
Started Jun 04 02:01:35 PM PDT 24
Finished Jun 04 02:01:43 PM PDT 24
Peak memory 218732 kb
Host smart-0b5e382d-050a-448b-a189-32b20f025c99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2775749491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2775749491
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1620363086
Short name T222
Test name
Test status
Simulation time 53142376667 ps
CPU time 481.61 seconds
Started Jun 04 02:01:35 PM PDT 24
Finished Jun 04 02:09:38 PM PDT 24
Peak memory 250248 kb
Host smart-4da26321-d438-459f-ad80-5f7f21d318d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620363086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1620363086
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.68257876
Short name T904
Test name
Test status
Simulation time 2467271802 ps
CPU time 17.09 seconds
Started Jun 04 02:01:36 PM PDT 24
Finished Jun 04 02:01:55 PM PDT 24
Peak memory 219336 kb
Host smart-0acf2b28-00c1-4d9a-8429-1803157797a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68257876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.68257876
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1685237498
Short name T951
Test name
Test status
Simulation time 33902519541 ps
CPU time 15.99 seconds
Started Jun 04 02:01:37 PM PDT 24
Finished Jun 04 02:01:55 PM PDT 24
Peak memory 216128 kb
Host smart-f93ba9ed-b7d8-4fb1-9712-8abb0d265887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685237498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1685237498
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.427378684
Short name T482
Test name
Test status
Simulation time 253833168 ps
CPU time 3.46 seconds
Started Jun 04 02:01:34 PM PDT 24
Finished Jun 04 02:01:38 PM PDT 24
Peak memory 216220 kb
Host smart-bcf03d29-1030-4521-b596-b0647242f1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427378684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.427378684
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1161707396
Short name T881
Test name
Test status
Simulation time 72372880 ps
CPU time 0.76 seconds
Started Jun 04 02:01:36 PM PDT 24
Finished Jun 04 02:01:38 PM PDT 24
Peak memory 205584 kb
Host smart-48319dce-5474-4fd7-9e88-99bc8a8940f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161707396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1161707396
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3931115505
Short name T238
Test name
Test status
Simulation time 3767132459 ps
CPU time 13.43 seconds
Started Jun 04 02:01:36 PM PDT 24
Finished Jun 04 02:01:51 PM PDT 24
Peak memory 218912 kb
Host smart-5f7ed229-bcac-41b4-ada6-e5ea98aa6ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931115505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3931115505
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.557749044
Short name T826
Test name
Test status
Simulation time 37210982 ps
CPU time 0.75 seconds
Started Jun 04 02:01:37 PM PDT 24
Finished Jun 04 02:01:38 PM PDT 24
Peak memory 204764 kb
Host smart-2383bab8-84f6-4feb-95ad-a8adab526aeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557749044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.557749044
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1315483582
Short name T28
Test name
Test status
Simulation time 551422596 ps
CPU time 4.5 seconds
Started Jun 04 02:01:35 PM PDT 24
Finished Jun 04 02:01:40 PM PDT 24
Peak memory 219888 kb
Host smart-f67d63bf-61d0-4ca5-801e-3f8df43833b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315483582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1315483582
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.453286626
Short name T508
Test name
Test status
Simulation time 34136560 ps
CPU time 0.81 seconds
Started Jun 04 02:01:35 PM PDT 24
Finished Jun 04 02:01:37 PM PDT 24
Peak memory 206684 kb
Host smart-cc11c276-32ab-440f-a3c2-fb6ec0097b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453286626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.453286626
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.332254279
Short name T181
Test name
Test status
Simulation time 24613198117 ps
CPU time 176.27 seconds
Started Jun 04 02:01:36 PM PDT 24
Finished Jun 04 02:04:34 PM PDT 24
Peak memory 250404 kb
Host smart-40700e84-22db-43a1-89ec-39a219a5df0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332254279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.332254279
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2785203416
Short name T83
Test name
Test status
Simulation time 22002024185 ps
CPU time 211.27 seconds
Started Jun 04 02:01:34 PM PDT 24
Finished Jun 04 02:05:06 PM PDT 24
Peak memory 249016 kb
Host smart-8626cb78-ff40-44a0-8b54-d424fc9f7e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785203416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2785203416
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3919880392
Short name T274
Test name
Test status
Simulation time 10057046954 ps
CPU time 122.97 seconds
Started Jun 04 02:01:37 PM PDT 24
Finished Jun 04 02:03:41 PM PDT 24
Peak memory 266360 kb
Host smart-e8657f7a-cdab-4f59-95d0-25429f11d9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919880392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3919880392
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3869209682
Short name T822
Test name
Test status
Simulation time 47008028536 ps
CPU time 39.5 seconds
Started Jun 04 02:01:38 PM PDT 24
Finished Jun 04 02:02:19 PM PDT 24
Peak memory 232296 kb
Host smart-d109b645-ee3f-4c91-8f5a-2cdb1f9dd793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869209682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3869209682
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1413440852
Short name T334
Test name
Test status
Simulation time 615712473 ps
CPU time 8.8 seconds
Started Jun 04 02:01:38 PM PDT 24
Finished Jun 04 02:01:49 PM PDT 24
Peak memory 220712 kb
Host smart-c4bdf405-5a9c-4f3b-93ec-1df55d7089a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413440852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1413440852
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3569100524
Short name T564
Test name
Test status
Simulation time 9930743500 ps
CPU time 78.04 seconds
Started Jun 04 02:01:36 PM PDT 24
Finished Jun 04 02:02:55 PM PDT 24
Peak memory 240604 kb
Host smart-17fab41b-c956-4617-96cc-4a9c8cd2ea97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569100524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3569100524
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2107807069
Short name T890
Test name
Test status
Simulation time 509017395 ps
CPU time 3.16 seconds
Started Jun 04 02:01:37 PM PDT 24
Finished Jun 04 02:01:42 PM PDT 24
Peak memory 232944 kb
Host smart-6d7d9db0-c69c-41d5-a93d-1e294f27d1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107807069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2107807069
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.4277492541
Short name T621
Test name
Test status
Simulation time 878280659 ps
CPU time 7.56 seconds
Started Jun 04 02:01:39 PM PDT 24
Finished Jun 04 02:01:47 PM PDT 24
Peak memory 232912 kb
Host smart-f54ef433-9c1b-4af0-bd1f-1206305060e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277492541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.4277492541
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4202813539
Short name T926
Test name
Test status
Simulation time 7650809825 ps
CPU time 11.15 seconds
Started Jun 04 02:01:33 PM PDT 24
Finished Jun 04 02:01:44 PM PDT 24
Peak memory 220292 kb
Host smart-49a1eb30-7aa5-4471-bdcb-f90614a27616
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4202813539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4202813539
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.348289212
Short name T789
Test name
Test status
Simulation time 35693014 ps
CPU time 1.01 seconds
Started Jun 04 02:01:37 PM PDT 24
Finished Jun 04 02:01:39 PM PDT 24
Peak memory 205428 kb
Host smart-8bd095c9-1744-4039-aa06-b746af865199
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348289212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.348289212
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3147930185
Short name T78
Test name
Test status
Simulation time 4245628880 ps
CPU time 20.55 seconds
Started Jun 04 02:01:33 PM PDT 24
Finished Jun 04 02:01:54 PM PDT 24
Peak memory 216464 kb
Host smart-7372a4c5-386e-45ff-bf1a-5556f5c47bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147930185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3147930185
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3565324609
Short name T869
Test name
Test status
Simulation time 2843050062 ps
CPU time 6.06 seconds
Started Jun 04 02:01:35 PM PDT 24
Finished Jun 04 02:01:42 PM PDT 24
Peak memory 216212 kb
Host smart-0b094c18-126f-471f-8e51-71639b239cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565324609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3565324609
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.906402593
Short name T538
Test name
Test status
Simulation time 4747755023 ps
CPU time 11.87 seconds
Started Jun 04 02:01:33 PM PDT 24
Finished Jun 04 02:01:46 PM PDT 24
Peak memory 216272 kb
Host smart-6c7d6f94-a73e-4295-9a9d-bf33eb7f9ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906402593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.906402593
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1384414559
Short name T11
Test name
Test status
Simulation time 65536820 ps
CPU time 0.88 seconds
Started Jun 04 02:01:35 PM PDT 24
Finished Jun 04 02:01:37 PM PDT 24
Peak memory 205552 kb
Host smart-b22f7dcc-ff5d-4ae8-a643-c5f7b4dcaaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384414559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1384414559
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3603437598
Short name T903
Test name
Test status
Simulation time 609863473 ps
CPU time 8.15 seconds
Started Jun 04 02:01:40 PM PDT 24
Finished Jun 04 02:01:49 PM PDT 24
Peak memory 234100 kb
Host smart-2d26bca3-371f-45e3-a2a8-cae9fb8bb264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603437598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3603437598
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1029584173
Short name T387
Test name
Test status
Simulation time 25999022 ps
CPU time 0.71 seconds
Started Jun 04 02:01:45 PM PDT 24
Finished Jun 04 02:01:47 PM PDT 24
Peak memory 204752 kb
Host smart-567c0b3c-5c06-4486-8840-b5e485cf1026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029584173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
029584173
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3818317344
Short name T189
Test name
Test status
Simulation time 371575480 ps
CPU time 5.09 seconds
Started Jun 04 02:01:45 PM PDT 24
Finished Jun 04 02:01:51 PM PDT 24
Peak memory 234256 kb
Host smart-6964b0ee-5d94-4330-abb7-d674094d3e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818317344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3818317344
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2177406915
Short name T735
Test name
Test status
Simulation time 15880887 ps
CPU time 0.83 seconds
Started Jun 04 02:01:35 PM PDT 24
Finished Jun 04 02:01:37 PM PDT 24
Peak memory 206468 kb
Host smart-31e317b9-2e92-4fa6-8ac0-cf11c5d6cd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177406915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2177406915
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.446738655
Short name T174
Test name
Test status
Simulation time 9310120128 ps
CPU time 98.17 seconds
Started Jun 04 02:01:39 PM PDT 24
Finished Jun 04 02:03:18 PM PDT 24
Peak memory 249128 kb
Host smart-e3a33a34-4c75-4535-9460-79107ba2da21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446738655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.446738655
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3951385305
Short name T264
Test name
Test status
Simulation time 23703166609 ps
CPU time 169.11 seconds
Started Jun 04 02:01:39 PM PDT 24
Finished Jun 04 02:04:29 PM PDT 24
Peak memory 254668 kb
Host smart-fea75749-873e-45d5-85c0-2fa73c9675cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951385305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3951385305
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3207403476
Short name T352
Test name
Test status
Simulation time 31979836101 ps
CPU time 54.81 seconds
Started Jun 04 02:01:38 PM PDT 24
Finished Jun 04 02:02:34 PM PDT 24
Peak memory 233676 kb
Host smart-84f13309-f24a-4ff8-ae59-f4cbf5440242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207403476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3207403476
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2095043493
Short name T77
Test name
Test status
Simulation time 582310369 ps
CPU time 4.58 seconds
Started Jun 04 02:01:40 PM PDT 24
Finished Jun 04 02:01:45 PM PDT 24
Peak memory 233104 kb
Host smart-aad60b9b-393f-4d29-80ce-79942b3a95ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095043493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2095043493
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.221693331
Short name T342
Test name
Test status
Simulation time 366475369 ps
CPU time 8.47 seconds
Started Jun 04 02:01:45 PM PDT 24
Finished Jun 04 02:01:54 PM PDT 24
Peak memory 233668 kb
Host smart-2fd66d4d-439e-405d-88a0-03d27b8ed089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221693331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.221693331
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1161914759
Short name T788
Test name
Test status
Simulation time 2102884812 ps
CPU time 5.8 seconds
Started Jun 04 02:01:38 PM PDT 24
Finished Jun 04 02:01:45 PM PDT 24
Peak memory 233044 kb
Host smart-68990160-59ca-4c2e-94ea-1ec37537f9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161914759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1161914759
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.213335114
Short name T307
Test name
Test status
Simulation time 17091863779 ps
CPU time 15.31 seconds
Started Jun 04 02:01:38 PM PDT 24
Finished Jun 04 02:01:54 PM PDT 24
Peak memory 237108 kb
Host smart-0e40fa86-ff93-4cf0-8aaf-5ca55f580d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213335114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.213335114
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1015593152
Short name T614
Test name
Test status
Simulation time 879061775 ps
CPU time 9.62 seconds
Started Jun 04 02:01:37 PM PDT 24
Finished Jun 04 02:01:48 PM PDT 24
Peak memory 222440 kb
Host smart-3911011c-117e-4b5e-b272-2b8219f86850
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1015593152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1015593152
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1264713294
Short name T658
Test name
Test status
Simulation time 50699394490 ps
CPU time 172.18 seconds
Started Jun 04 02:01:43 PM PDT 24
Finished Jun 04 02:04:36 PM PDT 24
Peak memory 253584 kb
Host smart-44622f7c-0435-492a-bb97-218d3a5da5a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264713294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1264713294
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3625691938
Short name T715
Test name
Test status
Simulation time 2106256029 ps
CPU time 13.49 seconds
Started Jun 04 02:01:34 PM PDT 24
Finished Jun 04 02:01:49 PM PDT 24
Peak memory 219372 kb
Host smart-e838a601-5bc3-426b-80e8-c48e989684da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625691938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3625691938
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.608896085
Short name T526
Test name
Test status
Simulation time 6594511173 ps
CPU time 17 seconds
Started Jun 04 02:01:35 PM PDT 24
Finished Jun 04 02:01:53 PM PDT 24
Peak memory 216188 kb
Host smart-38dcf45c-ced8-4e2a-b7a4-d0df16ad32c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608896085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.608896085
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.152030159
Short name T581
Test name
Test status
Simulation time 35192589 ps
CPU time 0.67 seconds
Started Jun 04 02:01:43 PM PDT 24
Finished Jun 04 02:01:44 PM PDT 24
Peak memory 205424 kb
Host smart-1efc9255-e09f-40e6-af6e-ccba060d12c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152030159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.152030159
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.24280891
Short name T491
Test name
Test status
Simulation time 95502502 ps
CPU time 0.73 seconds
Started Jun 04 02:01:36 PM PDT 24
Finished Jun 04 02:01:38 PM PDT 24
Peak memory 205724 kb
Host smart-615f80de-e06c-41b4-918f-cbd7e42a8953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24280891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.24280891
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.372300447
Short name T677
Test name
Test status
Simulation time 939791641 ps
CPU time 8.13 seconds
Started Jun 04 02:01:39 PM PDT 24
Finished Jun 04 02:01:49 PM PDT 24
Peak memory 218804 kb
Host smart-81cd12e2-47ea-4d79-90fb-d363ee8df216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372300447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.372300447
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2593557822
Short name T666
Test name
Test status
Simulation time 13449284 ps
CPU time 0.7 seconds
Started Jun 04 02:01:49 PM PDT 24
Finished Jun 04 02:01:51 PM PDT 24
Peak memory 204800 kb
Host smart-21e5f48e-d9c6-4341-b93d-ca1a961df05a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593557822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
593557822
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2696566579
Short name T337
Test name
Test status
Simulation time 685334094 ps
CPU time 4.24 seconds
Started Jun 04 02:01:40 PM PDT 24
Finished Jun 04 02:01:45 PM PDT 24
Peak memory 237188 kb
Host smart-ae29b065-a961-4fb4-acec-141cf46e2745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696566579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2696566579
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3001387255
Short name T652
Test name
Test status
Simulation time 22790201 ps
CPU time 0.74 seconds
Started Jun 04 02:01:39 PM PDT 24
Finished Jun 04 02:01:41 PM PDT 24
Peak memory 206428 kb
Host smart-d38ea4db-b84d-42d8-9150-97e7dbeafa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001387255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3001387255
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3651652344
Short name T948
Test name
Test status
Simulation time 8167635653 ps
CPU time 15.69 seconds
Started Jun 04 02:01:40 PM PDT 24
Finished Jun 04 02:01:56 PM PDT 24
Peak memory 233688 kb
Host smart-418ee444-ef23-4a6c-b279-93b14ab479cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651652344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3651652344
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.493435110
Short name T207
Test name
Test status
Simulation time 25007666568 ps
CPU time 67.64 seconds
Started Jun 04 02:01:41 PM PDT 24
Finished Jun 04 02:02:49 PM PDT 24
Peak memory 252256 kb
Host smart-a128cb4c-c442-471a-b7dc-c76ca29e81b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493435110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.493435110
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4146083899
Short name T901
Test name
Test status
Simulation time 5888582204 ps
CPU time 22.8 seconds
Started Jun 04 02:01:46 PM PDT 24
Finished Jun 04 02:02:10 PM PDT 24
Peak memory 222700 kb
Host smart-50e946a5-c00f-451d-b1ec-84133943375f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146083899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4146083899
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.538192197
Short name T55
Test name
Test status
Simulation time 302995373 ps
CPU time 4.71 seconds
Started Jun 04 02:01:43 PM PDT 24
Finished Jun 04 02:01:49 PM PDT 24
Peak memory 232576 kb
Host smart-20ecc9f1-03f8-4666-ba31-2be54c024820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538192197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.538192197
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1022469036
Short name T622
Test name
Test status
Simulation time 98453778 ps
CPU time 2.42 seconds
Started Jun 04 02:01:41 PM PDT 24
Finished Jun 04 02:01:44 PM PDT 24
Peak memory 221276 kb
Host smart-3a0c02a5-ef61-4eae-983b-55fbf371212f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022469036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1022469036
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1589301926
Short name T292
Test name
Test status
Simulation time 7677884647 ps
CPU time 53.34 seconds
Started Jun 04 02:01:43 PM PDT 24
Finished Jun 04 02:02:37 PM PDT 24
Peak memory 247284 kb
Host smart-6ec62c04-c8c1-4449-b0ac-27380be9edcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589301926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1589301926
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.794697975
Short name T270
Test name
Test status
Simulation time 19192572886 ps
CPU time 57.19 seconds
Started Jun 04 02:01:43 PM PDT 24
Finished Jun 04 02:02:40 PM PDT 24
Peak memory 248964 kb
Host smart-e6b5b4ec-8444-4651-824a-fb2e3bb6ec6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794697975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
794697975
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3736333003
Short name T854
Test name
Test status
Simulation time 2044022216 ps
CPU time 3.36 seconds
Started Jun 04 02:01:39 PM PDT 24
Finished Jun 04 02:01:44 PM PDT 24
Peak memory 233768 kb
Host smart-13bfc48b-c9f1-4a64-a0a4-b2a2102d84b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736333003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3736333003
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1374458178
Short name T73
Test name
Test status
Simulation time 109830464 ps
CPU time 3.27 seconds
Started Jun 04 02:01:43 PM PDT 24
Finished Jun 04 02:01:46 PM PDT 24
Peak memory 219164 kb
Host smart-212d2c84-1723-46f4-b56b-497df166401b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1374458178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1374458178
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1613635409
Short name T157
Test name
Test status
Simulation time 108983351 ps
CPU time 1.07 seconds
Started Jun 04 02:01:48 PM PDT 24
Finished Jun 04 02:01:50 PM PDT 24
Peak memory 206872 kb
Host smart-8b5998f5-061a-412b-b15b-60766caf65d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613635409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1613635409
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3719031298
Short name T597
Test name
Test status
Simulation time 15161175746 ps
CPU time 10.36 seconds
Started Jun 04 02:01:41 PM PDT 24
Finished Jun 04 02:01:52 PM PDT 24
Peak memory 219932 kb
Host smart-6de876cf-7931-49be-8d26-cabfade973ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719031298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3719031298
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2738713907
Short name T471
Test name
Test status
Simulation time 1580065747 ps
CPU time 7.72 seconds
Started Jun 04 02:01:43 PM PDT 24
Finished Jun 04 02:01:51 PM PDT 24
Peak memory 216068 kb
Host smart-4180ad0c-5b42-49f9-b5d0-23d6b4a12f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738713907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2738713907
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.652082416
Short name T624
Test name
Test status
Simulation time 449532751 ps
CPU time 2.25 seconds
Started Jun 04 02:01:39 PM PDT 24
Finished Jun 04 02:01:42 PM PDT 24
Peak memory 216176 kb
Host smart-14a7bfda-253c-4ca5-9957-edd78208d915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652082416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.652082416
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3527102789
Short name T768
Test name
Test status
Simulation time 112760633 ps
CPU time 0.83 seconds
Started Jun 04 02:01:39 PM PDT 24
Finished Jun 04 02:01:41 PM PDT 24
Peak memory 205628 kb
Host smart-18597d5a-7175-49df-af61-1026305db6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527102789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3527102789
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.4121915320
Short name T317
Test name
Test status
Simulation time 14099361391 ps
CPU time 22.86 seconds
Started Jun 04 02:01:38 PM PDT 24
Finished Jun 04 02:02:02 PM PDT 24
Peak memory 226680 kb
Host smart-b1e5d4c2-6095-4985-98db-177ddc07acea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121915320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4121915320
Directory /workspace/9.spi_device_upload/latest
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