Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3623655	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3910585

1

T1

513

T2

2189

T3

51

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4216873	1			T1	1		T2	829		T3	140
values[0x0]	1657046	1			T1	304		T2	870		T3	27
values[0x1]	1660321	1			T1	296		T2	897		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2559985	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4974255

1

T1

534

T2

2269

T3

101

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31053	1			T1	2		T3	2		T4	225
valid_sources[0x01]	29882	1			T3	1		T4	208		T6	3
valid_sources[0x02]	27641	1			T1	5		T4	197		T6	9
valid_sources[0x03]	29706	1			T4	207		T6	6		T9	17
valid_sources[0x04]	30085	1			T1	4		T4	191		T6	3
valid_sources[0x05]	27979	1			T1	2		T4	229		T6	4
valid_sources[0x06]	28224	1			T1	2		T4	231		T6	2
valid_sources[0x07]	28113	1			T4	244		T9	19		T11	834
valid_sources[0x08]	34246	1			T4	247		T6	4		T9	22
valid_sources[0x09]	30223	1			T1	1		T2	2		T3	5
valid_sources[0x0a]	30823	1			T3	2		T4	223		T6	4
valid_sources[0x0b]	29326	1			T4	201		T6	1		T9	16
valid_sources[0x0c]	26848	1			T4	190		T6	7		T9	20
valid_sources[0x0d]	28123	1			T3	3		T4	209		T6	3
valid_sources[0x0e]	30712	1			T2	416		T3	1		T4	248
valid_sources[0x0f]	37307	1			T2	1		T3	2		T4	225
valid_sources[0x10]	28435	1			T1	4		T4	236		T6	2
valid_sources[0x11]	27836	1			T4	200		T6	6		T9	14
valid_sources[0x12]	31841	1			T1	2		T4	255		T6	7
valid_sources[0x13]	28762	1			T1	2		T3	2		T4	241
valid_sources[0x14]	29398	1			T1	6		T4	259		T6	5
valid_sources[0x15]	29247	1			T3	1		T4	241		T6	6
valid_sources[0x16]	29134	1			T4	213		T6	2		T9	21
valid_sources[0x17]	28907	1			T4	220		T6	5		T9	6
valid_sources[0x18]	29857	1			T3	8		T4	234		T6	6
valid_sources[0x19]	30754	1			T3	1		T4	213		T6	5
valid_sources[0x1a]	27234	1			T1	5		T4	275		T6	3
valid_sources[0x1b]	29491	1			T1	2		T4	214		T6	6
valid_sources[0x1c]	42412	1			T1	16		T4	244		T6	3
valid_sources[0x1d]	28006	1			T1	9		T4	243		T6	1
valid_sources[0x1e]	29962	1			T3	2		T4	241		T6	4
valid_sources[0x1f]	28842	1			T1	1		T3	1		T4	240
valid_sources[0x20]	28517	1			T1	3		T3	1		T4	230
valid_sources[0x21]	33639	1			T1	1		T4	232		T6	6
valid_sources[0x22]	27668	1			T3	5		T4	226		T6	4
valid_sources[0x23]	33051	1			T1	2		T4	211		T6	4
valid_sources[0x24]	27944	1			T3	6		T4	219		T6	5
valid_sources[0x25]	35074	1			T1	3		T3	1		T4	218
valid_sources[0x26]	26276	1			T1	5		T4	241		T6	2
valid_sources[0x27]	32710	1			T1	3		T3	3		T4	282
valid_sources[0x28]	27744	1			T1	5		T4	225		T6	5
valid_sources[0x29]	29499	1			T1	2		T4	202		T6	4
valid_sources[0x2a]	26558	1			T3	1		T4	215		T6	5
valid_sources[0x2b]	27744	1			T1	2		T3	1		T4	230
valid_sources[0x2c]	27839	1			T3	3		T4	209		T6	3
valid_sources[0x2d]	29687	1			T3	2		T4	195		T6	7
valid_sources[0x2e]	28381	1			T1	5		T4	214		T6	2
valid_sources[0x2f]	31172	1			T4	260		T6	4		T11	232
valid_sources[0x30]	29757	1			T3	2		T4	196		T6	7
valid_sources[0x31]	28960	1			T3	3		T4	221		T6	5
valid_sources[0x32]	29122	1			T1	2		T4	258		T6	3
valid_sources[0x33]	27591	1			T3	3		T4	238		T6	6
valid_sources[0x34]	29974	1			T4	254		T6	5		T7	2
valid_sources[0x35]	28479	1			T4	270		T6	1		T9	4
valid_sources[0x36]	26396	1			T4	262		T6	6		T9	3
valid_sources[0x37]	30147	1			T4	228		T6	3		T9	2
valid_sources[0x38]	28516	1			T4	230		T6	1		T7	2
valid_sources[0x39]	32358	1			T4	239		T6	5		T9	26
valid_sources[0x3a]	28873	1			T4	244		T6	5		T9	18
valid_sources[0x3b]	29681	1			T1	4		T3	1		T4	277
valid_sources[0x3c]	30790	1			T1	1		T3	1		T4	224
valid_sources[0x3d]	34875	1			T3	6		T4	250		T6	8
valid_sources[0x3e]	28544	1			T4	238		T6	5		T9	34
valid_sources[0x3f]	29683	1			T4	221		T6	3		T9	11
valid_sources[0x40]	27775	1			T3	5		T4	225		T6	7
valid_sources[0x41]	30287	1			T4	253		T6	5		T9	15
valid_sources[0x42]	25848	1			T1	5		T4	220		T6	3
valid_sources[0x43]	27079	1			T1	3		T2	1		T4	249
valid_sources[0x44]	29996	1			T4	211		T6	5		T9	5
valid_sources[0x45]	28704	1			T3	2		T4	250		T6	4
valid_sources[0x46]	27872	1			T1	3		T4	246		T6	7
valid_sources[0x47]	27652	1			T4	201		T6	2		T9	16
valid_sources[0x48]	34212	1			T1	9		T4	231		T6	6
valid_sources[0x49]	26962	1			T1	5		T4	277		T6	4
valid_sources[0x4a]	27438	1			T3	2		T4	214		T6	9
valid_sources[0x4b]	33250	1			T4	209		T6	2		T9	21
valid_sources[0x4c]	27340	1			T3	3		T4	226		T6	2
valid_sources[0x4d]	30607	1			T1	2		T4	251		T6	9
valid_sources[0x4e]	28955	1			T4	224		T9	26		T11	102
valid_sources[0x4f]	28715	1			T4	216		T6	6		T9	5
valid_sources[0x50]	33999	1			T3	1		T4	248		T6	2
valid_sources[0x51]	27699	1			T1	1		T4	232		T6	3
valid_sources[0x52]	28841	1			T1	1		T3	1		T4	235
valid_sources[0x53]	26488	1			T4	203		T6	4		T9	14
valid_sources[0x54]	26297	1			T1	5		T3	2		T4	234
valid_sources[0x55]	27275	1			T3	4		T4	208		T9	5
valid_sources[0x56]	29520	1			T1	1		T4	264		T6	4
valid_sources[0x57]	28564	1			T1	4		T4	244		T6	3
valid_sources[0x58]	27539	1			T1	2		T4	248		T6	4
valid_sources[0x59]	27728	1			T1	9		T4	262		T6	3
valid_sources[0x5a]	29466	1			T1	3		T4	219		T6	1
valid_sources[0x5b]	28438	1			T4	208		T6	1		T9	17
valid_sources[0x5c]	28755	1			T1	2		T4	247		T6	5
valid_sources[0x5d]	30095	1			T4	218		T6	2		T7	3
valid_sources[0x5e]	30450	1			T1	1		T4	232		T6	2
valid_sources[0x5f]	27192	1			T4	223		T6	6		T9	10
valid_sources[0x60]	28120	1			T1	4		T3	3		T4	247
valid_sources[0x61]	30393	1			T3	2		T4	241		T6	1
valid_sources[0x62]	28785	1			T2	1		T3	1		T4	243
valid_sources[0x63]	31996	1			T3	2		T4	210		T6	3
valid_sources[0x64]	27955	1			T1	2		T4	232		T6	4
valid_sources[0x65]	27770	1			T1	1		T4	234		T6	2
valid_sources[0x66]	28713	1			T1	1		T4	235		T6	9
valid_sources[0x67]	28368	1			T1	3		T2	1		T4	228
valid_sources[0x68]	27360	1			T4	189		T6	2		T11	193
valid_sources[0x69]	27174	1			T1	9		T4	216		T6	9
valid_sources[0x6a]	29941	1			T4	193		T6	2		T9	32
valid_sources[0x6b]	32902	1			T3	1		T4	229		T6	6
valid_sources[0x6c]	29280	1			T4	217		T6	2		T8	426
valid_sources[0x6d]	26994	1			T4	252		T6	3		T9	5
valid_sources[0x6e]	31448	1			T1	15		T4	242		T6	2
valid_sources[0x6f]	28661	1			T4	196		T6	4		T9	15
valid_sources[0x70]	27317	1			T1	13		T4	219		T6	7
valid_sources[0x71]	48809	1			T1	5		T4	212		T6	4
valid_sources[0x72]	32269	1			T4	219		T6	6		T9	9
valid_sources[0x73]	26348	1			T4	221		T6	10		T9	11
valid_sources[0x74]	32122	1			T3	1		T4	209		T6	2
valid_sources[0x75]	30012	1			T1	5		T4	214		T6	4
valid_sources[0x76]	29854	1			T1	1		T4	238		T6	3
valid_sources[0x77]	29671	1			T1	14		T2	1		T4	235
valid_sources[0x78]	30050	1			T4	222		T6	7		T9	23
valid_sources[0x79]	29447	1			T1	1		T3	2		T4	244
valid_sources[0x7a]	26755	1			T1	1		T4	209		T6	2
valid_sources[0x7b]	27704	1			T1	4		T4	219		T6	5
valid_sources[0x7c]	27647	1			T3	3		T4	213		T6	7
valid_sources[0x7d]	26321	1			T4	220		T6	1		T9	27
valid_sources[0x7e]	29128	1			T4	258		T6	5		T9	9
valid_sources[0x7f]	28210	1			T1	2		T4	218		T6	2
valid_sources[0x80]	26830	1			T1	1		T4	222		T6	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

938436

1

T1

1

T2

430

T3

9

values[0x0]

all_enables

biggest_size

1497393

1

T1

259

T2

867

T3

24

values[0x1]

all_enables

biggest_size

1474756

1

T1

253

T2

892

T3

18