Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3648066

1

T1

88

T2

407

T3

138

full_word

3911988

1

T1

513

T2

2189

T3

51

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7559674	1			T1	601		T2	2596		T3	189
auto[TlIntgErrCmd]	133	1			T45	5		T80	7		T81	6
auto[TlIntgErrData]	130	1			T45	11		T80	13		T81	9
auto[TlIntgErrBoth]	117	1			T45	4		T80	10		T81	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4220788

1

T1

1

T2

829

T3

140

auto[1]

3339266

1

T1

600

T2

1767

T3

49

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3281863	1			T2	399		T3	131		T4	27519
auto[TlIntgErrNone]	partial	auto[1]	365850	1			T1	88		T2	8		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	938746	1			T1	1		T2	430		T3	9
auto[TlIntgErrNone]	full_word	auto[1]	2973215	1			T1	512		T2	1759		T3	42
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T45	2		T80	2		T81	6
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T45	2		T80	5		T96	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T45	1		T230	1		T231	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T96	1		T98	1		T232	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T45	9		T80	6		T81	4
auto[TlIntgErrData]	partial	auto[1]	59	1			T45	2		T80	7		T81	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T96	2		T231	1		T233	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T81	2		T96	1		T139	1
auto[TlIntgErrBoth]	partial	auto[0]	54	1			T45	3		T80	5		T81	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T45	1		T80	5		T81	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T234	1		T231	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T138	1		T233	1		T235	1