Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382372693	2504044	0	0
DepthKnown_A	382372693	382245004	0	0
RvalidKnown_A	382372693	382245004	0	0
WreadyKnown_A	382372693	382245004	0	0
gen_passthru_fifo.paramCheckPass	1079	1079	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	2504044	0	0
T2	544690	2502	0	0
T3	2323	0	0	0
T4	322640	17465	0	0
T5	2141	0	0	0
T6	79352	832	0	0
T7	1547	0	0	0
T8	2810	1664	0	0
T9	60405	1663	0	0
T10	1282	0	0	0
T11	480046	14138	0	0
T12	0	1669	0	0
T13	0	19988	0	0
T14	0	9149	0	0
T15	0	14156	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1079	1079	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382372693	2758300	0	0
DepthKnown_A	382372693	382245004	0	0
RvalidKnown_A	382372693	382245004	0	0
WreadyKnown_A	382372693	382245004	0	0
gen_passthru_fifo.paramCheckPass	1079	1079	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	2758300	0	0
T2	544690	4670	0	0
T3	2323	0	0	0
T4	322640	11648	0	0
T5	2141	0	0	0
T6	79352	832	0	0
T7	1547	0	0	0
T8	2810	833	0	0
T9	60405	832	0	0
T10	1282	0	0	0
T11	480046	9152	0	0
T12	0	838	0	0
T13	0	23745	0	0
T14	0	6656	0	0
T15	0	21890	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1079	1079	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382372693	164953	0	0
DepthKnown_A	382372693	382245004	0	0
RvalidKnown_A	382372693	382245004	0	0
WreadyKnown_A	382372693	382245004	0	0
gen_passthru_fifo.paramCheckPass	1079	1079	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	164953	0	0
T3	2323	3	0	0
T4	322640	794	0	0
T5	2141	0	0	0
T6	79352	0	0	0
T7	1547	0	0	0
T8	2810	0	0	0
T9	60405	0	0	0
T10	1282	0	0	0
T11	480046	488	0	0
T13	0	806	0	0
T14	0	1150	0	0
T15	0	1190	0	0
T16	0	521	0	0
T22	0	1338	0	0
T23	0	834	0	0
T24	0	841	0	0
T25	1297	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1079	1079	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382372693	386895	0	0
DepthKnown_A	382372693	382245004	0	0
RvalidKnown_A	382372693	382245004	0	0
WreadyKnown_A	382372693	382245004	0	0
gen_passthru_fifo.paramCheckPass	1079	1079	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	386895	0	0
T3	2323	3	0	0
T4	322640	794	0	0
T5	2141	0	0	0
T6	79352	0	0	0
T7	1547	0	0	0
T8	2810	0	0	0
T9	60405	0	0	0
T10	1282	0	0	0
T11	480046	488	0	0
T13	0	3726	0	0
T14	0	1150	0	0
T15	0	4762	0	0
T16	0	521	0	0
T22	0	6178	0	0
T23	0	834	0	0
T24	0	3687	0	0
T25	1297	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1079	1079	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382372693	6186309	0	0
DepthKnown_A	382372693	382245004	0	0
RvalidKnown_A	382372693	382245004	0	0
WreadyKnown_A	382372693	382245004	0	0
gen_passthru_fifo.paramCheckPass	1079	1079	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	6186309	0	0
T1	377823	601	0	0
T2	544690	932	0	0
T3	2323	186	0	0
T4	322640	46567	0	0
T5	2141	17	0	0
T6	79352	188	0	0
T7	1547	63	0	0
T8	2810	46	0	0
T9	60405	2347	0	0
T10	1282	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1079	1079	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	382372693	13220308	0	0
DepthKnown_A	382372693	382245004	0	0
RvalidKnown_A	382372693	382245004	0	0
WreadyKnown_A	382372693	382245004	0	0
gen_passthru_fifo.paramCheckPass	1079	1079	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	13220308	0	0
T1	377823	601	0	0
T2	544690	4138	0	0
T3	2323	186	0	0
T4	322640	46278	0	0
T5	2141	17	0	0
T6	79352	188	0	0
T7	1547	63	0	0
T8	2810	139	0	0
T9	60405	2347	0	0
T10	1282	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382372693	382245004	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1079	1079	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0