Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T11
1	0	Covered	T3,T4,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T4,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T11
1	0	Covered	T2,T4,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Unreachable
1	1	Covered	T2,T4,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	637496103	507421157	0	0
CheckNGreaterZero_A	2712	2712	0	0
GntImpliesReady_A	637496103	3142329	0	0
GntImpliesValid_A	637496103	3142329	0	0
GrantKnown_A	637496103	507421157	0	0
IdxKnown_A	637496103	507421157	0	0
IndexIsCorrect_A	637496103	3142329	0	0
LockArbDecision_A	637496103	0	0	0
NoReadyValidNoGrant_A	637496103	0	0	0
ReadyAndValidImplyGrant_A	637496103	3142329	0	0
ReqAndReadyImplyGrant_A	637496103	3142329	0	0
ReqImpliesValid_A	637496103	3142329	0	0
ReqStaysHighUntilGranted0_M	637496103	0	0	0
RoundRobin_A	637496103	4	0	904
ValidKnown_A	637496103	507421157	0	0
gen_data_port_assertion.DataFlow_A	637496103	3142329	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637496103	507421157	0	0
T1	450872	448456	0	0
T2	720304	631610	0	0
T3	5619	3916	0	0
T4	532666	1366960	0	0
T5	2861	2411	0	0
T6	222052	150504	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	117181	88736	0	0
T10	1282	1229	0	0
T11	1598510	794268	0	0
T12	115716	57824	0	0
T13	1889408	937266	0	0
T14	450350	441032	0	0
T15	0	487428	0	0
T16	0	66000	0	0
T17	0	99152	0	0
T22	0	141488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2712	2712	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637496103	3142329	0	0
T2	632497	1672	0	0
T3	5619	93	0	0
T4	532666	20407	0	0
T5	2861	0	0	0
T6	222052	832	0	0
T7	1547	0	0	0
T8	2810	832	0	0
T9	117181	832	0	0
T10	1282	0	0	0
T11	2078556	16717	0	0
T12	115716	832	0	0
T13	1889408	18430	0	0
T14	900700	18039	0	0
T15	494114	10214	0	0
T16	0	2955	0	0
T22	0	7526	0	0
T23	0	4336	0	0
T24	0	7567	0	0
T26	0	2730	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637496103	3142329	0	0
T2	632497	1672	0	0
T3	5619	93	0	0
T4	532666	20407	0	0
T5	2861	0	0	0
T6	222052	832	0	0
T7	1547	0	0	0
T8	2810	832	0	0
T9	117181	832	0	0
T10	1282	0	0	0
T11	2078556	16717	0	0
T12	115716	832	0	0
T13	1889408	18430	0	0
T14	900700	18039	0	0
T15	494114	10214	0	0
T16	0	2955	0	0
T22	0	7526	0	0
T23	0	4336	0	0
T24	0	7567	0	0
T26	0	2730	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637496103	507421157	0	0
T1	450872	448456	0	0
T2	720304	631610	0	0
T3	5619	3916	0	0
T4	532666	1366960	0	0
T5	2861	2411	0	0
T6	222052	150504	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	117181	88736	0	0
T10	1282	1229	0	0
T11	1598510	794268	0	0
T12	115716	57824	0	0
T13	1889408	937266	0	0
T14	450350	441032	0	0
T15	0	487428	0	0
T16	0	66000	0	0
T17	0	99152	0	0
T22	0	141488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637496103	507421157	0	0
T1	450872	448456	0	0
T2	720304	631610	0	0
T3	5619	3916	0	0
T4	532666	1366960	0	0
T5	2861	2411	0	0
T6	222052	150504	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	117181	88736	0	0
T10	1282	1229	0	0
T11	1598510	794268	0	0
T12	115716	57824	0	0
T13	1889408	937266	0	0
T14	450350	441032	0	0
T15	0	487428	0	0
T16	0	66000	0	0
T17	0	99152	0	0
T22	0	141488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637496103	3142329	0	0
T2	632497	1672	0	0
T3	5619	93	0	0
T4	532666	20407	0	0
T5	2861	0	0	0
T6	222052	832	0	0
T7	1547	0	0	0
T8	2810	832	0	0
T9	117181	832	0	0
T10	1282	0	0	0
T11	2078556	16717	0	0
T12	115716	832	0	0
T13	1889408	18430	0	0
T14	900700	18039	0	0
T15	494114	10214	0	0
T16	0	2955	0	0
T22	0	7526	0	0
T23	0	4336	0	0
T24	0	7567	0	0
T26	0	2730	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637496103	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637496103	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637496103	3142329	0	0
T2	632497	1672	0	0
T3	5619	93	0	0
T4	532666	20407	0	0
T5	2861	0	0	0
T6	222052	832	0	0
T7	1547	0	0	0
T8	2810	832	0	0
T9	117181	832	0	0
T10	1282	0	0	0
T11	2078556	16717	0	0
T12	115716	832	0	0
T13	1889408	18430	0	0
T14	900700	18039	0	0
T15	494114	10214	0	0
T16	0	2955	0	0
T22	0	7526	0	0
T23	0	4336	0	0
T24	0	7567	0	0
T26	0	2730	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637496103	3142329	0	0
T2	632497	1672	0	0
T3	5619	93	0	0
T4	532666	20407	0	0
T5	2861	0	0	0
T6	222052	832	0	0
T7	1547	0	0	0
T8	2810	832	0	0
T9	117181	832	0	0
T10	1282	0	0	0
T11	2078556	16717	0	0
T12	115716	832	0	0
T13	1889408	18430	0	0
T14	900700	18039	0	0
T15	494114	10214	0	0
T16	0	2955	0	0
T22	0	7526	0	0
T23	0	4336	0	0
T24	0	7567	0	0
T26	0	2730	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637496103	3142329	0	0
T2	632497	1672	0	0
T3	5619	93	0	0
T4	532666	20407	0	0
T5	2861	0	0	0
T6	222052	832	0	0
T7	1547	0	0	0
T8	2810	832	0	0
T9	117181	832	0	0
T10	1282	0	0	0
T11	2078556	16717	0	0
T12	115716	832	0	0
T13	1889408	18430	0	0
T14	900700	18039	0	0
T15	494114	10214	0	0
T16	0	2955	0	0
T22	0	7526	0	0
T23	0	4336	0	0
T24	0	7567	0	0
T26	0	2730	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	637496103	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637496103	4	0	904
T14	223697	1	0	1
T15	300018	0	0	1
T16	478715	0	0	1
T17	104427	0	0	1
T18	19217	0	0	1
T20	0	1	0	0
T22	470964	0	0	1
T32	8925	0	0	1
T35	0	1	0	0
T36	0	1	0	0
T37	211807	0	0	1
T38	86319	0	0	1
T39	20754	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637496103	507421157	0	0
T1	450872	448456	0	0
T2	720304	631610	0	0
T3	5619	3916	0	0
T4	532666	1366960	0	0
T5	2861	2411	0	0
T6	222052	150504	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	117181	88736	0	0
T10	1282	1229	0	0
T11	1598510	794268	0	0
T12	115716	57824	0	0
T13	1889408	937266	0	0
T14	450350	441032	0	0
T15	0	487428	0	0
T16	0	66000	0	0
T17	0	99152	0	0
T22	0	141488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	637496103	3142329	0	0
T2	632497	1672	0	0
T3	5619	93	0	0
T4	532666	20407	0	0
T5	2861	0	0	0
T6	222052	832	0	0
T7	1547	0	0	0
T8	2810	832	0	0
T9	117181	832	0	0
T10	1282	0	0	0
T11	2078556	16717	0	0
T12	115716	832	0	0
T13	1889408	18430	0	0
T14	900700	18039	0	0
T15	494114	10214	0	0
T16	0	2955	0	0
T22	0	7526	0	0
T23	0	4336	0	0
T24	0	7567	0	0
T26	0	2730	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T11
1	0	Covered	T3,T4,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T4,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T11
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	128681044	27655781	0	0
CheckNGreaterZero_A	904	904	0	0
GntImpliesReady_A	128681044	644824	0	0
GntImpliesValid_A	128681044	644824	0	0
GrantKnown_A	128681044	27655781	0	0
IdxKnown_A	128681044	27655781	0	0
IndexIsCorrect_A	128681044	644824	0	0
LockArbDecision_A	128681044	0	0	0
NoReadyValidNoGrant_A	128681044	0	0	0
ReadyAndValidImplyGrant_A	128681044	644824	0	0
ReqAndReadyImplyGrant_A	128681044	644824	0	0
ReqImpliesValid_A	128681044	644824	0	0
ReqStaysHighUntilGranted0_M	128681044	0	0	0
RoundRobin_A	128681044	0	0	0
ValidKnown_A	128681044	27655781	0	0
gen_data_port_assertion.DataFlow_A	128681044	644824	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	27655781	0	0
T1	73049	70728	0	0
T2	87807	0	0	0
T3	1648	1648	0	0
T4	105013	88568	0	0
T5	360	360	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	37904	0	0
T12	57858	0	0	0
T13	944704	70712	0	0
T14	0	137032	0	0
T15	0	87512	0	0
T16	0	66000	0	0
T22	0	141488	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	904	904	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	644824	0	0
T3	1648	51	0	0
T4	105013	3337	0	0
T5	360	0	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	1458	0	0
T12	57858	0	0	0
T13	944704	2593	0	0
T14	450350	5521	0	0
T15	494114	3902	0	0
T16	0	2955	0	0
T22	0	6610	0	0
T23	0	4326	0	0
T24	0	1701	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	644824	0	0
T3	1648	51	0	0
T4	105013	3337	0	0
T5	360	0	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	1458	0	0
T12	57858	0	0	0
T13	944704	2593	0	0
T14	450350	5521	0	0
T15	494114	3902	0	0
T16	0	2955	0	0
T22	0	6610	0	0
T23	0	4326	0	0
T24	0	1701	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	27655781	0	0
T1	73049	70728	0	0
T2	87807	0	0	0
T3	1648	1648	0	0
T4	105013	88568	0	0
T5	360	360	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	37904	0	0
T12	57858	0	0	0
T13	944704	70712	0	0
T14	0	137032	0	0
T15	0	87512	0	0
T16	0	66000	0	0
T22	0	141488	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	27655781	0	0
T1	73049	70728	0	0
T2	87807	0	0	0
T3	1648	1648	0	0
T4	105013	88568	0	0
T5	360	360	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	37904	0	0
T12	57858	0	0	0
T13	944704	70712	0	0
T14	0	137032	0	0
T15	0	87512	0	0
T16	0	66000	0	0
T22	0	141488	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	644824	0	0
T3	1648	51	0	0
T4	105013	3337	0	0
T5	360	0	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	1458	0	0
T12	57858	0	0	0
T13	944704	2593	0	0
T14	450350	5521	0	0
T15	494114	3902	0	0
T16	0	2955	0	0
T22	0	6610	0	0
T23	0	4326	0	0
T24	0	1701	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	644824	0	0
T3	1648	51	0	0
T4	105013	3337	0	0
T5	360	0	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	1458	0	0
T12	57858	0	0	0
T13	944704	2593	0	0
T14	450350	5521	0	0
T15	494114	3902	0	0
T16	0	2955	0	0
T22	0	6610	0	0
T23	0	4326	0	0
T24	0	1701	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	644824	0	0
T3	1648	51	0	0
T4	105013	3337	0	0
T5	360	0	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	1458	0	0
T12	57858	0	0	0
T13	944704	2593	0	0
T14	450350	5521	0	0
T15	494114	3902	0	0
T16	0	2955	0	0
T22	0	6610	0	0
T23	0	4326	0	0
T24	0	1701	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	644824	0	0
T3	1648	51	0	0
T4	105013	3337	0	0
T5	360	0	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	1458	0	0
T12	57858	0	0	0
T13	944704	2593	0	0
T14	450350	5521	0	0
T15	494114	3902	0	0
T16	0	2955	0	0
T22	0	6610	0	0
T23	0	4326	0	0
T24	0	1701	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	27655781	0	0
T1	73049	70728	0	0
T2	87807	0	0	0
T3	1648	1648	0	0
T4	105013	88568	0	0
T5	360	360	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	37904	0	0
T12	57858	0	0	0
T13	944704	70712	0	0
T14	0	137032	0	0
T15	0	87512	0	0
T16	0	66000	0	0
T22	0	141488	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	644824	0	0
T3	1648	51	0	0
T4	105013	3337	0	0
T5	360	0	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	1458	0	0
T12	57858	0	0	0
T13	944704	2593	0	0
T14	450350	5521	0	0
T15	494114	3902	0	0
T16	0	2955	0	0
T22	0	6610	0	0
T23	0	4326	0	0
T24	0	1701	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T11
1	0	Covered	T2,T4,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Unreachable
1	1	Covered	T2,T4,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T11
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	128681044	99715364	0	0
CheckNGreaterZero_A	904	904	0	0
GntImpliesReady_A	128681044	512611	0	0
GntImpliesValid_A	128681044	512611	0	0
GrantKnown_A	128681044	99715364	0	0
IdxKnown_A	128681044	99715364	0	0
IndexIsCorrect_A	128681044	512611	0	0
LockArbDecision_A	128681044	0	0	0
NoReadyValidNoGrant_A	128681044	0	0	0
ReadyAndValidImplyGrant_A	128681044	512611	0	0
ReqAndReadyImplyGrant_A	128681044	512611	0	0
ReqImpliesValid_A	128681044	512611	0	0
ReqStaysHighUntilGranted0_M	128681044	0	0	0
RoundRobin_A	128681044	0	0	0
ValidKnown_A	128681044	99715364	0	0
gen_data_port_assertion.DataFlow_A	128681044	512611	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	99715364	0	0
T2	87807	86993	0	0
T3	1648	0	0	0
T4	105013	955775	0	0
T5	360	0	0	0
T6	71350	71214	0	0
T9	28388	28388	0	0
T11	799255	756364	0	0
T12	57858	57824	0	0
T13	944704	866554	0	0
T14	450350	304000	0	0
T15	0	399916	0	0
T17	0	99152	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	904	904	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	512611	0	0
T2	87807	4	0	0
T3	1648	0	0	0
T4	105013	3534	0	0
T5	360	0	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	5180	0	0
T12	57858	0	0	0
T13	944704	2796	0	0
T14	450350	2580	0	0
T15	0	6312	0	0
T22	0	916	0	0
T23	0	10	0	0
T24	0	5866	0	0
T26	0	2730	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	512611	0	0
T2	87807	4	0	0
T3	1648	0	0	0
T4	105013	3534	0	0
T5	360	0	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	5180	0	0
T12	57858	0	0	0
T13	944704	2796	0	0
T14	450350	2580	0	0
T15	0	6312	0	0
T22	0	916	0	0
T23	0	10	0	0
T24	0	5866	0	0
T26	0	2730	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	99715364	0	0
T2	87807	86993	0	0
T3	1648	0	0	0
T4	105013	955775	0	0
T5	360	0	0	0
T6	71350	71214	0	0
T9	28388	28388	0	0
T11	799255	756364	0	0
T12	57858	57824	0	0
T13	944704	866554	0	0
T14	450350	304000	0	0
T15	0	399916	0	0
T17	0	99152	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	99715364	0	0
T2	87807	86993	0	0
T3	1648	0	0	0
T4	105013	955775	0	0
T5	360	0	0	0
T6	71350	71214	0	0
T9	28388	28388	0	0
T11	799255	756364	0	0
T12	57858	57824	0	0
T13	944704	866554	0	0
T14	450350	304000	0	0
T15	0	399916	0	0
T17	0	99152	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	512611	0	0
T2	87807	4	0	0
T3	1648	0	0	0
T4	105013	3534	0	0
T5	360	0	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	5180	0	0
T12	57858	0	0	0
T13	944704	2796	0	0
T14	450350	2580	0	0
T15	0	6312	0	0
T22	0	916	0	0
T23	0	10	0	0
T24	0	5866	0	0
T26	0	2730	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	512611	0	0
T2	87807	4	0	0
T3	1648	0	0	0
T4	105013	3534	0	0
T5	360	0	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	5180	0	0
T12	57858	0	0	0
T13	944704	2796	0	0
T14	450350	2580	0	0
T15	0	6312	0	0
T22	0	916	0	0
T23	0	10	0	0
T24	0	5866	0	0
T26	0	2730	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	512611	0	0
T2	87807	4	0	0
T3	1648	0	0	0
T4	105013	3534	0	0
T5	360	0	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	5180	0	0
T12	57858	0	0	0
T13	944704	2796	0	0
T14	450350	2580	0	0
T15	0	6312	0	0
T22	0	916	0	0
T23	0	10	0	0
T24	0	5866	0	0
T26	0	2730	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	512611	0	0
T2	87807	4	0	0
T3	1648	0	0	0
T4	105013	3534	0	0
T5	360	0	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	5180	0	0
T12	57858	0	0	0
T13	944704	2796	0	0
T14	450350	2580	0	0
T15	0	6312	0	0
T22	0	916	0	0
T23	0	10	0	0
T24	0	5866	0	0
T26	0	2730	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	99715364	0	0
T2	87807	86993	0	0
T3	1648	0	0	0
T4	105013	955775	0	0
T5	360	0	0	0
T6	71350	71214	0	0
T9	28388	28388	0	0
T11	799255	756364	0	0
T12	57858	57824	0	0
T13	944704	866554	0	0
T14	450350	304000	0	0
T15	0	399916	0	0
T17	0	99152	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128681044	512611	0	0
T2	87807	4	0	0
T3	1648	0	0	0
T4	105013	3534	0	0
T5	360	0	0	0
T6	71350	0	0	0
T9	28388	0	0	0
T11	799255	5180	0	0
T12	57858	0	0	0
T13	944704	2796	0	0
T14	450350	2580	0	0
T15	0	6312	0	0
T22	0	916	0	0
T23	0	10	0	0
T24	0	5866	0	0
T26	0	2730	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	380134015	380050012	0	0
CheckNGreaterZero_A	904	904	0	0
GntImpliesReady_A	380134015	1984894	0	0
GntImpliesValid_A	380134015	1984894	0	0
GrantKnown_A	380134015	380050012	0	0
IdxKnown_A	380134015	380050012	0	0
IndexIsCorrect_A	380134015	1984894	0	0
LockArbDecision_A	380134015	0	0	0
NoReadyValidNoGrant_A	380134015	0	0	0
ReadyAndValidImplyGrant_A	380134015	1984894	0	0
ReqAndReadyImplyGrant_A	380134015	1984894	0	0
ReqImpliesValid_A	380134015	1984894	0	0
ReqStaysHighUntilGranted0_M	380134015	0	0	0
RoundRobin_A	380134015	4	0	904
ValidKnown_A	380134015	380050012	0	0
gen_data_port_assertion.DataFlow_A	380134015	1984894	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380134015	380050012	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	904	904	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380134015	1984894	0	0
T2	544690	1668	0	0
T3	2323	42	0	0
T4	322640	13536	0	0
T5	2141	0	0	0
T6	79352	832	0	0
T7	1547	0	0	0
T8	2810	832	0	0
T9	60405	832	0	0
T10	1282	0	0	0
T11	480046	10079	0	0
T12	0	832	0	0
T13	0	13041	0	0
T14	0	9938	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380134015	1984894	0	0
T2	544690	1668	0	0
T3	2323	42	0	0
T4	322640	13536	0	0
T5	2141	0	0	0
T6	79352	832	0	0
T7	1547	0	0	0
T8	2810	832	0	0
T9	60405	832	0	0
T10	1282	0	0	0
T11	480046	10079	0	0
T12	0	832	0	0
T13	0	13041	0	0
T14	0	9938	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380134015	380050012	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380134015	380050012	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380134015	1984894	0	0
T2	544690	1668	0	0
T3	2323	42	0	0
T4	322640	13536	0	0
T5	2141	0	0	0
T6	79352	832	0	0
T7	1547	0	0	0
T8	2810	832	0	0
T9	60405	832	0	0
T10	1282	0	0	0
T11	480046	10079	0	0
T12	0	832	0	0
T13	0	13041	0	0
T14	0	9938	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380134015	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380134015	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380134015	1984894	0	0
T2	544690	1668	0	0
T3	2323	42	0	0
T4	322640	13536	0	0
T5	2141	0	0	0
T6	79352	832	0	0
T7	1547	0	0	0
T8	2810	832	0	0
T9	60405	832	0	0
T10	1282	0	0	0
T11	480046	10079	0	0
T12	0	832	0	0
T13	0	13041	0	0
T14	0	9938	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380134015	1984894	0	0
T2	544690	1668	0	0
T3	2323	42	0	0
T4	322640	13536	0	0
T5	2141	0	0	0
T6	79352	832	0	0
T7	1547	0	0	0
T8	2810	832	0	0
T9	60405	832	0	0
T10	1282	0	0	0
T11	480046	10079	0	0
T12	0	832	0	0
T13	0	13041	0	0
T14	0	9938	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380134015	1984894	0	0
T2	544690	1668	0	0
T3	2323	42	0	0
T4	322640	13536	0	0
T5	2141	0	0	0
T6	79352	832	0	0
T7	1547	0	0	0
T8	2810	832	0	0
T9	60405	832	0	0
T10	1282	0	0	0
T11	480046	10079	0	0
T12	0	832	0	0
T13	0	13041	0	0
T14	0	9938	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	380134015	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380134015	4	0	904
T14	223697	1	0	1
T15	300018	0	0	1
T16	478715	0	0	1
T17	104427	0	0	1
T18	19217	0	0	1
T20	0	1	0	0
T22	470964	0	0	1
T32	8925	0	0	1
T35	0	1	0	0
T36	0	1	0	0
T37	211807	0	0	1
T38	86319	0	0	1
T39	20754	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380134015	380050012	0	0
T1	377823	377728	0	0
T2	544690	544617	0	0
T3	2323	2268	0	0
T4	322640	322617	0	0
T5	2141	2051	0	0
T6	79352	79290	0	0
T7	1547	1458	0	0
T8	2810	2714	0	0
T9	60405	60348	0	0
T10	1282	1229	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380134015	1984894	0	0
T2	544690	1668	0	0
T3	2323	42	0	0
T4	322640	13536	0	0
T5	2141	0	0	0
T6	79352	832	0	0
T7	1547	0	0	0
T8	2810	832	0	0
T9	60405	832	0	0
T10	1282	0	0	0
T11	480046	10079	0	0
T12	0	832	0	0
T13	0	13041	0	0
T14	0	9938	0	0