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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.30 94.11 98.61 89.36 97.14 95.84 99.10


Total test records in report: 1079
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T1012 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2921966872 Jun 05 04:33:12 PM PDT 24 Jun 05 04:33:14 PM PDT 24 75677496 ps
T64 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2669838070 Jun 05 04:32:49 PM PDT 24 Jun 05 04:32:51 PM PDT 24 86652353 ps
T111 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.279541351 Jun 05 04:32:56 PM PDT 24 Jun 05 04:33:32 PM PDT 24 9385345636 ps
T1013 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2258710874 Jun 05 04:32:48 PM PDT 24 Jun 05 04:32:50 PM PDT 24 73187661 ps
T1014 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1353600692 Jun 05 04:32:53 PM PDT 24 Jun 05 04:32:57 PM PDT 24 137713638 ps
T1015 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3393492817 Jun 05 04:33:16 PM PDT 24 Jun 05 04:33:18 PM PDT 24 13146329 ps
T1016 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3618431163 Jun 05 04:33:09 PM PDT 24 Jun 05 04:33:12 PM PDT 24 98967208 ps
T1017 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.606194041 Jun 05 04:33:08 PM PDT 24 Jun 05 04:33:10 PM PDT 24 778259287 ps
T112 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1184750169 Jun 05 04:32:58 PM PDT 24 Jun 05 04:33:01 PM PDT 24 400220260 ps
T1018 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.782627015 Jun 05 04:32:49 PM PDT 24 Jun 05 04:32:51 PM PDT 24 46824111 ps
T1019 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3027885654 Jun 05 04:32:53 PM PDT 24 Jun 05 04:32:56 PM PDT 24 137150814 ps
T1020 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4128831405 Jun 05 04:33:16 PM PDT 24 Jun 05 04:33:21 PM PDT 24 339917416 ps
T1021 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.261642442 Jun 05 04:33:25 PM PDT 24 Jun 05 04:33:28 PM PDT 24 320093967 ps
T1022 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2735945273 Jun 05 04:33:06 PM PDT 24 Jun 05 04:33:09 PM PDT 24 76088950 ps
T1023 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.538501573 Jun 05 04:32:59 PM PDT 24 Jun 05 04:33:02 PM PDT 24 110221117 ps
T1024 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3221192117 Jun 05 04:33:13 PM PDT 24 Jun 05 04:33:15 PM PDT 24 39391378 ps
T1025 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1948242663 Jun 05 04:33:28 PM PDT 24 Jun 05 04:33:31 PM PDT 24 26546913 ps
T1026 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.640520841 Jun 05 04:32:56 PM PDT 24 Jun 05 04:32:58 PM PDT 24 40780172 ps
T1027 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3290214017 Jun 05 04:33:11 PM PDT 24 Jun 05 04:33:16 PM PDT 24 242511629 ps
T1028 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.990888185 Jun 05 04:33:05 PM PDT 24 Jun 05 04:33:06 PM PDT 24 27578497 ps
T1029 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.591110843 Jun 05 04:32:58 PM PDT 24 Jun 05 04:33:02 PM PDT 24 1024755790 ps
T234 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3895723936 Jun 05 04:33:09 PM PDT 24 Jun 05 04:33:23 PM PDT 24 405814214 ps
T1030 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1569285511 Jun 05 04:33:08 PM PDT 24 Jun 05 04:33:09 PM PDT 24 50451997 ps
T1031 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2216738177 Jun 05 04:33:16 PM PDT 24 Jun 05 04:33:32 PM PDT 24 650164551 ps
T1032 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.292333126 Jun 05 04:33:13 PM PDT 24 Jun 05 04:33:15 PM PDT 24 43679072 ps
T1033 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.259358504 Jun 05 04:33:12 PM PDT 24 Jun 05 04:33:14 PM PDT 24 23313088 ps
T1034 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1141105324 Jun 05 04:33:00 PM PDT 24 Jun 05 04:33:03 PM PDT 24 213242296 ps
T1035 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2921207265 Jun 05 04:32:53 PM PDT 24 Jun 05 04:32:54 PM PDT 24 13643802 ps
T1036 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.766051255 Jun 05 04:33:16 PM PDT 24 Jun 05 04:33:18 PM PDT 24 39688464 ps
T1037 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2714439815 Jun 05 04:32:58 PM PDT 24 Jun 05 04:33:01 PM PDT 24 155849023 ps
T1038 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3781199077 Jun 05 04:33:07 PM PDT 24 Jun 05 04:33:24 PM PDT 24 1215223500 ps
T1039 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.856174190 Jun 05 04:32:58 PM PDT 24 Jun 05 04:33:01 PM PDT 24 110403239 ps
T1040 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2988674891 Jun 05 04:33:12 PM PDT 24 Jun 05 04:33:14 PM PDT 24 50158500 ps
T1041 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1186288023 Jun 05 04:33:16 PM PDT 24 Jun 05 04:33:32 PM PDT 24 556179292 ps
T230 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2737676853 Jun 05 04:33:02 PM PDT 24 Jun 05 04:33:17 PM PDT 24 1787599689 ps
T1042 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3728208894 Jun 05 04:33:07 PM PDT 24 Jun 05 04:33:12 PM PDT 24 128518606 ps
T1043 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1332812877 Jun 05 04:33:07 PM PDT 24 Jun 05 04:33:09 PM PDT 24 56624022 ps
T1044 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1036895607 Jun 05 04:32:58 PM PDT 24 Jun 05 04:33:02 PM PDT 24 106376361 ps
T227 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1231620354 Jun 05 04:33:05 PM PDT 24 Jun 05 04:33:10 PM PDT 24 1096238118 ps
T1045 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3276982695 Jun 05 04:32:54 PM PDT 24 Jun 05 04:32:55 PM PDT 24 29297861 ps
T1046 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2648697256 Jun 05 04:33:06 PM PDT 24 Jun 05 04:33:08 PM PDT 24 61013297 ps
T1047 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1978898141 Jun 05 04:33:10 PM PDT 24 Jun 05 04:33:12 PM PDT 24 160065071 ps
T1048 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1764619152 Jun 05 04:32:53 PM PDT 24 Jun 05 04:33:20 PM PDT 24 7527992803 ps
T1049 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2291261453 Jun 05 04:33:13 PM PDT 24 Jun 05 04:33:14 PM PDT 24 22498783 ps
T1050 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2688776764 Jun 05 04:33:04 PM PDT 24 Jun 05 04:33:06 PM PDT 24 136533544 ps
T231 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3339648096 Jun 05 04:32:53 PM PDT 24 Jun 05 04:33:14 PM PDT 24 2606942108 ps
T1051 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1935452886 Jun 05 04:32:53 PM PDT 24 Jun 05 04:33:09 PM PDT 24 227618998 ps
T1052 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2291478925 Jun 05 04:32:56 PM PDT 24 Jun 05 04:33:01 PM PDT 24 211729593 ps
T1053 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1520279345 Jun 05 04:33:09 PM PDT 24 Jun 05 04:33:23 PM PDT 24 875868867 ps
T1054 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1155285905 Jun 05 04:33:13 PM PDT 24 Jun 05 04:33:15 PM PDT 24 45689044 ps
T1055 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2642359267 Jun 05 04:33:06 PM PDT 24 Jun 05 04:33:09 PM PDT 24 269405942 ps
T1056 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2444117987 Jun 05 04:32:49 PM PDT 24 Jun 05 04:32:50 PM PDT 24 9879517 ps
T1057 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2401345345 Jun 05 04:33:04 PM PDT 24 Jun 05 04:33:06 PM PDT 24 109813676 ps
T229 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4282662465 Jun 05 04:32:53 PM PDT 24 Jun 05 04:33:01 PM PDT 24 113761985 ps
T1058 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.114450148 Jun 05 04:33:05 PM PDT 24 Jun 05 04:33:06 PM PDT 24 45439009 ps
T1059 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2111834614 Jun 05 04:33:15 PM PDT 24 Jun 05 04:33:19 PM PDT 24 41899177 ps
T1060 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1083382439 Jun 05 04:33:11 PM PDT 24 Jun 05 04:33:15 PM PDT 24 111281744 ps
T1061 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.40980066 Jun 05 04:33:12 PM PDT 24 Jun 05 04:33:14 PM PDT 24 32937773 ps
T1062 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2055977360 Jun 05 04:32:59 PM PDT 24 Jun 05 04:33:00 PM PDT 24 57521519 ps
T1063 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2879670881 Jun 05 04:33:27 PM PDT 24 Jun 05 04:33:29 PM PDT 24 20838428 ps
T233 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4000006128 Jun 05 04:33:08 PM PDT 24 Jun 05 04:33:16 PM PDT 24 460587894 ps
T1064 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2438736896 Jun 05 04:33:19 PM PDT 24 Jun 05 04:33:20 PM PDT 24 71566167 ps
T1065 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1646580012 Jun 05 04:33:00 PM PDT 24 Jun 05 04:33:04 PM PDT 24 145468789 ps
T1066 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3444653329 Jun 05 04:33:00 PM PDT 24 Jun 05 04:33:18 PM PDT 24 608254484 ps
T1067 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3965263658 Jun 05 04:33:45 PM PDT 24 Jun 05 04:33:48 PM PDT 24 17968675 ps
T228 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2695778748 Jun 05 04:33:01 PM PDT 24 Jun 05 04:33:06 PM PDT 24 228851550 ps
T1068 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1143531416 Jun 05 04:32:52 PM PDT 24 Jun 05 04:32:54 PM PDT 24 74177806 ps
T1069 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2630332791 Jun 05 04:33:00 PM PDT 24 Jun 05 04:33:03 PM PDT 24 136135543 ps
T1070 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1713717055 Jun 05 04:33:07 PM PDT 24 Jun 05 04:33:10 PM PDT 24 54836868 ps
T1071 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3291678833 Jun 05 04:32:51 PM PDT 24 Jun 05 04:32:56 PM PDT 24 261923349 ps
T1072 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.143832288 Jun 05 04:32:56 PM PDT 24 Jun 05 04:32:59 PM PDT 24 90414091 ps
T1073 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2497614790 Jun 05 04:32:56 PM PDT 24 Jun 05 04:32:58 PM PDT 24 78551288 ps
T1074 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3608416287 Jun 05 04:32:49 PM PDT 24 Jun 05 04:32:51 PM PDT 24 78533160 ps
T235 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1491062077 Jun 05 04:33:04 PM PDT 24 Jun 05 04:33:23 PM PDT 24 285854657 ps
T1075 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1059751328 Jun 05 04:33:00 PM PDT 24 Jun 05 04:33:09 PM PDT 24 2050660915 ps
T1076 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4020560871 Jun 05 04:33:57 PM PDT 24 Jun 05 04:34:00 PM PDT 24 40234854 ps
T1077 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.556007419 Jun 05 04:32:54 PM PDT 24 Jun 05 04:33:02 PM PDT 24 212948945 ps
T1078 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3466320434 Jun 05 04:32:57 PM PDT 24 Jun 05 04:32:58 PM PDT 24 32250955 ps
T1079 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2477381389 Jun 05 04:33:16 PM PDT 24 Jun 05 04:33:19 PM PDT 24 103677384 ps

Test location /workspace/coverage/default/34.spi_device_stress_all.429153539
Short name T4
Test name
Test status
Simulation time 33609454451 ps
CPU time 371.17 seconds
Started Jun 05 05:38:06 PM PDT 24
Finished Jun 05 05:44:18 PM PDT 24
Peak memory 255852 kb
Host smart-ad464e40-e758-4dbf-ab50-b9ead068fd5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429153539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.429153539
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2450874732
Short name T23
Test name
Test status
Simulation time 152826917704 ps
CPU time 156.13 seconds
Started Jun 05 05:37:20 PM PDT 24
Finished Jun 05 05:39:57 PM PDT 24
Peak memory 265452 kb
Host smart-8fe81897-9f26-4c46-a0a1-39f47c3854b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450874732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2450874732
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1826176716
Short name T143
Test name
Test status
Simulation time 78163291165 ps
CPU time 199.85 seconds
Started Jun 05 05:39:09 PM PDT 24
Finished Jun 05 05:42:29 PM PDT 24
Peak memory 257504 kb
Host smart-d91c1e2a-b2e7-4ee9-92b8-c6267e560969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826176716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1826176716
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1702199744
Short name T80
Test name
Test status
Simulation time 3526697668 ps
CPU time 21.11 seconds
Started Jun 05 04:33:17 PM PDT 24
Finished Jun 05 04:33:39 PM PDT 24
Peak memory 216800 kb
Host smart-8b42d3ba-3acf-41d0-8473-7f6222435064
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702199744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1702199744
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.517711104
Short name T122
Test name
Test status
Simulation time 63532576459 ps
CPU time 297.49 seconds
Started Jun 05 05:39:02 PM PDT 24
Finished Jun 05 05:44:00 PM PDT 24
Peak memory 273384 kb
Host smart-fcd578b5-e6da-42c6-b57d-87196ae5a7a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517711104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.517711104
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.353335539
Short name T47
Test name
Test status
Simulation time 43818332 ps
CPU time 0.75 seconds
Started Jun 05 05:34:30 PM PDT 24
Finished Jun 05 05:34:31 PM PDT 24
Peak memory 216280 kb
Host smart-92325c05-3a98-410e-bfc4-bac22b414edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353335539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.353335539
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.4250147478
Short name T15
Test name
Test status
Simulation time 31252903333 ps
CPU time 306.4 seconds
Started Jun 05 05:38:10 PM PDT 24
Finished Jun 05 05:43:17 PM PDT 24
Peak memory 257576 kb
Host smart-9cef1e90-23c8-41ba-ab41-d2fdd04b68ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250147478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.4250147478
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3636550261
Short name T13
Test name
Test status
Simulation time 38835141799 ps
CPU time 419.93 seconds
Started Jun 05 05:35:43 PM PDT 24
Finished Jun 05 05:42:44 PM PDT 24
Peak memory 253120 kb
Host smart-aaa07f96-19dc-43a8-840d-17a66372902a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636550261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3636550261
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.994913200
Short name T152
Test name
Test status
Simulation time 693442438106 ps
CPU time 908.49 seconds
Started Jun 05 05:35:05 PM PDT 24
Finished Jun 05 05:50:14 PM PDT 24
Peak memory 290068 kb
Host smart-7960e8bd-f58c-482e-b5ed-dcfea8ab3461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994913200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.994913200
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2848508015
Short name T155
Test name
Test status
Simulation time 120432227675 ps
CPU time 427.09 seconds
Started Jun 05 05:36:35 PM PDT 24
Finished Jun 05 05:43:43 PM PDT 24
Peak memory 273896 kb
Host smart-51077564-754d-4394-8013-5c4b52c2ac79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848508015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2848508015
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3651371237
Short name T79
Test name
Test status
Simulation time 438638213 ps
CPU time 5.34 seconds
Started Jun 05 04:33:07 PM PDT 24
Finished Jun 05 04:33:13 PM PDT 24
Peak memory 215152 kb
Host smart-58ebfebb-2359-43fb-8c30-9fb72ef3e597
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651371237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3651371237
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3112474037
Short name T20
Test name
Test status
Simulation time 30071587813 ps
CPU time 134 seconds
Started Jun 05 05:37:47 PM PDT 24
Finished Jun 05 05:40:01 PM PDT 24
Peak memory 289832 kb
Host smart-6c842d8e-5104-4546-823b-33d2a1420c6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112474037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3112474037
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.890385514
Short name T33
Test name
Test status
Simulation time 2661765735 ps
CPU time 10.81 seconds
Started Jun 05 05:36:21 PM PDT 24
Finished Jun 05 05:36:32 PM PDT 24
Peak memory 224708 kb
Host smart-ca94c88e-1676-4a01-924c-fb174d448ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890385514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.890385514
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.269055983
Short name T344
Test name
Test status
Simulation time 43322753 ps
CPU time 0.72 seconds
Started Jun 05 05:34:47 PM PDT 24
Finished Jun 05 05:34:49 PM PDT 24
Peak memory 205536 kb
Host smart-146de685-926c-4774-af39-d5aee3d61adf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269055983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.269055983
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3041661705
Short name T24
Test name
Test status
Simulation time 23104303418 ps
CPU time 253.54 seconds
Started Jun 05 05:38:45 PM PDT 24
Finished Jun 05 05:42:59 PM PDT 24
Peak memory 256336 kb
Host smart-0e75a276-19cb-481a-8d35-1d201567b686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041661705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3041661705
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.671266131
Short name T101
Test name
Test status
Simulation time 205946774 ps
CPU time 15.23 seconds
Started Jun 05 04:32:53 PM PDT 24
Finished Jun 05 04:33:09 PM PDT 24
Peak memory 215020 kb
Host smart-dd4b4b06-534b-4765-8b3a-3f0964b41dd6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671266131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.671266131
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1687504843
Short name T28
Test name
Test status
Simulation time 25127203965 ps
CPU time 320.25 seconds
Started Jun 05 05:35:29 PM PDT 24
Finished Jun 05 05:40:49 PM PDT 24
Peak memory 265964 kb
Host smart-9bafe0a2-b81b-4ca6-b606-c7bc4d7f0b1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687504843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1687504843
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.478295073
Short name T177
Test name
Test status
Simulation time 131441804718 ps
CPU time 621.21 seconds
Started Jun 05 05:35:43 PM PDT 24
Finished Jun 05 05:46:05 PM PDT 24
Peak memory 281888 kb
Host smart-eb37a04d-1dcc-4eca-a8df-abe832bcbf4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478295073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.478295073
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1769697686
Short name T48
Test name
Test status
Simulation time 139816796 ps
CPU time 1.1 seconds
Started Jun 05 05:34:44 PM PDT 24
Finished Jun 05 05:34:45 PM PDT 24
Peak memory 235240 kb
Host smart-8e6b9e62-b8ba-4759-8622-d8876d3d854f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769697686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1769697686
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1603916232
Short name T193
Test name
Test status
Simulation time 74555235642 ps
CPU time 819.09 seconds
Started Jun 05 05:36:23 PM PDT 24
Finished Jun 05 05:50:03 PM PDT 24
Peak memory 281308 kb
Host smart-9d5f648f-57ba-436a-9aed-998490bdcd9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603916232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1603916232
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2745732210
Short name T27
Test name
Test status
Simulation time 3778223091 ps
CPU time 81.48 seconds
Started Jun 05 05:37:28 PM PDT 24
Finished Jun 05 05:38:50 PM PDT 24
Peak memory 256308 kb
Host smart-ec9380a9-d529-422e-9c60-22bcf93f2da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745732210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2745732210
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1284193673
Short name T191
Test name
Test status
Simulation time 77021659506 ps
CPU time 451.96 seconds
Started Jun 05 05:36:04 PM PDT 24
Finished Jun 05 05:43:37 PM PDT 24
Peak memory 282072 kb
Host smart-48c7b56d-d889-4156-8c3b-4671734aef0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284193673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1284193673
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.40366109
Short name T171
Test name
Test status
Simulation time 175458486540 ps
CPU time 388 seconds
Started Jun 05 05:35:52 PM PDT 24
Finished Jun 05 05:42:21 PM PDT 24
Peak memory 255820 kb
Host smart-a0b162c7-8218-465a-bf32-9e834b1deb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40366109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.40366109
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3939559648
Short name T251
Test name
Test status
Simulation time 16872022834 ps
CPU time 169.75 seconds
Started Jun 05 05:36:54 PM PDT 24
Finished Jun 05 05:39:44 PM PDT 24
Peak memory 249364 kb
Host smart-6c0d650f-1d7e-442b-9570-8ced1a2715a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939559648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3939559648
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2354460318
Short name T197
Test name
Test status
Simulation time 36909546750 ps
CPU time 469.62 seconds
Started Jun 05 05:38:08 PM PDT 24
Finished Jun 05 05:45:58 PM PDT 24
Peak memory 268868 kb
Host smart-0b43cc91-b6af-4516-950e-c8f1970bd2fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354460318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2354460318
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2047389125
Short name T90
Test name
Test status
Simulation time 1885127240 ps
CPU time 5.25 seconds
Started Jun 05 04:33:03 PM PDT 24
Finished Jun 05 04:33:09 PM PDT 24
Peak memory 215244 kb
Host smart-be8c0ce2-b71a-4957-8f0e-1f421f6ddc5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047389125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
047389125
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.986622004
Short name T17
Test name
Test status
Simulation time 1076559556 ps
CPU time 14.73 seconds
Started Jun 05 05:38:07 PM PDT 24
Finished Jun 05 05:38:23 PM PDT 24
Peak memory 232848 kb
Host smart-ae3484ca-f5aa-4e67-8305-868aa64b3d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986622004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.986622004
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3308781830
Short name T96
Test name
Test status
Simulation time 1495811367 ps
CPU time 19.78 seconds
Started Jun 05 04:33:12 PM PDT 24
Finished Jun 05 04:33:32 PM PDT 24
Peak memory 223308 kb
Host smart-a8652eae-df37-4774-a197-478e7b4a6915
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308781830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3308781830
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.42103109
Short name T320
Test name
Test status
Simulation time 1451306026 ps
CPU time 3.65 seconds
Started Jun 05 05:34:31 PM PDT 24
Finished Jun 05 05:34:35 PM PDT 24
Peak memory 216396 kb
Host smart-df21b7c5-2ee5-4fce-838c-33deb4fbad4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42103109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.42103109
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2125761240
Short name T169
Test name
Test status
Simulation time 2758544875 ps
CPU time 50.67 seconds
Started Jun 05 05:37:23 PM PDT 24
Finished Jun 05 05:38:15 PM PDT 24
Peak memory 241156 kb
Host smart-1b54bd8c-fed9-489c-83c6-7d64ab19d53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125761240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2125761240
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2772011702
Short name T195
Test name
Test status
Simulation time 10437464715 ps
CPU time 58.77 seconds
Started Jun 05 05:35:20 PM PDT 24
Finished Jun 05 05:36:19 PM PDT 24
Peak memory 256316 kb
Host smart-a72745ef-8ac5-42c3-a7a8-9f6e9624d967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772011702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2772011702
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3013813255
Short name T199
Test name
Test status
Simulation time 14419664202 ps
CPU time 228.64 seconds
Started Jun 05 05:38:48 PM PDT 24
Finished Jun 05 05:42:37 PM PDT 24
Peak memory 265704 kb
Host smart-354d71fd-a42b-4946-aee9-7580602b045f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013813255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3013813255
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1491062077
Short name T235
Test name
Test status
Simulation time 285854657 ps
CPU time 18.47 seconds
Started Jun 05 04:33:04 PM PDT 24
Finished Jun 05 04:33:23 PM PDT 24
Peak memory 222632 kb
Host smart-c5ed5aff-4967-4053-8c7b-86f9f452ba27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491062077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1491062077
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.373197471
Short name T121
Test name
Test status
Simulation time 1131032753 ps
CPU time 22.4 seconds
Started Jun 05 05:36:56 PM PDT 24
Finished Jun 05 05:37:19 PM PDT 24
Peak memory 232832 kb
Host smart-51629d33-7a72-4d15-89a9-30090ea0c72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373197471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.373197471
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.329152079
Short name T487
Test name
Test status
Simulation time 6078614646 ps
CPU time 77.16 seconds
Started Jun 05 05:37:02 PM PDT 24
Finished Jun 05 05:38:20 PM PDT 24
Peak memory 253312 kb
Host smart-9e5ff469-ff23-4bd0-aa23-574544a3138b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329152079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.329152079
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2404749307
Short name T273
Test name
Test status
Simulation time 1337119527 ps
CPU time 23.06 seconds
Started Jun 05 05:35:36 PM PDT 24
Finished Jun 05 05:36:00 PM PDT 24
Peak memory 224792 kb
Host smart-fe19cee5-25f0-4f0d-8e55-eeaa50041566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404749307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2404749307
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3756876493
Short name T744
Test name
Test status
Simulation time 199870213 ps
CPU time 4.27 seconds
Started Jun 05 05:35:58 PM PDT 24
Finished Jun 05 05:36:03 PM PDT 24
Peak memory 224660 kb
Host smart-700eee40-d3e8-487c-8e6f-32359de30c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756876493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3756876493
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4282662465
Short name T229
Test name
Test status
Simulation time 113761985 ps
CPU time 6.98 seconds
Started Jun 05 04:32:53 PM PDT 24
Finished Jun 05 04:33:01 PM PDT 24
Peak memory 215248 kb
Host smart-a0a1bd49-8f97-4332-a9fa-dde592649836
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282662465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4282662465
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3895723936
Short name T234
Test name
Test status
Simulation time 405814214 ps
CPU time 13.01 seconds
Started Jun 05 04:33:09 PM PDT 24
Finished Jun 05 04:33:23 PM PDT 24
Peak memory 215164 kb
Host smart-13834bff-fa17-44cc-bd0a-4790b8d3e49b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895723936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3895723936
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2434048225
Short name T190
Test name
Test status
Simulation time 11182638531 ps
CPU time 171.14 seconds
Started Jun 05 05:34:45 PM PDT 24
Finished Jun 05 05:37:36 PM PDT 24
Peak memory 263724 kb
Host smart-46974685-80e2-410e-8c1b-7be1764a7558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434048225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2434048225
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.735114115
Short name T756
Test name
Test status
Simulation time 775907416 ps
CPU time 16.78 seconds
Started Jun 05 05:37:01 PM PDT 24
Finished Jun 05 05:37:19 PM PDT 24
Peak memory 250812 kb
Host smart-729a4f3e-5cff-4d18-b1d2-30e759e23a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735114115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.735114115
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3140680122
Short name T259
Test name
Test status
Simulation time 12729029664 ps
CPU time 32.74 seconds
Started Jun 05 05:37:28 PM PDT 24
Finished Jun 05 05:38:02 PM PDT 24
Peak memory 239576 kb
Host smart-e8c09020-07bb-44a5-8ce0-1f0a6aa55e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140680122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3140680122
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3573464343
Short name T207
Test name
Test status
Simulation time 28709405443 ps
CPU time 307.42 seconds
Started Jun 05 05:37:38 PM PDT 24
Finished Jun 05 05:42:46 PM PDT 24
Peak memory 254808 kb
Host smart-78c9c16b-227e-40da-bdab-ff27b0485e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573464343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3573464343
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2962886696
Short name T217
Test name
Test status
Simulation time 53407143335 ps
CPU time 492.23 seconds
Started Jun 05 05:38:54 PM PDT 24
Finished Jun 05 05:47:07 PM PDT 24
Peak memory 272232 kb
Host smart-2c585c23-3baa-48b4-b249-b8f5a7a6fb1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962886696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2962886696
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.890219850
Short name T160
Test name
Test status
Simulation time 14952687819 ps
CPU time 21.2 seconds
Started Jun 05 05:34:32 PM PDT 24
Finished Jun 05 05:34:54 PM PDT 24
Peak memory 232916 kb
Host smart-d35c61be-0eba-41fe-ba62-54451fe95aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890219850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.890219850
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2233021906
Short name T63
Test name
Test status
Simulation time 36762539 ps
CPU time 1.16 seconds
Started Jun 05 04:32:48 PM PDT 24
Finished Jun 05 04:32:50 PM PDT 24
Peak memory 206608 kb
Host smart-761ef1ae-8e70-4358-b64e-b298ce29ec2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233021906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2233021906
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2714439815
Short name T1037
Test name
Test status
Simulation time 155849023 ps
CPU time 2.55 seconds
Started Jun 05 04:32:58 PM PDT 24
Finished Jun 05 04:33:01 PM PDT 24
Peak memory 215192 kb
Host smart-cc457890-38b8-4e23-8bc9-5580408b2fb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714439815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
714439815
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3444653329
Short name T1066
Test name
Test status
Simulation time 608254484 ps
CPU time 16.84 seconds
Started Jun 05 04:33:00 PM PDT 24
Finished Jun 05 04:33:18 PM PDT 24
Peak memory 206836 kb
Host smart-9086178e-25fb-4ad5-9e1b-e38b3a624a8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444653329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3444653329
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1764619152
Short name T1048
Test name
Test status
Simulation time 7527992803 ps
CPU time 26.89 seconds
Started Jun 05 04:32:53 PM PDT 24
Finished Jun 05 04:33:20 PM PDT 24
Peak memory 206876 kb
Host smart-6914d62a-c141-4e1d-b053-9889573b402c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764619152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1764619152
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.143832288
Short name T1072
Test name
Test status
Simulation time 90414091 ps
CPU time 2.65 seconds
Started Jun 05 04:32:56 PM PDT 24
Finished Jun 05 04:32:59 PM PDT 24
Peak memory 217348 kb
Host smart-9e663753-91a6-42eb-970c-5812d2e03eca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143832288 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.143832288
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.755984675
Short name T140
Test name
Test status
Simulation time 181790851 ps
CPU time 2.03 seconds
Started Jun 05 04:33:24 PM PDT 24
Finished Jun 05 04:33:27 PM PDT 24
Peak memory 206812 kb
Host smart-60a2639d-96b4-459f-bdac-bcedfe26def9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755984675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.755984675
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3608416287
Short name T1074
Test name
Test status
Simulation time 78533160 ps
CPU time 0.71 seconds
Started Jun 05 04:32:49 PM PDT 24
Finished Jun 05 04:32:51 PM PDT 24
Peak memory 203920 kb
Host smart-85d297fe-e0bb-4310-9b56-253af03c5222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608416287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
608416287
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2889368623
Short name T108
Test name
Test status
Simulation time 39334303 ps
CPU time 1.35 seconds
Started Jun 05 04:32:52 PM PDT 24
Finished Jun 05 04:32:54 PM PDT 24
Peak memory 215148 kb
Host smart-8250795a-f591-493f-8730-ea7221050ecd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889368623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2889368623
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2444117987
Short name T1056
Test name
Test status
Simulation time 9879517 ps
CPU time 0.72 seconds
Started Jun 05 04:32:49 PM PDT 24
Finished Jun 05 04:32:50 PM PDT 24
Peak memory 203808 kb
Host smart-af3c8a31-3b80-4cc8-8084-7dd873534a80
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444117987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2444117987
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1433453603
Short name T975
Test name
Test status
Simulation time 602635190 ps
CPU time 3.04 seconds
Started Jun 05 04:32:50 PM PDT 24
Finished Jun 05 04:32:54 PM PDT 24
Peak memory 215144 kb
Host smart-fd8b4aea-bf00-4285-9cb6-51e51ba3e250
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433453603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1433453603
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3291678833
Short name T1071
Test name
Test status
Simulation time 261923349 ps
CPU time 4.9 seconds
Started Jun 05 04:32:51 PM PDT 24
Finished Jun 05 04:32:56 PM PDT 24
Peak memory 215204 kb
Host smart-c513307f-d1e6-4e93-a775-dce862879ff5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291678833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
291678833
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3639501582
Short name T957
Test name
Test status
Simulation time 380352300 ps
CPU time 11.33 seconds
Started Jun 05 04:32:53 PM PDT 24
Finished Jun 05 04:33:05 PM PDT 24
Peak memory 206876 kb
Host smart-7961f098-dafd-4bf3-b95c-5ae1b7be5388
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639501582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3639501582
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2497614790
Short name T1073
Test name
Test status
Simulation time 78551288 ps
CPU time 1.35 seconds
Started Jun 05 04:32:56 PM PDT 24
Finished Jun 05 04:32:58 PM PDT 24
Peak memory 206804 kb
Host smart-aeb64661-15f2-4247-8740-9aea9fd43978
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497614790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2497614790
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2606909250
Short name T988
Test name
Test status
Simulation time 25075619 ps
CPU time 1.68 seconds
Started Jun 05 04:32:51 PM PDT 24
Finished Jun 05 04:32:53 PM PDT 24
Peak memory 215228 kb
Host smart-854ed90d-4d47-4c8e-9069-3ebb84b22f6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606909250 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2606909250
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2258710874
Short name T1013
Test name
Test status
Simulation time 73187661 ps
CPU time 1.35 seconds
Started Jun 05 04:32:48 PM PDT 24
Finished Jun 05 04:32:50 PM PDT 24
Peak memory 206768 kb
Host smart-cd204c55-addb-4459-92b9-4d173059f1c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258710874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
258710874
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1589266261
Short name T959
Test name
Test status
Simulation time 11361600 ps
CPU time 0.74 seconds
Started Jun 05 04:32:58 PM PDT 24
Finished Jun 05 04:32:59 PM PDT 24
Peak memory 203492 kb
Host smart-067c7dc4-f1ad-4947-bc6e-7b6195a789f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589266261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
589266261
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1332812877
Short name T1043
Test name
Test status
Simulation time 56624022 ps
CPU time 1.31 seconds
Started Jun 05 04:33:07 PM PDT 24
Finished Jun 05 04:33:09 PM PDT 24
Peak memory 215124 kb
Host smart-87faad21-8c11-459b-aae7-41413374e7e9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332812877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1332812877
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3276982695
Short name T1045
Test name
Test status
Simulation time 29297861 ps
CPU time 0.68 seconds
Started Jun 05 04:32:54 PM PDT 24
Finished Jun 05 04:32:55 PM PDT 24
Peak memory 203832 kb
Host smart-6550df47-3fa6-424a-8f04-8e0151201812
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276982695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3276982695
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3027885654
Short name T1019
Test name
Test status
Simulation time 137150814 ps
CPU time 1.85 seconds
Started Jun 05 04:32:53 PM PDT 24
Finished Jun 05 04:32:56 PM PDT 24
Peak memory 215148 kb
Host smart-aa9e1be7-8ae2-4975-ba62-06091bbbd428
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027885654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3027885654
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.556007419
Short name T1077
Test name
Test status
Simulation time 212948945 ps
CPU time 6.73 seconds
Started Jun 05 04:32:54 PM PDT 24
Finished Jun 05 04:33:02 PM PDT 24
Peak memory 215032 kb
Host smart-36a45c14-c6c5-4446-b265-68bebdd2e36b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556007419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.556007419
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2853799835
Short name T985
Test name
Test status
Simulation time 87514260 ps
CPU time 2.95 seconds
Started Jun 05 04:33:04 PM PDT 24
Finished Jun 05 04:33:08 PM PDT 24
Peak memory 216704 kb
Host smart-2654fbf2-13c8-445b-ac06-e2f335377517
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853799835 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2853799835
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1184750169
Short name T112
Test name
Test status
Simulation time 400220260 ps
CPU time 2.08 seconds
Started Jun 05 04:32:58 PM PDT 24
Finished Jun 05 04:33:01 PM PDT 24
Peak memory 206820 kb
Host smart-91098df1-ef25-4d5b-816c-e9e9590e4aac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184750169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1184750169
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1978898141
Short name T1047
Test name
Test status
Simulation time 160065071 ps
CPU time 0.8 seconds
Started Jun 05 04:33:10 PM PDT 24
Finished Jun 05 04:33:12 PM PDT 24
Peak memory 203608 kb
Host smart-5243a8a1-4276-4130-894b-ed63483362ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978898141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1978898141
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2642359267
Short name T1055
Test name
Test status
Simulation time 269405942 ps
CPU time 1.87 seconds
Started Jun 05 04:33:06 PM PDT 24
Finished Jun 05 04:33:09 PM PDT 24
Peak memory 215112 kb
Host smart-7229943e-2b73-41cb-a723-85e322d0fc21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642359267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2642359267
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4279773255
Short name T86
Test name
Test status
Simulation time 210605047 ps
CPU time 5.34 seconds
Started Jun 05 04:33:01 PM PDT 24
Finished Jun 05 04:33:07 PM PDT 24
Peak memory 215240 kb
Host smart-c18b0c3e-1f6a-4f1a-a223-44dcfe36ca0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279773255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4279773255
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2291478925
Short name T1052
Test name
Test status
Simulation time 211729593 ps
CPU time 3.77 seconds
Started Jun 05 04:32:56 PM PDT 24
Finished Jun 05 04:33:01 PM PDT 24
Peak memory 217100 kb
Host smart-4d72d2c8-a9e5-4147-8481-9c2e0eab73e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291478925 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2291478925
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3855551877
Short name T107
Test name
Test status
Simulation time 76037593 ps
CPU time 2.04 seconds
Started Jun 05 04:32:55 PM PDT 24
Finished Jun 05 04:32:57 PM PDT 24
Peak memory 215024 kb
Host smart-87b940ea-1c5e-49d2-9f87-179d8ebf2fb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855551877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3855551877
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1916806129
Short name T969
Test name
Test status
Simulation time 12581266 ps
CPU time 0.73 seconds
Started Jun 05 04:33:13 PM PDT 24
Finished Jun 05 04:33:15 PM PDT 24
Peak memory 203552 kb
Host smart-6cd07338-9cda-4ce4-ba1f-89c268ecc9ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916806129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1916806129
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1036895607
Short name T1044
Test name
Test status
Simulation time 106376361 ps
CPU time 3.2 seconds
Started Jun 05 04:32:58 PM PDT 24
Finished Jun 05 04:33:02 PM PDT 24
Peak memory 215076 kb
Host smart-9ad90682-de93-4f02-b2a4-4d15bb8013b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036895607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1036895607
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2695778748
Short name T228
Test name
Test status
Simulation time 228851550 ps
CPU time 4.12 seconds
Started Jun 05 04:33:01 PM PDT 24
Finished Jun 05 04:33:06 PM PDT 24
Peak memory 215288 kb
Host smart-465fffc6-2efc-4570-bc4a-42cc921f76f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695778748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2695778748
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1520279345
Short name T1053
Test name
Test status
Simulation time 875868867 ps
CPU time 12.34 seconds
Started Jun 05 04:33:09 PM PDT 24
Finished Jun 05 04:33:23 PM PDT 24
Peak memory 215092 kb
Host smart-0b2237a2-d5e3-49a9-a9eb-2dbd90d125d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520279345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1520279345
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.606194041
Short name T1017
Test name
Test status
Simulation time 778259287 ps
CPU time 1.93 seconds
Started Jun 05 04:33:08 PM PDT 24
Finished Jun 05 04:33:10 PM PDT 24
Peak memory 216188 kb
Host smart-d5a25ae1-a0cd-46fd-9455-dccbe2fd5894
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606194041 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.606194041
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4225533528
Short name T105
Test name
Test status
Simulation time 361617702 ps
CPU time 2.84 seconds
Started Jun 05 04:33:02 PM PDT 24
Finished Jun 05 04:33:06 PM PDT 24
Peak memory 215028 kb
Host smart-6a1a57a9-e63a-448e-bb98-149bef9003b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225533528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4225533528
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3640829245
Short name T984
Test name
Test status
Simulation time 22221305 ps
CPU time 0.74 seconds
Started Jun 05 04:33:05 PM PDT 24
Finished Jun 05 04:33:07 PM PDT 24
Peak memory 203616 kb
Host smart-fd47102a-b340-428a-9a9d-78e565efe2d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640829245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3640829245
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.98278354
Short name T1005
Test name
Test status
Simulation time 147783909 ps
CPU time 3.46 seconds
Started Jun 05 04:33:01 PM PDT 24
Finished Jun 05 04:33:05 PM PDT 24
Peak memory 215068 kb
Host smart-80dd2d71-6125-43f7-8930-01fae8a3a206
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98278354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sp
i_device_same_csr_outstanding.98278354
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1353600692
Short name T1014
Test name
Test status
Simulation time 137713638 ps
CPU time 3.16 seconds
Started Jun 05 04:32:53 PM PDT 24
Finished Jun 05 04:32:57 PM PDT 24
Peak memory 215264 kb
Host smart-44dc4bd2-cd9d-4c7f-81cd-d5889d17e3ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353600692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1353600692
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3664355919
Short name T983
Test name
Test status
Simulation time 54489543 ps
CPU time 3.61 seconds
Started Jun 05 04:33:09 PM PDT 24
Finished Jun 05 04:33:14 PM PDT 24
Peak memory 217380 kb
Host smart-b5d3eb78-e80f-4b07-8b21-296399f24d27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664355919 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3664355919
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1758748610
Short name T110
Test name
Test status
Simulation time 121431761 ps
CPU time 2.24 seconds
Started Jun 05 04:33:01 PM PDT 24
Finished Jun 05 04:33:04 PM PDT 24
Peak memory 215080 kb
Host smart-d37346dc-af16-4963-b1a1-a28d357909c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758748610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1758748610
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2055977360
Short name T1062
Test name
Test status
Simulation time 57521519 ps
CPU time 0.77 seconds
Started Jun 05 04:32:59 PM PDT 24
Finished Jun 05 04:33:00 PM PDT 24
Peak memory 203536 kb
Host smart-83d9b6d1-1aef-4010-ac82-9b7d1eaac276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055977360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2055977360
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4128831405
Short name T1020
Test name
Test status
Simulation time 339917416 ps
CPU time 4.03 seconds
Started Jun 05 04:33:16 PM PDT 24
Finished Jun 05 04:33:21 PM PDT 24
Peak memory 215028 kb
Host smart-04416f17-1ce3-4763-b712-8f4bcdcc4366
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128831405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.4128831405
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3518953885
Short name T93
Test name
Test status
Simulation time 1772997681 ps
CPU time 5.2 seconds
Started Jun 05 04:33:15 PM PDT 24
Finished Jun 05 04:33:21 PM PDT 24
Peak memory 215340 kb
Host smart-6141f9d3-85d4-4e30-bb65-c5c613ee9f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518953885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3518953885
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3618431163
Short name T1016
Test name
Test status
Simulation time 98967208 ps
CPU time 1.92 seconds
Started Jun 05 04:33:09 PM PDT 24
Finished Jun 05 04:33:12 PM PDT 24
Peak memory 216220 kb
Host smart-97fcb434-9158-49d8-b687-77d0728df372
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618431163 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3618431163
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2688776764
Short name T1050
Test name
Test status
Simulation time 136533544 ps
CPU time 2.3 seconds
Started Jun 05 04:33:04 PM PDT 24
Finished Jun 05 04:33:06 PM PDT 24
Peak memory 206804 kb
Host smart-f735e612-f880-41f7-a7e9-702ce00f7de0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688776764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2688776764
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3819533160
Short name T970
Test name
Test status
Simulation time 21830384 ps
CPU time 0.74 seconds
Started Jun 05 04:33:03 PM PDT 24
Finished Jun 05 04:33:04 PM PDT 24
Peak memory 203604 kb
Host smart-4a3b5193-086a-4f5f-a6d7-bec9beef9de2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819533160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3819533160
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.931250810
Short name T962
Test name
Test status
Simulation time 119581824 ps
CPU time 1.74 seconds
Started Jun 05 04:33:09 PM PDT 24
Finished Jun 05 04:33:12 PM PDT 24
Peak memory 215304 kb
Host smart-5e73d05d-d977-46c4-bf9d-2b89f40bfb68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931250810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.931250810
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2923275913
Short name T1006
Test name
Test status
Simulation time 265534998 ps
CPU time 4.2 seconds
Started Jun 05 04:33:14 PM PDT 24
Finished Jun 05 04:33:19 PM PDT 24
Peak memory 215276 kb
Host smart-cbdeb6e8-b230-4460-a384-3bbbdce236ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923275913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2923275913
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.932246035
Short name T45
Test name
Test status
Simulation time 5434536059 ps
CPU time 14.12 seconds
Started Jun 05 04:33:06 PM PDT 24
Finished Jun 05 04:33:21 PM PDT 24
Peak memory 215940 kb
Host smart-e3c0a40f-afd3-4dd0-ab38-942e233e5dff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932246035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.932246035
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1948242663
Short name T1025
Test name
Test status
Simulation time 26546913 ps
CPU time 1.68 seconds
Started Jun 05 04:33:28 PM PDT 24
Finished Jun 05 04:33:31 PM PDT 24
Peak memory 215220 kb
Host smart-dc0632f7-d9a3-4a9e-af54-c7b249b6edc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948242663 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1948242663
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1858206395
Short name T103
Test name
Test status
Simulation time 53825366 ps
CPU time 1.6 seconds
Started Jun 05 04:33:13 PM PDT 24
Finished Jun 05 04:33:16 PM PDT 24
Peak memory 206848 kb
Host smart-7633a2b7-b600-461b-999c-ca41bd4d8df0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858206395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1858206395
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1633359575
Short name T1002
Test name
Test status
Simulation time 56237633 ps
CPU time 0.77 seconds
Started Jun 05 04:33:06 PM PDT 24
Finished Jun 05 04:33:07 PM PDT 24
Peak memory 203608 kb
Host smart-eb911c65-da95-4129-ac17-c8e44f5981b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633359575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1633359575
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.261642442
Short name T1021
Test name
Test status
Simulation time 320093967 ps
CPU time 2.05 seconds
Started Jun 05 04:33:25 PM PDT 24
Finished Jun 05 04:33:28 PM PDT 24
Peak memory 215144 kb
Host smart-16d5f4ad-4ad9-4534-92bf-dd2af3ddfe95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261642442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.261642442
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1016257637
Short name T1001
Test name
Test status
Simulation time 92492128 ps
CPU time 3.12 seconds
Started Jun 05 04:33:05 PM PDT 24
Finished Jun 05 04:33:09 PM PDT 24
Peak memory 215328 kb
Host smart-9e207baf-df0c-47eb-a656-c69efa689bef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016257637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1016257637
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3759682842
Short name T1009
Test name
Test status
Simulation time 109085458 ps
CPU time 7.21 seconds
Started Jun 05 04:33:05 PM PDT 24
Finished Jun 05 04:33:13 PM PDT 24
Peak memory 215096 kb
Host smart-35768539-6a2d-47a4-9975-f67c6b83b8f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759682842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3759682842
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.634950270
Short name T43
Test name
Test status
Simulation time 509121760 ps
CPU time 3.82 seconds
Started Jun 05 04:33:05 PM PDT 24
Finished Jun 05 04:33:10 PM PDT 24
Peak memory 218052 kb
Host smart-256eda57-0f0c-4a2e-8299-1a7a5db415cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634950270 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.634950270
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.368487953
Short name T978
Test name
Test status
Simulation time 29735204 ps
CPU time 1.84 seconds
Started Jun 05 04:33:16 PM PDT 24
Finished Jun 05 04:33:18 PM PDT 24
Peak memory 215084 kb
Host smart-e33e5208-1bb9-442a-9598-f7ffad041c83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368487953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.368487953
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.766051255
Short name T1036
Test name
Test status
Simulation time 39688464 ps
CPU time 0.7 seconds
Started Jun 05 04:33:16 PM PDT 24
Finished Jun 05 04:33:18 PM PDT 24
Peak memory 204076 kb
Host smart-9e157b63-10f6-4be7-acc9-71548b3cf88e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766051255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.766051255
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2903962494
Short name T958
Test name
Test status
Simulation time 310106444 ps
CPU time 4.08 seconds
Started Jun 05 04:33:09 PM PDT 24
Finished Jun 05 04:33:20 PM PDT 24
Peak memory 215132 kb
Host smart-cfc637d7-df92-4b5f-b6db-63f9d3a5cc74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903962494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2903962494
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1592192117
Short name T139
Test name
Test status
Simulation time 1826413715 ps
CPU time 20.62 seconds
Started Jun 05 04:33:07 PM PDT 24
Finished Jun 05 04:33:28 PM PDT 24
Peak memory 215148 kb
Host smart-12517b47-3fc8-40d8-8ba8-909484335228
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592192117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1592192117
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3525468142
Short name T78
Test name
Test status
Simulation time 118110187 ps
CPU time 3.78 seconds
Started Jun 05 04:33:14 PM PDT 24
Finished Jun 05 04:33:19 PM PDT 24
Peak memory 217364 kb
Host smart-97911f97-faa0-42c7-858a-924383aa4298
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525468142 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3525468142
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2477381389
Short name T1079
Test name
Test status
Simulation time 103677384 ps
CPU time 2.45 seconds
Started Jun 05 04:33:16 PM PDT 24
Finished Jun 05 04:33:19 PM PDT 24
Peak memory 215036 kb
Host smart-9537e17f-044c-4133-ab4b-a336d439b989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477381389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2477381389
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.990888185
Short name T1028
Test name
Test status
Simulation time 27578497 ps
CPU time 0.76 seconds
Started Jun 05 04:33:05 PM PDT 24
Finished Jun 05 04:33:06 PM PDT 24
Peak memory 203888 kb
Host smart-d6fc0405-3e2f-4e5d-9f2c-31d812e53b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990888185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.990888185
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3695420899
Short name T1000
Test name
Test status
Simulation time 593918321 ps
CPU time 3.52 seconds
Started Jun 05 04:33:14 PM PDT 24
Finished Jun 05 04:33:18 PM PDT 24
Peak memory 215104 kb
Host smart-5b308d01-e8dc-491b-b61c-37dec86441ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695420899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3695420899
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.225143266
Short name T92
Test name
Test status
Simulation time 298927803 ps
CPU time 2.33 seconds
Started Jun 05 04:33:04 PM PDT 24
Finished Jun 05 04:33:07 PM PDT 24
Peak memory 215236 kb
Host smart-f6c3cea3-cd71-4273-9256-2e86cc6dbdcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225143266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.225143266
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4000006128
Short name T233
Test name
Test status
Simulation time 460587894 ps
CPU time 7.13 seconds
Started Jun 05 04:33:08 PM PDT 24
Finished Jun 05 04:33:16 PM PDT 24
Peak memory 222100 kb
Host smart-e6e70813-6457-4748-a2aa-4af7aaacfd2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000006128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.4000006128
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.959628825
Short name T137
Test name
Test status
Simulation time 749066614 ps
CPU time 3.66 seconds
Started Jun 05 04:33:03 PM PDT 24
Finished Jun 05 04:33:07 PM PDT 24
Peak memory 217424 kb
Host smart-c196b7a8-11cd-43fb-9aaf-0c19be6559ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959628825 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.959628825
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3468043082
Short name T100
Test name
Test status
Simulation time 63350523 ps
CPU time 1.23 seconds
Started Jun 05 04:33:10 PM PDT 24
Finished Jun 05 04:33:12 PM PDT 24
Peak memory 206864 kb
Host smart-4e6b5d86-ea14-402f-a40d-d656bac561be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468043082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3468043082
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.114450148
Short name T1058
Test name
Test status
Simulation time 45439009 ps
CPU time 0.71 seconds
Started Jun 05 04:33:05 PM PDT 24
Finished Jun 05 04:33:06 PM PDT 24
Peak memory 203912 kb
Host smart-03baf081-2018-4391-b73b-05c82434aa83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114450148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.114450148
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1369694666
Short name T136
Test name
Test status
Simulation time 199504195 ps
CPU time 4.35 seconds
Started Jun 05 04:33:15 PM PDT 24
Finished Jun 05 04:33:20 PM PDT 24
Peak memory 215060 kb
Host smart-77a550f8-df8a-4de7-9621-d4cbd26e68a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369694666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1369694666
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4007663984
Short name T94
Test name
Test status
Simulation time 60763090 ps
CPU time 3.55 seconds
Started Jun 05 04:33:05 PM PDT 24
Finished Jun 05 04:33:09 PM PDT 24
Peak memory 215244 kb
Host smart-e44ceedf-dc61-4e80-9db9-cabcaf3bd168
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007663984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
4007663984
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1838102204
Short name T98
Test name
Test status
Simulation time 1430037962 ps
CPU time 8.24 seconds
Started Jun 05 04:33:07 PM PDT 24
Finished Jun 05 04:33:16 PM PDT 24
Peak memory 215144 kb
Host smart-7065f28c-4d26-47f1-9998-1c95b2f048db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838102204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1838102204
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2245284656
Short name T1010
Test name
Test status
Simulation time 191495266 ps
CPU time 3.24 seconds
Started Jun 05 04:33:05 PM PDT 24
Finished Jun 05 04:33:09 PM PDT 24
Peak memory 218012 kb
Host smart-9ef1a310-d5b4-44a5-9855-5ca2698ab4c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245284656 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2245284656
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3590524063
Short name T994
Test name
Test status
Simulation time 176279873 ps
CPU time 2.71 seconds
Started Jun 05 04:33:14 PM PDT 24
Finished Jun 05 04:33:18 PM PDT 24
Peak memory 215044 kb
Host smart-7c668235-1908-4b0d-b1a7-448ab866f9c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590524063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3590524063
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4213027467
Short name T963
Test name
Test status
Simulation time 12286066 ps
CPU time 0.74 seconds
Started Jun 05 04:33:13 PM PDT 24
Finished Jun 05 04:33:15 PM PDT 24
Peak memory 203608 kb
Host smart-8a94f176-e317-45d0-afe5-9b42afde72bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213027467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
4213027467
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2413366723
Short name T977
Test name
Test status
Simulation time 213539826 ps
CPU time 2.97 seconds
Started Jun 05 04:33:07 PM PDT 24
Finished Jun 05 04:33:11 PM PDT 24
Peak memory 215076 kb
Host smart-0d060589-f344-40ce-8cdc-96c6c1176f20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413366723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2413366723
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4035891051
Short name T95
Test name
Test status
Simulation time 51137313 ps
CPU time 3.01 seconds
Started Jun 05 04:33:09 PM PDT 24
Finished Jun 05 04:33:13 PM PDT 24
Peak memory 215200 kb
Host smart-c80e09c0-2645-44c0-9127-badb1ced5656
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035891051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4035891051
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1059751328
Short name T1075
Test name
Test status
Simulation time 2050660915 ps
CPU time 7.88 seconds
Started Jun 05 04:33:00 PM PDT 24
Finished Jun 05 04:33:09 PM PDT 24
Peak memory 215036 kb
Host smart-5d9ea136-0d85-44eb-85e5-604d7aac255e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059751328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1059751328
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3848513115
Short name T1011
Test name
Test status
Simulation time 2426948721 ps
CPU time 13.78 seconds
Started Jun 05 04:32:49 PM PDT 24
Finished Jun 05 04:33:03 PM PDT 24
Peak memory 206888 kb
Host smart-c7403565-6a63-4611-ac29-eaead2d792d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848513115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3848513115
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2669838070
Short name T64
Test name
Test status
Simulation time 86652353 ps
CPU time 1.5 seconds
Started Jun 05 04:32:49 PM PDT 24
Finished Jun 05 04:32:51 PM PDT 24
Peak memory 216056 kb
Host smart-e5161e41-0917-462a-980a-4875c5b0f19a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669838070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2669838070
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.822331520
Short name T982
Test name
Test status
Simulation time 80065033 ps
CPU time 1.74 seconds
Started Jun 05 04:32:53 PM PDT 24
Finished Jun 05 04:32:55 PM PDT 24
Peak memory 215196 kb
Host smart-8f9ff34f-a940-4f13-9d4e-6b4f21e7ca1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822331520 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.822331520
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1143531416
Short name T1068
Test name
Test status
Simulation time 74177806 ps
CPU time 2.04 seconds
Started Jun 05 04:32:52 PM PDT 24
Finished Jun 05 04:32:54 PM PDT 24
Peak memory 215084 kb
Host smart-cbaa8020-26d8-41aa-b715-bc6f049bba67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143531416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
143531416
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1177671748
Short name T992
Test name
Test status
Simulation time 11310115 ps
CPU time 0.79 seconds
Started Jun 05 04:32:53 PM PDT 24
Finished Jun 05 04:32:55 PM PDT 24
Peak memory 203908 kb
Host smart-5c64eb2a-48f4-4ec1-9801-64e05878a0b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177671748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
177671748
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.782627015
Short name T1018
Test name
Test status
Simulation time 46824111 ps
CPU time 1.88 seconds
Started Jun 05 04:32:49 PM PDT 24
Finished Jun 05 04:32:51 PM PDT 24
Peak memory 215016 kb
Host smart-e0bb1f5c-dfc7-4db9-9ecc-bd8dd6eea7e5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782627015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.782627015
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1285872345
Short name T999
Test name
Test status
Simulation time 12660902 ps
CPU time 0.67 seconds
Started Jun 05 04:32:55 PM PDT 24
Finished Jun 05 04:32:56 PM PDT 24
Peak memory 203444 kb
Host smart-2ff43c80-9423-4800-9b66-4550f828e340
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285872345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1285872345
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.591110843
Short name T1029
Test name
Test status
Simulation time 1024755790 ps
CPU time 3.2 seconds
Started Jun 05 04:32:58 PM PDT 24
Finished Jun 05 04:33:02 PM PDT 24
Peak memory 215116 kb
Host smart-3a33b047-de68-406b-9cbd-cbd70370754b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591110843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.591110843
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3339648096
Short name T231
Test name
Test status
Simulation time 2606942108 ps
CPU time 19.89 seconds
Started Jun 05 04:32:53 PM PDT 24
Finished Jun 05 04:33:14 PM PDT 24
Peak memory 215168 kb
Host smart-64cfea55-5c3a-4089-a65f-9cdfc99d9853
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339648096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3339648096
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2062327862
Short name T997
Test name
Test status
Simulation time 24861515 ps
CPU time 0.69 seconds
Started Jun 05 04:33:10 PM PDT 24
Finished Jun 05 04:33:11 PM PDT 24
Peak memory 203616 kb
Host smart-b4359432-5caf-4fc7-b514-9a521bc7f315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062327862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2062327862
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3590137477
Short name T972
Test name
Test status
Simulation time 57489436 ps
CPU time 0.8 seconds
Started Jun 05 04:33:06 PM PDT 24
Finished Jun 05 04:33:07 PM PDT 24
Peak memory 203592 kb
Host smart-676b1dba-0e0c-4867-a1f9-1a10da7082f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590137477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3590137477
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1569285511
Short name T1030
Test name
Test status
Simulation time 50451997 ps
CPU time 0.77 seconds
Started Jun 05 04:33:08 PM PDT 24
Finished Jun 05 04:33:09 PM PDT 24
Peak memory 203568 kb
Host smart-c0e2ac1a-dcd0-4bac-85d9-64bdee1a25a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569285511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1569285511
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2291261453
Short name T1049
Test name
Test status
Simulation time 22498783 ps
CPU time 0.74 seconds
Started Jun 05 04:33:13 PM PDT 24
Finished Jun 05 04:33:14 PM PDT 24
Peak memory 203612 kb
Host smart-0a95947a-369d-49f0-a7ae-65f1c8b05bdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291261453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2291261453
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3702063575
Short name T955
Test name
Test status
Simulation time 36991597 ps
CPU time 0.73 seconds
Started Jun 05 04:33:08 PM PDT 24
Finished Jun 05 04:33:09 PM PDT 24
Peak memory 203584 kb
Host smart-f0a8c775-9fb8-43b6-8fc7-8bd7294492c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702063575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3702063575
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2648697256
Short name T1046
Test name
Test status
Simulation time 61013297 ps
CPU time 0.75 seconds
Started Jun 05 04:33:06 PM PDT 24
Finished Jun 05 04:33:08 PM PDT 24
Peak memory 203616 kb
Host smart-6a2fd84f-3a2a-4e95-a0ee-bb85f42f40cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648697256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2648697256
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3670952194
Short name T986
Test name
Test status
Simulation time 43713652 ps
CPU time 0.72 seconds
Started Jun 05 04:33:04 PM PDT 24
Finished Jun 05 04:33:05 PM PDT 24
Peak memory 203916 kb
Host smart-a2ad084c-fd8c-4bb7-a198-3d66b578fdb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670952194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3670952194
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2019618592
Short name T987
Test name
Test status
Simulation time 34784905 ps
CPU time 0.76 seconds
Started Jun 05 04:33:12 PM PDT 24
Finished Jun 05 04:33:13 PM PDT 24
Peak memory 203600 kb
Host smart-b227ceed-833a-4173-b0e6-4574e1d27615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019618592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2019618592
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3221192117
Short name T1024
Test name
Test status
Simulation time 39391378 ps
CPU time 0.75 seconds
Started Jun 05 04:33:13 PM PDT 24
Finished Jun 05 04:33:15 PM PDT 24
Peak memory 203596 kb
Host smart-d074123c-02d9-468d-9d1f-12c363c5633f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221192117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3221192117
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3393492817
Short name T1015
Test name
Test status
Simulation time 13146329 ps
CPU time 0.71 seconds
Started Jun 05 04:33:16 PM PDT 24
Finished Jun 05 04:33:18 PM PDT 24
Peak memory 203604 kb
Host smart-b58c6587-d78b-4ec8-bf3c-25c8d23950db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393492817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3393492817
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3781199077
Short name T1038
Test name
Test status
Simulation time 1215223500 ps
CPU time 15.55 seconds
Started Jun 05 04:33:07 PM PDT 24
Finished Jun 05 04:33:24 PM PDT 24
Peak memory 215040 kb
Host smart-5314916b-a2dd-4c45-96b6-e3bba8d9ba36
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781199077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3781199077
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3262052740
Short name T965
Test name
Test status
Simulation time 3597477021 ps
CPU time 13.92 seconds
Started Jun 05 04:32:54 PM PDT 24
Finished Jun 05 04:33:09 PM PDT 24
Peak memory 215120 kb
Host smart-9cdf71cb-fe88-492b-89c9-152070abd84b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262052740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3262052740
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3972275760
Short name T62
Test name
Test status
Simulation time 46173480 ps
CPU time 0.92 seconds
Started Jun 05 04:32:58 PM PDT 24
Finished Jun 05 04:32:59 PM PDT 24
Peak memory 206752 kb
Host smart-3972aa1d-1f4d-45d8-a8b6-b277313927ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972275760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3972275760
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3728208894
Short name T1042
Test name
Test status
Simulation time 128518606 ps
CPU time 3.71 seconds
Started Jun 05 04:33:07 PM PDT 24
Finished Jun 05 04:33:12 PM PDT 24
Peak memory 217984 kb
Host smart-e0e33072-abe0-4830-8e01-2a470fca2d38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728208894 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3728208894
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2233004809
Short name T109
Test name
Test status
Simulation time 149156600 ps
CPU time 1.29 seconds
Started Jun 05 04:32:51 PM PDT 24
Finished Jun 05 04:32:53 PM PDT 24
Peak memory 206824 kb
Host smart-869e127f-d016-4dbc-8653-096ebce9eb9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233004809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
233004809
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.360927227
Short name T980
Test name
Test status
Simulation time 12041776 ps
CPU time 0.72 seconds
Started Jun 05 04:32:54 PM PDT 24
Finished Jun 05 04:32:55 PM PDT 24
Peak memory 203916 kb
Host smart-0d89b2e7-478d-4b18-adb3-a76208ea7878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360927227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.360927227
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2630332791
Short name T1069
Test name
Test status
Simulation time 136135543 ps
CPU time 2.41 seconds
Started Jun 05 04:33:00 PM PDT 24
Finished Jun 05 04:33:03 PM PDT 24
Peak memory 215172 kb
Host smart-a3b6a723-4ac3-4133-ba42-01e5fb399fdb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630332791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2630332791
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2921207265
Short name T1035
Test name
Test status
Simulation time 13643802 ps
CPU time 0.68 seconds
Started Jun 05 04:32:53 PM PDT 24
Finished Jun 05 04:32:54 PM PDT 24
Peak memory 203820 kb
Host smart-4e9b4566-5461-4f62-b71a-349fc4ac4a07
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921207265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2921207265
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2397828337
Short name T998
Test name
Test status
Simulation time 145985759 ps
CPU time 1.85 seconds
Started Jun 05 04:33:00 PM PDT 24
Finished Jun 05 04:33:07 PM PDT 24
Peak memory 215088 kb
Host smart-07d64405-a07e-40f5-9510-cd05ecf5e063
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397828337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2397828337
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.583625662
Short name T1008
Test name
Test status
Simulation time 99987132 ps
CPU time 1.67 seconds
Started Jun 05 04:32:50 PM PDT 24
Finished Jun 05 04:32:52 PM PDT 24
Peak memory 215332 kb
Host smart-909c444b-4b1d-48de-80ec-b2a7ff7187d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583625662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.583625662
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3937178284
Short name T138
Test name
Test status
Simulation time 1447521010 ps
CPU time 16.74 seconds
Started Jun 05 04:32:50 PM PDT 24
Finished Jun 05 04:33:07 PM PDT 24
Peak memory 215500 kb
Host smart-8270a253-cb35-4a8a-a669-632c5a648dde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937178284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3937178284
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.40980066
Short name T1061
Test name
Test status
Simulation time 32937773 ps
CPU time 0.78 seconds
Started Jun 05 04:33:12 PM PDT 24
Finished Jun 05 04:33:14 PM PDT 24
Peak memory 203568 kb
Host smart-a06233fb-89dc-449f-bc72-ff8228ff70d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40980066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.40980066
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1311679639
Short name T961
Test name
Test status
Simulation time 90428267 ps
CPU time 0.77 seconds
Started Jun 05 04:33:13 PM PDT 24
Finished Jun 05 04:33:15 PM PDT 24
Peak memory 203932 kb
Host smart-b458aceb-135f-40cf-a488-66996aa068ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311679639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1311679639
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1500274891
Short name T960
Test name
Test status
Simulation time 71911856 ps
CPU time 0.71 seconds
Started Jun 05 04:33:06 PM PDT 24
Finished Jun 05 04:33:08 PM PDT 24
Peak memory 203596 kb
Host smart-abf9e859-cc8e-4ebf-994b-55d7027b2bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500274891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1500274891
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2921966872
Short name T1012
Test name
Test status
Simulation time 75677496 ps
CPU time 0.69 seconds
Started Jun 05 04:33:12 PM PDT 24
Finished Jun 05 04:33:14 PM PDT 24
Peak memory 203928 kb
Host smart-2f1ca9bb-7c5c-464a-9707-319b5f82589a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921966872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2921966872
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1155285905
Short name T1054
Test name
Test status
Simulation time 45689044 ps
CPU time 0.76 seconds
Started Jun 05 04:33:13 PM PDT 24
Finished Jun 05 04:33:15 PM PDT 24
Peak memory 203604 kb
Host smart-d62aea8d-e8e8-43dc-a2ff-bd6971864705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155285905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1155285905
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2438736896
Short name T1064
Test name
Test status
Simulation time 71566167 ps
CPU time 0.75 seconds
Started Jun 05 04:33:19 PM PDT 24
Finished Jun 05 04:33:20 PM PDT 24
Peak memory 203564 kb
Host smart-88e0d06a-440f-40ae-b3af-4c6fabf5cbb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438736896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2438736896
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1853121555
Short name T981
Test name
Test status
Simulation time 41991022 ps
CPU time 0.76 seconds
Started Jun 05 04:33:15 PM PDT 24
Finished Jun 05 04:33:17 PM PDT 24
Peak memory 203616 kb
Host smart-3f69e9f8-99e7-426c-b3b6-25a0993ad7e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853121555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1853121555
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3376929093
Short name T974
Test name
Test status
Simulation time 23233250 ps
CPU time 0.74 seconds
Started Jun 05 04:33:20 PM PDT 24
Finished Jun 05 04:33:21 PM PDT 24
Peak memory 203900 kb
Host smart-401e9e10-7250-41ee-bcc6-a8e4001b5fc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376929093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3376929093
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2244128028
Short name T1007
Test name
Test status
Simulation time 15057394 ps
CPU time 0.74 seconds
Started Jun 05 04:33:19 PM PDT 24
Finished Jun 05 04:33:21 PM PDT 24
Peak memory 203580 kb
Host smart-371dc207-0dcd-437c-b47e-e04d19111c0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244128028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2244128028
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3965263658
Short name T1067
Test name
Test status
Simulation time 17968675 ps
CPU time 0.77 seconds
Started Jun 05 04:33:45 PM PDT 24
Finished Jun 05 04:33:48 PM PDT 24
Peak memory 203596 kb
Host smart-59fd7cdc-05d4-451c-8261-30eb1e39ddff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965263658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3965263658
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1935452886
Short name T1051
Test name
Test status
Simulation time 227618998 ps
CPU time 15.09 seconds
Started Jun 05 04:32:53 PM PDT 24
Finished Jun 05 04:33:09 PM PDT 24
Peak memory 206804 kb
Host smart-994d28e1-7ff5-4324-8844-ce1c0fd87070
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935452886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1935452886
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.279541351
Short name T111
Test name
Test status
Simulation time 9385345636 ps
CPU time 36.13 seconds
Started Jun 05 04:32:56 PM PDT 24
Finished Jun 05 04:33:32 PM PDT 24
Peak memory 215012 kb
Host smart-d7bd5ac2-1493-423b-95d1-ef66234a3e85
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279541351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.279541351
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4020560871
Short name T1076
Test name
Test status
Simulation time 40234854 ps
CPU time 1.33 seconds
Started Jun 05 04:33:57 PM PDT 24
Finished Jun 05 04:34:00 PM PDT 24
Peak memory 205820 kb
Host smart-256bd0a6-e053-4c35-9615-7cd53499e041
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020560871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.4020560871
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1141105324
Short name T1034
Test name
Test status
Simulation time 213242296 ps
CPU time 1.82 seconds
Started Jun 05 04:33:00 PM PDT 24
Finished Jun 05 04:33:03 PM PDT 24
Peak memory 216304 kb
Host smart-b437f875-64c2-4200-9a26-1bd90a3c2b38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141105324 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1141105324
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1444605354
Short name T104
Test name
Test status
Simulation time 249196792 ps
CPU time 1.87 seconds
Started Jun 05 04:32:53 PM PDT 24
Finished Jun 05 04:32:55 PM PDT 24
Peak memory 215096 kb
Host smart-153cbe6c-e70c-4eed-bee6-3c6d22c7b8f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444605354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
444605354
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2041849886
Short name T967
Test name
Test status
Simulation time 62910462 ps
CPU time 0.72 seconds
Started Jun 05 04:32:53 PM PDT 24
Finished Jun 05 04:32:55 PM PDT 24
Peak memory 203912 kb
Host smart-4a1f69b9-9aea-4a0d-b4a1-ae0e3785b09e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041849886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
041849886
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1459333409
Short name T102
Test name
Test status
Simulation time 17802279 ps
CPU time 1.31 seconds
Started Jun 05 04:33:09 PM PDT 24
Finished Jun 05 04:33:11 PM PDT 24
Peak memory 215372 kb
Host smart-41648770-17d6-4f02-8759-4d41fe81d5ad
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459333409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1459333409
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1677281492
Short name T979
Test name
Test status
Simulation time 13330394 ps
CPU time 0.71 seconds
Started Jun 05 04:32:59 PM PDT 24
Finished Jun 05 04:33:00 PM PDT 24
Peak memory 203480 kb
Host smart-e66f3410-ad8c-418d-bee2-4a9b203c8313
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677281492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1677281492
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.178421701
Short name T989
Test name
Test status
Simulation time 114661059 ps
CPU time 1.82 seconds
Started Jun 05 04:32:53 PM PDT 24
Finished Jun 05 04:32:55 PM PDT 24
Peak memory 215072 kb
Host smart-715fe6f3-3772-492e-9d2f-37341c916c23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178421701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.178421701
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2154243293
Short name T89
Test name
Test status
Simulation time 622229266 ps
CPU time 3.95 seconds
Started Jun 05 04:33:02 PM PDT 24
Finished Jun 05 04:33:07 PM PDT 24
Peak memory 215244 kb
Host smart-42ca71dc-8190-46f1-9250-f1fa24225d0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154243293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
154243293
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.349950428
Short name T81
Test name
Test status
Simulation time 400494067 ps
CPU time 12.76 seconds
Started Jun 05 04:33:00 PM PDT 24
Finished Jun 05 04:33:14 PM PDT 24
Peak memory 215204 kb
Host smart-2967493f-8ba2-425f-a868-0a10d34192b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349950428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.349950428
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2114043101
Short name T991
Test name
Test status
Simulation time 17088199 ps
CPU time 0.78 seconds
Started Jun 05 04:33:13 PM PDT 24
Finished Jun 05 04:33:15 PM PDT 24
Peak memory 203916 kb
Host smart-7660ae08-26a6-498f-97b1-371e113f5b3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114043101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2114043101
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.259358504
Short name T1033
Test name
Test status
Simulation time 23313088 ps
CPU time 0.77 seconds
Started Jun 05 04:33:12 PM PDT 24
Finished Jun 05 04:33:14 PM PDT 24
Peak memory 204080 kb
Host smart-1f9ad4b9-3f97-4da0-8d8e-d51cba4a6914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259358504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.259358504
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3395051023
Short name T973
Test name
Test status
Simulation time 18042229 ps
CPU time 0.74 seconds
Started Jun 05 04:33:14 PM PDT 24
Finished Jun 05 04:33:16 PM PDT 24
Peak memory 203608 kb
Host smart-5c168bd5-9b87-4da0-a220-c50a2fe7bf8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395051023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3395051023
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2879670881
Short name T1063
Test name
Test status
Simulation time 20838428 ps
CPU time 0.75 seconds
Started Jun 05 04:33:27 PM PDT 24
Finished Jun 05 04:33:29 PM PDT 24
Peak memory 203596 kb
Host smart-8e51b6c4-9862-497f-bd20-a84e765d81ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879670881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2879670881
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3608958356
Short name T990
Test name
Test status
Simulation time 14281457 ps
CPU time 0.77 seconds
Started Jun 05 04:33:13 PM PDT 24
Finished Jun 05 04:33:15 PM PDT 24
Peak memory 203880 kb
Host smart-c8d86079-20ae-4c92-88bb-2393bf9321d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608958356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3608958356
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1132320059
Short name T964
Test name
Test status
Simulation time 41017829 ps
CPU time 0.74 seconds
Started Jun 05 04:33:29 PM PDT 24
Finished Jun 05 04:33:31 PM PDT 24
Peak memory 203572 kb
Host smart-23e7d8f6-1abd-40c9-b7b5-81e0fd334c3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132320059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1132320059
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3932341665
Short name T976
Test name
Test status
Simulation time 46144903 ps
CPU time 0.74 seconds
Started Jun 05 04:33:12 PM PDT 24
Finished Jun 05 04:33:14 PM PDT 24
Peak memory 203600 kb
Host smart-983eaf07-2e97-488d-a486-fb7f2634cac7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932341665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3932341665
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2946992294
Short name T968
Test name
Test status
Simulation time 17271388 ps
CPU time 0.76 seconds
Started Jun 05 04:33:31 PM PDT 24
Finished Jun 05 04:33:33 PM PDT 24
Peak memory 203600 kb
Host smart-57ac4a46-9387-4923-a49e-0e513155975d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946992294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2946992294
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.292333126
Short name T1032
Test name
Test status
Simulation time 43679072 ps
CPU time 0.71 seconds
Started Jun 05 04:33:13 PM PDT 24
Finished Jun 05 04:33:15 PM PDT 24
Peak memory 203560 kb
Host smart-af2fe0ce-1243-437e-918d-a268342f1bf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292333126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.292333126
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2133248258
Short name T971
Test name
Test status
Simulation time 16745149 ps
CPU time 0.76 seconds
Started Jun 05 04:33:15 PM PDT 24
Finished Jun 05 04:33:17 PM PDT 24
Peak memory 203600 kb
Host smart-350b960c-359a-47d5-b1ce-8f34e7bd8605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133248258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2133248258
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.85599392
Short name T995
Test name
Test status
Simulation time 216575782 ps
CPU time 3.75 seconds
Started Jun 05 04:33:03 PM PDT 24
Finished Jun 05 04:33:07 PM PDT 24
Peak memory 218044 kb
Host smart-5de0ede2-fb18-4f8a-9c76-fba81b4c7cf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85599392 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.85599392
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2401345345
Short name T1057
Test name
Test status
Simulation time 109813676 ps
CPU time 1.84 seconds
Started Jun 05 04:33:04 PM PDT 24
Finished Jun 05 04:33:06 PM PDT 24
Peak memory 206832 kb
Host smart-fe90ad4e-b045-4b39-94db-c98fa90bb68b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401345345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
401345345
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.570404661
Short name T966
Test name
Test status
Simulation time 46728346 ps
CPU time 0.73 seconds
Started Jun 05 04:33:08 PM PDT 24
Finished Jun 05 04:33:09 PM PDT 24
Peak memory 203576 kb
Host smart-93126640-f645-4a33-9e40-e2f18e03e625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570404661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.570404661
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2441450821
Short name T1003
Test name
Test status
Simulation time 161261544 ps
CPU time 4.31 seconds
Started Jun 05 04:32:59 PM PDT 24
Finished Jun 05 04:33:04 PM PDT 24
Peak memory 215088 kb
Host smart-d7c062d5-2eea-42e3-b686-104eeff1d6ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441450821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2441450821
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.301669817
Short name T44
Test name
Test status
Simulation time 528394486 ps
CPU time 2.64 seconds
Started Jun 05 04:33:09 PM PDT 24
Finished Jun 05 04:33:13 PM PDT 24
Peak memory 215276 kb
Host smart-15e95049-4b8b-4f13-946c-7042961df8b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301669817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.301669817
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2737676853
Short name T230
Test name
Test status
Simulation time 1787599689 ps
CPU time 14.16 seconds
Started Jun 05 04:33:02 PM PDT 24
Finished Jun 05 04:33:17 PM PDT 24
Peak memory 215108 kb
Host smart-83ca31ba-4cbc-4486-aa72-13b405573b7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737676853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2737676853
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1646580012
Short name T1065
Test name
Test status
Simulation time 145468789 ps
CPU time 3.67 seconds
Started Jun 05 04:33:00 PM PDT 24
Finished Jun 05 04:33:04 PM PDT 24
Peak memory 216972 kb
Host smart-11ff0a83-2ebe-4fad-bd5a-b815955885e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646580012 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1646580012
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1083382439
Short name T1060
Test name
Test status
Simulation time 111281744 ps
CPU time 2.71 seconds
Started Jun 05 04:33:11 PM PDT 24
Finished Jun 05 04:33:15 PM PDT 24
Peak memory 215020 kb
Host smart-abc3e3ca-ffd9-4046-9530-5f8bfb35f2a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083382439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
083382439
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.640520841
Short name T1026
Test name
Test status
Simulation time 40780172 ps
CPU time 0.71 seconds
Started Jun 05 04:32:56 PM PDT 24
Finished Jun 05 04:32:58 PM PDT 24
Peak memory 203560 kb
Host smart-bba87b27-b200-4cbf-afc0-3cb31d652223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640520841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.640520841
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.538501573
Short name T1023
Test name
Test status
Simulation time 110221117 ps
CPU time 2.8 seconds
Started Jun 05 04:32:59 PM PDT 24
Finished Jun 05 04:33:02 PM PDT 24
Peak memory 215024 kb
Host smart-6381f808-63a3-48b6-b71f-5e42ff19bcf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538501573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.538501573
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.856174190
Short name T1039
Test name
Test status
Simulation time 110403239 ps
CPU time 2.33 seconds
Started Jun 05 04:32:58 PM PDT 24
Finished Jun 05 04:33:01 PM PDT 24
Peak memory 215096 kb
Host smart-d8c58146-d269-40d7-b614-28e9b28dd031
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856174190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.856174190
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2216738177
Short name T1031
Test name
Test status
Simulation time 650164551 ps
CPU time 14.67 seconds
Started Jun 05 04:33:16 PM PDT 24
Finished Jun 05 04:33:32 PM PDT 24
Peak memory 215308 kb
Host smart-9d53597f-2238-445f-9df4-e819b25e32dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216738177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2216738177
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3489848643
Short name T87
Test name
Test status
Simulation time 166241991 ps
CPU time 3.9 seconds
Started Jun 05 04:33:10 PM PDT 24
Finished Jun 05 04:33:15 PM PDT 24
Peak memory 216712 kb
Host smart-01f90877-6fd5-4638-afeb-f66cd5cdd1e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489848643 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3489848643
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2996876908
Short name T106
Test name
Test status
Simulation time 190264985 ps
CPU time 2.52 seconds
Started Jun 05 04:33:01 PM PDT 24
Finished Jun 05 04:33:04 PM PDT 24
Peak memory 214896 kb
Host smart-94848349-aca5-4f15-bac2-f354deff5190
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996876908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
996876908
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.62159536
Short name T996
Test name
Test status
Simulation time 14179418 ps
CPU time 0.71 seconds
Started Jun 05 04:33:10 PM PDT 24
Finished Jun 05 04:33:11 PM PDT 24
Peak memory 203544 kb
Host smart-d11164aa-9f46-450a-84db-b26b439e20b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62159536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.62159536
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3290214017
Short name T1027
Test name
Test status
Simulation time 242511629 ps
CPU time 4.04 seconds
Started Jun 05 04:33:11 PM PDT 24
Finished Jun 05 04:33:16 PM PDT 24
Peak memory 215116 kb
Host smart-5c5b0568-ccb7-42f2-b86f-aed8c6d7cb66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290214017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3290214017
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3388096585
Short name T88
Test name
Test status
Simulation time 190103313 ps
CPU time 4.43 seconds
Started Jun 05 04:33:10 PM PDT 24
Finished Jun 05 04:33:15 PM PDT 24
Peak memory 215180 kb
Host smart-58d48d28-5ae0-44de-90cb-e00ad5e4b732
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388096585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
388096585
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1186288023
Short name T1041
Test name
Test status
Simulation time 556179292 ps
CPU time 15.32 seconds
Started Jun 05 04:33:16 PM PDT 24
Finished Jun 05 04:33:32 PM PDT 24
Peak memory 215104 kb
Host smart-47f3e236-114f-4119-95e2-f03d39b87bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186288023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1186288023
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1690426813
Short name T993
Test name
Test status
Simulation time 116818091 ps
CPU time 2.66 seconds
Started Jun 05 04:33:28 PM PDT 24
Finished Jun 05 04:33:32 PM PDT 24
Peak memory 217784 kb
Host smart-28ccc3b2-41c7-4f9f-9c4a-97d65ce6551f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690426813 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1690426813
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.353251221
Short name T956
Test name
Test status
Simulation time 433058239 ps
CPU time 2.59 seconds
Started Jun 05 04:33:10 PM PDT 24
Finished Jun 05 04:33:14 PM PDT 24
Peak memory 215020 kb
Host smart-233204eb-2758-42f9-9751-c9ab88fd0ce2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353251221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.353251221
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2988674891
Short name T1040
Test name
Test status
Simulation time 50158500 ps
CPU time 0.75 seconds
Started Jun 05 04:33:12 PM PDT 24
Finished Jun 05 04:33:14 PM PDT 24
Peak memory 203604 kb
Host smart-3ec785b0-2ef4-4f55-a621-a64a50b58fe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988674891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
988674891
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1713717055
Short name T1070
Test name
Test status
Simulation time 54836868 ps
CPU time 1.83 seconds
Started Jun 05 04:33:07 PM PDT 24
Finished Jun 05 04:33:10 PM PDT 24
Peak memory 214980 kb
Host smart-0aca25aa-8d73-4fe5-b2d2-18576d04ef65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713717055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1713717055
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1231620354
Short name T227
Test name
Test status
Simulation time 1096238118 ps
CPU time 5.03 seconds
Started Jun 05 04:33:05 PM PDT 24
Finished Jun 05 04:33:10 PM PDT 24
Peak memory 215344 kb
Host smart-0310867f-9495-40c3-8d2b-4d6b6c6362f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231620354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
231620354
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1844208793
Short name T232
Test name
Test status
Simulation time 720777296 ps
CPU time 7.78 seconds
Started Jun 05 04:32:58 PM PDT 24
Finished Jun 05 04:33:06 PM PDT 24
Peak memory 215896 kb
Host smart-c2289e56-9655-479e-a21b-c2fec3a49baa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844208793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1844208793
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1183037289
Short name T97
Test name
Test status
Simulation time 105379647 ps
CPU time 2.78 seconds
Started Jun 05 04:33:14 PM PDT 24
Finished Jun 05 04:33:18 PM PDT 24
Peak memory 216532 kb
Host smart-6eaec61c-7f6b-47e8-abb7-b98272ff560e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183037289 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1183037289
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2735945273
Short name T1022
Test name
Test status
Simulation time 76088950 ps
CPU time 1.48 seconds
Started Jun 05 04:33:06 PM PDT 24
Finished Jun 05 04:33:09 PM PDT 24
Peak memory 215024 kb
Host smart-f8ba4aae-bf7b-49d8-b465-f03ec3925cc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735945273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
735945273
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3466320434
Short name T1078
Test name
Test status
Simulation time 32250955 ps
CPU time 0.7 seconds
Started Jun 05 04:32:57 PM PDT 24
Finished Jun 05 04:32:58 PM PDT 24
Peak memory 203880 kb
Host smart-adbdb27c-7f13-40a9-a6c6-56cde953dcee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466320434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
466320434
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2111834614
Short name T1059
Test name
Test status
Simulation time 41899177 ps
CPU time 2.72 seconds
Started Jun 05 04:33:15 PM PDT 24
Finished Jun 05 04:33:19 PM PDT 24
Peak memory 215152 kb
Host smart-5c023b76-b8b3-4637-8414-fb6671da4881
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111834614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2111834614
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3494456235
Short name T91
Test name
Test status
Simulation time 100747043 ps
CPU time 1.48 seconds
Started Jun 05 04:32:57 PM PDT 24
Finished Jun 05 04:32:59 PM PDT 24
Peak memory 215160 kb
Host smart-0f2660b5-f2b9-49a0-9d28-93d940baa2c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494456235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
494456235
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.361938010
Short name T1004
Test name
Test status
Simulation time 369090878 ps
CPU time 9.26 seconds
Started Jun 05 04:33:00 PM PDT 24
Finished Jun 05 04:33:09 PM PDT 24
Peak memory 216636 kb
Host smart-e66af525-2551-47eb-9444-97718e5064e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361938010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.361938010
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2367088518
Short name T816
Test name
Test status
Simulation time 1023913839 ps
CPU time 4.63 seconds
Started Jun 05 05:34:38 PM PDT 24
Finished Jun 05 05:34:43 PM PDT 24
Peak memory 227424 kb
Host smart-fb80a954-2196-44dc-a035-da444dbcb3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367088518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2367088518
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.759787105
Short name T319
Test name
Test status
Simulation time 16406989 ps
CPU time 0.75 seconds
Started Jun 05 05:34:29 PM PDT 24
Finished Jun 05 05:34:30 PM PDT 24
Peak memory 207084 kb
Host smart-f9f93fe5-d5ee-46b3-b926-a0f457ed9af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759787105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.759787105
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1566539985
Short name T692
Test name
Test status
Simulation time 79569450058 ps
CPU time 54.06 seconds
Started Jun 05 05:34:46 PM PDT 24
Finished Jun 05 05:35:41 PM PDT 24
Peak memory 249316 kb
Host smart-572d994d-ae8c-4db7-a33d-b6ff0402c45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566539985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1566539985
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.206677987
Short name T127
Test name
Test status
Simulation time 31489742327 ps
CPU time 312.85 seconds
Started Jun 05 05:34:45 PM PDT 24
Finished Jun 05 05:39:59 PM PDT 24
Peak memory 264576 kb
Host smart-e6418370-fb3f-42d9-ad0d-ebae3571ec1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206677987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
206677987
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3537996221
Short name T34
Test name
Test status
Simulation time 770536759 ps
CPU time 13.48 seconds
Started Jun 05 05:34:37 PM PDT 24
Finished Jun 05 05:34:51 PM PDT 24
Peak memory 234996 kb
Host smart-92d00109-490f-4683-a818-d570a039551b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537996221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3537996221
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2147414180
Short name T586
Test name
Test status
Simulation time 1052629225 ps
CPU time 14.47 seconds
Started Jun 05 05:34:38 PM PDT 24
Finished Jun 05 05:34:53 PM PDT 24
Peak memory 224616 kb
Host smart-026b96d0-5412-41a9-b234-e580db7c52ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147414180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2147414180
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2075098467
Short name T542
Test name
Test status
Simulation time 15976851250 ps
CPU time 125.34 seconds
Started Jun 05 05:34:36 PM PDT 24
Finished Jun 05 05:36:42 PM PDT 24
Peak memory 224620 kb
Host smart-5dc7e368-0a97-4f0d-8750-1a5c62c3ce5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075098467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2075098467
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3259912459
Short name T807
Test name
Test status
Simulation time 377595224 ps
CPU time 5.75 seconds
Started Jun 05 05:34:28 PM PDT 24
Finished Jun 05 05:34:35 PM PDT 24
Peak memory 232808 kb
Host smart-3a47418f-f5c1-48bd-a9f2-5aff6ed77857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259912459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3259912459
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1439256163
Short name T670
Test name
Test status
Simulation time 2921955378 ps
CPU time 10.17 seconds
Started Jun 05 05:34:36 PM PDT 24
Finished Jun 05 05:34:47 PM PDT 24
Peak memory 223084 kb
Host smart-632465d8-9564-47cb-836b-9bd1644a1516
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1439256163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1439256163
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1903489144
Short name T646
Test name
Test status
Simulation time 18373257693 ps
CPU time 116.3 seconds
Started Jun 05 05:34:46 PM PDT 24
Finished Jun 05 05:36:43 PM PDT 24
Peak memory 270836 kb
Host smart-345a6c74-084e-4536-be51-e0bd0327c353
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903489144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1903489144
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2084848995
Short name T289
Test name
Test status
Simulation time 808857995 ps
CPU time 2.96 seconds
Started Jun 05 05:34:27 PM PDT 24
Finished Jun 05 05:34:30 PM PDT 24
Peak memory 216656 kb
Host smart-94518957-9155-4929-ac65-598b4db34cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084848995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2084848995
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2569793472
Short name T314
Test name
Test status
Simulation time 890921891 ps
CPU time 3.14 seconds
Started Jun 05 05:34:32 PM PDT 24
Finished Jun 05 05:34:36 PM PDT 24
Peak memory 216460 kb
Host smart-c62c07df-728e-4635-aabd-134362ffec49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569793472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2569793472
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1018841562
Short name T637
Test name
Test status
Simulation time 170886539 ps
CPU time 0.89 seconds
Started Jun 05 05:34:30 PM PDT 24
Finished Jun 05 05:34:31 PM PDT 24
Peak memory 207028 kb
Host smart-f7665b45-98b8-4f68-8b36-6f8de03ffdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018841562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1018841562
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.135675023
Short name T157
Test name
Test status
Simulation time 3792759911 ps
CPU time 14.22 seconds
Started Jun 05 05:34:38 PM PDT 24
Finished Jun 05 05:34:53 PM PDT 24
Peak memory 232848 kb
Host smart-fb5f64fa-bcf4-4894-af09-61adb1da7c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135675023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.135675023
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.570141922
Short name T470
Test name
Test status
Simulation time 14488667 ps
CPU time 0.72 seconds
Started Jun 05 05:34:57 PM PDT 24
Finished Jun 05 05:34:59 PM PDT 24
Peak memory 204960 kb
Host smart-52d47501-7b35-4f75-b4bb-08962d7aad9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570141922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.570141922
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1562372533
Short name T332
Test name
Test status
Simulation time 949707240 ps
CPU time 4.89 seconds
Started Jun 05 05:34:51 PM PDT 24
Finished Jun 05 05:34:57 PM PDT 24
Peak memory 224628 kb
Host smart-0daaa6b0-d7d6-4752-a665-7f0fdf52e095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562372533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1562372533
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1215005891
Short name T939
Test name
Test status
Simulation time 20238294 ps
CPU time 0.85 seconds
Started Jun 05 05:34:46 PM PDT 24
Finished Jun 05 05:34:48 PM PDT 24
Peak memory 207072 kb
Host smart-607527be-2445-4288-a22f-8f3e9c1560be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215005891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1215005891
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2843995341
Short name T361
Test name
Test status
Simulation time 50870941657 ps
CPU time 109.93 seconds
Started Jun 05 05:34:49 PM PDT 24
Finished Jun 05 05:36:39 PM PDT 24
Peak memory 249308 kb
Host smart-c0118c30-5e15-4988-ae8e-3241989f1dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843995341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2843995341
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2185173736
Short name T35
Test name
Test status
Simulation time 17698587485 ps
CPU time 81.02 seconds
Started Jun 05 05:34:50 PM PDT 24
Finished Jun 05 05:36:11 PM PDT 24
Peak memory 249336 kb
Host smart-f0f78777-da27-494e-9ff0-97be23213152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185173736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2185173736
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.4214185718
Short name T778
Test name
Test status
Simulation time 184173244159 ps
CPU time 213.1 seconds
Started Jun 05 05:34:51 PM PDT 24
Finished Jun 05 05:38:25 PM PDT 24
Peak memory 257520 kb
Host smart-5ab08c08-71da-4ef4-b4a0-cb98dc1baa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214185718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.4214185718
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3342047409
Short name T275
Test name
Test status
Simulation time 4432631629 ps
CPU time 12.94 seconds
Started Jun 05 05:34:49 PM PDT 24
Finished Jun 05 05:35:02 PM PDT 24
Peak memory 224748 kb
Host smart-64568600-e84b-4f94-b506-982f271963b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342047409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3342047409
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2883893180
Short name T421
Test name
Test status
Simulation time 443160686 ps
CPU time 7.02 seconds
Started Jun 05 05:34:50 PM PDT 24
Finished Jun 05 05:34:57 PM PDT 24
Peak memory 232864 kb
Host smart-d7479af7-8802-4665-90c3-c969c97d3e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883893180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2883893180
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.451974333
Short name T912
Test name
Test status
Simulation time 4419571631 ps
CPU time 44.85 seconds
Started Jun 05 05:34:49 PM PDT 24
Finished Jun 05 05:35:35 PM PDT 24
Peak memory 240784 kb
Host smart-b1ba797d-6237-41b7-b016-9a083558e82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451974333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.451974333
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3356039543
Short name T245
Test name
Test status
Simulation time 18346556538 ps
CPU time 13.18 seconds
Started Jun 05 05:34:44 PM PDT 24
Finished Jun 05 05:34:58 PM PDT 24
Peak memory 232852 kb
Host smart-56f9722c-7a75-4a7b-834f-218e8512bdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356039543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3356039543
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1023174654
Short name T39
Test name
Test status
Simulation time 211793566 ps
CPU time 3.25 seconds
Started Jun 05 05:34:47 PM PDT 24
Finished Jun 05 05:34:51 PM PDT 24
Peak memory 232868 kb
Host smart-7a1ee227-7ec0-47b2-80f8-ccce1f30794f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023174654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1023174654
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3602831456
Short name T82
Test name
Test status
Simulation time 584977904 ps
CPU time 4.9 seconds
Started Jun 05 05:34:48 PM PDT 24
Finished Jun 05 05:34:53 PM PDT 24
Peak memory 220356 kb
Host smart-8d3b15a8-0918-48ae-9e8e-92f681dde0fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3602831456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3602831456
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1348049927
Short name T50
Test name
Test status
Simulation time 149628165 ps
CPU time 1.06 seconds
Started Jun 05 05:34:59 PM PDT 24
Finished Jun 05 05:35:00 PM PDT 24
Peak memory 235200 kb
Host smart-ef92f969-bdee-449e-9b5b-7f5af7bd2d02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348049927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1348049927
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2196774943
Short name T367
Test name
Test status
Simulation time 60920118 ps
CPU time 1.11 seconds
Started Jun 05 05:34:52 PM PDT 24
Finished Jun 05 05:34:54 PM PDT 24
Peak memory 207172 kb
Host smart-4ffedb0f-9fec-4eb9-9be9-162b0a43ecc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196774943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2196774943
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4100654142
Short name T458
Test name
Test status
Simulation time 10340964183 ps
CPU time 17.98 seconds
Started Jun 05 05:34:47 PM PDT 24
Finished Jun 05 05:35:06 PM PDT 24
Peak memory 216536 kb
Host smart-50f7c00f-1a0e-4355-aae0-7ab2cf278ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100654142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4100654142
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2589604440
Short name T372
Test name
Test status
Simulation time 6901270140 ps
CPU time 13.33 seconds
Started Jun 05 05:34:43 PM PDT 24
Finished Jun 05 05:34:57 PM PDT 24
Peak memory 216528 kb
Host smart-80deef22-7962-4a4e-891a-6261b6042f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589604440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2589604440
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2934280033
Short name T584
Test name
Test status
Simulation time 65258611 ps
CPU time 0.67 seconds
Started Jun 05 05:34:45 PM PDT 24
Finished Jun 05 05:34:46 PM PDT 24
Peak memory 205748 kb
Host smart-d758e6c6-fbbf-490c-8353-99a3332c2c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934280033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2934280033
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2957426664
Short name T707
Test name
Test status
Simulation time 24805603 ps
CPU time 0.79 seconds
Started Jun 05 05:34:47 PM PDT 24
Finished Jun 05 05:34:48 PM PDT 24
Peak memory 205984 kb
Host smart-8931f298-bfa0-4985-8538-a4ce592bb69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957426664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2957426664
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3335505887
Short name T161
Test name
Test status
Simulation time 456001404 ps
CPU time 4.95 seconds
Started Jun 05 05:34:53 PM PDT 24
Finished Jun 05 05:34:58 PM PDT 24
Peak memory 230268 kb
Host smart-e436facd-28d5-4d8d-bbda-ba2dee99e363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335505887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3335505887
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2625548125
Short name T570
Test name
Test status
Simulation time 14536497 ps
CPU time 0.74 seconds
Started Jun 05 05:36:06 PM PDT 24
Finished Jun 05 05:36:07 PM PDT 24
Peak memory 205560 kb
Host smart-dbae8112-ae3e-4713-8889-dc1316a9a802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625548125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2625548125
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3200143309
Short name T147
Test name
Test status
Simulation time 1160327794 ps
CPU time 4.64 seconds
Started Jun 05 05:35:56 PM PDT 24
Finished Jun 05 05:36:01 PM PDT 24
Peak memory 232888 kb
Host smart-22b66746-aae2-426a-9070-bf43f9c6f45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200143309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3200143309
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3482657678
Short name T392
Test name
Test status
Simulation time 45501210 ps
CPU time 0.73 seconds
Started Jun 05 05:35:59 PM PDT 24
Finished Jun 05 05:36:00 PM PDT 24
Peak memory 205780 kb
Host smart-c841ea9e-d157-4e13-bce0-1092218f47cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482657678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3482657678
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.561169062
Short name T156
Test name
Test status
Simulation time 10249315297 ps
CPU time 87.31 seconds
Started Jun 05 05:36:05 PM PDT 24
Finished Jun 05 05:37:33 PM PDT 24
Peak memory 249284 kb
Host smart-3abd3037-3058-4a37-906d-44699fb2a45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561169062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.561169062
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3707362337
Short name T951
Test name
Test status
Simulation time 156993028 ps
CPU time 6.29 seconds
Started Jun 05 05:35:58 PM PDT 24
Finished Jun 05 05:36:05 PM PDT 24
Peak memory 239668 kb
Host smart-18fd8be9-5efb-4f71-a2b9-8b44e5038310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707362337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3707362337
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1177039182
Short name T8
Test name
Test status
Simulation time 104077899 ps
CPU time 2.14 seconds
Started Jun 05 05:35:57 PM PDT 24
Finished Jun 05 05:36:00 PM PDT 24
Peak memory 232608 kb
Host smart-9a3e5554-8401-4cb7-9081-7f0ea8eabf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177039182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1177039182
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.4094790104
Short name T545
Test name
Test status
Simulation time 4723144651 ps
CPU time 8.24 seconds
Started Jun 05 05:35:58 PM PDT 24
Finished Jun 05 05:36:07 PM PDT 24
Peak memory 232872 kb
Host smart-ea09cdaa-e08d-4eec-85a3-d15807bdda76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094790104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.4094790104
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2835151075
Short name T872
Test name
Test status
Simulation time 10545650594 ps
CPU time 8.86 seconds
Started Jun 05 05:35:56 PM PDT 24
Finished Jun 05 05:36:05 PM PDT 24
Peak memory 224724 kb
Host smart-945abcb9-836b-4be3-b867-72276faa680b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835151075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2835151075
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2092564425
Short name T832
Test name
Test status
Simulation time 1698622339 ps
CPU time 6.34 seconds
Started Jun 05 05:35:57 PM PDT 24
Finished Jun 05 05:36:03 PM PDT 24
Peak memory 220604 kb
Host smart-0d50415b-2364-440e-b3ed-480196c97d8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2092564425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2092564425
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.4152485013
Short name T295
Test name
Test status
Simulation time 4163380029 ps
CPU time 23 seconds
Started Jun 05 05:35:56 PM PDT 24
Finished Jun 05 05:36:19 PM PDT 24
Peak memory 216532 kb
Host smart-9b3595e1-c36a-4de3-a7cc-6c1298417b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152485013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4152485013
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2515141220
Short name T811
Test name
Test status
Simulation time 798582979 ps
CPU time 5.62 seconds
Started Jun 05 05:35:57 PM PDT 24
Finished Jun 05 05:36:03 PM PDT 24
Peak memory 216428 kb
Host smart-67bf2d3e-fd2e-479f-ae7f-cce896edf07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515141220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2515141220
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.655099929
Short name T10
Test name
Test status
Simulation time 13100956 ps
CPU time 0.74 seconds
Started Jun 05 05:35:56 PM PDT 24
Finished Jun 05 05:35:57 PM PDT 24
Peak memory 205748 kb
Host smart-8042f5d3-e709-4f29-b630-ba5c52a49be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655099929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.655099929
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.616677625
Short name T538
Test name
Test status
Simulation time 47272070 ps
CPU time 0.83 seconds
Started Jun 05 05:35:56 PM PDT 24
Finished Jun 05 05:35:57 PM PDT 24
Peak memory 206004 kb
Host smart-ee1da742-0135-476f-bf57-c2ab48a8e306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616677625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.616677625
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3403520620
Short name T604
Test name
Test status
Simulation time 44615240303 ps
CPU time 33.94 seconds
Started Jun 05 05:35:57 PM PDT 24
Finished Jun 05 05:36:31 PM PDT 24
Peak memory 232948 kb
Host smart-5c12fc34-70da-4fc0-893b-adc5295a4e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403520620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3403520620
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.413970695
Short name T41
Test name
Test status
Simulation time 34690896 ps
CPU time 0.69 seconds
Started Jun 05 05:36:11 PM PDT 24
Finished Jun 05 05:36:12 PM PDT 24
Peak memory 205568 kb
Host smart-354a6a37-93e4-44c4-b43b-f6da7bb038f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413970695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.413970695
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3905380678
Short name T385
Test name
Test status
Simulation time 562007568 ps
CPU time 2.7 seconds
Started Jun 05 05:36:08 PM PDT 24
Finished Jun 05 05:36:11 PM PDT 24
Peak memory 224632 kb
Host smart-94ce78ee-da54-487d-9ee1-ec14067c41ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905380678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3905380678
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2757505219
Short name T389
Test name
Test status
Simulation time 27446091 ps
CPU time 0.76 seconds
Started Jun 05 05:36:07 PM PDT 24
Finished Jun 05 05:36:08 PM PDT 24
Peak memory 207020 kb
Host smart-bab7114e-2563-4bbc-bcc8-5bae03d2be9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757505219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2757505219
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.564296040
Short name T174
Test name
Test status
Simulation time 17213442008 ps
CPU time 64.2 seconds
Started Jun 05 05:36:06 PM PDT 24
Finished Jun 05 05:37:11 PM PDT 24
Peak memory 237388 kb
Host smart-b4604265-f3b8-4e14-a1ee-a794584b77a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564296040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.564296040
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.553977211
Short name T200
Test name
Test status
Simulation time 2852636263 ps
CPU time 63.43 seconds
Started Jun 05 05:36:12 PM PDT 24
Finished Jun 05 05:37:16 PM PDT 24
Peak memory 249540 kb
Host smart-3609bc28-cbe5-4de3-a06e-2dbaa775ed34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553977211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.553977211
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2522594682
Short name T783
Test name
Test status
Simulation time 3140231984 ps
CPU time 21.21 seconds
Started Jun 05 05:36:15 PM PDT 24
Finished Jun 05 05:36:37 PM PDT 24
Peak memory 217996 kb
Host smart-ffde15a3-5132-4f28-8698-28aded8b078e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522594682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2522594682
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.776041274
Short name T366
Test name
Test status
Simulation time 349971226 ps
CPU time 4.98 seconds
Started Jun 05 05:36:05 PM PDT 24
Finished Jun 05 05:36:11 PM PDT 24
Peak memory 232820 kb
Host smart-ebd12552-277e-4010-adad-a1e927e98d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776041274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.776041274
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1135481680
Short name T384
Test name
Test status
Simulation time 339136560 ps
CPU time 2.69 seconds
Started Jun 05 05:36:05 PM PDT 24
Finished Jun 05 05:36:08 PM PDT 24
Peak memory 224596 kb
Host smart-96011938-e5dc-49aa-ad05-bc2f2dc06b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135481680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1135481680
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1129513279
Short name T722
Test name
Test status
Simulation time 3743482207 ps
CPU time 40.74 seconds
Started Jun 05 05:36:05 PM PDT 24
Finished Jun 05 05:36:46 PM PDT 24
Peak memory 232836 kb
Host smart-6954cee5-f45f-4c72-98f3-6060217b2200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129513279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1129513279
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2160791750
Short name T519
Test name
Test status
Simulation time 33541024 ps
CPU time 2.29 seconds
Started Jun 05 05:36:04 PM PDT 24
Finished Jun 05 05:36:07 PM PDT 24
Peak memory 232816 kb
Host smart-aaf977bf-67d1-4772-85d8-4979a0dc6209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160791750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2160791750
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1368868130
Short name T948
Test name
Test status
Simulation time 33015087977 ps
CPU time 22.39 seconds
Started Jun 05 05:36:06 PM PDT 24
Finished Jun 05 05:36:29 PM PDT 24
Peak memory 224740 kb
Host smart-093094ae-49cf-4ac3-9215-5e969b54f6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368868130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1368868130
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.574129631
Short name T129
Test name
Test status
Simulation time 322872903 ps
CPU time 4.03 seconds
Started Jun 05 05:36:04 PM PDT 24
Finished Jun 05 05:36:09 PM PDT 24
Peak memory 219152 kb
Host smart-63cc609d-a656-41aa-a18b-7d886046f1c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=574129631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.574129631
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1576484357
Short name T142
Test name
Test status
Simulation time 44182067429 ps
CPU time 139.05 seconds
Started Jun 05 05:36:13 PM PDT 24
Finished Jun 05 05:38:32 PM PDT 24
Peak memory 249460 kb
Host smart-25a756f1-018b-45d0-adc9-85bdda990876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576484357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1576484357
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2518764514
Short name T743
Test name
Test status
Simulation time 6659833719 ps
CPU time 28.49 seconds
Started Jun 05 05:36:05 PM PDT 24
Finished Jun 05 05:36:35 PM PDT 24
Peak memory 216536 kb
Host smart-f8a15f79-f82d-4dfb-b125-7b37b5c38dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518764514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2518764514
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2918066952
Short name T876
Test name
Test status
Simulation time 996152790 ps
CPU time 4.39 seconds
Started Jun 05 05:36:06 PM PDT 24
Finished Jun 05 05:36:11 PM PDT 24
Peak memory 216384 kb
Host smart-ac6905d4-d449-4192-9427-a818b989bb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918066952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2918066952
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2719909751
Short name T810
Test name
Test status
Simulation time 129081704 ps
CPU time 0.84 seconds
Started Jun 05 05:36:06 PM PDT 24
Finished Jun 05 05:36:08 PM PDT 24
Peak memory 206456 kb
Host smart-a65ff3ce-aa2d-46b5-b0d5-c3c95f388cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719909751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2719909751
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3567728299
Short name T599
Test name
Test status
Simulation time 214990706 ps
CPU time 0.88 seconds
Started Jun 05 05:36:06 PM PDT 24
Finished Jun 05 05:36:07 PM PDT 24
Peak memory 205980 kb
Host smart-c04e318d-5009-43e6-830d-c2f232bc93c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567728299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3567728299
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.644764129
Short name T627
Test name
Test status
Simulation time 865941025 ps
CPU time 7.22 seconds
Started Jun 05 05:36:06 PM PDT 24
Finished Jun 05 05:36:14 PM PDT 24
Peak memory 240976 kb
Host smart-352f411c-db43-477e-8dab-ba58af1ef0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644764129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.644764129
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1402094277
Short name T479
Test name
Test status
Simulation time 45558224 ps
CPU time 0.73 seconds
Started Jun 05 05:36:11 PM PDT 24
Finished Jun 05 05:36:13 PM PDT 24
Peak memory 204972 kb
Host smart-2a3f4c75-0d91-4e97-9e45-8dac198ab6ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402094277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1402094277
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1736445369
Short name T674
Test name
Test status
Simulation time 719047275 ps
CPU time 3.49 seconds
Started Jun 05 05:36:15 PM PDT 24
Finished Jun 05 05:36:19 PM PDT 24
Peak memory 232828 kb
Host smart-9b394146-f3d2-4f31-882b-3398b7cdce88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736445369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1736445369
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4033418362
Short name T561
Test name
Test status
Simulation time 50998624 ps
CPU time 0.82 seconds
Started Jun 05 05:36:12 PM PDT 24
Finished Jun 05 05:36:13 PM PDT 24
Peak memory 206728 kb
Host smart-5258a93b-a813-4eac-b9df-6ea19ef25a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033418362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4033418362
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.704469028
Short name T220
Test name
Test status
Simulation time 3554229298 ps
CPU time 81.54 seconds
Started Jun 05 05:36:12 PM PDT 24
Finished Jun 05 05:37:34 PM PDT 24
Peak memory 256908 kb
Host smart-d76f6428-0e4c-48ea-8957-4cfd947c2bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704469028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.704469028
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2681841219
Short name T125
Test name
Test status
Simulation time 7152070020 ps
CPU time 50.12 seconds
Started Jun 05 05:36:15 PM PDT 24
Finished Jun 05 05:37:06 PM PDT 24
Peak memory 256728 kb
Host smart-3d2de70c-8072-464e-b2ba-34dffa61c03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681841219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2681841219
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2716774237
Short name T269
Test name
Test status
Simulation time 14732410245 ps
CPU time 178.27 seconds
Started Jun 05 05:36:14 PM PDT 24
Finished Jun 05 05:39:13 PM PDT 24
Peak memory 251536 kb
Host smart-b110c16c-55da-4bd2-87e0-769a47b8a845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716774237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2716774237
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1893649332
Short name T649
Test name
Test status
Simulation time 5627761025 ps
CPU time 21.25 seconds
Started Jun 05 05:36:13 PM PDT 24
Finished Jun 05 05:36:34 PM PDT 24
Peak memory 224660 kb
Host smart-0cb2d665-637d-42f1-98ac-78938b1a5325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893649332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1893649332
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1710464996
Short name T306
Test name
Test status
Simulation time 207440027 ps
CPU time 2.37 seconds
Started Jun 05 05:36:15 PM PDT 24
Finished Jun 05 05:36:18 PM PDT 24
Peak memory 223972 kb
Host smart-873bd2e0-a0be-475f-b2d3-84beb4faf2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710464996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1710464996
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1916013080
Short name T305
Test name
Test status
Simulation time 2904517667 ps
CPU time 11.27 seconds
Started Jun 05 05:36:14 PM PDT 24
Finished Jun 05 05:36:26 PM PDT 24
Peak memory 232816 kb
Host smart-38e371e6-5190-4db7-9860-244e2de46310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916013080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1916013080
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3732064486
Short name T76
Test name
Test status
Simulation time 8674064384 ps
CPU time 6.16 seconds
Started Jun 05 05:36:14 PM PDT 24
Finished Jun 05 05:36:21 PM PDT 24
Peak memory 228100 kb
Host smart-7a3ef7c7-6f70-4beb-b889-6df42c1118e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732064486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3732064486
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.314073441
Short name T375
Test name
Test status
Simulation time 242319316 ps
CPU time 2.25 seconds
Started Jun 05 05:36:13 PM PDT 24
Finished Jun 05 05:36:16 PM PDT 24
Peak memory 218744 kb
Host smart-bf683f72-7495-453c-a625-0fc07f9c3e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314073441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.314073441
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1015431462
Short name T311
Test name
Test status
Simulation time 1820623008 ps
CPU time 16.39 seconds
Started Jun 05 05:36:13 PM PDT 24
Finished Jun 05 05:36:30 PM PDT 24
Peak memory 219516 kb
Host smart-04a9df21-392d-4e2c-8072-78f0748b9ba9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1015431462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1015431462
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3291897390
Short name T239
Test name
Test status
Simulation time 180178027157 ps
CPU time 328.45 seconds
Started Jun 05 05:36:15 PM PDT 24
Finished Jun 05 05:41:44 PM PDT 24
Peak memory 267576 kb
Host smart-8b2f2d09-b63a-4ea7-9cc6-fb12fafc7fc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291897390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3291897390
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3681102326
Short name T567
Test name
Test status
Simulation time 9534196754 ps
CPU time 26.07 seconds
Started Jun 05 05:36:13 PM PDT 24
Finished Jun 05 05:36:40 PM PDT 24
Peak memory 216604 kb
Host smart-ed4a3cf4-38f0-442e-967a-ed51c03dcd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681102326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3681102326
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1323071386
Short name T462
Test name
Test status
Simulation time 10845992844 ps
CPU time 8.44 seconds
Started Jun 05 05:36:12 PM PDT 24
Finished Jun 05 05:36:21 PM PDT 24
Peak memory 216500 kb
Host smart-96c1aac7-7322-41de-8e0f-176109741de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323071386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1323071386
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1228473257
Short name T612
Test name
Test status
Simulation time 31804274 ps
CPU time 0.95 seconds
Started Jun 05 05:36:20 PM PDT 24
Finished Jun 05 05:36:21 PM PDT 24
Peak memory 206960 kb
Host smart-38dd3d03-092a-420f-813b-5f743f870fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228473257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1228473257
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3374762856
Short name T914
Test name
Test status
Simulation time 206179358 ps
CPU time 0.93 seconds
Started Jun 05 05:36:12 PM PDT 24
Finished Jun 05 05:36:13 PM PDT 24
Peak memory 207040 kb
Host smart-41a3bb2c-dbad-4ccb-b0dc-edc11628139e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374762856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3374762856
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2934725325
Short name T38
Test name
Test status
Simulation time 1798297596 ps
CPU time 7.48 seconds
Started Jun 05 05:36:14 PM PDT 24
Finished Jun 05 05:36:22 PM PDT 24
Peak memory 240752 kb
Host smart-4c9149bb-24cf-44c2-8793-1ddb03bb430a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934725325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2934725325
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3506009860
Short name T610
Test name
Test status
Simulation time 25716248 ps
CPU time 0.72 seconds
Started Jun 05 05:36:21 PM PDT 24
Finished Jun 05 05:36:23 PM PDT 24
Peak memory 204984 kb
Host smart-f117c5bd-ccc3-4dab-a943-6432808626a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506009860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3506009860
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.554228391
Short name T439
Test name
Test status
Simulation time 125273217 ps
CPU time 2.44 seconds
Started Jun 05 05:36:22 PM PDT 24
Finished Jun 05 05:36:25 PM PDT 24
Peak memory 232884 kb
Host smart-d6b63e7f-1180-4b7a-96bb-978c16d4897a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554228391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.554228391
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3407622763
Short name T694
Test name
Test status
Simulation time 18308261 ps
CPU time 0.81 seconds
Started Jun 05 05:36:13 PM PDT 24
Finished Jun 05 05:36:14 PM PDT 24
Peak memory 206760 kb
Host smart-23ea1ba4-b081-44c1-a17a-246ff0fe14f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407622763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3407622763
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2997625895
Short name T932
Test name
Test status
Simulation time 13222834079 ps
CPU time 61.62 seconds
Started Jun 05 05:36:23 PM PDT 24
Finished Jun 05 05:37:26 PM PDT 24
Peak memory 253084 kb
Host smart-e46e394d-8538-4536-9f1c-487ddc6b7da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997625895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2997625895
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1375662031
Short name T902
Test name
Test status
Simulation time 17067311797 ps
CPU time 62.76 seconds
Started Jun 05 05:36:23 PM PDT 24
Finished Jun 05 05:37:26 PM PDT 24
Peak memory 241180 kb
Host smart-b23aa508-f8f6-4fd6-95ba-5dc0518e6fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375662031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1375662031
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2161038623
Short name T210
Test name
Test status
Simulation time 46617394907 ps
CPU time 456.9 seconds
Started Jun 05 05:36:22 PM PDT 24
Finished Jun 05 05:44:00 PM PDT 24
Peak memory 249360 kb
Host smart-d0d4e2d3-3111-4be7-a50f-4dffcc43d3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161038623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2161038623
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3526020442
Short name T77
Test name
Test status
Simulation time 8661613192 ps
CPU time 22.43 seconds
Started Jun 05 05:36:21 PM PDT 24
Finished Jun 05 05:36:44 PM PDT 24
Peak memory 224644 kb
Host smart-a5f4e503-c3e8-438e-b801-96d234acb8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526020442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3526020442
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1638006682
Short name T621
Test name
Test status
Simulation time 35041902934 ps
CPU time 38.23 seconds
Started Jun 05 05:36:23 PM PDT 24
Finished Jun 05 05:37:02 PM PDT 24
Peak memory 232836 kb
Host smart-07cc5685-e3af-4026-9940-983d7004fa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638006682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1638006682
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.456163027
Short name T212
Test name
Test status
Simulation time 1006352747 ps
CPU time 2.52 seconds
Started Jun 05 05:36:23 PM PDT 24
Finished Jun 05 05:36:26 PM PDT 24
Peak memory 224676 kb
Host smart-8779c551-a724-461e-9dc7-d4725cf1b8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456163027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.456163027
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2224896527
Short name T435
Test name
Test status
Simulation time 32873321 ps
CPU time 2.46 seconds
Started Jun 05 05:36:21 PM PDT 24
Finished Jun 05 05:36:25 PM PDT 24
Peak memory 232680 kb
Host smart-95b42c98-3b43-4a20-aa92-9c785519f5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224896527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2224896527
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2772921094
Short name T724
Test name
Test status
Simulation time 1091481725 ps
CPU time 13.62 seconds
Started Jun 05 05:36:21 PM PDT 24
Finished Jun 05 05:36:36 PM PDT 24
Peak memory 219404 kb
Host smart-1275ebd7-7e23-4d0f-a26c-b396bc2bbf06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2772921094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2772921094
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.900652617
Short name T683
Test name
Test status
Simulation time 14255764402 ps
CPU time 39.08 seconds
Started Jun 05 05:36:19 PM PDT 24
Finished Jun 05 05:36:59 PM PDT 24
Peak memory 216444 kb
Host smart-047558eb-82fc-4150-911b-8144d5ec8bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900652617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.900652617
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.886792254
Short name T66
Test name
Test status
Simulation time 4252786024 ps
CPU time 2.18 seconds
Started Jun 05 05:36:14 PM PDT 24
Finished Jun 05 05:36:17 PM PDT 24
Peak memory 216276 kb
Host smart-b18bfe94-fb2a-4838-9279-d9c49a69f09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886792254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.886792254
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.627350040
Short name T741
Test name
Test status
Simulation time 1683304998 ps
CPU time 2.49 seconds
Started Jun 05 05:36:21 PM PDT 24
Finished Jun 05 05:36:25 PM PDT 24
Peak memory 216424 kb
Host smart-216b895a-b46c-4737-a39b-7524738304da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627350040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.627350040
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3321858757
Short name T410
Test name
Test status
Simulation time 239568252 ps
CPU time 0.92 seconds
Started Jun 05 05:36:22 PM PDT 24
Finished Jun 05 05:36:23 PM PDT 24
Peak memory 205936 kb
Host smart-f3bae20e-f7cf-46a2-8aee-0cc0a414fd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321858757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3321858757
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1522019665
Short name T822
Test name
Test status
Simulation time 1729105760 ps
CPU time 5.42 seconds
Started Jun 05 05:36:22 PM PDT 24
Finished Jun 05 05:36:28 PM PDT 24
Peak memory 224628 kb
Host smart-37456a7d-aabf-43da-912f-b186892450e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522019665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1522019665
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2063500758
Short name T708
Test name
Test status
Simulation time 106161765 ps
CPU time 0.69 seconds
Started Jun 05 05:36:51 PM PDT 24
Finished Jun 05 05:36:52 PM PDT 24
Peak memory 205852 kb
Host smart-463cd916-7d1c-4017-8160-09beef64bbd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063500758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2063500758
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2855709341
Short name T430
Test name
Test status
Simulation time 495495365 ps
CPU time 6.7 seconds
Started Jun 05 05:36:21 PM PDT 24
Finished Jun 05 05:36:29 PM PDT 24
Peak memory 232756 kb
Host smart-8ba26fd4-6898-440a-a49a-4a3fc386cb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855709341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2855709341
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2809839806
Short name T742
Test name
Test status
Simulation time 40794805 ps
CPU time 0.72 seconds
Started Jun 05 05:36:23 PM PDT 24
Finished Jun 05 05:36:24 PM PDT 24
Peak memory 206080 kb
Host smart-3f2592ef-a4d8-48f1-bede-ea37738953cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809839806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2809839806
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.4214937431
Short name T316
Test name
Test status
Simulation time 32337558 ps
CPU time 0.74 seconds
Started Jun 05 05:36:21 PM PDT 24
Finished Jun 05 05:36:23 PM PDT 24
Peak memory 216080 kb
Host smart-2db9bbbd-43a6-474b-8bae-116535e05709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214937431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4214937431
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3868377747
Short name T176
Test name
Test status
Simulation time 3423686581 ps
CPU time 23.33 seconds
Started Jun 05 05:36:25 PM PDT 24
Finished Jun 05 05:36:49 PM PDT 24
Peak memory 251432 kb
Host smart-54a5b602-6bff-434c-b695-e911e7d99229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868377747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3868377747
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3142725101
Short name T616
Test name
Test status
Simulation time 3527005143 ps
CPU time 52.01 seconds
Started Jun 05 05:36:50 PM PDT 24
Finished Jun 05 05:37:42 PM PDT 24
Peak memory 244516 kb
Host smart-635abbc5-7ea1-4835-aac2-2a061a4213eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142725101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3142725101
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3819356152
Short name T454
Test name
Test status
Simulation time 3947496301 ps
CPU time 5.65 seconds
Started Jun 05 05:36:25 PM PDT 24
Finished Jun 05 05:36:31 PM PDT 24
Peak memory 224712 kb
Host smart-17a5a8ea-9d30-403c-bc8a-5514782e5ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819356152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3819356152
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2013325938
Short name T585
Test name
Test status
Simulation time 1790701802 ps
CPU time 19.96 seconds
Started Jun 05 05:36:25 PM PDT 24
Finished Jun 05 05:36:46 PM PDT 24
Peak memory 232808 kb
Host smart-50001a8b-10c0-49d3-9d83-cb11947d1b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013325938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2013325938
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.544431822
Short name T448
Test name
Test status
Simulation time 776939190 ps
CPU time 6.73 seconds
Started Jun 05 05:36:25 PM PDT 24
Finished Jun 05 05:36:32 PM PDT 24
Peak memory 232844 kb
Host smart-86ad50a2-529d-4615-8bc9-36fbba4b7e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544431822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.544431822
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2318188900
Short name T29
Test name
Test status
Simulation time 3061092471 ps
CPU time 12.39 seconds
Started Jun 05 05:36:25 PM PDT 24
Finished Jun 05 05:36:37 PM PDT 24
Peak memory 249316 kb
Host smart-a3a1b197-f27d-4b60-a45e-c9b249399359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318188900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2318188900
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3672756134
Short name T596
Test name
Test status
Simulation time 45911331443 ps
CPU time 33.62 seconds
Started Jun 05 05:36:25 PM PDT 24
Finished Jun 05 05:36:59 PM PDT 24
Peak memory 233952 kb
Host smart-445d2fbb-259c-4328-b56a-d418bb0ebc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672756134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3672756134
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2497800570
Short name T896
Test name
Test status
Simulation time 495184635 ps
CPU time 3.9 seconds
Started Jun 05 05:36:26 PM PDT 24
Finished Jun 05 05:36:30 PM PDT 24
Peak memory 222960 kb
Host smart-762c40ac-8c40-413a-b7b5-8b2456c4d6a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2497800570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2497800570
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1197897776
Short name T827
Test name
Test status
Simulation time 9098125950 ps
CPU time 186.14 seconds
Started Jun 05 05:36:52 PM PDT 24
Finished Jun 05 05:39:59 PM PDT 24
Peak memory 261800 kb
Host smart-e0dad1a2-6e96-420c-8a01-a0bce73a3b8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197897776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1197897776
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1353868787
Short name T809
Test name
Test status
Simulation time 1121438047 ps
CPU time 14.2 seconds
Started Jun 05 05:36:22 PM PDT 24
Finished Jun 05 05:36:37 PM PDT 24
Peak memory 216588 kb
Host smart-b60d3dd4-3ce1-492a-8977-002eeb324531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353868787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1353868787
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2451509681
Short name T293
Test name
Test status
Simulation time 41690623069 ps
CPU time 16.58 seconds
Started Jun 05 05:36:21 PM PDT 24
Finished Jun 05 05:36:38 PM PDT 24
Peak memory 216460 kb
Host smart-d55f29ef-2334-4fdb-b131-8054c1a86b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451509681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2451509681
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3298986540
Short name T400
Test name
Test status
Simulation time 134026002 ps
CPU time 4.02 seconds
Started Jun 05 05:36:23 PM PDT 24
Finished Jun 05 05:36:28 PM PDT 24
Peak memory 216364 kb
Host smart-569cc7f7-6139-4637-b6da-bd56b93c3917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298986540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3298986540
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2446893332
Short name T815
Test name
Test status
Simulation time 141473367 ps
CPU time 0.88 seconds
Started Jun 05 05:36:21 PM PDT 24
Finished Jun 05 05:36:23 PM PDT 24
Peak memory 206032 kb
Host smart-b2519c64-cad6-4c6f-a3eb-4f48f0d28311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446893332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2446893332
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.4181408767
Short name T835
Test name
Test status
Simulation time 837667650 ps
CPU time 7.52 seconds
Started Jun 05 05:36:24 PM PDT 24
Finished Jun 05 05:36:32 PM PDT 24
Peak memory 232828 kb
Host smart-a8734d49-cdea-4e97-9ab2-8de06564dcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181408767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.4181408767
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3361508523
Short name T526
Test name
Test status
Simulation time 41870392 ps
CPU time 0.72 seconds
Started Jun 05 05:36:55 PM PDT 24
Finished Jun 05 05:36:56 PM PDT 24
Peak memory 205536 kb
Host smart-417f6574-957f-4f6c-b635-f7d9750449ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361508523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3361508523
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3385090979
Short name T437
Test name
Test status
Simulation time 168725139 ps
CPU time 2.46 seconds
Started Jun 05 05:36:54 PM PDT 24
Finished Jun 05 05:36:57 PM PDT 24
Peak memory 224560 kb
Host smart-4762a74e-c39c-4ae2-a86b-def607b265f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385090979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3385090979
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1157198941
Short name T359
Test name
Test status
Simulation time 45167211 ps
CPU time 0.74 seconds
Started Jun 05 05:36:51 PM PDT 24
Finished Jun 05 05:36:52 PM PDT 24
Peak memory 205760 kb
Host smart-2d5b7415-1cb8-4b16-91c2-ba5720b94251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157198941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1157198941
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1673906581
Short name T801
Test name
Test status
Simulation time 18936924120 ps
CPU time 138.34 seconds
Started Jun 05 05:36:54 PM PDT 24
Finished Jun 05 05:39:13 PM PDT 24
Peak memory 255596 kb
Host smart-4f8836d0-5cd1-423e-ab2a-3c168a476dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673906581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1673906581
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2595234826
Short name T238
Test name
Test status
Simulation time 5359085478 ps
CPU time 111.24 seconds
Started Jun 05 05:36:51 PM PDT 24
Finished Jun 05 05:38:43 PM PDT 24
Peak memory 256188 kb
Host smart-62ea36bd-7901-4c9a-af7a-a0206214eacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595234826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2595234826
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2606701769
Short name T418
Test name
Test status
Simulation time 8901006911 ps
CPU time 36.55 seconds
Started Jun 05 05:36:54 PM PDT 24
Finished Jun 05 05:37:31 PM PDT 24
Peak memory 233924 kb
Host smart-f5de84c3-13f6-401f-bd59-b382cf9190ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606701769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2606701769
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.282859548
Short name T347
Test name
Test status
Simulation time 287823994 ps
CPU time 3.94 seconds
Started Jun 05 05:36:57 PM PDT 24
Finished Jun 05 05:37:02 PM PDT 24
Peak memory 232844 kb
Host smart-34e794cf-78b4-4e58-83c1-51ea6dd65740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282859548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.282859548
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3167203820
Short name T263
Test name
Test status
Simulation time 2060038942 ps
CPU time 13.59 seconds
Started Jun 05 05:36:55 PM PDT 24
Finished Jun 05 05:37:09 PM PDT 24
Peak memory 249224 kb
Host smart-2f4f92e5-825d-4c63-9ddd-8f2fdf35fdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167203820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3167203820
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1459990740
Short name T249
Test name
Test status
Simulation time 639741383 ps
CPU time 3.13 seconds
Started Jun 05 05:36:51 PM PDT 24
Finished Jun 05 05:36:54 PM PDT 24
Peak memory 218696 kb
Host smart-0e77d9d2-3132-4814-872d-a90f2b910b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459990740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1459990740
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2814544328
Short name T415
Test name
Test status
Simulation time 155808101 ps
CPU time 2.44 seconds
Started Jun 05 05:36:53 PM PDT 24
Finished Jun 05 05:36:56 PM PDT 24
Peak memory 227228 kb
Host smart-52a6f599-578a-4d1d-8c33-912dbb40cee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814544328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2814544328
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.347378282
Short name T818
Test name
Test status
Simulation time 5485475298 ps
CPU time 14.24 seconds
Started Jun 05 05:36:58 PM PDT 24
Finished Jun 05 05:37:14 PM PDT 24
Peak memory 218936 kb
Host smart-1a6f40d0-0c14-4e21-b803-5548867f5001
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=347378282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.347378282
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2537024102
Short name T369
Test name
Test status
Simulation time 48454356 ps
CPU time 1.13 seconds
Started Jun 05 05:36:54 PM PDT 24
Finished Jun 05 05:36:56 PM PDT 24
Peak memory 207212 kb
Host smart-86e4d6ae-a016-462b-97ce-d212cae70d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537024102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2537024102
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.481836873
Short name T513
Test name
Test status
Simulation time 956559897 ps
CPU time 9.45 seconds
Started Jun 05 05:36:51 PM PDT 24
Finished Jun 05 05:37:01 PM PDT 24
Peak memory 216424 kb
Host smart-9ade3cf2-1ea4-4702-afa9-cb33ee9c1314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481836873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.481836873
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2071068719
Short name T518
Test name
Test status
Simulation time 3776972274 ps
CPU time 4.26 seconds
Started Jun 05 05:36:52 PM PDT 24
Finished Jun 05 05:36:57 PM PDT 24
Peak memory 216408 kb
Host smart-8deb5b65-bf73-4015-96b9-ca3bfc3f1b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071068719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2071068719
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1445531706
Short name T393
Test name
Test status
Simulation time 36592534 ps
CPU time 1.36 seconds
Started Jun 05 05:36:51 PM PDT 24
Finished Jun 05 05:36:53 PM PDT 24
Peak memory 216448 kb
Host smart-c25ed983-6e68-4934-8af5-1c921f359716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445531706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1445531706
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.4137830339
Short name T388
Test name
Test status
Simulation time 30989242 ps
CPU time 0.77 seconds
Started Jun 05 05:36:51 PM PDT 24
Finished Jun 05 05:36:52 PM PDT 24
Peak memory 205980 kb
Host smart-843bb715-129a-4674-af80-cd99616fd8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137830339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.4137830339
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.472192207
Short name T798
Test name
Test status
Simulation time 140314102 ps
CPU time 3.63 seconds
Started Jun 05 05:36:51 PM PDT 24
Finished Jun 05 05:36:55 PM PDT 24
Peak memory 232844 kb
Host smart-045d9093-e557-4697-8b4f-fb46d941bcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472192207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.472192207
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2913898923
Short name T840
Test name
Test status
Simulation time 35218327 ps
CPU time 0.76 seconds
Started Jun 05 05:36:36 PM PDT 24
Finished Jun 05 05:36:38 PM PDT 24
Peak memory 204992 kb
Host smart-67251fcb-945a-435b-82a9-27ef1ab4f432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913898923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2913898923
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3002630664
Short name T622
Test name
Test status
Simulation time 2923687132 ps
CPU time 13.22 seconds
Started Jun 05 05:36:34 PM PDT 24
Finished Jun 05 05:36:48 PM PDT 24
Peak memory 232948 kb
Host smart-d5aad7bc-98a8-4c6f-8bf0-8e86ffa53d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002630664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3002630664
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1237966413
Short name T303
Test name
Test status
Simulation time 52514181 ps
CPU time 0.77 seconds
Started Jun 05 05:36:52 PM PDT 24
Finished Jun 05 05:36:54 PM PDT 24
Peak memory 206764 kb
Host smart-21162e1c-be43-4657-90a4-938d7385ba21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237966413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1237966413
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1534513639
Short name T732
Test name
Test status
Simulation time 30210792737 ps
CPU time 71.1 seconds
Started Jun 05 05:36:35 PM PDT 24
Finished Jun 05 05:37:47 PM PDT 24
Peak memory 249340 kb
Host smart-bafa764a-4392-45a5-95f9-0422fa9f7b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534513639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1534513639
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2019262462
Short name T213
Test name
Test status
Simulation time 6152285256 ps
CPU time 88.94 seconds
Started Jun 05 05:36:36 PM PDT 24
Finished Jun 05 05:38:06 PM PDT 24
Peak memory 249368 kb
Host smart-cd9bff15-ac34-4d6a-9adb-ce58d61d2f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019262462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2019262462
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1526047225
Short name T221
Test name
Test status
Simulation time 122993741765 ps
CPU time 281.49 seconds
Started Jun 05 05:36:36 PM PDT 24
Finished Jun 05 05:41:18 PM PDT 24
Peak memory 241088 kb
Host smart-62a0af86-6a5c-45b8-ac43-15eb02e63088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526047225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1526047225
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.120023638
Short name T591
Test name
Test status
Simulation time 2383928500 ps
CPU time 20.16 seconds
Started Jun 05 05:36:37 PM PDT 24
Finished Jun 05 05:36:58 PM PDT 24
Peak memory 240744 kb
Host smart-9de92b30-ab50-4b97-8808-9c81760588d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120023638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.120023638
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4266570935
Short name T789
Test name
Test status
Simulation time 2615707534 ps
CPU time 6.2 seconds
Started Jun 05 05:36:36 PM PDT 24
Finished Jun 05 05:36:43 PM PDT 24
Peak memory 224688 kb
Host smart-67fd8c53-e0f4-4059-9f78-2e2253b72e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266570935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4266570935
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2031375863
Short name T897
Test name
Test status
Simulation time 297709931 ps
CPU time 4.33 seconds
Started Jun 05 05:36:36 PM PDT 24
Finished Jun 05 05:36:41 PM PDT 24
Peak memory 224620 kb
Host smart-ac6c67bb-7d8e-4a6d-aa96-defbf2dd7581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031375863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2031375863
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2182600154
Short name T850
Test name
Test status
Simulation time 794824149 ps
CPU time 8.78 seconds
Started Jun 05 05:36:35 PM PDT 24
Finished Jun 05 05:36:44 PM PDT 24
Peak memory 224652 kb
Host smart-012de6dc-8760-415b-8bf7-31110323c17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182600154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2182600154
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3784815066
Short name T425
Test name
Test status
Simulation time 41528833 ps
CPU time 2.49 seconds
Started Jun 05 05:36:39 PM PDT 24
Finished Jun 05 05:36:42 PM PDT 24
Peak memory 224580 kb
Host smart-6ae16f57-9915-4e79-9c2e-9ef6f6ee7cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784815066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3784815066
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2461620206
Short name T609
Test name
Test status
Simulation time 3249948014 ps
CPU time 11.52 seconds
Started Jun 05 05:36:35 PM PDT 24
Finished Jun 05 05:36:47 PM PDT 24
Peak memory 223364 kb
Host smart-984826f4-ff60-449f-95dc-14f92ac7bef7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2461620206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2461620206
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3448524414
Short name T431
Test name
Test status
Simulation time 67150318 ps
CPU time 1.11 seconds
Started Jun 05 05:36:39 PM PDT 24
Finished Jun 05 05:36:41 PM PDT 24
Peak memory 207292 kb
Host smart-9027fb04-ea2e-4947-9f72-95e46086b0c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448524414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3448524414
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3794310192
Short name T420
Test name
Test status
Simulation time 1994722521 ps
CPU time 6.37 seconds
Started Jun 05 05:36:52 PM PDT 24
Finished Jun 05 05:36:59 PM PDT 24
Peak memory 216816 kb
Host smart-eecfb373-45e3-4715-8040-d249c7d45dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794310192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3794310192
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1121889800
Short name T654
Test name
Test status
Simulation time 1856444429 ps
CPU time 5.54 seconds
Started Jun 05 05:36:54 PM PDT 24
Finished Jun 05 05:37:00 PM PDT 24
Peak memory 216448 kb
Host smart-cfccf898-9061-4591-ab29-e5b9893cd915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121889800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1121889800
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.440685051
Short name T226
Test name
Test status
Simulation time 35180637 ps
CPU time 1.12 seconds
Started Jun 05 05:36:35 PM PDT 24
Finished Jun 05 05:36:37 PM PDT 24
Peak memory 208060 kb
Host smart-52057c5d-d275-48e9-ab07-12582aa08b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440685051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.440685051
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4002067583
Short name T717
Test name
Test status
Simulation time 155880776 ps
CPU time 0.95 seconds
Started Jun 05 05:36:54 PM PDT 24
Finished Jun 05 05:36:55 PM PDT 24
Peak memory 206972 kb
Host smart-7db0cac5-2869-4624-8a59-2ffa46adcd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002067583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4002067583
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1261327543
Short name T679
Test name
Test status
Simulation time 858470764 ps
CPU time 7.24 seconds
Started Jun 05 05:36:35 PM PDT 24
Finished Jun 05 05:36:43 PM PDT 24
Peak memory 232828 kb
Host smart-62ad5011-be32-4452-85d8-0a09882bb4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261327543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1261327543
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3730522707
Short name T828
Test name
Test status
Simulation time 45160772 ps
CPU time 0.71 seconds
Started Jun 05 05:36:37 PM PDT 24
Finished Jun 05 05:36:39 PM PDT 24
Peak memory 205728 kb
Host smart-b5698f0e-23f1-49eb-a7aa-15bbb55241a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730522707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3730522707
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.729858335
Short name T346
Test name
Test status
Simulation time 651738009 ps
CPU time 8.57 seconds
Started Jun 05 05:36:36 PM PDT 24
Finished Jun 05 05:36:45 PM PDT 24
Peak memory 224560 kb
Host smart-ef0d8d68-b26e-4b96-9196-b005b850e943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729858335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.729858335
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2735239670
Short name T804
Test name
Test status
Simulation time 33291804 ps
CPU time 0.85 seconds
Started Jun 05 05:36:35 PM PDT 24
Finished Jun 05 05:36:36 PM PDT 24
Peak memory 206792 kb
Host smart-193c28db-cfd4-43db-abd8-6672111c8193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735239670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2735239670
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1214420749
Short name T256
Test name
Test status
Simulation time 82821534440 ps
CPU time 158.42 seconds
Started Jun 05 05:36:32 PM PDT 24
Finished Jun 05 05:39:11 PM PDT 24
Peak memory 250228 kb
Host smart-a6a465fd-0947-4109-b2f4-2b908ec7f51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214420749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1214420749
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3742866225
Short name T492
Test name
Test status
Simulation time 1800191388 ps
CPU time 3.78 seconds
Started Jun 05 05:36:33 PM PDT 24
Finished Jun 05 05:36:37 PM PDT 24
Peak memory 217568 kb
Host smart-b7c800a9-1483-445b-9598-f642718115d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742866225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3742866225
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.830848638
Short name T792
Test name
Test status
Simulation time 29201956085 ps
CPU time 88.18 seconds
Started Jun 05 05:36:35 PM PDT 24
Finished Jun 05 05:38:04 PM PDT 24
Peak memory 249356 kb
Host smart-2acfeb9d-babc-41b9-9e8c-d45d0255ec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830848638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.830848638
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1688722501
Short name T277
Test name
Test status
Simulation time 2735433387 ps
CPU time 15.73 seconds
Started Jun 05 05:36:34 PM PDT 24
Finished Jun 05 05:36:51 PM PDT 24
Peak memory 224664 kb
Host smart-08ba0d7e-0f18-4cfb-957e-f7f4f9799946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688722501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1688722501
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3516588607
Short name T776
Test name
Test status
Simulation time 887220534 ps
CPU time 6.63 seconds
Started Jun 05 05:36:37 PM PDT 24
Finished Jun 05 05:36:45 PM PDT 24
Peak memory 224572 kb
Host smart-f24c8a5f-70a8-4956-b728-fd12b54480e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516588607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3516588607
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2875451786
Short name T509
Test name
Test status
Simulation time 1115046317 ps
CPU time 6.65 seconds
Started Jun 05 05:36:33 PM PDT 24
Finished Jun 05 05:36:40 PM PDT 24
Peak memory 232840 kb
Host smart-5c5a5071-2daf-49c6-bff6-a58369270f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875451786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2875451786
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.343275593
Short name T752
Test name
Test status
Simulation time 3631647823 ps
CPU time 11.18 seconds
Started Jun 05 05:36:35 PM PDT 24
Finished Jun 05 05:36:47 PM PDT 24
Peak memory 224708 kb
Host smart-e1efd05b-92e0-4836-84ac-a7eaf5ab2ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343275593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.343275593
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1653311288
Short name T406
Test name
Test status
Simulation time 14678065284 ps
CPU time 27.97 seconds
Started Jun 05 05:36:37 PM PDT 24
Finished Jun 05 05:37:05 PM PDT 24
Peak memory 240900 kb
Host smart-7f290a4c-038b-4567-b847-6c77a6ae4e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653311288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1653311288
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4283684068
Short name T335
Test name
Test status
Simulation time 211073872 ps
CPU time 4.17 seconds
Started Jun 05 05:36:34 PM PDT 24
Finished Jun 05 05:36:39 PM PDT 24
Peak memory 223100 kb
Host smart-0c663046-dbdd-4bf1-9c3d-2373db14982f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4283684068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4283684068
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.554754926
Short name T117
Test name
Test status
Simulation time 4051327047 ps
CPU time 32.19 seconds
Started Jun 05 05:36:34 PM PDT 24
Finished Jun 05 05:37:07 PM PDT 24
Peak memory 216828 kb
Host smart-0ea4b1c6-3665-4b25-9fa4-c0799f883b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554754926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.554754926
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1707326846
Short name T803
Test name
Test status
Simulation time 3411883945 ps
CPU time 9.68 seconds
Started Jun 05 05:36:34 PM PDT 24
Finished Jun 05 05:36:44 PM PDT 24
Peak memory 216536 kb
Host smart-77c53ce8-69c6-4901-bbf6-9d99442bb8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707326846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1707326846
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3210373848
Short name T358
Test name
Test status
Simulation time 22647281 ps
CPU time 0.68 seconds
Started Jun 05 05:36:34 PM PDT 24
Finished Jun 05 05:36:35 PM PDT 24
Peak memory 205716 kb
Host smart-28635e57-e0ee-437c-83ef-5f64db5ec537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210373848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3210373848
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3923105260
Short name T857
Test name
Test status
Simulation time 64087115 ps
CPU time 0.89 seconds
Started Jun 05 05:36:35 PM PDT 24
Finished Jun 05 05:36:36 PM PDT 24
Peak memory 205988 kb
Host smart-62350a3f-c58b-4888-8f76-ad4c33858469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923105260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3923105260
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2453072638
Short name T729
Test name
Test status
Simulation time 1889110401 ps
CPU time 5.89 seconds
Started Jun 05 05:36:36 PM PDT 24
Finished Jun 05 05:36:42 PM PDT 24
Peak memory 224768 kb
Host smart-6ba3d18f-488b-4bb2-a330-e0ea2970c897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453072638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2453072638
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2727926575
Short name T445
Test name
Test status
Simulation time 106502907 ps
CPU time 0.69 seconds
Started Jun 05 05:36:46 PM PDT 24
Finished Jun 05 05:36:47 PM PDT 24
Peak memory 205540 kb
Host smart-7538bacc-3a80-41d8-952b-d4e540e2d32e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727926575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2727926575
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1511649823
Short name T928
Test name
Test status
Simulation time 113682999 ps
CPU time 2.33 seconds
Started Jun 05 05:36:44 PM PDT 24
Finished Jun 05 05:36:47 PM PDT 24
Peak memory 224588 kb
Host smart-1bcf9fa3-cf38-4bb1-ae2e-388ec5845b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511649823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1511649823
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2414732561
Short name T475
Test name
Test status
Simulation time 27199537 ps
CPU time 0.78 seconds
Started Jun 05 05:36:46 PM PDT 24
Finished Jun 05 05:36:48 PM PDT 24
Peak memory 205740 kb
Host smart-9120dcd6-2ca9-4c18-a5f9-11a8f788f4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414732561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2414732561
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.674959730
Short name T834
Test name
Test status
Simulation time 6164650416 ps
CPU time 44.43 seconds
Started Jun 05 05:36:45 PM PDT 24
Finished Jun 05 05:37:30 PM PDT 24
Peak memory 249376 kb
Host smart-7760d675-1726-4799-9e04-a6daff2ef87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674959730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.674959730
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.107894411
Short name T838
Test name
Test status
Simulation time 52853540456 ps
CPU time 176.09 seconds
Started Jun 05 05:36:49 PM PDT 24
Finished Jun 05 05:39:46 PM PDT 24
Peak memory 241056 kb
Host smart-aa8edeff-b03f-4746-9816-7d3942c8721e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107894411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.107894411
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1020395097
Short name T488
Test name
Test status
Simulation time 3132204228 ps
CPU time 14.16 seconds
Started Jun 05 05:36:46 PM PDT 24
Finished Jun 05 05:37:01 PM PDT 24
Peak memory 217796 kb
Host smart-5e1b239c-f9d0-4ca6-a286-fdfd2d2b2474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020395097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1020395097
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3696419403
Short name T779
Test name
Test status
Simulation time 53791568294 ps
CPU time 29.51 seconds
Started Jun 05 05:36:49 PM PDT 24
Finished Jun 05 05:37:19 PM PDT 24
Peak memory 249292 kb
Host smart-f8d9d362-4f6b-48f1-9ea9-eca3e5593490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696419403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3696419403
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3882973452
Short name T266
Test name
Test status
Simulation time 1166129490 ps
CPU time 12.8 seconds
Started Jun 05 05:36:46 PM PDT 24
Finished Jun 05 05:37:00 PM PDT 24
Peak memory 224572 kb
Host smart-b3c3edb3-4033-46ae-8a99-1ea89194ac85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882973452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3882973452
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.392584228
Short name T57
Test name
Test status
Simulation time 11998699773 ps
CPU time 46.12 seconds
Started Jun 05 05:36:47 PM PDT 24
Finished Jun 05 05:37:34 PM PDT 24
Peak memory 227816 kb
Host smart-1c5b11a7-0f42-402f-96c0-7bba0d5da53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392584228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.392584228
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2016356177
Short name T933
Test name
Test status
Simulation time 10471850814 ps
CPU time 5.02 seconds
Started Jun 05 05:36:45 PM PDT 24
Finished Jun 05 05:36:51 PM PDT 24
Peak memory 232884 kb
Host smart-56d7c17c-6b91-4f81-878d-5e1b44962af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016356177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2016356177
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3214393692
Short name T383
Test name
Test status
Simulation time 22197111251 ps
CPU time 15.33 seconds
Started Jun 05 05:36:46 PM PDT 24
Finished Jun 05 05:37:02 PM PDT 24
Peak memory 232888 kb
Host smart-dea2b5c9-45c3-4175-b141-9b5ed5306872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214393692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3214393692
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2187287151
Short name T589
Test name
Test status
Simulation time 2803609174 ps
CPU time 11.54 seconds
Started Jun 05 05:36:46 PM PDT 24
Finished Jun 05 05:36:59 PM PDT 24
Peak memory 218956 kb
Host smart-18f76ca8-1361-4f21-a505-06332dfebe87
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2187287151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2187287151
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2309221153
Short name T145
Test name
Test status
Simulation time 124386988030 ps
CPU time 287.39 seconds
Started Jun 05 05:36:49 PM PDT 24
Finished Jun 05 05:41:37 PM PDT 24
Peak memory 249336 kb
Host smart-f673dca7-84d0-47cf-8df9-c489e4b639b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309221153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2309221153
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3657908046
Short name T484
Test name
Test status
Simulation time 6295582738 ps
CPU time 9.77 seconds
Started Jun 05 05:36:44 PM PDT 24
Finished Jun 05 05:36:55 PM PDT 24
Peak memory 216436 kb
Host smart-b99a2b7f-42da-4b71-8cd0-f613f1384e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657908046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3657908046
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1720514876
Short name T1
Test name
Test status
Simulation time 5321677454 ps
CPU time 11.57 seconds
Started Jun 05 05:36:44 PM PDT 24
Finished Jun 05 05:36:56 PM PDT 24
Peak memory 216468 kb
Host smart-26f9fcff-a13a-41c7-97de-c2f4acf8321b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720514876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1720514876
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3274444914
Short name T3
Test name
Test status
Simulation time 92975685 ps
CPU time 1.06 seconds
Started Jun 05 05:36:44 PM PDT 24
Finished Jun 05 05:36:46 PM PDT 24
Peak memory 207264 kb
Host smart-e7c07163-824c-40c2-98b6-1670f8cc8597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274444914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3274444914
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.29717114
Short name T340
Test name
Test status
Simulation time 112083824 ps
CPU time 1.05 seconds
Started Jun 05 05:36:44 PM PDT 24
Finished Jun 05 05:36:46 PM PDT 24
Peak memory 206956 kb
Host smart-46c55f4c-ee0f-472d-a23d-81b390b77a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29717114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.29717114
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3981059638
Short name T719
Test name
Test status
Simulation time 144816061 ps
CPU time 2.43 seconds
Started Jun 05 05:36:47 PM PDT 24
Finished Jun 05 05:36:50 PM PDT 24
Peak memory 234384 kb
Host smart-5931fbde-2857-497f-bb9f-54d2d7103e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981059638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3981059638
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2191558954
Short name T494
Test name
Test status
Simulation time 14432262 ps
CPU time 0.72 seconds
Started Jun 05 05:36:55 PM PDT 24
Finished Jun 05 05:36:56 PM PDT 24
Peak memory 205012 kb
Host smart-fea7f3b7-7c11-4d2a-9e8c-4372a322a331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191558954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2191558954
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.4012910637
Short name T600
Test name
Test status
Simulation time 316588261 ps
CPU time 3.52 seconds
Started Jun 05 05:36:54 PM PDT 24
Finished Jun 05 05:36:58 PM PDT 24
Peak memory 224648 kb
Host smart-04f2eb38-1bd2-4f97-b3e0-12f040dfa233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012910637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.4012910637
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2013373372
Short name T695
Test name
Test status
Simulation time 34994259 ps
CPU time 0.78 seconds
Started Jun 05 05:36:46 PM PDT 24
Finished Jun 05 05:36:48 PM PDT 24
Peak memory 206756 kb
Host smart-1090a0d6-09d3-45e9-a083-2488b45abff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013373372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2013373372
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.588262206
Short name T224
Test name
Test status
Simulation time 2974997248 ps
CPU time 15.41 seconds
Started Jun 05 05:36:59 PM PDT 24
Finished Jun 05 05:37:15 PM PDT 24
Peak memory 237300 kb
Host smart-191c7c2a-b3d4-49da-8996-2c9a84d59da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588262206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.588262206
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1387071052
Short name T381
Test name
Test status
Simulation time 3244498117 ps
CPU time 33.75 seconds
Started Jun 05 05:36:57 PM PDT 24
Finished Jun 05 05:37:32 PM PDT 24
Peak memory 240028 kb
Host smart-c346e681-1e7a-4724-a2a6-e8c85850737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387071052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1387071052
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3610507101
Short name T162
Test name
Test status
Simulation time 25599473231 ps
CPU time 228.62 seconds
Started Jun 05 05:36:58 PM PDT 24
Finished Jun 05 05:40:48 PM PDT 24
Peak memory 249316 kb
Host smart-02b35055-8acf-4fca-9542-697e66272760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610507101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3610507101
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4242404334
Short name T666
Test name
Test status
Simulation time 216028945 ps
CPU time 2.87 seconds
Started Jun 05 05:36:52 PM PDT 24
Finished Jun 05 05:36:56 PM PDT 24
Peak memory 224612 kb
Host smart-350caf4d-695a-45f2-b481-cc5223df5563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242404334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4242404334
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.4076152702
Short name T787
Test name
Test status
Simulation time 518821628 ps
CPU time 7.47 seconds
Started Jun 05 05:36:56 PM PDT 24
Finished Jun 05 05:37:04 PM PDT 24
Peak memory 232784 kb
Host smart-0f645a11-1f31-4e4a-9f5c-a90df239c311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076152702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.4076152702
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2125987332
Short name T497
Test name
Test status
Simulation time 774424674 ps
CPU time 4.56 seconds
Started Jun 05 05:36:54 PM PDT 24
Finished Jun 05 05:37:00 PM PDT 24
Peak memory 232840 kb
Host smart-0208cdc9-6e80-4928-8a77-374f46a1207b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125987332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2125987332
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.893199463
Short name T550
Test name
Test status
Simulation time 238820317 ps
CPU time 3 seconds
Started Jun 05 05:36:57 PM PDT 24
Finished Jun 05 05:37:01 PM PDT 24
Peak memory 232836 kb
Host smart-4d7a13b4-b4e1-4d33-8544-1aa1e5fdb1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893199463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.893199463
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.936724542
Short name T444
Test name
Test status
Simulation time 648956443 ps
CPU time 5.74 seconds
Started Jun 05 05:36:56 PM PDT 24
Finished Jun 05 05:37:02 PM PDT 24
Peak memory 221912 kb
Host smart-4e403036-522f-42d0-af3b-289963a1a5f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=936724542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.936724542
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.4007823790
Short name T875
Test name
Test status
Simulation time 78084266169 ps
CPU time 91.12 seconds
Started Jun 05 05:36:58 PM PDT 24
Finished Jun 05 05:38:30 PM PDT 24
Peak memory 252964 kb
Host smart-dca3d219-345a-4ed8-b43d-db250d924c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007823790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.4007823790
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1538025552
Short name T288
Test name
Test status
Simulation time 342735605 ps
CPU time 3.17 seconds
Started Jun 05 05:36:52 PM PDT 24
Finished Jun 05 05:36:56 PM PDT 24
Peak memory 218780 kb
Host smart-bee27a73-07cd-442d-bd00-be31f267de9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538025552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1538025552
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3525573122
Short name T395
Test name
Test status
Simulation time 4865082449 ps
CPU time 12.8 seconds
Started Jun 05 05:36:52 PM PDT 24
Finished Jun 05 05:37:06 PM PDT 24
Peak memory 216520 kb
Host smart-82447b12-4071-43b5-8be4-f2ebb24a48f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525573122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3525573122
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1333132962
Short name T595
Test name
Test status
Simulation time 44164074 ps
CPU time 1.84 seconds
Started Jun 05 05:36:55 PM PDT 24
Finished Jun 05 05:36:58 PM PDT 24
Peak memory 216384 kb
Host smart-7861ad9f-86d0-44f7-9245-ef822fafe3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333132962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1333132962
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.326957691
Short name T782
Test name
Test status
Simulation time 56942815 ps
CPU time 0.84 seconds
Started Jun 05 05:36:54 PM PDT 24
Finished Jun 05 05:36:56 PM PDT 24
Peak memory 205980 kb
Host smart-c71b361b-7526-4032-9df3-279696c18bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326957691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.326957691
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3554785170
Short name T397
Test name
Test status
Simulation time 214407558 ps
CPU time 3.34 seconds
Started Jun 05 05:36:58 PM PDT 24
Finished Jun 05 05:37:02 PM PDT 24
Peak memory 224520 kb
Host smart-e613b0aa-f0b2-4cfe-92fe-01ba5ef55891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554785170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3554785170
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.236043156
Short name T449
Test name
Test status
Simulation time 22125973 ps
CPU time 0.71 seconds
Started Jun 05 05:35:04 PM PDT 24
Finished Jun 05 05:35:05 PM PDT 24
Peak memory 205576 kb
Host smart-8b06ec5c-ba32-4a7c-8a9c-d6116827102e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236043156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.236043156
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2736907864
Short name T537
Test name
Test status
Simulation time 670164309 ps
CPU time 3.65 seconds
Started Jun 05 05:34:57 PM PDT 24
Finished Jun 05 05:35:02 PM PDT 24
Peak memory 232804 kb
Host smart-cdf3b8e1-065f-47c9-b37a-06eb9945a9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736907864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2736907864
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1413656803
Short name T299
Test name
Test status
Simulation time 16237610 ps
CPU time 0.76 seconds
Started Jun 05 05:34:57 PM PDT 24
Finished Jun 05 05:34:59 PM PDT 24
Peak memory 205692 kb
Host smart-1d89520f-4223-4640-9e64-90511e14b177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413656803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1413656803
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1101701422
Short name T464
Test name
Test status
Simulation time 24464936383 ps
CPU time 45.59 seconds
Started Jun 05 05:35:03 PM PDT 24
Finished Jun 05 05:35:49 PM PDT 24
Peak memory 249268 kb
Host smart-a1c5b3a9-f83f-4f84-83a4-44322dcdd14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101701422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1101701422
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1123764443
Short name T209
Test name
Test status
Simulation time 29103674513 ps
CPU time 156.18 seconds
Started Jun 05 05:35:05 PM PDT 24
Finished Jun 05 05:37:41 PM PDT 24
Peak memory 249608 kb
Host smart-64538fb6-a6ce-4bb1-85c3-1fa55305ac40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123764443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1123764443
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1815449907
Short name T720
Test name
Test status
Simulation time 10055415701 ps
CPU time 52.15 seconds
Started Jun 05 05:35:05 PM PDT 24
Finished Jun 05 05:35:57 PM PDT 24
Peak memory 217764 kb
Host smart-19530803-b076-4ba2-aeb0-b81fd4412947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815449907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1815449907
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.997253254
Short name T310
Test name
Test status
Simulation time 1340315802 ps
CPU time 23.58 seconds
Started Jun 05 05:34:57 PM PDT 24
Finished Jun 05 05:35:21 PM PDT 24
Peak memory 249248 kb
Host smart-fcc30015-3b50-45fe-ae44-f90e14d9a327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997253254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.997253254
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3935222463
Short name T688
Test name
Test status
Simulation time 277939979 ps
CPU time 4.83 seconds
Started Jun 05 05:34:58 PM PDT 24
Finished Jun 05 05:35:04 PM PDT 24
Peak memory 220136 kb
Host smart-c4a5177c-200e-49bd-91eb-eb9be7b4930c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935222463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3935222463
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.408684621
Short name T521
Test name
Test status
Simulation time 1773522984 ps
CPU time 24.88 seconds
Started Jun 05 05:34:57 PM PDT 24
Finished Jun 05 05:35:23 PM PDT 24
Peak memory 232844 kb
Host smart-ad160f38-4c24-4ec2-acc5-1a5dc575fb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408684621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.408684621
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.5221659
Short name T745
Test name
Test status
Simulation time 1157785558 ps
CPU time 3.8 seconds
Started Jun 05 05:34:58 PM PDT 24
Finished Jun 05 05:35:02 PM PDT 24
Peak memory 232820 kb
Host smart-9a761af9-2c23-490b-90f8-1d2454b82ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5221659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.5221659
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1985740040
Short name T506
Test name
Test status
Simulation time 624939492 ps
CPU time 3.95 seconds
Started Jun 05 05:35:01 PM PDT 24
Finished Jun 05 05:35:06 PM PDT 24
Peak memory 224632 kb
Host smart-e3a615b1-5d89-48e8-9021-f8362fabbf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985740040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1985740040
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1194773229
Short name T132
Test name
Test status
Simulation time 883519169 ps
CPU time 3.73 seconds
Started Jun 05 05:35:07 PM PDT 24
Finished Jun 05 05:35:11 PM PDT 24
Peak memory 220132 kb
Host smart-88b0ae27-d433-4841-bfad-57488bb853cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1194773229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1194773229
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.112312454
Short name T51
Test name
Test status
Simulation time 426026476 ps
CPU time 1.17 seconds
Started Jun 05 05:35:05 PM PDT 24
Finished Jun 05 05:35:06 PM PDT 24
Peak memory 235240 kb
Host smart-79ddc176-91a1-4a65-a6c4-46ad642751fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112312454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.112312454
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.87577948
Short name T882
Test name
Test status
Simulation time 6553407022 ps
CPU time 25.84 seconds
Started Jun 05 05:34:56 PM PDT 24
Finished Jun 05 05:35:23 PM PDT 24
Peak memory 216452 kb
Host smart-9017d3a8-dc7a-4c24-a79a-760e96f1f4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87577948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.87577948
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4243355559
Short name T401
Test name
Test status
Simulation time 1025222836 ps
CPU time 3.34 seconds
Started Jun 05 05:34:58 PM PDT 24
Finished Jun 05 05:35:01 PM PDT 24
Peak memory 216396 kb
Host smart-1189aadf-cf18-4e24-8cbb-ddaf3abb8f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243355559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4243355559
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3900208836
Short name T659
Test name
Test status
Simulation time 41414784 ps
CPU time 1.15 seconds
Started Jun 05 05:34:58 PM PDT 24
Finished Jun 05 05:35:00 PM PDT 24
Peak memory 208012 kb
Host smart-0abacfe7-b049-42a1-819c-27de5b84b71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900208836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3900208836
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3529738273
Short name T790
Test name
Test status
Simulation time 86239667 ps
CPU time 0.95 seconds
Started Jun 05 05:34:57 PM PDT 24
Finished Jun 05 05:34:58 PM PDT 24
Peak memory 205972 kb
Host smart-73878274-446a-43ce-838a-48c6b494043f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529738273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3529738273
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.748454807
Short name T170
Test name
Test status
Simulation time 2888660773 ps
CPU time 15.45 seconds
Started Jun 05 05:34:56 PM PDT 24
Finished Jun 05 05:35:12 PM PDT 24
Peak memory 232956 kb
Host smart-3455d465-a843-489a-982f-a5f8ae9e335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748454807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.748454807
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2772296477
Short name T42
Test name
Test status
Simulation time 24979119 ps
CPU time 0.75 seconds
Started Jun 05 05:37:02 PM PDT 24
Finished Jun 05 05:37:03 PM PDT 24
Peak memory 205484 kb
Host smart-d795e0be-edac-4b85-bc1e-e444db9d85ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772296477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2772296477
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1057297079
Short name T500
Test name
Test status
Simulation time 61762393 ps
CPU time 2.27 seconds
Started Jun 05 05:37:01 PM PDT 24
Finished Jun 05 05:37:04 PM PDT 24
Peak memory 224484 kb
Host smart-a7bd08eb-58df-4b6f-b38d-6db99013ac19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057297079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1057297079
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3002256981
Short name T574
Test name
Test status
Simulation time 12974030 ps
CPU time 0.74 seconds
Started Jun 05 05:36:56 PM PDT 24
Finished Jun 05 05:36:57 PM PDT 24
Peak memory 205768 kb
Host smart-0cf1a785-c406-4706-a72a-f257829e439c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002256981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3002256981
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1465769140
Short name T551
Test name
Test status
Simulation time 5316018267 ps
CPU time 25.27 seconds
Started Jun 05 05:37:00 PM PDT 24
Finished Jun 05 05:37:25 PM PDT 24
Peak memory 241100 kb
Host smart-3ef1c75f-3a39-46fd-b5eb-199a0e8608a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465769140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1465769140
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.280792537
Short name T736
Test name
Test status
Simulation time 8960771211 ps
CPU time 86.45 seconds
Started Jun 05 05:37:01 PM PDT 24
Finished Jun 05 05:38:28 PM PDT 24
Peak memory 251620 kb
Host smart-7c505f2e-5c46-49b6-bf3f-053fdc4c8645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280792537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.280792537
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1533937291
Short name T556
Test name
Test status
Simulation time 35114625931 ps
CPU time 77.11 seconds
Started Jun 05 05:37:02 PM PDT 24
Finished Jun 05 05:38:20 PM PDT 24
Peak memory 250424 kb
Host smart-94f3e00b-a79e-4be4-8fe8-13118a57468f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533937291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1533937291
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.66220538
Short name T820
Test name
Test status
Simulation time 237823086 ps
CPU time 3.79 seconds
Started Jun 05 05:36:57 PM PDT 24
Finished Jun 05 05:37:02 PM PDT 24
Peak memory 241048 kb
Host smart-945edae7-28c2-410f-a296-ecc0e7852a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66220538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.66220538
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1352854612
Short name T860
Test name
Test status
Simulation time 4707959228 ps
CPU time 22.67 seconds
Started Jun 05 05:37:01 PM PDT 24
Finished Jun 05 05:37:24 PM PDT 24
Peak memory 224620 kb
Host smart-950d17d0-e83a-424a-8f69-650830b14eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352854612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1352854612
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1668335320
Short name T647
Test name
Test status
Simulation time 15208764031 ps
CPU time 25.66 seconds
Started Jun 05 05:36:58 PM PDT 24
Finished Jun 05 05:37:24 PM PDT 24
Peak memory 232928 kb
Host smart-c307f6d2-f91c-4313-bdde-de5937430a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668335320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1668335320
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3089685696
Short name T603
Test name
Test status
Simulation time 538036817 ps
CPU time 2.57 seconds
Started Jun 05 05:36:58 PM PDT 24
Finished Jun 05 05:37:01 PM PDT 24
Peak memory 224580 kb
Host smart-98c6b369-1628-42d7-9398-8d76a2f2801f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089685696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3089685696
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3229545975
Short name T655
Test name
Test status
Simulation time 142562561 ps
CPU time 3 seconds
Started Jun 05 05:36:57 PM PDT 24
Finished Jun 05 05:37:00 PM PDT 24
Peak memory 224576 kb
Host smart-0305979b-bdab-4037-bfed-7279d863c0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229545975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3229545975
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2495769807
Short name T463
Test name
Test status
Simulation time 415063141 ps
CPU time 6.59 seconds
Started Jun 05 05:36:58 PM PDT 24
Finished Jun 05 05:37:05 PM PDT 24
Peak memory 220516 kb
Host smart-e40019d7-33ae-4b3f-aadb-34b24570a9d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2495769807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2495769807
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.4272181648
Short name T192
Test name
Test status
Simulation time 164666174393 ps
CPU time 460.93 seconds
Started Jun 05 05:36:57 PM PDT 24
Finished Jun 05 05:44:39 PM PDT 24
Peak memory 270072 kb
Host smart-54e05316-805e-4773-af05-a624a21f2c7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272181648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.4272181648
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.733766516
Short name T297
Test name
Test status
Simulation time 30046890 ps
CPU time 0.71 seconds
Started Jun 05 05:36:58 PM PDT 24
Finished Jun 05 05:37:00 PM PDT 24
Peak memory 205820 kb
Host smart-dfffabe8-62c9-47fb-b461-77f0e541b0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733766516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.733766516
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2231403487
Short name T697
Test name
Test status
Simulation time 107225682 ps
CPU time 0.74 seconds
Started Jun 05 05:36:55 PM PDT 24
Finished Jun 05 05:36:56 PM PDT 24
Peak memory 205716 kb
Host smart-e2b79cfe-5ae7-4253-b28a-dee0b5e058f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231403487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2231403487
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2769762481
Short name T523
Test name
Test status
Simulation time 75892667 ps
CPU time 1.34 seconds
Started Jun 05 05:36:56 PM PDT 24
Finished Jun 05 05:36:58 PM PDT 24
Peak memory 208180 kb
Host smart-27d4e3cf-e7db-4806-b463-c662ab968a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769762481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2769762481
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.279645675
Short name T615
Test name
Test status
Simulation time 215317244 ps
CPU time 0.91 seconds
Started Jun 05 05:36:59 PM PDT 24
Finished Jun 05 05:37:00 PM PDT 24
Peak memory 206016 kb
Host smart-ea6dc929-85ba-44da-ab8d-a150583c26e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279645675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.279645675
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1576223445
Short name T893
Test name
Test status
Simulation time 1032523592 ps
CPU time 9.24 seconds
Started Jun 05 05:37:01 PM PDT 24
Finished Jun 05 05:37:11 PM PDT 24
Peak memory 249252 kb
Host smart-fdcdc91a-3016-406e-91c9-ade48415a0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576223445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1576223445
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3699387440
Short name T878
Test name
Test status
Simulation time 17011349 ps
CPU time 0.72 seconds
Started Jun 05 05:37:04 PM PDT 24
Finished Jun 05 05:37:06 PM PDT 24
Peak memory 204944 kb
Host smart-73084c32-541a-49f0-9e3d-3ccad54c0a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699387440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3699387440
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.976922360
Short name T696
Test name
Test status
Simulation time 221956698 ps
CPU time 4.25 seconds
Started Jun 05 05:36:58 PM PDT 24
Finished Jun 05 05:37:03 PM PDT 24
Peak memory 232864 kb
Host smart-56fadd41-c6b8-44a5-87ee-aa0b0fc8a8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976922360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.976922360
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3992765616
Short name T758
Test name
Test status
Simulation time 23295853 ps
CPU time 0.81 seconds
Started Jun 05 05:37:02 PM PDT 24
Finished Jun 05 05:37:03 PM PDT 24
Peak memory 207024 kb
Host smart-28615a0c-8fbc-41fd-820d-0e033af2b79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992765616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3992765616
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.756067475
Short name T26
Test name
Test status
Simulation time 13407580177 ps
CPU time 49.82 seconds
Started Jun 05 05:37:05 PM PDT 24
Finished Jun 05 05:37:56 PM PDT 24
Peak memory 249276 kb
Host smart-13e4b8d6-f261-477b-8aca-d858d767ac65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756067475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.756067475
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3457930679
Short name T765
Test name
Test status
Simulation time 2133313844 ps
CPU time 23.2 seconds
Started Jun 05 05:37:03 PM PDT 24
Finished Jun 05 05:37:27 PM PDT 24
Peak memory 232936 kb
Host smart-0bbdba4d-e363-4dc8-be9c-e9fc76ee274f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457930679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3457930679
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3327406561
Short name T617
Test name
Test status
Simulation time 13923956388 ps
CPU time 62.5 seconds
Started Jun 05 05:37:03 PM PDT 24
Finished Jun 05 05:38:06 PM PDT 24
Peak memory 250368 kb
Host smart-e6b74d65-540a-41e9-87c0-43d9c5033989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327406561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3327406561
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2437653202
Short name T60
Test name
Test status
Simulation time 254878267 ps
CPU time 3.04 seconds
Started Jun 05 05:37:06 PM PDT 24
Finished Jun 05 05:37:09 PM PDT 24
Peak memory 235716 kb
Host smart-cdefa033-5e52-49c5-985e-3437ffe86c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437653202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2437653202
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3425913661
Short name T264
Test name
Test status
Simulation time 460874646 ps
CPU time 4.21 seconds
Started Jun 05 05:37:01 PM PDT 24
Finished Jun 05 05:37:07 PM PDT 24
Peak memory 232868 kb
Host smart-9cf977e0-3c7d-4c7a-aeaf-159f2a7c391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425913661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3425913661
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1115852078
Short name T830
Test name
Test status
Simulation time 1538767420 ps
CPU time 19.62 seconds
Started Jun 05 05:37:02 PM PDT 24
Finished Jun 05 05:37:23 PM PDT 24
Peak memory 232832 kb
Host smart-2c6140b2-1a6a-4354-9e10-d995aec6b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115852078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1115852078
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.463422306
Short name T842
Test name
Test status
Simulation time 2901094638 ps
CPU time 10.44 seconds
Started Jun 05 05:36:59 PM PDT 24
Finished Jun 05 05:37:10 PM PDT 24
Peak memory 233008 kb
Host smart-11a86168-da47-451a-b561-2b4c24d25fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463422306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.463422306
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.926842486
Short name T243
Test name
Test status
Simulation time 1279241030 ps
CPU time 5.89 seconds
Started Jun 05 05:37:01 PM PDT 24
Finished Jun 05 05:37:07 PM PDT 24
Peak memory 219624 kb
Host smart-8036b488-ec1d-443a-b2f9-f0d495fd2810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926842486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.926842486
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1900379005
Short name T394
Test name
Test status
Simulation time 234953521 ps
CPU time 3.94 seconds
Started Jun 05 05:37:05 PM PDT 24
Finished Jun 05 05:37:09 PM PDT 24
Peak memory 223196 kb
Host smart-f85629fa-0ca5-42f1-a43a-f187281cdbe6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1900379005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1900379005
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3482790689
Short name T918
Test name
Test status
Simulation time 13755290569 ps
CPU time 150.15 seconds
Started Jun 05 05:37:03 PM PDT 24
Finished Jun 05 05:39:34 PM PDT 24
Peak memory 257240 kb
Host smart-40b9102f-609d-4686-847b-5433da72ea7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482790689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3482790689
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.523063987
Short name T302
Test name
Test status
Simulation time 39528363 ps
CPU time 0.69 seconds
Started Jun 05 05:37:02 PM PDT 24
Finished Jun 05 05:37:03 PM PDT 24
Peak memory 206100 kb
Host smart-01a455f6-d328-42c1-a127-ee561f0a33a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523063987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.523063987
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2581327614
Short name T894
Test name
Test status
Simulation time 107401702 ps
CPU time 1.5 seconds
Started Jun 05 05:37:00 PM PDT 24
Finished Jun 05 05:37:02 PM PDT 24
Peak memory 208004 kb
Host smart-5250028c-c8e6-4d60-af1d-9c06d2902fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581327614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2581327614
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.4086027471
Short name T485
Test name
Test status
Simulation time 34035854 ps
CPU time 1.04 seconds
Started Jun 05 05:36:58 PM PDT 24
Finished Jun 05 05:37:00 PM PDT 24
Peak memory 207436 kb
Host smart-273d3c77-bb28-4ad9-8ea6-f16d3d79cbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086027471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.4086027471
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3775655258
Short name T328
Test name
Test status
Simulation time 98319137 ps
CPU time 1 seconds
Started Jun 05 05:37:02 PM PDT 24
Finished Jun 05 05:37:03 PM PDT 24
Peak memory 206500 kb
Host smart-f6e06e57-f341-4e84-9740-5818b8276f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775655258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3775655258
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.722977097
Short name T554
Test name
Test status
Simulation time 78576609188 ps
CPU time 17.83 seconds
Started Jun 05 05:37:05 PM PDT 24
Finished Jun 05 05:37:24 PM PDT 24
Peak memory 224704 kb
Host smart-f56e22ec-677f-4ff3-a0c5-c01d304c6a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722977097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.722977097
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3633651357
Short name T768
Test name
Test status
Simulation time 22669254 ps
CPU time 0.73 seconds
Started Jun 05 05:37:12 PM PDT 24
Finished Jun 05 05:37:13 PM PDT 24
Peak memory 204932 kb
Host smart-6f004fd8-7b4f-44d0-a05e-79a9ab75a118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633651357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3633651357
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2649907429
Short name T333
Test name
Test status
Simulation time 2383656953 ps
CPU time 9.13 seconds
Started Jun 05 05:37:04 PM PDT 24
Finished Jun 05 05:37:14 PM PDT 24
Peak memory 232876 kb
Host smart-be1cde2b-3820-4341-a339-e6fc0747e29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649907429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2649907429
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.4270219470
Short name T339
Test name
Test status
Simulation time 24334644 ps
CPU time 0.83 seconds
Started Jun 05 05:37:03 PM PDT 24
Finished Jun 05 05:37:05 PM PDT 24
Peak memory 206724 kb
Host smart-b81f1a77-69c3-4f76-801a-9ca706df9d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270219470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4270219470
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2142592044
Short name T356
Test name
Test status
Simulation time 10817172793 ps
CPU time 74.49 seconds
Started Jun 05 05:37:16 PM PDT 24
Finished Jun 05 05:38:31 PM PDT 24
Peak memory 252728 kb
Host smart-996ab2f7-7a97-4fc7-840c-f1d7a7071725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142592044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2142592044
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.4211575610
Short name T566
Test name
Test status
Simulation time 2082638629 ps
CPU time 44.56 seconds
Started Jun 05 05:37:12 PM PDT 24
Finished Jun 05 05:37:57 PM PDT 24
Peak memory 249248 kb
Host smart-0ac4b735-9717-4cf5-9cac-f35d974ab2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211575610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.4211575610
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1988756188
Short name T9
Test name
Test status
Simulation time 635845561 ps
CPU time 9.2 seconds
Started Jun 05 05:37:06 PM PDT 24
Finished Jun 05 05:37:16 PM PDT 24
Peak memory 232848 kb
Host smart-1543dbd4-7d0c-4365-8629-9527f5c12f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988756188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1988756188
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1962363689
Short name T478
Test name
Test status
Simulation time 169964925 ps
CPU time 2.28 seconds
Started Jun 05 05:37:03 PM PDT 24
Finished Jun 05 05:37:06 PM PDT 24
Peak memory 232636 kb
Host smart-e21b438f-817e-4159-aff1-aea9c8d49e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962363689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1962363689
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3867829364
Short name T614
Test name
Test status
Simulation time 3269347511 ps
CPU time 8.9 seconds
Started Jun 05 05:37:03 PM PDT 24
Finished Jun 05 05:37:12 PM PDT 24
Peak memory 240344 kb
Host smart-24665ad6-9288-4a44-a9ab-9fa2eae7ad21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867829364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3867829364
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.597562317
Short name T868
Test name
Test status
Simulation time 2868282957 ps
CPU time 11.94 seconds
Started Jun 05 05:37:04 PM PDT 24
Finished Jun 05 05:37:16 PM PDT 24
Peak memory 241056 kb
Host smart-a34d3ca0-85a2-4a88-bc7c-ef257a9509a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597562317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.597562317
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.20692725
Short name T826
Test name
Test status
Simulation time 1106728677 ps
CPU time 7.43 seconds
Started Jun 05 05:37:05 PM PDT 24
Finished Jun 05 05:37:13 PM PDT 24
Peak memory 220844 kb
Host smart-f22ff08b-17e8-4383-89dd-b23c5f73f1be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=20692725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direc
t.20692725
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2308058667
Short name T892
Test name
Test status
Simulation time 96034475439 ps
CPU time 388.29 seconds
Started Jun 05 05:37:13 PM PDT 24
Finished Jun 05 05:43:42 PM PDT 24
Peak memory 249596 kb
Host smart-b84c784b-0f76-40cc-a692-ac09d40ae531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308058667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2308058667
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1674577281
Short name T904
Test name
Test status
Simulation time 9656941747 ps
CPU time 51.2 seconds
Started Jun 05 05:37:03 PM PDT 24
Finished Jun 05 05:37:55 PM PDT 24
Peak memory 216528 kb
Host smart-2247c44b-1fbe-419a-9fa0-69d60fd13332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674577281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1674577281
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4142625421
Short name T865
Test name
Test status
Simulation time 22860493 ps
CPU time 0.71 seconds
Started Jun 05 05:37:05 PM PDT 24
Finished Jun 05 05:37:06 PM PDT 24
Peak memory 205736 kb
Host smart-d0449564-13d0-4285-8eb4-7db4f496be7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142625421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4142625421
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3519309859
Short name T290
Test name
Test status
Simulation time 28948298 ps
CPU time 1.09 seconds
Started Jun 05 05:37:03 PM PDT 24
Finished Jun 05 05:37:05 PM PDT 24
Peak memory 216264 kb
Host smart-26b49827-091f-48ac-8319-cc2a62ab5988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519309859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3519309859
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2153428765
Short name T403
Test name
Test status
Simulation time 108412024 ps
CPU time 0.79 seconds
Started Jun 05 05:37:02 PM PDT 24
Finished Jun 05 05:37:03 PM PDT 24
Peak memory 205968 kb
Host smart-adf604af-6de1-4336-9124-d9c3423211c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153428765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2153428765
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3883880491
Short name T417
Test name
Test status
Simulation time 1156222442 ps
CPU time 5.76 seconds
Started Jun 05 05:37:05 PM PDT 24
Finished Jun 05 05:37:12 PM PDT 24
Peak memory 232824 kb
Host smart-7dd8d272-1fae-4e6c-8e72-b92ca33254f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883880491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3883880491
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.313230840
Short name T357
Test name
Test status
Simulation time 30920006 ps
CPU time 0.69 seconds
Started Jun 05 05:37:20 PM PDT 24
Finished Jun 05 05:37:22 PM PDT 24
Peak memory 205612 kb
Host smart-be1d9a79-579c-495a-8a77-9e61b7bfbc0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313230840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.313230840
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.4127526525
Short name T74
Test name
Test status
Simulation time 1891771816 ps
CPU time 11.69 seconds
Started Jun 05 05:37:12 PM PDT 24
Finished Jun 05 05:37:24 PM PDT 24
Peak memory 224576 kb
Host smart-b1b70066-5e74-4692-ab88-fc6ab641d251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127526525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.4127526525
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1361017634
Short name T635
Test name
Test status
Simulation time 15657305 ps
CPU time 0.77 seconds
Started Jun 05 05:37:12 PM PDT 24
Finished Jun 05 05:37:13 PM PDT 24
Peak memory 206736 kb
Host smart-21f59200-e95b-4892-8c11-0a6109cefe06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361017634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1361017634
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.287289627
Short name T841
Test name
Test status
Simulation time 45982843934 ps
CPU time 171.98 seconds
Started Jun 05 05:37:21 PM PDT 24
Finished Jun 05 05:40:15 PM PDT 24
Peak memory 249732 kb
Host smart-f66319cd-426d-420a-b4ab-7480b75f027e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287289627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.287289627
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3610362746
Short name T270
Test name
Test status
Simulation time 148755069790 ps
CPU time 315.92 seconds
Started Jun 05 05:37:22 PM PDT 24
Finished Jun 05 05:42:40 PM PDT 24
Peak memory 241120 kb
Host smart-2bf26533-cbcf-4621-b63d-9138e39833b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610362746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3610362746
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2706772209
Short name T471
Test name
Test status
Simulation time 5104176183 ps
CPU time 14.22 seconds
Started Jun 05 05:37:20 PM PDT 24
Finished Jun 05 05:37:35 PM PDT 24
Peak memory 217764 kb
Host smart-45259097-fb63-4072-b750-fce65fca33f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706772209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2706772209
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3942680913
Short name T675
Test name
Test status
Simulation time 430501510 ps
CPU time 4 seconds
Started Jun 05 05:37:16 PM PDT 24
Finished Jun 05 05:37:21 PM PDT 24
Peak memory 234144 kb
Host smart-7a8ebf10-0ed2-4775-ad41-c72d2c8d6455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942680913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3942680913
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4236715100
Short name T241
Test name
Test status
Simulation time 4974037532 ps
CPU time 15.12 seconds
Started Jun 05 05:37:13 PM PDT 24
Finished Jun 05 05:37:29 PM PDT 24
Peak memory 224656 kb
Host smart-da0a14f1-0d8b-4d37-a37f-cf3bf465cade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236715100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4236715100
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3901672423
Short name T167
Test name
Test status
Simulation time 5982611412 ps
CPU time 69.82 seconds
Started Jun 05 05:37:15 PM PDT 24
Finished Jun 05 05:38:25 PM PDT 24
Peak memory 232836 kb
Host smart-addec136-fd15-4c7e-a74d-4349fee55e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901672423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3901672423
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3656592144
Short name T915
Test name
Test status
Simulation time 2307497018 ps
CPU time 6.23 seconds
Started Jun 05 05:37:15 PM PDT 24
Finished Jun 05 05:37:22 PM PDT 24
Peak memory 240868 kb
Host smart-e21b6af2-9e01-46cc-8d9f-f5f9cd1a2d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656592144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3656592144
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.646642735
Short name T377
Test name
Test status
Simulation time 319295625 ps
CPU time 2.3 seconds
Started Jun 05 05:37:17 PM PDT 24
Finished Jun 05 05:37:20 PM PDT 24
Peak memory 224548 kb
Host smart-f53a9fec-7c84-4b53-b19a-3ce17e8d729a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646642735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.646642735
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1064784663
Short name T84
Test name
Test status
Simulation time 567735010 ps
CPU time 7.27 seconds
Started Jun 05 05:37:19 PM PDT 24
Finished Jun 05 05:37:27 PM PDT 24
Peak memory 218884 kb
Host smart-9fc74978-5a51-4398-adae-cd0afba8d005
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1064784663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1064784663
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.4281762256
Short name T40
Test name
Test status
Simulation time 110565700 ps
CPU time 1.08 seconds
Started Jun 05 05:37:21 PM PDT 24
Finished Jun 05 05:37:24 PM PDT 24
Peak memory 207268 kb
Host smart-cfa9a97d-973c-4086-8026-2fde7b07de79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281762256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.4281762256
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2628517973
Short name T839
Test name
Test status
Simulation time 4987441512 ps
CPU time 25.74 seconds
Started Jun 05 05:37:14 PM PDT 24
Finished Jun 05 05:37:40 PM PDT 24
Peak memory 216408 kb
Host smart-e6f764ef-3d07-4b23-8c82-0644ec0cd88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628517973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2628517973
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2794526389
Short name T901
Test name
Test status
Simulation time 5442609959 ps
CPU time 6.29 seconds
Started Jun 05 05:37:12 PM PDT 24
Finished Jun 05 05:37:19 PM PDT 24
Peak memory 216500 kb
Host smart-51236e31-ce13-4ec3-89f2-df81d58aae72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794526389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2794526389
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3744825139
Short name T285
Test name
Test status
Simulation time 292190139 ps
CPU time 1.34 seconds
Started Jun 05 05:37:10 PM PDT 24
Finished Jun 05 05:37:12 PM PDT 24
Peak memory 216428 kb
Host smart-f2ff8ed7-c027-43fe-915a-f62dc359c30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744825139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3744825139
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.4209298413
Short name T817
Test name
Test status
Simulation time 75440029 ps
CPU time 0.95 seconds
Started Jun 05 05:37:13 PM PDT 24
Finished Jun 05 05:37:14 PM PDT 24
Peak memory 206028 kb
Host smart-27bbcb55-28ac-44ca-835c-177a429fede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209298413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.4209298413
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1665266274
Short name T821
Test name
Test status
Simulation time 182190476 ps
CPU time 2.5 seconds
Started Jun 05 05:37:12 PM PDT 24
Finished Jun 05 05:37:15 PM PDT 24
Peak memory 241036 kb
Host smart-633fa794-2f88-4d2f-aa45-c82ad798ca9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665266274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1665266274
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1700729770
Short name T626
Test name
Test status
Simulation time 14216816 ps
CPU time 0.74 seconds
Started Jun 05 05:37:18 PM PDT 24
Finished Jun 05 05:37:20 PM PDT 24
Peak memory 205848 kb
Host smart-b6c37df7-89f6-41d0-8912-aa34ba18b61d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700729770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1700729770
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2431695496
Short name T158
Test name
Test status
Simulation time 4686272636 ps
CPU time 9.5 seconds
Started Jun 05 05:37:20 PM PDT 24
Finished Jun 05 05:37:30 PM PDT 24
Peak memory 232896 kb
Host smart-e4c69b76-d31a-4b3a-a94c-bc53baf98f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431695496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2431695496
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1640319454
Short name T710
Test name
Test status
Simulation time 41172476 ps
CPU time 0.83 seconds
Started Jun 05 05:37:21 PM PDT 24
Finished Jun 05 05:37:23 PM PDT 24
Peak memory 206744 kb
Host smart-b1597714-f916-4872-b045-99037b3dce1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640319454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1640319454
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.779986903
Short name T68
Test name
Test status
Simulation time 135426289089 ps
CPU time 323.97 seconds
Started Jun 05 05:37:19 PM PDT 24
Finished Jun 05 05:42:44 PM PDT 24
Peak memory 249360 kb
Host smart-784c8ad3-e0a6-4896-9a06-c64a0c859ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779986903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.779986903
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1301419595
Short name T678
Test name
Test status
Simulation time 17538536190 ps
CPU time 144.46 seconds
Started Jun 05 05:37:21 PM PDT 24
Finished Jun 05 05:39:46 PM PDT 24
Peak memory 238304 kb
Host smart-798a4b58-de92-456c-83c6-52cb87bbf3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301419595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1301419595
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3912803511
Short name T953
Test name
Test status
Simulation time 1304971795 ps
CPU time 9.3 seconds
Started Jun 05 05:37:23 PM PDT 24
Finished Jun 05 05:37:34 PM PDT 24
Peak memory 232892 kb
Host smart-4d3927e1-3569-4d5a-a944-a0e765e19551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912803511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3912803511
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3071802642
Short name T179
Test name
Test status
Simulation time 189143547 ps
CPU time 6.3 seconds
Started Jun 05 05:37:18 PM PDT 24
Finished Jun 05 05:37:24 PM PDT 24
Peak memory 232884 kb
Host smart-010c098c-159c-4695-82dc-74b8dbce1dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071802642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3071802642
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2438262670
Short name T175
Test name
Test status
Simulation time 1596107940 ps
CPU time 10.33 seconds
Started Jun 05 05:37:23 PM PDT 24
Finished Jun 05 05:37:35 PM PDT 24
Peak memory 249168 kb
Host smart-b6765a84-10c2-4f04-925b-b40781db9cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438262670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2438262670
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2744798319
Short name T795
Test name
Test status
Simulation time 362201779 ps
CPU time 3.25 seconds
Started Jun 05 05:37:22 PM PDT 24
Finished Jun 05 05:37:27 PM PDT 24
Peak memory 232872 kb
Host smart-44861ad1-831d-4d91-896b-167ef764a876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744798319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2744798319
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1291089167
Short name T700
Test name
Test status
Simulation time 7225681747 ps
CPU time 6.88 seconds
Started Jun 05 05:37:20 PM PDT 24
Finished Jun 05 05:37:28 PM PDT 24
Peak memory 224724 kb
Host smart-7e209e67-2dc9-4e5e-8ae4-a36ce9a1efa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291089167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1291089167
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2879307138
Short name T308
Test name
Test status
Simulation time 777715702 ps
CPU time 6.7 seconds
Started Jun 05 05:37:20 PM PDT 24
Finished Jun 05 05:37:28 PM PDT 24
Peak memory 221872 kb
Host smart-d2eb1b9d-99df-47c4-8ee7-6c5fddf36649
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2879307138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2879307138
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3809795556
Short name T847
Test name
Test status
Simulation time 543224594 ps
CPU time 3.34 seconds
Started Jun 05 05:37:20 PM PDT 24
Finished Jun 05 05:37:24 PM PDT 24
Peak memory 217800 kb
Host smart-bee7b42d-d640-4138-8a61-61b9f4288dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809795556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3809795556
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3555369399
Short name T763
Test name
Test status
Simulation time 11143884758 ps
CPU time 10.1 seconds
Started Jun 05 05:37:18 PM PDT 24
Finished Jun 05 05:37:28 PM PDT 24
Peak memory 216528 kb
Host smart-923dd127-dbed-48e7-98f8-2ac08330bcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555369399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3555369399
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2092407314
Short name T602
Test name
Test status
Simulation time 14260206 ps
CPU time 0.84 seconds
Started Jun 05 05:37:18 PM PDT 24
Finished Jun 05 05:37:20 PM PDT 24
Peak memory 206752 kb
Host smart-c10deb70-9387-4492-b72e-030ab8804c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092407314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2092407314
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1782702848
Short name T480
Test name
Test status
Simulation time 90442474 ps
CPU time 0.79 seconds
Started Jun 05 05:37:22 PM PDT 24
Finished Jun 05 05:37:24 PM PDT 24
Peak memory 205996 kb
Host smart-2424d23b-aba4-4e36-b22e-451c3dd9f5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782702848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1782702848
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1124745659
Short name T714
Test name
Test status
Simulation time 4562216000 ps
CPU time 4.8 seconds
Started Jun 05 05:37:20 PM PDT 24
Finished Jun 05 05:37:25 PM PDT 24
Peak memory 232924 kb
Host smart-c36e4cc3-41fc-4cd7-a47d-30aca82c5ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124745659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1124745659
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3002348773
Short name T522
Test name
Test status
Simulation time 39663139 ps
CPU time 0.74 seconds
Started Jun 05 05:37:27 PM PDT 24
Finished Jun 05 05:37:29 PM PDT 24
Peak memory 205540 kb
Host smart-5e98dd54-111b-42e0-b58f-74764ba363e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002348773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3002348773
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1721640763
Short name T806
Test name
Test status
Simulation time 461789472 ps
CPU time 5.58 seconds
Started Jun 05 05:37:28 PM PDT 24
Finished Jun 05 05:37:35 PM PDT 24
Peak memory 232840 kb
Host smart-56ac53f2-1ace-4324-978a-bbcc6b4dd5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721640763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1721640763
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.990180339
Short name T703
Test name
Test status
Simulation time 19500861 ps
CPU time 0.75 seconds
Started Jun 05 05:37:23 PM PDT 24
Finished Jun 05 05:37:25 PM PDT 24
Peak memory 205764 kb
Host smart-33bc3909-7e0b-4d78-90ef-20dc8420791f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990180339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.990180339
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.4062402081
Short name T255
Test name
Test status
Simulation time 4195790385 ps
CPU time 46.1 seconds
Started Jun 05 05:37:29 PM PDT 24
Finished Jun 05 05:38:16 PM PDT 24
Peak memory 251276 kb
Host smart-6e53aeb1-03c4-4b39-802b-c110b0b3a126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062402081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.4062402081
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1452079795
Short name T296
Test name
Test status
Simulation time 92275216337 ps
CPU time 200.37 seconds
Started Jun 05 05:37:30 PM PDT 24
Finished Jun 05 05:40:51 PM PDT 24
Peak memory 253532 kb
Host smart-04d1bed9-fc8b-42bc-aad8-3e228a5ce148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452079795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1452079795
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.312552784
Short name T687
Test name
Test status
Simulation time 38856788337 ps
CPU time 239.32 seconds
Started Jun 05 05:37:28 PM PDT 24
Finished Jun 05 05:41:29 PM PDT 24
Peak memory 249300 kb
Host smart-28d87d2d-0b7d-4b7b-b846-a0770bb9b21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312552784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.312552784
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2867761163
Short name T702
Test name
Test status
Simulation time 3830213496 ps
CPU time 45.44 seconds
Started Jun 05 05:37:24 PM PDT 24
Finished Jun 05 05:38:10 PM PDT 24
Peak memory 249288 kb
Host smart-ea8711d3-d233-4701-a8a5-a105b202842d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867761163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2867761163
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2435284390
Short name T502
Test name
Test status
Simulation time 55735142 ps
CPU time 2.17 seconds
Started Jun 05 05:37:28 PM PDT 24
Finished Jun 05 05:37:32 PM PDT 24
Peak memory 222960 kb
Host smart-4b2c0f47-99a3-4614-a327-00b5e095c775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435284390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2435284390
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1556615671
Short name T271
Test name
Test status
Simulation time 6532859284 ps
CPU time 19.13 seconds
Started Jun 05 05:37:28 PM PDT 24
Finished Jun 05 05:37:49 PM PDT 24
Peak memory 228308 kb
Host smart-c8eef97b-0ba9-4331-b69e-09eacdb0b0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556615671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1556615671
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1827210846
Short name T664
Test name
Test status
Simulation time 1346922037 ps
CPU time 6.34 seconds
Started Jun 05 05:37:20 PM PDT 24
Finished Jun 05 05:37:28 PM PDT 24
Peak memory 237180 kb
Host smart-35e57064-5fe5-421c-b9c7-ee1fc85a8211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827210846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1827210846
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2094778077
Short name T409
Test name
Test status
Simulation time 141918136 ps
CPU time 3.53 seconds
Started Jun 05 05:37:30 PM PDT 24
Finished Jun 05 05:37:34 PM PDT 24
Peak memory 222568 kb
Host smart-89e539b7-cd2f-4cc4-89e4-b6785520d240
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2094778077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2094778077
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.623693743
Short name T208
Test name
Test status
Simulation time 123545601403 ps
CPU time 278.55 seconds
Started Jun 05 05:37:30 PM PDT 24
Finished Jun 05 05:42:09 PM PDT 24
Peak memory 240756 kb
Host smart-c412bd28-22b9-476a-8434-65934a236ca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623693743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.623693743
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3419636576
Short name T924
Test name
Test status
Simulation time 1007331232 ps
CPU time 10.67 seconds
Started Jun 05 05:37:20 PM PDT 24
Finished Jun 05 05:37:32 PM PDT 24
Peak memory 220156 kb
Host smart-ad46e055-1c37-45e0-8d78-2c37e2d65e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419636576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3419636576
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3198195412
Short name T634
Test name
Test status
Simulation time 1387589211 ps
CPU time 5.67 seconds
Started Jun 05 05:37:21 PM PDT 24
Finished Jun 05 05:37:29 PM PDT 24
Peak memory 216488 kb
Host smart-6c725942-8d5e-456c-a871-5ac28b02c790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198195412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3198195412
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2538492903
Short name T905
Test name
Test status
Simulation time 20417776 ps
CPU time 1.34 seconds
Started Jun 05 05:37:22 PM PDT 24
Finished Jun 05 05:37:26 PM PDT 24
Peak memory 216480 kb
Host smart-69813ea2-e09f-4f2b-9aea-4eac27880c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538492903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2538492903
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.891510108
Short name T608
Test name
Test status
Simulation time 102626682 ps
CPU time 0.83 seconds
Started Jun 05 05:37:21 PM PDT 24
Finished Jun 05 05:37:23 PM PDT 24
Peak memory 205996 kb
Host smart-2e714acc-55d9-4f48-a794-8688ff351937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891510108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.891510108
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.619146221
Short name T466
Test name
Test status
Simulation time 581238957 ps
CPU time 4.58 seconds
Started Jun 05 05:37:26 PM PDT 24
Finished Jun 05 05:37:31 PM PDT 24
Peak memory 224592 kb
Host smart-f52b4fad-0e60-4ed7-a24d-4ece912dba42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619146221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.619146221
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.996908847
Short name T351
Test name
Test status
Simulation time 13994919 ps
CPU time 0.72 seconds
Started Jun 05 05:37:27 PM PDT 24
Finished Jun 05 05:37:29 PM PDT 24
Peak memory 205004 kb
Host smart-d05b990a-8da0-4e6b-984a-e829e7d07fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996908847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.996908847
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3825907631
Short name T73
Test name
Test status
Simulation time 353763588 ps
CPU time 2.45 seconds
Started Jun 05 05:37:30 PM PDT 24
Finished Jun 05 05:37:33 PM PDT 24
Peak memory 224604 kb
Host smart-77b6b6d5-c5bc-414e-967f-9564e57c498d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825907631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3825907631
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1336179576
Short name T886
Test name
Test status
Simulation time 37924349 ps
CPU time 0.73 seconds
Started Jun 05 05:37:29 PM PDT 24
Finished Jun 05 05:37:31 PM PDT 24
Peak memory 205700 kb
Host smart-ba426e05-98c6-4394-a679-b5398364a0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336179576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1336179576
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1383427124
Short name T16
Test name
Test status
Simulation time 19946720335 ps
CPU time 25.23 seconds
Started Jun 05 05:37:26 PM PDT 24
Finished Jun 05 05:37:52 PM PDT 24
Peak memory 217828 kb
Host smart-6d00543d-39a8-467f-b307-b6ed2c976677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383427124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1383427124
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3153101671
Short name T223
Test name
Test status
Simulation time 40358551316 ps
CPU time 62.34 seconds
Started Jun 05 05:37:31 PM PDT 24
Finished Jun 05 05:38:34 PM PDT 24
Peak memory 249292 kb
Host smart-24ca3146-1b62-41f2-8589-3a5d19385d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153101671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3153101671
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2712974890
Short name T130
Test name
Test status
Simulation time 803602023 ps
CPU time 14.79 seconds
Started Jun 05 05:37:31 PM PDT 24
Finished Jun 05 05:37:46 PM PDT 24
Peak memory 234404 kb
Host smart-c6f0b1bb-eef5-44d0-bfdb-ec2d6f2a542e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712974890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2712974890
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.195355158
Short name T114
Test name
Test status
Simulation time 314883494 ps
CPU time 3.4 seconds
Started Jun 05 05:37:31 PM PDT 24
Finished Jun 05 05:37:34 PM PDT 24
Peak memory 232836 kb
Host smart-1cbc653d-7998-4f97-a4df-9b756dd4146e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195355158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.195355158
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3979658814
Short name T906
Test name
Test status
Simulation time 2861219440 ps
CPU time 16.02 seconds
Started Jun 05 05:37:28 PM PDT 24
Finished Jun 05 05:37:44 PM PDT 24
Peak memory 240416 kb
Host smart-bcdef81c-9407-4c62-9a3b-55233bb23409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979658814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3979658814
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.167680587
Short name T185
Test name
Test status
Simulation time 744933448 ps
CPU time 4.12 seconds
Started Jun 05 05:37:27 PM PDT 24
Finished Jun 05 05:37:32 PM PDT 24
Peak memory 232872 kb
Host smart-240e4ef3-f852-4250-a777-4a5fd8e5fb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167680587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.167680587
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3063250924
Short name T378
Test name
Test status
Simulation time 5015259856 ps
CPU time 11.93 seconds
Started Jun 05 05:37:28 PM PDT 24
Finished Jun 05 05:37:41 PM PDT 24
Peak memory 249040 kb
Host smart-05885dd0-4884-4656-8004-e395e4249740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063250924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3063250924
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3069695
Short name T737
Test name
Test status
Simulation time 80302437 ps
CPU time 3.7 seconds
Started Jun 05 05:37:29 PM PDT 24
Finished Jun 05 05:37:34 PM PDT 24
Peak memory 223064 kb
Host smart-2fb4da9b-392e-4cd6-b0ee-58948534e47c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3069695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.3069695
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2805683166
Short name T913
Test name
Test status
Simulation time 115060046958 ps
CPU time 579.44 seconds
Started Jun 05 05:37:28 PM PDT 24
Finished Jun 05 05:47:08 PM PDT 24
Peak memory 269372 kb
Host smart-4c2e3710-134f-486c-9974-5254624d25e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805683166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2805683166
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1810103841
Short name T573
Test name
Test status
Simulation time 3157333326 ps
CPU time 11.16 seconds
Started Jun 05 05:37:28 PM PDT 24
Finished Jun 05 05:37:40 PM PDT 24
Peak memory 216824 kb
Host smart-0342b902-2407-4aab-b86b-71abbc955155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810103841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1810103841
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3307364474
Short name T607
Test name
Test status
Simulation time 2098230846 ps
CPU time 6.71 seconds
Started Jun 05 05:37:29 PM PDT 24
Finished Jun 05 05:37:37 PM PDT 24
Peak memory 216448 kb
Host smart-ef6831bb-f050-49ca-873f-c73a9ec6816d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307364474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3307364474
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.4068207142
Short name T286
Test name
Test status
Simulation time 633370868 ps
CPU time 2.1 seconds
Started Jun 05 05:37:28 PM PDT 24
Finished Jun 05 05:37:31 PM PDT 24
Peak memory 216348 kb
Host smart-7a9a3a96-0549-4b1d-90c4-28ff1c868a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068207142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.4068207142
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3679831004
Short name T434
Test name
Test status
Simulation time 38100239 ps
CPU time 0.81 seconds
Started Jun 05 05:37:31 PM PDT 24
Finished Jun 05 05:37:33 PM PDT 24
Peak memory 205976 kb
Host smart-234a7db8-c0da-493f-8d59-dcd8df0b52fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679831004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3679831004
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.467595887
Short name T408
Test name
Test status
Simulation time 1968821979 ps
CPU time 9.78 seconds
Started Jun 05 05:37:27 PM PDT 24
Finished Jun 05 05:37:37 PM PDT 24
Peak memory 224576 kb
Host smart-3135ef27-0012-48cc-917d-fcbe3cb40375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467595887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.467595887
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1822508012
Short name T315
Test name
Test status
Simulation time 17119747 ps
CPU time 0.73 seconds
Started Jun 05 05:37:36 PM PDT 24
Finished Jun 05 05:37:37 PM PDT 24
Peak memory 204960 kb
Host smart-91f62050-906d-480e-9211-3bfca1046ac1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822508012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1822508012
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3248842776
Short name T583
Test name
Test status
Simulation time 180043976 ps
CPU time 2.34 seconds
Started Jun 05 05:37:35 PM PDT 24
Finished Jun 05 05:37:38 PM PDT 24
Peak memory 224628 kb
Host smart-2fbb02e5-e20a-40d4-b067-e0ba8139eadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248842776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3248842776
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2444482337
Short name T7
Test name
Test status
Simulation time 64518416 ps
CPU time 0.8 seconds
Started Jun 05 05:37:28 PM PDT 24
Finished Jun 05 05:37:30 PM PDT 24
Peak memory 206744 kb
Host smart-2cbd9e23-ce31-4a3f-b3b1-f51a6494889c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444482337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2444482337
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.624309466
Short name T866
Test name
Test status
Simulation time 46963515506 ps
CPU time 78.01 seconds
Started Jun 05 05:37:36 PM PDT 24
Finished Jun 05 05:38:55 PM PDT 24
Peak memory 239252 kb
Host smart-0590afe1-24e8-462c-b6fc-86763ac730e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624309466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.624309466
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.42625906
Short name T721
Test name
Test status
Simulation time 838188484 ps
CPU time 8.69 seconds
Started Jun 05 05:37:36 PM PDT 24
Finished Jun 05 05:37:46 PM PDT 24
Peak memory 217584 kb
Host smart-3a14a7b5-8b9a-4e45-af2a-f9a0aefa07b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42625906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.42625906
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1559846989
Short name T330
Test name
Test status
Simulation time 6167035855 ps
CPU time 20.15 seconds
Started Jun 05 05:37:35 PM PDT 24
Finished Jun 05 05:37:56 PM PDT 24
Peak memory 224696 kb
Host smart-49c8ce94-e48a-4350-845b-cc848bb8d583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559846989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1559846989
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1459005112
Short name T942
Test name
Test status
Simulation time 398704887 ps
CPU time 3.75 seconds
Started Jun 05 05:37:37 PM PDT 24
Finished Jun 05 05:37:41 PM PDT 24
Peak memory 232888 kb
Host smart-af09b3fc-8a84-48c0-87eb-c53edab3e39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459005112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1459005112
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2265845320
Short name T446
Test name
Test status
Simulation time 139762054 ps
CPU time 2.38 seconds
Started Jun 05 05:37:35 PM PDT 24
Finished Jun 05 05:37:38 PM PDT 24
Peak memory 224636 kb
Host smart-81fc4fe5-dfe1-417f-8974-e317e8e2ede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265845320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2265845320
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1603378057
Short name T869
Test name
Test status
Simulation time 3480503671 ps
CPU time 6.98 seconds
Started Jun 05 05:37:36 PM PDT 24
Finished Jun 05 05:37:43 PM PDT 24
Peak memory 224620 kb
Host smart-e2ddb53f-40d5-48e9-b5bc-0e9ecd6ad1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603378057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1603378057
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2548900383
Short name T709
Test name
Test status
Simulation time 115913610584 ps
CPU time 15.54 seconds
Started Jun 05 05:37:38 PM PDT 24
Finished Jun 05 05:37:54 PM PDT 24
Peak memory 224724 kb
Host smart-8a2a5cd1-3e39-49ae-8613-88973f62e065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548900383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2548900383
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3901512638
Short name T909
Test name
Test status
Simulation time 2098724678 ps
CPU time 7.67 seconds
Started Jun 05 05:37:36 PM PDT 24
Finished Jun 05 05:37:45 PM PDT 24
Peak memory 223104 kb
Host smart-36c9f28f-4d14-45e9-845f-086c82cda2d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3901512638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3901512638
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2232603026
Short name T19
Test name
Test status
Simulation time 58078853069 ps
CPU time 536.41 seconds
Started Jun 05 05:37:36 PM PDT 24
Finished Jun 05 05:46:34 PM PDT 24
Peak memory 267116 kb
Host smart-6e729958-cd1c-47b4-9aa6-82fe48eeb277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232603026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2232603026
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1834733920
Short name T284
Test name
Test status
Simulation time 17338251843 ps
CPU time 39.04 seconds
Started Jun 05 05:37:37 PM PDT 24
Finished Jun 05 05:38:17 PM PDT 24
Peak memory 216728 kb
Host smart-dd43d2a5-74ea-45df-9f10-0143e6f2e351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834733920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1834733920
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.362118110
Short name T652
Test name
Test status
Simulation time 1264718289 ps
CPU time 4.68 seconds
Started Jun 05 05:37:29 PM PDT 24
Finished Jun 05 05:37:35 PM PDT 24
Peak memory 216424 kb
Host smart-de3b8424-e587-4f44-98de-fb8ed6621208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362118110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.362118110
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.502736405
Short name T291
Test name
Test status
Simulation time 75171139 ps
CPU time 0.74 seconds
Started Jun 05 05:37:35 PM PDT 24
Finished Jun 05 05:37:37 PM PDT 24
Peak memory 205972 kb
Host smart-c609f9cd-2d18-4f2d-8dd2-eeea4b319d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502736405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.502736405
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2366723694
Short name T524
Test name
Test status
Simulation time 26064558 ps
CPU time 0.73 seconds
Started Jun 05 05:37:37 PM PDT 24
Finished Jun 05 05:37:39 PM PDT 24
Peak memory 205980 kb
Host smart-5be56166-b89c-4605-a7f9-149eb22baa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366723694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2366723694
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2861587743
Short name T468
Test name
Test status
Simulation time 4519752243 ps
CPU time 8.91 seconds
Started Jun 05 05:37:37 PM PDT 24
Finished Jun 05 05:37:46 PM PDT 24
Peak memory 232816 kb
Host smart-ce01ed31-b68c-4cb7-a079-523a191a016f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861587743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2861587743
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1225425111
Short name T643
Test name
Test status
Simulation time 115165197 ps
CPU time 0.75 seconds
Started Jun 05 05:37:44 PM PDT 24
Finished Jun 05 05:37:46 PM PDT 24
Peak memory 205512 kb
Host smart-978f0029-4be0-46df-a843-d11019d02722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225425111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1225425111
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.407945049
Short name T777
Test name
Test status
Simulation time 158519427 ps
CPU time 2.87 seconds
Started Jun 05 05:37:35 PM PDT 24
Finished Jun 05 05:37:39 PM PDT 24
Peak memory 224668 kb
Host smart-47b2d40c-a3e8-4546-8eb0-c26c1227587e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407945049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.407945049
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1184457132
Short name T662
Test name
Test status
Simulation time 45657940 ps
CPU time 0.76 seconds
Started Jun 05 05:37:36 PM PDT 24
Finished Jun 05 05:37:38 PM PDT 24
Peak memory 206752 kb
Host smart-502cd788-a8f5-4c9b-a1c4-6045514ea890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184457132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1184457132
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2947654357
Short name T645
Test name
Test status
Simulation time 113030386 ps
CPU time 0.75 seconds
Started Jun 05 05:37:36 PM PDT 24
Finished Jun 05 05:37:38 PM PDT 24
Peak memory 216040 kb
Host smart-a8177d6a-1f93-4270-9436-3979a8f4c02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947654357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2947654357
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.766028372
Short name T352
Test name
Test status
Simulation time 14293865348 ps
CPU time 79.55 seconds
Started Jun 05 05:37:38 PM PDT 24
Finished Jun 05 05:38:58 PM PDT 24
Peak memory 249488 kb
Host smart-39d9e7e6-5d18-48fe-b772-a7f79dc965b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766028372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.766028372
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3321706659
Short name T862
Test name
Test status
Simulation time 5390263628 ps
CPU time 31.45 seconds
Started Jun 05 05:37:37 PM PDT 24
Finished Jun 05 05:38:09 PM PDT 24
Peak memory 217832 kb
Host smart-6fe50a21-3410-42a4-9dd1-41825aacd934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321706659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3321706659
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.504781324
Short name T279
Test name
Test status
Simulation time 7395942314 ps
CPU time 24.57 seconds
Started Jun 05 05:37:38 PM PDT 24
Finished Jun 05 05:38:03 PM PDT 24
Peak memory 238296 kb
Host smart-ad7776c3-5c31-4a35-a16c-07de8e11526b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504781324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.504781324
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.536213064
Short name T658
Test name
Test status
Simulation time 710119294 ps
CPU time 2.88 seconds
Started Jun 05 05:37:35 PM PDT 24
Finished Jun 05 05:37:38 PM PDT 24
Peak memory 224580 kb
Host smart-b65f83b3-829b-4c06-a879-9b81fa96d3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536213064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.536213064
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2606271469
Short name T163
Test name
Test status
Simulation time 21666441071 ps
CPU time 45.58 seconds
Started Jun 05 05:37:38 PM PDT 24
Finished Jun 05 05:38:24 PM PDT 24
Peak memory 224688 kb
Host smart-93ce1f22-5abd-4268-83ea-fefa4c7efe4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606271469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2606271469
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3723303633
Short name T843
Test name
Test status
Simulation time 38216439769 ps
CPU time 15.79 seconds
Started Jun 05 05:37:35 PM PDT 24
Finished Jun 05 05:37:52 PM PDT 24
Peak memory 224708 kb
Host smart-c0abb690-8623-419e-8aba-bf790e6cd917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723303633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3723303633
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3966089480
Short name T938
Test name
Test status
Simulation time 121986514 ps
CPU time 2.33 seconds
Started Jun 05 05:37:36 PM PDT 24
Finished Jun 05 05:37:39 PM PDT 24
Peak memory 222956 kb
Host smart-4876fbe4-03d1-428f-bf44-3050f07eb07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966089480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3966089480
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2183830903
Short name T317
Test name
Test status
Simulation time 307819593 ps
CPU time 3.26 seconds
Started Jun 05 05:37:35 PM PDT 24
Finished Jun 05 05:37:39 PM PDT 24
Peak memory 220204 kb
Host smart-47586d06-427f-4628-a686-fb126a991875
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2183830903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2183830903
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1470860301
Short name T527
Test name
Test status
Simulation time 12480815927 ps
CPU time 67.12 seconds
Started Jun 05 05:37:49 PM PDT 24
Finished Jun 05 05:38:56 PM PDT 24
Peak memory 250188 kb
Host smart-97720c7c-6d86-489b-b308-f837ba84d9ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470860301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1470860301
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.849013379
Short name T716
Test name
Test status
Simulation time 11409339506 ps
CPU time 28.29 seconds
Started Jun 05 05:37:37 PM PDT 24
Finished Jun 05 05:38:06 PM PDT 24
Peak memory 216520 kb
Host smart-6e64ef5b-2b8d-4e73-a7ee-a3ee0622830c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849013379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.849013379
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2736857846
Short name T365
Test name
Test status
Simulation time 5198546938 ps
CPU time 7.78 seconds
Started Jun 05 05:37:34 PM PDT 24
Finished Jun 05 05:37:43 PM PDT 24
Peak memory 216440 kb
Host smart-d5ed620d-fe10-4803-95df-59e7acd5c70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736857846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2736857846
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1669759747
Short name T355
Test name
Test status
Simulation time 12943478 ps
CPU time 0.75 seconds
Started Jun 05 05:37:35 PM PDT 24
Finished Jun 05 05:37:37 PM PDT 24
Peak memory 205952 kb
Host smart-d8ffe0e6-72bd-4ebd-a89e-1a33ee56579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669759747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1669759747
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.4051829103
Short name T940
Test name
Test status
Simulation time 13027802 ps
CPU time 0.7 seconds
Started Jun 05 05:37:36 PM PDT 24
Finished Jun 05 05:37:37 PM PDT 24
Peak memory 205948 kb
Host smart-dd6e97cd-5f40-4ef4-89c1-77b3ab65a347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051829103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4051829103
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1931418288
Short name T242
Test name
Test status
Simulation time 296838390 ps
CPU time 2.83 seconds
Started Jun 05 05:37:36 PM PDT 24
Finished Jun 05 05:37:40 PM PDT 24
Peak memory 232816 kb
Host smart-5e28f322-6930-4a5f-ac1e-d8293e2e36c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931418288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1931418288
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2878793733
Short name T382
Test name
Test status
Simulation time 17277184 ps
CPU time 0.71 seconds
Started Jun 05 05:37:42 PM PDT 24
Finished Jun 05 05:37:44 PM PDT 24
Peak memory 204992 kb
Host smart-986ed58b-6d26-4076-8a89-a2a7aedbe6cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878793733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2878793733
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.358380763
Short name T572
Test name
Test status
Simulation time 38024682 ps
CPU time 2.54 seconds
Started Jun 05 05:37:48 PM PDT 24
Finished Jun 05 05:37:51 PM PDT 24
Peak memory 232824 kb
Host smart-f60ab4fb-9f8b-40c8-8234-a0ade20f208f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358380763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.358380763
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.4212781846
Short name T440
Test name
Test status
Simulation time 13405293 ps
CPU time 0.77 seconds
Started Jun 05 05:37:43 PM PDT 24
Finished Jun 05 05:37:45 PM PDT 24
Peak memory 207096 kb
Host smart-3dcbf9a4-a0cb-4b94-9a80-4163aca7bb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212781846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.4212781846
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3670483359
Short name T186
Test name
Test status
Simulation time 7876208925 ps
CPU time 51.49 seconds
Started Jun 05 05:37:42 PM PDT 24
Finished Jun 05 05:38:34 PM PDT 24
Peak memory 249296 kb
Host smart-a4948b5c-e3b3-4fde-93dd-054a8d8ec4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670483359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3670483359
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2210367648
Short name T429
Test name
Test status
Simulation time 7090000309 ps
CPU time 50.18 seconds
Started Jun 05 05:37:41 PM PDT 24
Finished Jun 05 05:38:31 PM PDT 24
Peak memory 251100 kb
Host smart-4d321389-8bc9-4241-91d3-86567c91b82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210367648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2210367648
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2166364509
Short name T592
Test name
Test status
Simulation time 28672654275 ps
CPU time 23.07 seconds
Started Jun 05 05:37:43 PM PDT 24
Finished Jun 05 05:38:07 PM PDT 24
Peak memory 236868 kb
Host smart-aaf526ca-bf15-435b-9690-4f8715c513f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166364509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2166364509
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2760457739
Short name T134
Test name
Test status
Simulation time 819721075 ps
CPU time 11.01 seconds
Started Jun 05 05:37:46 PM PDT 24
Finished Jun 05 05:37:57 PM PDT 24
Peak memory 233356 kb
Host smart-7b6eced9-be15-485a-ba70-6cb97ac96e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760457739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2760457739
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3116495568
Short name T668
Test name
Test status
Simulation time 443796774 ps
CPU time 4.89 seconds
Started Jun 05 05:37:45 PM PDT 24
Finished Jun 05 05:37:51 PM PDT 24
Peak memory 224632 kb
Host smart-ead84d2b-457f-4b6c-bdc8-2b265d7192b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116495568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3116495568
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.4165594650
Short name T178
Test name
Test status
Simulation time 933808308 ps
CPU time 4.74 seconds
Started Jun 05 05:37:45 PM PDT 24
Finished Jun 05 05:37:50 PM PDT 24
Peak memory 232856 kb
Host smart-1bd1a8ef-ab35-402c-b415-39130ca0ca0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165594650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.4165594650
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1186301003
Short name T871
Test name
Test status
Simulation time 60091168513 ps
CPU time 16.3 seconds
Started Jun 05 05:37:46 PM PDT 24
Finished Jun 05 05:38:03 PM PDT 24
Peak memory 232856 kb
Host smart-053ae7a5-c107-4d2c-ba4c-093921694f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186301003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1186301003
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3403981330
Short name T436
Test name
Test status
Simulation time 117394941 ps
CPU time 2.41 seconds
Started Jun 05 05:37:48 PM PDT 24
Finished Jun 05 05:37:51 PM PDT 24
Peak memory 232684 kb
Host smart-2c049e5f-c38c-4aae-a775-38651f9dc9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403981330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3403981330
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2449697464
Short name T131
Test name
Test status
Simulation time 3265976911 ps
CPU time 12.1 seconds
Started Jun 05 05:37:43 PM PDT 24
Finished Jun 05 05:37:56 PM PDT 24
Peak memory 219108 kb
Host smart-30c9adae-b291-45bc-b9b0-48d40fa40406
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2449697464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2449697464
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3111696682
Short name T900
Test name
Test status
Simulation time 65125157698 ps
CPU time 32.06 seconds
Started Jun 05 05:37:42 PM PDT 24
Finished Jun 05 05:38:15 PM PDT 24
Peak memory 216452 kb
Host smart-9e2dcebd-9b10-4b1b-8a9c-858eb5415278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111696682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3111696682
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4221179874
Short name T727
Test name
Test status
Simulation time 541566553 ps
CPU time 2.44 seconds
Started Jun 05 05:37:46 PM PDT 24
Finished Jun 05 05:37:49 PM PDT 24
Peak memory 216208 kb
Host smart-7e6c1ffe-332b-4fff-ad82-47df078442b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221179874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4221179874
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2823941376
Short name T120
Test name
Test status
Simulation time 40202147 ps
CPU time 0.72 seconds
Started Jun 05 05:37:47 PM PDT 24
Finished Jun 05 05:37:48 PM PDT 24
Peak memory 205716 kb
Host smart-32ed7e8a-6633-4e5d-89a0-dd70cdbaf8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823941376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2823941376
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1626060923
Short name T326
Test name
Test status
Simulation time 422066284 ps
CPU time 0.82 seconds
Started Jun 05 05:37:45 PM PDT 24
Finished Jun 05 05:37:47 PM PDT 24
Peak memory 205988 kb
Host smart-64794d33-a874-4e59-9549-93ea9b9b7f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626060923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1626060923
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3021494205
Short name T498
Test name
Test status
Simulation time 11119288490 ps
CPU time 12.43 seconds
Started Jun 05 05:37:44 PM PDT 24
Finished Jun 05 05:37:57 PM PDT 24
Peak memory 224632 kb
Host smart-73662d34-0571-403b-81ef-c310d3c97a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021494205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3021494205
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.166851525
Short name T864
Test name
Test status
Simulation time 14325547 ps
CPU time 0.75 seconds
Started Jun 05 05:35:11 PM PDT 24
Finished Jun 05 05:35:13 PM PDT 24
Peak memory 205544 kb
Host smart-ba0bd45c-7633-495b-b0bf-8ff11e35ab55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166851525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.166851525
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1566768791
Short name T546
Test name
Test status
Simulation time 121877357 ps
CPU time 2.6 seconds
Started Jun 05 05:35:11 PM PDT 24
Finished Jun 05 05:35:15 PM PDT 24
Peak memory 224632 kb
Host smart-ffb62c9a-2f60-408a-bff4-39598380107e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566768791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1566768791
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2371619439
Short name T620
Test name
Test status
Simulation time 48322391 ps
CPU time 0.75 seconds
Started Jun 05 05:35:06 PM PDT 24
Finished Jun 05 05:35:07 PM PDT 24
Peak memory 206084 kb
Host smart-f8a9396d-7b61-443c-850a-64ddf07fd69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371619439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2371619439
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3883739628
Short name T922
Test name
Test status
Simulation time 7402135281 ps
CPU time 40.42 seconds
Started Jun 05 05:35:12 PM PDT 24
Finished Jun 05 05:35:53 PM PDT 24
Peak memory 257160 kb
Host smart-697121ce-ea2e-46e2-a94b-bb5a448aacdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883739628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3883739628
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4064476113
Short name T153
Test name
Test status
Simulation time 445588319086 ps
CPU time 325.93 seconds
Started Jun 05 05:35:14 PM PDT 24
Finished Jun 05 05:40:41 PM PDT 24
Peak memory 249400 kb
Host smart-a37389b5-d421-438d-b53d-c55773d7341b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064476113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4064476113
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3798058331
Short name T711
Test name
Test status
Simulation time 30270070758 ps
CPU time 38.37 seconds
Started Jun 05 05:35:13 PM PDT 24
Finished Jun 05 05:35:51 PM PDT 24
Peak memory 236252 kb
Host smart-82bc9647-8e56-419c-92dc-141660b99d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798058331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3798058331
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3302865511
Short name T898
Test name
Test status
Simulation time 430712340 ps
CPU time 8.18 seconds
Started Jun 05 05:35:11 PM PDT 24
Finished Jun 05 05:35:20 PM PDT 24
Peak memory 224656 kb
Host smart-3205f8c6-239b-4c6e-9c38-1edee8e9a2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302865511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3302865511
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2475682068
Short name T159
Test name
Test status
Simulation time 1089723204 ps
CPU time 13.48 seconds
Started Jun 05 05:35:11 PM PDT 24
Finished Jun 05 05:35:25 PM PDT 24
Peak memory 224600 kb
Host smart-176c0079-87ca-4aa3-a404-d6243d50a55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475682068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2475682068
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.598841165
Short name T432
Test name
Test status
Simulation time 366227880 ps
CPU time 2.96 seconds
Started Jun 05 05:35:11 PM PDT 24
Finished Jun 05 05:35:14 PM PDT 24
Peak memory 232804 kb
Host smart-16fb1028-673c-4831-8158-3497e061a8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598841165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.598841165
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3513655009
Short name T532
Test name
Test status
Simulation time 2857618608 ps
CPU time 4.61 seconds
Started Jun 05 05:35:11 PM PDT 24
Finished Jun 05 05:35:17 PM PDT 24
Peak memory 232892 kb
Host smart-1c307325-9cdf-4ec4-82ec-5c5b99c64c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513655009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3513655009
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2673724194
Short name T391
Test name
Test status
Simulation time 2068997637 ps
CPU time 9.66 seconds
Started Jun 05 05:35:12 PM PDT 24
Finished Jun 05 05:35:22 PM PDT 24
Peak memory 240836 kb
Host smart-59551d53-49d3-4118-9489-942f093eabfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673724194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2673724194
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.512968251
Short name T343
Test name
Test status
Simulation time 3776105920 ps
CPU time 11.83 seconds
Started Jun 05 05:35:12 PM PDT 24
Finished Jun 05 05:35:24 PM PDT 24
Peak memory 220672 kb
Host smart-1f38e3fa-e9a4-48ba-9998-87f09d6027c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=512968251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.512968251
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4174454549
Short name T52
Test name
Test status
Simulation time 641229133 ps
CPU time 1.17 seconds
Started Jun 05 05:35:11 PM PDT 24
Finished Jun 05 05:35:13 PM PDT 24
Peak memory 235180 kb
Host smart-bb15e30d-9fdd-4e1b-b140-c028c2ccfeed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174454549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4174454549
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.883685946
Short name T128
Test name
Test status
Simulation time 12570306420 ps
CPU time 253.53 seconds
Started Jun 05 05:35:15 PM PDT 24
Finished Jun 05 05:39:29 PM PDT 24
Peak memory 288368 kb
Host smart-865e3111-1a5b-4e70-bf7d-59758e897a71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883685946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.883685946
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3014298346
Short name T501
Test name
Test status
Simulation time 2016173196 ps
CPU time 10.61 seconds
Started Jun 05 05:35:04 PM PDT 24
Finished Jun 05 05:35:15 PM PDT 24
Peak memory 216644 kb
Host smart-c6065693-d77d-40da-ab81-c4f62cf76d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014298346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3014298346
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.122178647
Short name T837
Test name
Test status
Simulation time 1612784498 ps
CPU time 8.7 seconds
Started Jun 05 05:35:04 PM PDT 24
Finished Jun 05 05:35:13 PM PDT 24
Peak memory 216328 kb
Host smart-54a146ba-1845-4d25-b92a-276c26437e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122178647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.122178647
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1690995740
Short name T499
Test name
Test status
Simulation time 106630819 ps
CPU time 1.39 seconds
Started Jun 05 05:35:14 PM PDT 24
Finished Jun 05 05:35:16 PM PDT 24
Peak memory 216432 kb
Host smart-3f04ce19-4aa8-40ec-b1b7-15ac705ce570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690995740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1690995740
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.292138494
Short name T5
Test name
Test status
Simulation time 48688332 ps
CPU time 0.75 seconds
Started Jun 05 05:35:05 PM PDT 24
Finished Jun 05 05:35:07 PM PDT 24
Peak memory 205952 kb
Host smart-faaff0c9-23da-461e-8fc2-6a9c95f8ddbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292138494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.292138494
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1718068395
Short name T246
Test name
Test status
Simulation time 4822695069 ps
CPU time 6.16 seconds
Started Jun 05 05:35:11 PM PDT 24
Finished Jun 05 05:35:18 PM PDT 24
Peak memory 232844 kb
Host smart-b8bf130c-d4c2-4b56-99a7-be5ccd75e465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718068395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1718068395
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1026917877
Short name T368
Test name
Test status
Simulation time 12779327 ps
CPU time 0.75 seconds
Started Jun 05 05:37:48 PM PDT 24
Finished Jun 05 05:37:49 PM PDT 24
Peak memory 204980 kb
Host smart-87732e04-a794-48de-a9a6-037b1dedf63d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026917877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1026917877
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.4193157919
Short name T70
Test name
Test status
Simulation time 141912323 ps
CPU time 3.33 seconds
Started Jun 05 05:37:41 PM PDT 24
Finished Jun 05 05:37:45 PM PDT 24
Peak memory 232812 kb
Host smart-86918989-f6e1-4865-99bf-863a1985aecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193157919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4193157919
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2526151632
Short name T746
Test name
Test status
Simulation time 59127685 ps
CPU time 0.8 seconds
Started Jun 05 05:37:46 PM PDT 24
Finished Jun 05 05:37:47 PM PDT 24
Peak memory 206732 kb
Host smart-20a8d638-1380-46bf-a643-77f3a7e8ecfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526151632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2526151632
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2060140611
Short name T531
Test name
Test status
Simulation time 2308848905 ps
CPU time 20.41 seconds
Started Jun 05 05:37:46 PM PDT 24
Finished Jun 05 05:38:07 PM PDT 24
Peak memory 236220 kb
Host smart-69a5cdb0-3b6f-4b40-9c94-5c734f31d062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060140611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2060140611
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2462205947
Short name T516
Test name
Test status
Simulation time 804551548 ps
CPU time 16.02 seconds
Started Jun 05 05:37:43 PM PDT 24
Finished Jun 05 05:37:59 PM PDT 24
Peak memory 249304 kb
Host smart-adeb94ab-e96e-40fa-9e73-4f7e8ba7c5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462205947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2462205947
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.548381071
Short name T283
Test name
Test status
Simulation time 88506894724 ps
CPU time 307.91 seconds
Started Jun 05 05:37:42 PM PDT 24
Finished Jun 05 05:42:51 PM PDT 24
Peak memory 249320 kb
Host smart-5f207605-93c9-44a7-9da2-fee1ed837ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548381071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.548381071
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3808337181
Short name T272
Test name
Test status
Simulation time 340095609 ps
CPU time 6.98 seconds
Started Jun 05 05:37:43 PM PDT 24
Finished Jun 05 05:37:51 PM PDT 24
Peak memory 232828 kb
Host smart-78bad7d2-eeb1-4108-9b74-d51b1a105f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808337181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3808337181
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1926902842
Short name T772
Test name
Test status
Simulation time 385535068 ps
CPU time 3.68 seconds
Started Jun 05 05:37:44 PM PDT 24
Finished Jun 05 05:37:48 PM PDT 24
Peak memory 228008 kb
Host smart-6eefd8b8-c985-4f63-8f7b-5b17f093ab97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926902842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1926902842
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1755688815
Short name T883
Test name
Test status
Simulation time 24333014798 ps
CPU time 124.49 seconds
Started Jun 05 05:37:44 PM PDT 24
Finished Jun 05 05:39:49 PM PDT 24
Peak memory 232820 kb
Host smart-6e2ba889-bbaf-4340-b17d-9ddc336c305c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755688815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1755688815
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.554551726
Short name T211
Test name
Test status
Simulation time 4091560295 ps
CPU time 13.87 seconds
Started Jun 05 05:37:41 PM PDT 24
Finished Jun 05 05:37:55 PM PDT 24
Peak memory 232804 kb
Host smart-7e2d6db7-8d35-43dc-97ed-d925341c6583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554551726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.554551726
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4190576946
Short name T507
Test name
Test status
Simulation time 1883380136 ps
CPU time 7.57 seconds
Started Jun 05 05:37:43 PM PDT 24
Finished Jun 05 05:37:51 PM PDT 24
Peak memory 232804 kb
Host smart-322ac3e9-c510-407c-9e36-952ce79bb821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190576946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4190576946
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.593988811
Short name T483
Test name
Test status
Simulation time 5632189918 ps
CPU time 15.82 seconds
Started Jun 05 05:37:46 PM PDT 24
Finished Jun 05 05:38:03 PM PDT 24
Peak memory 219028 kb
Host smart-8cbfde6b-67ac-45de-8209-e2978c02ed85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=593988811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.593988811
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2016098164
Short name T144
Test name
Test status
Simulation time 47553135198 ps
CPU time 266.22 seconds
Started Jun 05 05:37:48 PM PDT 24
Finished Jun 05 05:42:15 PM PDT 24
Peak memory 272392 kb
Host smart-82a7ebb3-8492-4a24-96c2-c46792d505e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016098164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2016098164
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2438486000
Short name T797
Test name
Test status
Simulation time 17275986393 ps
CPU time 26.48 seconds
Started Jun 05 05:37:44 PM PDT 24
Finished Jun 05 05:38:11 PM PDT 24
Peak memory 216448 kb
Host smart-f6c5a6f7-1a8e-4250-912c-a59a769f32ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438486000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2438486000
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1398591302
Short name T547
Test name
Test status
Simulation time 3233059063 ps
CPU time 2.95 seconds
Started Jun 05 05:37:44 PM PDT 24
Finished Jun 05 05:37:48 PM PDT 24
Peak memory 216268 kb
Host smart-7b5f7828-48f7-40ca-b095-9a81acd755aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398591302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1398591302
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2471265913
Short name T936
Test name
Test status
Simulation time 104201137 ps
CPU time 1.29 seconds
Started Jun 05 05:37:44 PM PDT 24
Finished Jun 05 05:37:46 PM PDT 24
Peak memory 208240 kb
Host smart-73ea0030-fb6c-4b96-8af2-b3dd4d11bc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471265913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2471265913
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2093541742
Short name T525
Test name
Test status
Simulation time 173238550 ps
CPU time 0.89 seconds
Started Jun 05 05:37:45 PM PDT 24
Finished Jun 05 05:37:47 PM PDT 24
Peak memory 207000 kb
Host smart-fe11ede5-2625-4e9f-b64c-993e506e1171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093541742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2093541742
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2578810376
Short name T764
Test name
Test status
Simulation time 769688570 ps
CPU time 2.34 seconds
Started Jun 05 05:37:44 PM PDT 24
Finished Jun 05 05:37:47 PM PDT 24
Peak memory 223176 kb
Host smart-8d50f139-94ce-41cc-9311-6283aa77e813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578810376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2578810376
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3052537867
Short name T438
Test name
Test status
Simulation time 10846164 ps
CPU time 0.73 seconds
Started Jun 05 05:37:50 PM PDT 24
Finished Jun 05 05:37:52 PM PDT 24
Peak memory 205880 kb
Host smart-338cf203-d119-4ef5-bdce-6416f6485696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052537867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3052537867
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3372542118
Short name T53
Test name
Test status
Simulation time 37421056 ps
CPU time 2.3 seconds
Started Jun 05 05:37:47 PM PDT 24
Finished Jun 05 05:37:50 PM PDT 24
Peak memory 224476 kb
Host smart-67074fc5-8e22-4ed2-aa4d-92aa52c47442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372542118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3372542118
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.498816151
Short name T619
Test name
Test status
Simulation time 65338969 ps
CPU time 0.81 seconds
Started Jun 05 05:37:45 PM PDT 24
Finished Jun 05 05:37:46 PM PDT 24
Peak memory 206740 kb
Host smart-4c19d60a-2e4e-48bc-b04c-19bc8505c63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498816151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.498816151
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2687019787
Short name T443
Test name
Test status
Simulation time 370938701 ps
CPU time 4.43 seconds
Started Jun 05 05:37:49 PM PDT 24
Finished Jun 05 05:37:53 PM PDT 24
Peak memory 224608 kb
Host smart-aa3c1ce0-3fb9-4f4e-abd5-a6da3b83d4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687019787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2687019787
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.777326809
Short name T183
Test name
Test status
Simulation time 73289187316 ps
CPU time 364.82 seconds
Started Jun 05 05:37:49 PM PDT 24
Finished Jun 05 05:43:54 PM PDT 24
Peak memory 249376 kb
Host smart-f352aed0-14db-416c-bf3c-fcab1d6a1866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777326809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.777326809
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3280549797
Short name T510
Test name
Test status
Simulation time 78845481865 ps
CPU time 68.75 seconds
Started Jun 05 05:37:49 PM PDT 24
Finished Jun 05 05:38:59 PM PDT 24
Peak memory 250400 kb
Host smart-5cc95278-77fb-4a8e-8873-8c4a850a7fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280549797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3280549797
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2495164879
Short name T258
Test name
Test status
Simulation time 588662053 ps
CPU time 10.12 seconds
Started Jun 05 05:37:47 PM PDT 24
Finished Jun 05 05:37:58 PM PDT 24
Peak memory 241040 kb
Host smart-e7ccb3f2-6d4c-4444-9b07-feaaba586d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495164879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2495164879
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1136085113
Short name T166
Test name
Test status
Simulation time 1614689867 ps
CPU time 4.77 seconds
Started Jun 05 05:37:46 PM PDT 24
Finished Jun 05 05:37:51 PM PDT 24
Peak memory 232804 kb
Host smart-066cf4cd-b3e8-4d8f-92a6-d2052b7ad21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136085113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1136085113
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1713026966
Short name T433
Test name
Test status
Simulation time 29914964 ps
CPU time 2.45 seconds
Started Jun 05 05:37:44 PM PDT 24
Finished Jun 05 05:37:47 PM PDT 24
Peak memory 226820 kb
Host smart-26a4c667-f3f7-4261-96b3-febbd1721c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713026966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1713026966
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1620565825
Short name T907
Test name
Test status
Simulation time 135610456 ps
CPU time 3.41 seconds
Started Jun 05 05:37:48 PM PDT 24
Finished Jun 05 05:37:52 PM PDT 24
Peak memory 224552 kb
Host smart-aff09945-8514-4253-a87b-4cf2e75bcef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620565825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1620565825
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.447822777
Short name T503
Test name
Test status
Simulation time 14903960880 ps
CPU time 13.11 seconds
Started Jun 05 05:37:45 PM PDT 24
Finished Jun 05 05:37:59 PM PDT 24
Peak memory 240872 kb
Host smart-47147ff7-bc1a-4fe7-8800-987812883c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447822777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.447822777
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1082357247
Short name T133
Test name
Test status
Simulation time 2196784411 ps
CPU time 4.51 seconds
Started Jun 05 05:37:45 PM PDT 24
Finished Jun 05 05:37:50 PM PDT 24
Peak memory 223116 kb
Host smart-de228125-df14-414c-8fb0-37803649289c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1082357247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1082357247
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3002415890
Short name T935
Test name
Test status
Simulation time 13348835811 ps
CPU time 91.17 seconds
Started Jun 05 05:37:49 PM PDT 24
Finished Jun 05 05:39:21 PM PDT 24
Peak memory 252772 kb
Host smart-20acd11f-4c99-4902-b72a-c82711d412d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002415890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3002415890
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2178627583
Short name T895
Test name
Test status
Simulation time 2934296992 ps
CPU time 24.05 seconds
Started Jun 05 05:37:48 PM PDT 24
Finished Jun 05 05:38:12 PM PDT 24
Peak memory 216816 kb
Host smart-b5835772-c792-4703-8849-89fd69783e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178627583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2178627583
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2990230781
Short name T441
Test name
Test status
Simulation time 258858487 ps
CPU time 1.88 seconds
Started Jun 05 05:37:44 PM PDT 24
Finished Jun 05 05:37:47 PM PDT 24
Peak memory 207112 kb
Host smart-d3bb482c-96a8-4ac0-83ed-b6f6554462ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990230781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2990230781
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3786941594
Short name T657
Test name
Test status
Simulation time 511704444 ps
CPU time 1.74 seconds
Started Jun 05 05:37:46 PM PDT 24
Finished Jun 05 05:37:48 PM PDT 24
Peak memory 216480 kb
Host smart-db19b1a3-4b01-43cf-a721-218010fc8802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786941594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3786941594
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.264050359
Short name T354
Test name
Test status
Simulation time 1008088705 ps
CPU time 0.87 seconds
Started Jun 05 05:37:41 PM PDT 24
Finished Jun 05 05:37:42 PM PDT 24
Peak memory 205988 kb
Host smart-727e3070-4ae8-4a84-bae6-c3672edbcd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264050359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.264050359
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.260046428
Short name T83
Test name
Test status
Simulation time 521093787 ps
CPU time 3.94 seconds
Started Jun 05 05:37:45 PM PDT 24
Finished Jun 05 05:37:50 PM PDT 24
Peak memory 232828 kb
Host smart-a38d83b2-b74a-4002-92b0-94afc2c79a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260046428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.260046428
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2549209787
Short name T723
Test name
Test status
Simulation time 33306704 ps
CPU time 0.72 seconds
Started Jun 05 05:37:55 PM PDT 24
Finished Jun 05 05:37:57 PM PDT 24
Peak memory 205488 kb
Host smart-a109fbd1-80b1-4016-8d25-1d241f6e4b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549209787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2549209787
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2351863626
Short name T72
Test name
Test status
Simulation time 307636082 ps
CPU time 2.95 seconds
Started Jun 05 05:37:51 PM PDT 24
Finished Jun 05 05:37:54 PM PDT 24
Peak memory 224640 kb
Host smart-fd8b7205-337f-47dc-9459-feba027c786c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351863626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2351863626
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2411230106
Short name T660
Test name
Test status
Simulation time 14522657 ps
CPU time 0.78 seconds
Started Jun 05 05:37:51 PM PDT 24
Finished Jun 05 05:37:52 PM PDT 24
Peak memory 206744 kb
Host smart-48db6648-0e08-413e-94a8-a36d2b43a64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411230106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2411230106
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3334480151
Short name T69
Test name
Test status
Simulation time 3778197662 ps
CPU time 35.38 seconds
Started Jun 05 05:37:48 PM PDT 24
Finished Jun 05 05:38:24 PM PDT 24
Peak memory 241104 kb
Host smart-a7517bd4-4aae-4a86-bc76-37007a79a3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334480151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3334480151
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3619871699
Short name T253
Test name
Test status
Simulation time 19291872062 ps
CPU time 98.71 seconds
Started Jun 05 05:37:57 PM PDT 24
Finished Jun 05 05:39:36 PM PDT 24
Peak memory 249328 kb
Host smart-0019dc22-aba4-40a2-8fd1-8fd74f9ad34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619871699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3619871699
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1347309456
Short name T85
Test name
Test status
Simulation time 18286805151 ps
CPU time 146.76 seconds
Started Jun 05 05:37:58 PM PDT 24
Finished Jun 05 05:40:25 PM PDT 24
Peak memory 252432 kb
Host smart-b012f3d1-dfa1-4efb-bd9a-907b62c1629a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347309456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1347309456
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3892938442
Short name T274
Test name
Test status
Simulation time 3119102591 ps
CPU time 8.54 seconds
Started Jun 05 05:37:50 PM PDT 24
Finished Jun 05 05:37:59 PM PDT 24
Peak memory 232948 kb
Host smart-15e892b7-fc8d-4a83-b641-5b67fc08a187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892938442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3892938442
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3482714149
Short name T690
Test name
Test status
Simulation time 7430862283 ps
CPU time 13.3 seconds
Started Jun 05 05:37:54 PM PDT 24
Finished Jun 05 05:38:07 PM PDT 24
Peak memory 232792 kb
Host smart-75824591-a909-431b-896c-bae5c53f9106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482714149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3482714149
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3443489865
Short name T184
Test name
Test status
Simulation time 7288537224 ps
CPU time 54.31 seconds
Started Jun 05 05:37:48 PM PDT 24
Finished Jun 05 05:38:43 PM PDT 24
Peak memory 232884 kb
Host smart-33fec126-4559-451d-9aa1-390b62b76c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443489865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3443489865
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.62876106
Short name T205
Test name
Test status
Simulation time 2652805654 ps
CPU time 9.17 seconds
Started Jun 05 05:37:51 PM PDT 24
Finished Jun 05 05:38:00 PM PDT 24
Peak memory 224652 kb
Host smart-0d002396-bedd-4bed-b4b0-09522789e71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62876106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.62876106
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1535862665
Short name T726
Test name
Test status
Simulation time 17569730863 ps
CPU time 26.57 seconds
Started Jun 05 05:37:50 PM PDT 24
Finished Jun 05 05:38:17 PM PDT 24
Peak memory 224752 kb
Host smart-0fe1d215-6ad9-4591-b793-a55868ea8204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535862665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1535862665
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2748511494
Short name T954
Test name
Test status
Simulation time 952770202 ps
CPU time 7.1 seconds
Started Jun 05 05:37:51 PM PDT 24
Finished Jun 05 05:37:58 PM PDT 24
Peak memory 223112 kb
Host smart-b15c18ce-f234-4e3a-922c-81df56ab952b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2748511494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2748511494
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3354873945
Short name T46
Test name
Test status
Simulation time 63945715 ps
CPU time 1.09 seconds
Started Jun 05 05:38:00 PM PDT 24
Finished Jun 05 05:38:02 PM PDT 24
Peak memory 207108 kb
Host smart-d7043cab-f765-41bf-9db3-58c1451ea996
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354873945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3354873945
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1151998339
Short name T412
Test name
Test status
Simulation time 1802055863 ps
CPU time 18.04 seconds
Started Jun 05 05:37:49 PM PDT 24
Finished Jun 05 05:38:07 PM PDT 24
Peak memory 219468 kb
Host smart-e47b06a2-ae62-48dd-8715-b323be3e8c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151998339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1151998339
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3127646693
Short name T472
Test name
Test status
Simulation time 2050861790 ps
CPU time 6.38 seconds
Started Jun 05 05:37:47 PM PDT 24
Finished Jun 05 05:37:54 PM PDT 24
Peak memory 216640 kb
Host smart-c43ffc32-a0f1-405f-a29a-aff3c5867829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127646693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3127646693
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3454134515
Short name T861
Test name
Test status
Simulation time 693016246 ps
CPU time 2.12 seconds
Started Jun 05 05:37:54 PM PDT 24
Finished Jun 05 05:37:57 PM PDT 24
Peak memory 216448 kb
Host smart-727a1307-cbc5-446a-9ef6-5f152bc35d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454134515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3454134515
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2953885548
Short name T671
Test name
Test status
Simulation time 29080812 ps
CPU time 0.85 seconds
Started Jun 05 05:37:52 PM PDT 24
Finished Jun 05 05:37:53 PM PDT 24
Peak memory 205984 kb
Host smart-fec07829-0409-4abe-acd3-af08b7e297cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953885548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2953885548
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.4190472738
Short name T785
Test name
Test status
Simulation time 2207431278 ps
CPU time 3.79 seconds
Started Jun 05 05:37:54 PM PDT 24
Finished Jun 05 05:37:58 PM PDT 24
Peak memory 224564 kb
Host smart-0fddf91d-ce47-44a4-8491-5dd9785fc1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190472738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4190472738
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1926137347
Short name T950
Test name
Test status
Simulation time 13500119 ps
CPU time 0.7 seconds
Started Jun 05 05:38:05 PM PDT 24
Finished Jun 05 05:38:06 PM PDT 24
Peak memory 204952 kb
Host smart-c5808921-231b-4ab4-80db-22cd0db5e44e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926137347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1926137347
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2383493685
Short name T738
Test name
Test status
Simulation time 3151520362 ps
CPU time 23.01 seconds
Started Jun 05 05:37:56 PM PDT 24
Finished Jun 05 05:38:20 PM PDT 24
Peak memory 224744 kb
Host smart-de5f52a1-c62e-41c7-bbef-4cf777f5d451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383493685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2383493685
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.242009052
Short name T540
Test name
Test status
Simulation time 38990832 ps
CPU time 0.78 seconds
Started Jun 05 05:37:56 PM PDT 24
Finished Jun 05 05:37:58 PM PDT 24
Peak memory 206768 kb
Host smart-2667ad5e-1d7e-4b1c-9941-0f63b1f72264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242009052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.242009052
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1347104494
Short name T836
Test name
Test status
Simulation time 14562162671 ps
CPU time 115.03 seconds
Started Jun 05 05:37:58 PM PDT 24
Finished Jun 05 05:39:54 PM PDT 24
Peak memory 249768 kb
Host smart-1228e365-fd7c-4c1a-aa12-46da37a870d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347104494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1347104494
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3908367849
Short name T225
Test name
Test status
Simulation time 29482765372 ps
CPU time 96.79 seconds
Started Jun 05 05:37:57 PM PDT 24
Finished Jun 05 05:39:35 PM PDT 24
Peak memory 250832 kb
Host smart-7be6db38-ce4d-40b5-95a7-f52d9fdc152b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908367849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3908367849
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2301568373
Short name T206
Test name
Test status
Simulation time 37015325726 ps
CPU time 49.2 seconds
Started Jun 05 05:37:55 PM PDT 24
Finished Jun 05 05:38:45 PM PDT 24
Peak memory 241152 kb
Host smart-aeca1f5b-bfbc-45f8-a132-a2b0053ee63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301568373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2301568373
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3264906033
Short name T278
Test name
Test status
Simulation time 594085878 ps
CPU time 12.99 seconds
Started Jun 05 05:37:58 PM PDT 24
Finished Jun 05 05:38:12 PM PDT 24
Peak memory 235608 kb
Host smart-cfbe0990-b261-42df-b55a-a74aaf0ab3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264906033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3264906033
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2708829724
Short name T568
Test name
Test status
Simulation time 433386443 ps
CPU time 5.23 seconds
Started Jun 05 05:37:57 PM PDT 24
Finished Jun 05 05:38:04 PM PDT 24
Peak memory 224596 kb
Host smart-e20fc0ff-4f8c-4df9-b467-48d4cc704473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708829724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2708829724
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2725615255
Short name T336
Test name
Test status
Simulation time 2520571297 ps
CPU time 11.37 seconds
Started Jun 05 05:37:57 PM PDT 24
Finished Jun 05 05:38:09 PM PDT 24
Peak memory 224628 kb
Host smart-67a6fe30-a3dc-4b8f-b19a-bc1f7dae615c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725615255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2725615255
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2039781386
Short name T565
Test name
Test status
Simulation time 1927096684 ps
CPU time 9.23 seconds
Started Jun 05 05:37:57 PM PDT 24
Finished Jun 05 05:38:07 PM PDT 24
Peak memory 232848 kb
Host smart-c33357bd-a02f-4a22-8472-41be268bdea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039781386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2039781386
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2459977725
Short name T640
Test name
Test status
Simulation time 2474452604 ps
CPU time 7.88 seconds
Started Jun 05 05:37:57 PM PDT 24
Finished Jun 05 05:38:06 PM PDT 24
Peak memory 232952 kb
Host smart-841a12f1-4154-49e9-965d-736d4da1c41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459977725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2459977725
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3540112175
Short name T345
Test name
Test status
Simulation time 6892973899 ps
CPU time 10.94 seconds
Started Jun 05 05:37:57 PM PDT 24
Finished Jun 05 05:38:09 PM PDT 24
Peak memory 223292 kb
Host smart-3d9268b3-26c5-47db-a8f2-812f7a3fcc5c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3540112175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3540112175
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.102667821
Short name T926
Test name
Test status
Simulation time 1786380930 ps
CPU time 7.52 seconds
Started Jun 05 05:38:00 PM PDT 24
Finished Jun 05 05:38:09 PM PDT 24
Peak memory 219800 kb
Host smart-9afee41b-0f63-4ace-a414-dc1ba4c89b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102667821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.102667821
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.255625257
Short name T813
Test name
Test status
Simulation time 11678294 ps
CPU time 0.71 seconds
Started Jun 05 05:37:57 PM PDT 24
Finished Jun 05 05:37:59 PM PDT 24
Peak memory 205812 kb
Host smart-077f87ab-2334-4ce1-a4df-1159a74eff49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255625257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.255625257
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4072920033
Short name T426
Test name
Test status
Simulation time 11893656 ps
CPU time 0.7 seconds
Started Jun 05 05:37:59 PM PDT 24
Finished Jun 05 05:38:01 PM PDT 24
Peak memory 205688 kb
Host smart-e08867e0-f0d6-42cd-ad55-74206a2b0d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072920033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4072920033
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1562074113
Short name T582
Test name
Test status
Simulation time 26532118 ps
CPU time 0.75 seconds
Started Jun 05 05:38:00 PM PDT 24
Finished Jun 05 05:38:02 PM PDT 24
Peak memory 205772 kb
Host smart-10e172a7-7354-4e7c-b637-0e703e5becdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562074113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1562074113
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3952878642
Short name T481
Test name
Test status
Simulation time 3657273393 ps
CPU time 6.93 seconds
Started Jun 05 05:37:58 PM PDT 24
Finished Jun 05 05:38:06 PM PDT 24
Peak memory 224732 kb
Host smart-6b8c845e-c74c-46e0-aa38-c4e5ebdbb6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952878642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3952878642
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3232888357
Short name T419
Test name
Test status
Simulation time 20773608 ps
CPU time 0.74 seconds
Started Jun 05 05:38:05 PM PDT 24
Finished Jun 05 05:38:07 PM PDT 24
Peak memory 205500 kb
Host smart-60f833b3-0e71-4a14-bed8-487859cbc0d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232888357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3232888357
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3045699409
Short name T749
Test name
Test status
Simulation time 5048010591 ps
CPU time 13.59 seconds
Started Jun 05 05:38:04 PM PDT 24
Finished Jun 05 05:38:19 PM PDT 24
Peak memory 224688 kb
Host smart-ee60f01f-8f98-4b8f-924e-9516780219e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045699409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3045699409
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2247727663
Short name T579
Test name
Test status
Simulation time 18979555 ps
CPU time 0.74 seconds
Started Jun 05 05:38:08 PM PDT 24
Finished Jun 05 05:38:09 PM PDT 24
Peak memory 205728 kb
Host smart-4256fc84-a8bd-402b-918f-c1717b6a7e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247727663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2247727663
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2987777898
Short name T252
Test name
Test status
Simulation time 11289258063 ps
CPU time 34.09 seconds
Started Jun 05 05:38:08 PM PDT 24
Finished Jun 05 05:38:43 PM PDT 24
Peak memory 249308 kb
Host smart-39ebc524-ad97-4585-9de3-6792d509aa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987777898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2987777898
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.804677471
Short name T407
Test name
Test status
Simulation time 16900787711 ps
CPU time 180.98 seconds
Started Jun 05 05:38:06 PM PDT 24
Finished Jun 05 05:41:08 PM PDT 24
Peak memory 250376 kb
Host smart-da8e9ffc-7f56-4ffe-99f0-d266672b8e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804677471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.804677471
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2849294081
Short name T628
Test name
Test status
Simulation time 2351426245 ps
CPU time 55.4 seconds
Started Jun 05 05:38:06 PM PDT 24
Finished Jun 05 05:39:02 PM PDT 24
Peak memory 250940 kb
Host smart-3ad6b118-7c94-4c02-be73-d108946c77b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849294081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2849294081
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1268436218
Short name T859
Test name
Test status
Simulation time 110216219 ps
CPU time 5.69 seconds
Started Jun 05 05:38:06 PM PDT 24
Finished Jun 05 05:38:12 PM PDT 24
Peak memory 224616 kb
Host smart-f14791e6-57a8-40e6-bc53-913cc4b8a144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268436218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1268436218
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1756383671
Short name T75
Test name
Test status
Simulation time 1211091849 ps
CPU time 4.37 seconds
Started Jun 05 05:38:03 PM PDT 24
Finished Jun 05 05:38:09 PM PDT 24
Peak memory 232884 kb
Host smart-15e2904f-b1ba-4161-baa8-f4996775836a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756383671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1756383671
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2854589941
Short name T495
Test name
Test status
Simulation time 2678630650 ps
CPU time 7.46 seconds
Started Jun 05 05:38:05 PM PDT 24
Finished Jun 05 05:38:13 PM PDT 24
Peak memory 232896 kb
Host smart-7b77163e-3873-434c-a555-9205ef8fbd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854589941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2854589941
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1603730608
Short name T154
Test name
Test status
Simulation time 188162909 ps
CPU time 4.19 seconds
Started Jun 05 05:38:06 PM PDT 24
Finished Jun 05 05:38:11 PM PDT 24
Peak memory 224652 kb
Host smart-836a5d27-5952-424f-983d-4728402c0af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603730608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1603730608
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1963067506
Short name T534
Test name
Test status
Simulation time 1292345308 ps
CPU time 6.5 seconds
Started Jun 05 05:38:03 PM PDT 24
Finished Jun 05 05:38:11 PM PDT 24
Peak memory 222636 kb
Host smart-19af3746-71ce-489a-b50c-88ee92a0355a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1963067506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1963067506
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3377296595
Short name T287
Test name
Test status
Simulation time 717565780 ps
CPU time 4.65 seconds
Started Jun 05 05:38:08 PM PDT 24
Finished Jun 05 05:38:13 PM PDT 24
Peak memory 216448 kb
Host smart-5946f7dd-94bd-45af-9bdd-cc84b8be2bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377296595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3377296595
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2093540208
Short name T469
Test name
Test status
Simulation time 10415776272 ps
CPU time 8.78 seconds
Started Jun 05 05:38:06 PM PDT 24
Finished Jun 05 05:38:16 PM PDT 24
Peak memory 216408 kb
Host smart-b1d5bb63-7f53-4a98-9589-65708ace2e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093540208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2093540208
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1550027524
Short name T309
Test name
Test status
Simulation time 45604660 ps
CPU time 0.77 seconds
Started Jun 05 05:38:04 PM PDT 24
Finished Jun 05 05:38:06 PM PDT 24
Peak memory 205960 kb
Host smart-18ddbdfd-5f2b-4689-9b6c-060221e441e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550027524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1550027524
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3013704921
Short name T786
Test name
Test status
Simulation time 16260918 ps
CPU time 0.74 seconds
Started Jun 05 05:38:04 PM PDT 24
Finished Jun 05 05:38:06 PM PDT 24
Peak memory 206012 kb
Host smart-e21db681-509d-4251-bb2a-d30743e7f659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013704921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3013704921
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3433337172
Short name T148
Test name
Test status
Simulation time 1140734276 ps
CPU time 3.14 seconds
Started Jun 05 05:38:05 PM PDT 24
Finished Jun 05 05:38:09 PM PDT 24
Peak memory 232860 kb
Host smart-9200d9af-43af-44bf-af64-69158027bec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433337172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3433337172
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3174983272
Short name T529
Test name
Test status
Simulation time 12051958 ps
CPU time 0.74 seconds
Started Jun 05 05:38:13 PM PDT 24
Finished Jun 05 05:38:14 PM PDT 24
Peak memory 204996 kb
Host smart-25477fba-197c-4b9a-a8ab-d5cdfc509922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174983272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3174983272
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2653322664
Short name T728
Test name
Test status
Simulation time 75900566 ps
CPU time 2.26 seconds
Started Jun 05 05:38:04 PM PDT 24
Finished Jun 05 05:38:08 PM PDT 24
Peak memory 224032 kb
Host smart-eb5cbd1a-2f01-41e1-942d-7cbf4d8d7319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653322664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2653322664
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3190043344
Short name T327
Test name
Test status
Simulation time 17773092 ps
CPU time 0.8 seconds
Started Jun 05 05:38:05 PM PDT 24
Finished Jun 05 05:38:07 PM PDT 24
Peak memory 205920 kb
Host smart-2a9f244b-14ce-44c3-9e58-15abea4b6bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190043344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3190043344
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1474604102
Short name T260
Test name
Test status
Simulation time 17661621763 ps
CPU time 120.49 seconds
Started Jun 05 05:38:12 PM PDT 24
Finished Jun 05 05:40:13 PM PDT 24
Peak memory 241132 kb
Host smart-b5d1be69-c1f8-4c7e-aa87-76bf9910f144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474604102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1474604102
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3040041612
Short name T250
Test name
Test status
Simulation time 304373877598 ps
CPU time 734.94 seconds
Started Jun 05 05:38:11 PM PDT 24
Finished Jun 05 05:50:26 PM PDT 24
Peak memory 267260 kb
Host smart-ee0535da-1085-49a0-beda-fb8b20663d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040041612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3040041612
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.4230929666
Short name T528
Test name
Test status
Simulation time 7558744771 ps
CPU time 27.9 seconds
Started Jun 05 05:38:05 PM PDT 24
Finished Jun 05 05:38:34 PM PDT 24
Peak memory 232844 kb
Host smart-3676439e-e9ac-4c9e-9963-e85c9de9d5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230929666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4230929666
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.160582532
Short name T825
Test name
Test status
Simulation time 1347797102 ps
CPU time 3.62 seconds
Started Jun 05 05:38:06 PM PDT 24
Finished Jun 05 05:38:11 PM PDT 24
Peak memory 224568 kb
Host smart-d3081e57-82d6-466c-848c-d71e86677515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160582532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.160582532
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3255719216
Short name T684
Test name
Test status
Simulation time 1946437762 ps
CPU time 13.24 seconds
Started Jun 05 05:38:08 PM PDT 24
Finished Jun 05 05:38:22 PM PDT 24
Peak memory 227056 kb
Host smart-787ff751-8286-4739-87c1-867485d87875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255719216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3255719216
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1796909843
Short name T544
Test name
Test status
Simulation time 12863349635 ps
CPU time 34.87 seconds
Started Jun 05 05:38:02 PM PDT 24
Finished Jun 05 05:38:38 PM PDT 24
Peak memory 251732 kb
Host smart-222b5eda-640a-40c8-93de-6992475950cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796909843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1796909843
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2635367700
Short name T937
Test name
Test status
Simulation time 14362277171 ps
CPU time 37.67 seconds
Started Jun 05 05:38:04 PM PDT 24
Finished Jun 05 05:38:43 PM PDT 24
Peak memory 240932 kb
Host smart-6ad5a9f4-ba27-4ef9-9eb7-e179e78903c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635367700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2635367700
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.844445419
Short name T416
Test name
Test status
Simulation time 2323671655 ps
CPU time 14.32 seconds
Started Jun 05 05:38:13 PM PDT 24
Finished Jun 05 05:38:28 PM PDT 24
Peak memory 223176 kb
Host smart-27a81315-6001-43fc-bbdf-caf248929bad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=844445419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.844445419
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1089778161
Short name T146
Test name
Test status
Simulation time 24052077040 ps
CPU time 123.01 seconds
Started Jun 05 05:38:11 PM PDT 24
Finished Jun 05 05:40:15 PM PDT 24
Peak memory 273704 kb
Host smart-8ddae86e-9537-4336-a2fc-0d8b9254dc4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089778161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1089778161
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.4243548850
Short name T794
Test name
Test status
Simulation time 1099454063 ps
CPU time 14.8 seconds
Started Jun 05 05:38:04 PM PDT 24
Finished Jun 05 05:38:20 PM PDT 24
Peak memory 216756 kb
Host smart-2f833d17-7a09-460f-9a2e-62bb094e7f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243548850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4243548850
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3460056495
Short name T67
Test name
Test status
Simulation time 238518095 ps
CPU time 1.99 seconds
Started Jun 05 05:38:07 PM PDT 24
Finished Jun 05 05:38:10 PM PDT 24
Peak memory 208200 kb
Host smart-4ec41a57-46a0-443c-bcd9-19d738661fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460056495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3460056495
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3247840013
Short name T476
Test name
Test status
Simulation time 162399838 ps
CPU time 1.19 seconds
Started Jun 05 05:38:07 PM PDT 24
Finished Jun 05 05:38:09 PM PDT 24
Peak memory 208196 kb
Host smart-aed8a73f-6ca5-4ff5-9e63-417ae400d23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247840013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3247840013
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3204925926
Short name T362
Test name
Test status
Simulation time 79057354 ps
CPU time 0.84 seconds
Started Jun 05 05:38:08 PM PDT 24
Finished Jun 05 05:38:09 PM PDT 24
Peak memory 205984 kb
Host smart-971db01d-c494-4fc3-9358-ad6cc015a846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204925926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3204925926
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4088159587
Short name T759
Test name
Test status
Simulation time 2731312026 ps
CPU time 4.75 seconds
Started Jun 05 05:38:06 PM PDT 24
Finished Jun 05 05:38:12 PM PDT 24
Peak memory 232920 kb
Host smart-58a21df5-1ddb-4e66-9c1c-fe719bb59d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088159587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4088159587
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.583397475
Short name T650
Test name
Test status
Simulation time 21332119 ps
CPU time 0.69 seconds
Started Jun 05 05:38:13 PM PDT 24
Finished Jun 05 05:38:14 PM PDT 24
Peak memory 204996 kb
Host smart-d616aeb6-9d30-4eff-aad7-c2e0d1422310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583397475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.583397475
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.395709930
Short name T135
Test name
Test status
Simulation time 163851973 ps
CPU time 2.78 seconds
Started Jun 05 05:38:11 PM PDT 24
Finished Jun 05 05:38:15 PM PDT 24
Peak memory 232832 kb
Host smart-7e5a2f7f-f227-4721-bca6-e6b45e2812ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395709930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.395709930
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1572949063
Short name T376
Test name
Test status
Simulation time 13987979 ps
CPU time 0.77 seconds
Started Jun 05 05:38:10 PM PDT 24
Finished Jun 05 05:38:11 PM PDT 24
Peak memory 207052 kb
Host smart-e1798862-2971-4d7e-8b51-6deb73110fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572949063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1572949063
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.468993672
Short name T196
Test name
Test status
Simulation time 5929746626 ps
CPU time 56.57 seconds
Started Jun 05 05:38:12 PM PDT 24
Finished Jun 05 05:39:09 PM PDT 24
Peak memory 249292 kb
Host smart-bcaacda5-cdaa-4850-8b51-94ba1d4d4701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468993672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.468993672
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2877882897
Short name T533
Test name
Test status
Simulation time 3323254219 ps
CPU time 67.37 seconds
Started Jun 05 05:38:10 PM PDT 24
Finished Jun 05 05:39:18 PM PDT 24
Peak memory 249724 kb
Host smart-5a01739e-e0a5-404a-aee8-97d5167fe51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877882897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2877882897
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3157839563
Short name T601
Test name
Test status
Simulation time 8942108487 ps
CPU time 16.1 seconds
Started Jun 05 05:38:12 PM PDT 24
Finished Jun 05 05:38:28 PM PDT 24
Peak memory 217604 kb
Host smart-837bd3da-b45a-49f5-9b38-c05fcc1895fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157839563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3157839563
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3508630186
Short name T701
Test name
Test status
Simulation time 1944340424 ps
CPU time 9.42 seconds
Started Jun 05 05:38:10 PM PDT 24
Finished Jun 05 05:38:20 PM PDT 24
Peak memory 232884 kb
Host smart-908b71b1-367a-476d-bacf-d062be472c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508630186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3508630186
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2376905380
Short name T870
Test name
Test status
Simulation time 1301877401 ps
CPU time 10.17 seconds
Started Jun 05 05:38:11 PM PDT 24
Finished Jun 05 05:38:22 PM PDT 24
Peak memory 224656 kb
Host smart-abb19ce1-210d-4071-8331-9682e3d7a9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376905380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2376905380
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.680850338
Short name T164
Test name
Test status
Simulation time 6938014164 ps
CPU time 23.07 seconds
Started Jun 05 05:38:14 PM PDT 24
Finished Jun 05 05:38:38 PM PDT 24
Peak memory 249280 kb
Host smart-12070a7a-bb43-444b-98cf-854dc0679dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680850338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.680850338
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3314063763
Short name T952
Test name
Test status
Simulation time 345415924 ps
CPU time 2.27 seconds
Started Jun 05 05:38:12 PM PDT 24
Finished Jun 05 05:38:15 PM PDT 24
Peak memory 224652 kb
Host smart-b6c9757c-f500-40e6-b158-f8d00fcf2d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314063763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3314063763
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3886918834
Short name T353
Test name
Test status
Simulation time 59244005 ps
CPU time 2.41 seconds
Started Jun 05 05:38:11 PM PDT 24
Finished Jun 05 05:38:14 PM PDT 24
Peak memory 232880 kb
Host smart-7b3dda0a-ab18-4a86-aef4-49a5394b53e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886918834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3886918834
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2533654012
Short name T856
Test name
Test status
Simulation time 2175619902 ps
CPU time 6.46 seconds
Started Jun 05 05:38:10 PM PDT 24
Finished Jun 05 05:38:17 PM PDT 24
Peak memory 222528 kb
Host smart-bf786102-aec1-4bc5-9ac7-9a3bc62c424a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2533654012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2533654012
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2162018845
Short name T30
Test name
Test status
Simulation time 15393483968 ps
CPU time 120.12 seconds
Started Jun 05 05:38:15 PM PDT 24
Finished Jun 05 05:40:16 PM PDT 24
Peak memory 264812 kb
Host smart-a312c38f-ca4d-49b2-968d-ab0be06f25c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162018845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2162018845
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1626539701
Short name T770
Test name
Test status
Simulation time 816993124 ps
CPU time 5 seconds
Started Jun 05 05:38:12 PM PDT 24
Finished Jun 05 05:38:18 PM PDT 24
Peak memory 216352 kb
Host smart-c218835b-89d9-4d33-a2e9-690fa9c88f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626539701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1626539701
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.551541272
Short name T323
Test name
Test status
Simulation time 7698513867 ps
CPU time 5.54 seconds
Started Jun 05 05:38:11 PM PDT 24
Finished Jun 05 05:38:17 PM PDT 24
Peak memory 216476 kb
Host smart-24b94f27-28e3-48f4-bf3f-e456f4bd2d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551541272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.551541272
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.765809311
Short name T919
Test name
Test status
Simulation time 41906739 ps
CPU time 0.73 seconds
Started Jun 05 05:38:12 PM PDT 24
Finished Jun 05 05:38:14 PM PDT 24
Peak memory 205932 kb
Host smart-2cd448b9-0592-4f3a-9c09-4907ac73a5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765809311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.765809311
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3892150972
Short name T833
Test name
Test status
Simulation time 15657912 ps
CPU time 0.77 seconds
Started Jun 05 05:38:11 PM PDT 24
Finished Jun 05 05:38:13 PM PDT 24
Peak memory 206012 kb
Host smart-57ccf1a8-b7ba-4bbc-b222-411f959fba4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892150972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3892150972
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2166875232
Short name T118
Test name
Test status
Simulation time 91160338 ps
CPU time 2.28 seconds
Started Jun 05 05:38:10 PM PDT 24
Finished Jun 05 05:38:13 PM PDT 24
Peak memory 223576 kb
Host smart-b1734e72-41ac-4c31-b6f8-5f42fee39eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166875232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2166875232
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.20459545
Short name T929
Test name
Test status
Simulation time 53888512 ps
CPU time 0.76 seconds
Started Jun 05 05:38:20 PM PDT 24
Finished Jun 05 05:38:21 PM PDT 24
Peak memory 205508 kb
Host smart-9b5625f5-1d19-40d3-8572-95a3635cdebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20459545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.20459545
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2134578209
Short name T791
Test name
Test status
Simulation time 60078466 ps
CPU time 2.95 seconds
Started Jun 05 05:38:18 PM PDT 24
Finished Jun 05 05:38:22 PM PDT 24
Peak memory 224676 kb
Host smart-08e67b86-b99b-47c7-8735-6ac8c22dc8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134578209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2134578209
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1476012418
Short name T605
Test name
Test status
Simulation time 117194572 ps
CPU time 0.79 seconds
Started Jun 05 05:38:13 PM PDT 24
Finished Jun 05 05:38:14 PM PDT 24
Peak memory 206752 kb
Host smart-84639265-8ec3-4838-b644-dbf561de1168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476012418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1476012418
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.869200235
Short name T851
Test name
Test status
Simulation time 186951427284 ps
CPU time 407.26 seconds
Started Jun 05 05:38:17 PM PDT 24
Finished Jun 05 05:45:05 PM PDT 24
Peak memory 250320 kb
Host smart-00455d04-6a0d-4ac6-9f78-be10079df25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869200235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.869200235
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1191833431
Short name T11
Test name
Test status
Simulation time 685780002188 ps
CPU time 433.16 seconds
Started Jun 05 05:38:24 PM PDT 24
Finished Jun 05 05:45:37 PM PDT 24
Peak memory 267348 kb
Host smart-53fb848d-8764-4720-ad25-f5b181b42bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191833431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1191833431
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1634836010
Short name T613
Test name
Test status
Simulation time 28532203877 ps
CPU time 102.75 seconds
Started Jun 05 05:38:24 PM PDT 24
Finished Jun 05 05:40:07 PM PDT 24
Peak memory 238780 kb
Host smart-c8cd3699-5bb7-4c4b-ada3-386516721258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634836010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1634836010
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3326648365
Short name T276
Test name
Test status
Simulation time 1066807483 ps
CPU time 8.99 seconds
Started Jun 05 05:38:18 PM PDT 24
Finished Jun 05 05:38:28 PM PDT 24
Peak memory 232844 kb
Host smart-8958e59b-190f-4767-99e2-5da07ec222ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326648365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3326648365
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1651535378
Short name T398
Test name
Test status
Simulation time 100105246 ps
CPU time 3.77 seconds
Started Jun 05 05:38:18 PM PDT 24
Finished Jun 05 05:38:23 PM PDT 24
Peak memory 224764 kb
Host smart-47136fc2-4c4b-43fe-b3a9-81b983550758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651535378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1651535378
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3292627199
Short name T493
Test name
Test status
Simulation time 8794760733 ps
CPU time 47.78 seconds
Started Jun 05 05:38:18 PM PDT 24
Finished Jun 05 05:39:07 PM PDT 24
Peak memory 234436 kb
Host smart-0738bca6-9d82-46a1-83a3-d94c87fc88bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292627199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3292627199
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1690782014
Short name T56
Test name
Test status
Simulation time 51153058837 ps
CPU time 27.32 seconds
Started Jun 05 05:38:19 PM PDT 24
Finished Jun 05 05:38:47 PM PDT 24
Peak memory 248876 kb
Host smart-0ec75428-9544-4946-93f5-9a88824b7a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690782014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1690782014
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3362371722
Short name T113
Test name
Test status
Simulation time 991049616 ps
CPU time 6.83 seconds
Started Jun 05 05:38:19 PM PDT 24
Finished Jun 05 05:38:26 PM PDT 24
Peak memory 232820 kb
Host smart-479ad376-72aa-46a0-9717-a366dd083c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362371722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3362371722
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.4106809446
Short name T588
Test name
Test status
Simulation time 1281418257 ps
CPU time 4.04 seconds
Started Jun 05 05:38:23 PM PDT 24
Finished Jun 05 05:38:28 PM PDT 24
Peak memory 221908 kb
Host smart-fe1004b1-a832-40e4-923a-f6809087d986
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4106809446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.4106809446
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2790527531
Short name T563
Test name
Test status
Simulation time 99450285 ps
CPU time 1.12 seconds
Started Jun 05 05:38:21 PM PDT 24
Finished Jun 05 05:38:22 PM PDT 24
Peak memory 215488 kb
Host smart-4162da2c-8735-41d7-8b5d-7c8e0e98942e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790527531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2790527531
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.181048094
Short name T282
Test name
Test status
Simulation time 2228689448 ps
CPU time 9.86 seconds
Started Jun 05 05:38:19 PM PDT 24
Finished Jun 05 05:38:30 PM PDT 24
Peak memory 216448 kb
Host smart-eff89a16-e060-425e-a8cc-95df04d33633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181048094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.181048094
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2340585395
Short name T474
Test name
Test status
Simulation time 20084673579 ps
CPU time 12.72 seconds
Started Jun 05 05:38:12 PM PDT 24
Finished Jun 05 05:38:26 PM PDT 24
Peak memory 216444 kb
Host smart-99226571-47bf-4731-9bbe-a7cc61c7f2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340585395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2340585395
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1136401907
Short name T715
Test name
Test status
Simulation time 726986171 ps
CPU time 3.44 seconds
Started Jun 05 05:38:24 PM PDT 24
Finished Jun 05 05:38:27 PM PDT 24
Peak memory 216444 kb
Host smart-66b35892-1a57-480c-ab3c-8dcd58975987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136401907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1136401907
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.866305963
Short name T884
Test name
Test status
Simulation time 492543221 ps
CPU time 0.84 seconds
Started Jun 05 05:38:21 PM PDT 24
Finished Jun 05 05:38:22 PM PDT 24
Peak memory 205964 kb
Host smart-d69a8f8c-481b-43a0-a1c1-eba8c7c23f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866305963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.866305963
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3330761351
Short name T515
Test name
Test status
Simulation time 6159551810 ps
CPU time 20.59 seconds
Started Jun 05 05:38:18 PM PDT 24
Finished Jun 05 05:38:40 PM PDT 24
Peak memory 224692 kb
Host smart-d263ce70-d278-4e9c-92ba-c7bbbb19d261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330761351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3330761351
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4151729981
Short name T788
Test name
Test status
Simulation time 23850536 ps
CPU time 0.74 seconds
Started Jun 05 05:38:29 PM PDT 24
Finished Jun 05 05:38:31 PM PDT 24
Peak memory 205860 kb
Host smart-caaa3d16-b65e-4215-a058-948896a5ffb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151729981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4151729981
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3071840120
Short name T831
Test name
Test status
Simulation time 465183179 ps
CPU time 5.86 seconds
Started Jun 05 05:38:18 PM PDT 24
Finished Jun 05 05:38:25 PM PDT 24
Peak memory 224632 kb
Host smart-430d8d1c-fcf0-40ef-867d-3570e461598d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071840120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3071840120
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2636483473
Short name T931
Test name
Test status
Simulation time 20520037 ps
CPU time 0.8 seconds
Started Jun 05 05:38:20 PM PDT 24
Finished Jun 05 05:38:21 PM PDT 24
Peak memory 206704 kb
Host smart-e341dee9-2db9-4ead-aed2-24dfdf4483a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636483473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2636483473
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.386845477
Short name T517
Test name
Test status
Simulation time 7651763756 ps
CPU time 45.4 seconds
Started Jun 05 05:38:19 PM PDT 24
Finished Jun 05 05:39:05 PM PDT 24
Peak memory 251344 kb
Host smart-329c4cca-abef-4afc-aef3-a87616128d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386845477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.386845477
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1130426516
Short name T36
Test name
Test status
Simulation time 4140474099 ps
CPU time 55.59 seconds
Started Jun 05 05:38:18 PM PDT 24
Finished Jun 05 05:39:14 PM PDT 24
Peak memory 249392 kb
Host smart-e90b625d-f6a8-4b19-a812-e7a61793c052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130426516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1130426516
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.4060303583
Short name T165
Test name
Test status
Simulation time 5895604253 ps
CPU time 85.92 seconds
Started Jun 05 05:38:27 PM PDT 24
Finished Jun 05 05:39:54 PM PDT 24
Peak memory 253796 kb
Host smart-2b8378a2-679c-429b-ba47-d04b055e37b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060303583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.4060303583
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2693510156
Short name T313
Test name
Test status
Simulation time 4852608009 ps
CPU time 9.39 seconds
Started Jun 05 05:38:21 PM PDT 24
Finished Jun 05 05:38:31 PM PDT 24
Peak memory 224684 kb
Host smart-0e367ecb-90ab-4e2c-87d5-2bc6fe30ab23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693510156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2693510156
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.4086918815
Short name T374
Test name
Test status
Simulation time 2490465581 ps
CPU time 6.59 seconds
Started Jun 05 05:38:17 PM PDT 24
Finished Jun 05 05:38:24 PM PDT 24
Peak memory 232900 kb
Host smart-b6527986-c6f5-48cc-ac12-bc75575cff62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086918815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.4086918815
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3431921667
Short name T943
Test name
Test status
Simulation time 26782654792 ps
CPU time 16.8 seconds
Started Jun 05 05:38:18 PM PDT 24
Finished Jun 05 05:38:36 PM PDT 24
Peak memory 233188 kb
Host smart-9684e431-f7f5-4b33-9ab4-28033b4c09ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431921667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3431921667
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.4286908269
Short name T774
Test name
Test status
Simulation time 3877125661 ps
CPU time 9.91 seconds
Started Jun 05 05:38:17 PM PDT 24
Finished Jun 05 05:38:27 PM PDT 24
Peak memory 232948 kb
Host smart-a9daf15a-3496-49da-933c-20639cffc27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286908269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.4286908269
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3716866852
Short name T248
Test name
Test status
Simulation time 2226958374 ps
CPU time 10.77 seconds
Started Jun 05 05:38:18 PM PDT 24
Finished Jun 05 05:38:29 PM PDT 24
Peak memory 232812 kb
Host smart-1630f57c-f5bf-4b31-81f3-7e56cb66412d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716866852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3716866852
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3740434652
Short name T844
Test name
Test status
Simulation time 3105061543 ps
CPU time 7.94 seconds
Started Jun 05 05:38:20 PM PDT 24
Finished Jun 05 05:38:28 PM PDT 24
Peak memory 222640 kb
Host smart-f77fe60d-7a04-433e-9b19-96d6fbcb4c25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3740434652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3740434652
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2879846060
Short name T22
Test name
Test status
Simulation time 277039988291 ps
CPU time 457.38 seconds
Started Jun 05 05:38:25 PM PDT 24
Finished Jun 05 05:46:03 PM PDT 24
Peak memory 255464 kb
Host smart-3778c066-bec2-4871-8cd0-47f6c1961b4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879846060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2879846060
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3653766010
Short name T947
Test name
Test status
Simulation time 10951565951 ps
CPU time 51.46 seconds
Started Jun 05 05:38:19 PM PDT 24
Finished Jun 05 05:39:11 PM PDT 24
Peak memory 216448 kb
Host smart-53378999-9e63-4659-a55d-1edb98744ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653766010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3653766010
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2244066648
Short name T363
Test name
Test status
Simulation time 4918551082 ps
CPU time 5.3 seconds
Started Jun 05 05:38:18 PM PDT 24
Finished Jun 05 05:38:23 PM PDT 24
Peak memory 216484 kb
Host smart-5f732861-bff4-4995-a639-b310c23d74ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244066648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2244066648
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.959036730
Short name T593
Test name
Test status
Simulation time 66711550 ps
CPU time 1.21 seconds
Started Jun 05 05:38:18 PM PDT 24
Finished Jun 05 05:38:20 PM PDT 24
Peak memory 216312 kb
Host smart-9a4935be-6447-49f5-a691-7f4808d884c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959036730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.959036730
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2939574488
Short name T298
Test name
Test status
Simulation time 44215172 ps
CPU time 0.83 seconds
Started Jun 05 05:38:19 PM PDT 24
Finished Jun 05 05:38:20 PM PDT 24
Peak memory 206000 kb
Host smart-75c65267-e3a6-4448-81e1-856f17c0d362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939574488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2939574488
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3892506775
Short name T682
Test name
Test status
Simulation time 8337555779 ps
CPU time 5.64 seconds
Started Jun 05 05:38:19 PM PDT 24
Finished Jun 05 05:38:25 PM PDT 24
Peak memory 224608 kb
Host smart-6d82eda8-c8a7-49af-9dec-616ab71c0c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892506775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3892506775
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1458327718
Short name T656
Test name
Test status
Simulation time 18194144 ps
CPU time 0.68 seconds
Started Jun 05 05:38:26 PM PDT 24
Finished Jun 05 05:38:27 PM PDT 24
Peak memory 205536 kb
Host smart-58721e7c-f7e8-443a-b966-4a3e47acb337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458327718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1458327718
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.112794035
Short name T37
Test name
Test status
Simulation time 23534268214 ps
CPU time 20.83 seconds
Started Jun 05 05:38:28 PM PDT 24
Finished Jun 05 05:38:50 PM PDT 24
Peak memory 232892 kb
Host smart-a8504ed8-7a43-42d1-a0aa-5c753daaea13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112794035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.112794035
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2384246863
Short name T873
Test name
Test status
Simulation time 41169186 ps
CPU time 0.76 seconds
Started Jun 05 05:38:31 PM PDT 24
Finished Jun 05 05:38:33 PM PDT 24
Peak memory 205720 kb
Host smart-9dcf4570-ea55-4961-a422-ebc8ac0a9294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384246863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2384246863
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.148462592
Short name T204
Test name
Test status
Simulation time 11579009515 ps
CPU time 93.14 seconds
Started Jun 05 05:38:26 PM PDT 24
Finished Jun 05 05:39:59 PM PDT 24
Peak memory 254220 kb
Host smart-454a810a-2e80-4b66-82b9-c5e216cb5d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148462592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.148462592
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.911758584
Short name T648
Test name
Test status
Simulation time 13017121667 ps
CPU time 97.15 seconds
Started Jun 05 05:38:24 PM PDT 24
Finished Jun 05 05:40:02 PM PDT 24
Peak memory 249348 kb
Host smart-a1396d1d-ac92-4b58-90b0-935b69b72504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911758584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.911758584
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3814079939
Short name T712
Test name
Test status
Simulation time 4760633315 ps
CPU time 48.24 seconds
Started Jun 05 05:38:26 PM PDT 24
Finished Jun 05 05:39:15 PM PDT 24
Peak memory 235828 kb
Host smart-0566b999-4b66-4c16-bf29-76cc5e1c8384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814079939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3814079939
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1843796633
Short name T663
Test name
Test status
Simulation time 707180011 ps
CPU time 14.47 seconds
Started Jun 05 05:38:28 PM PDT 24
Finished Jun 05 05:38:43 PM PDT 24
Peak memory 232740 kb
Host smart-afb25d0b-4830-454b-8c18-f1f481ffcfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843796633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1843796633
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1417594422
Short name T453
Test name
Test status
Simulation time 296173583 ps
CPU time 6.06 seconds
Started Jun 05 05:38:26 PM PDT 24
Finished Jun 05 05:38:33 PM PDT 24
Peak memory 232888 kb
Host smart-dbaf4cb3-5529-4cdb-892e-ad47d5a43358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417594422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1417594422
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.646440776
Short name T661
Test name
Test status
Simulation time 995247045 ps
CPU time 8.96 seconds
Started Jun 05 05:38:25 PM PDT 24
Finished Jun 05 05:38:35 PM PDT 24
Peak memory 232828 kb
Host smart-d101b99c-d408-4e57-85f9-6e64990b46c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646440776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.646440776
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2360314540
Short name T215
Test name
Test status
Simulation time 10657527042 ps
CPU time 9.57 seconds
Started Jun 05 05:38:27 PM PDT 24
Finished Jun 05 05:38:37 PM PDT 24
Peak memory 232932 kb
Host smart-3e00fa62-8884-4cca-83a6-1a097a076476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360314540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2360314540
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1458877596
Short name T644
Test name
Test status
Simulation time 1070616723 ps
CPU time 5.24 seconds
Started Jun 05 05:38:27 PM PDT 24
Finished Jun 05 05:38:33 PM PDT 24
Peak memory 232836 kb
Host smart-1e8c586b-5b46-4b35-b661-e045774e6c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458877596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1458877596
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.4267264805
Short name T753
Test name
Test status
Simulation time 781261412 ps
CPU time 4.89 seconds
Started Jun 05 05:38:26 PM PDT 24
Finished Jun 05 05:38:32 PM PDT 24
Peak memory 223140 kb
Host smart-f924f39c-a9db-4285-9e8e-f7e9c5fa4e0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4267264805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.4267264805
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1185087244
Short name T218
Test name
Test status
Simulation time 129092728597 ps
CPU time 372.54 seconds
Started Jun 05 05:38:27 PM PDT 24
Finished Jun 05 05:44:40 PM PDT 24
Peak memory 265684 kb
Host smart-5f09cc30-1ad8-41f3-8bf7-a5af83cd3cb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185087244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1185087244
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1620996054
Short name T689
Test name
Test status
Simulation time 13148311 ps
CPU time 0.73 seconds
Started Jun 05 05:38:28 PM PDT 24
Finished Jun 05 05:38:30 PM PDT 24
Peak memory 206088 kb
Host smart-8ff6838b-50e5-423f-8474-010f2b5244e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620996054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1620996054
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3006103997
Short name T543
Test name
Test status
Simulation time 1601453699 ps
CPU time 9.28 seconds
Started Jun 05 05:38:29 PM PDT 24
Finished Jun 05 05:38:38 PM PDT 24
Peak memory 216408 kb
Host smart-9c90b8a9-107e-4cb8-8654-9cf661634621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006103997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3006103997
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.744407358
Short name T784
Test name
Test status
Simulation time 1256466841 ps
CPU time 3.52 seconds
Started Jun 05 05:38:27 PM PDT 24
Finished Jun 05 05:38:31 PM PDT 24
Peak memory 216472 kb
Host smart-d683c115-da80-4d97-b40b-6168bf45c440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744407358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.744407358
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1593778088
Short name T559
Test name
Test status
Simulation time 62380788 ps
CPU time 0.91 seconds
Started Jun 05 05:38:28 PM PDT 24
Finished Jun 05 05:38:30 PM PDT 24
Peak memory 206020 kb
Host smart-818481da-6bd6-44b5-a60f-df4edd51ac86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593778088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1593778088
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1569213047
Short name T399
Test name
Test status
Simulation time 5443691077 ps
CPU time 13.47 seconds
Started Jun 05 05:38:25 PM PDT 24
Finished Jun 05 05:38:39 PM PDT 24
Peak memory 240616 kb
Host smart-ab322ad4-73e1-4f43-a64f-b41da50b9718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569213047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1569213047
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3654096277
Short name T949
Test name
Test status
Simulation time 51725566 ps
CPU time 0.77 seconds
Started Jun 05 05:35:28 PM PDT 24
Finished Jun 05 05:35:30 PM PDT 24
Peak memory 204972 kb
Host smart-72401b8d-d741-4848-9a37-6f48ab078635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654096277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
654096277
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.39648975
Short name T698
Test name
Test status
Simulation time 1894997176 ps
CPU time 18.04 seconds
Started Jun 05 05:35:21 PM PDT 24
Finished Jun 05 05:35:40 PM PDT 24
Peak memory 224648 kb
Host smart-5168c713-0c63-4fc7-931a-b1138fdc9d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39648975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.39648975
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1653250463
Short name T569
Test name
Test status
Simulation time 15188789 ps
CPU time 0.81 seconds
Started Jun 05 05:35:14 PM PDT 24
Finished Jun 05 05:35:16 PM PDT 24
Peak memory 206056 kb
Host smart-53c0fba3-328f-451e-aba2-20125e60a666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653250463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1653250463
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.54822251
Short name T21
Test name
Test status
Simulation time 3503586513 ps
CPU time 53.87 seconds
Started Jun 05 05:35:20 PM PDT 24
Finished Jun 05 05:36:15 PM PDT 24
Peak memory 249388 kb
Host smart-20ffe50b-8a8b-4ec6-9518-71548dab8619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54822251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.54822251
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.4238271397
Short name T633
Test name
Test status
Simulation time 7443435537 ps
CPU time 21.51 seconds
Started Jun 05 05:35:20 PM PDT 24
Finished Jun 05 05:35:43 PM PDT 24
Peak memory 224840 kb
Host smart-dfd9afa8-aca9-430a-9354-68fb75152ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238271397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.4238271397
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3843480043
Short name T456
Test name
Test status
Simulation time 2177176905 ps
CPU time 5.98 seconds
Started Jun 05 05:35:22 PM PDT 24
Finished Jun 05 05:35:28 PM PDT 24
Peak memory 232924 kb
Host smart-43dd204c-fd88-40cf-ad62-97f9bc64398f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843480043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3843480043
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2574712929
Short name T115
Test name
Test status
Simulation time 137253927 ps
CPU time 2.4 seconds
Started Jun 05 05:35:22 PM PDT 24
Finished Jun 05 05:35:25 PM PDT 24
Peak memory 224540 kb
Host smart-bb392f8d-0295-4833-a97b-04798d998eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574712929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2574712929
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2795134832
Short name T268
Test name
Test status
Simulation time 1467453087 ps
CPU time 23.37 seconds
Started Jun 05 05:35:20 PM PDT 24
Finished Jun 05 05:35:44 PM PDT 24
Peak memory 240920 kb
Host smart-a59149e8-c89c-40cb-abda-75ecc7e0dfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795134832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2795134832
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1021049416
Short name T594
Test name
Test status
Simulation time 142617830 ps
CPU time 2.78 seconds
Started Jun 05 05:35:19 PM PDT 24
Finished Jun 05 05:35:23 PM PDT 24
Peak memory 224536 kb
Host smart-a347cfac-8f48-44fb-9108-e7785010777f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021049416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1021049416
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.434745120
Short name T189
Test name
Test status
Simulation time 169515200 ps
CPU time 3.04 seconds
Started Jun 05 05:35:19 PM PDT 24
Finished Jun 05 05:35:23 PM PDT 24
Peak memory 232880 kb
Host smart-306ee4ea-2c8c-4c20-8b34-c59bf4441dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434745120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.434745120
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3211026167
Short name T325
Test name
Test status
Simulation time 455025478 ps
CPU time 4.9 seconds
Started Jun 05 05:35:20 PM PDT 24
Finished Jun 05 05:35:25 PM PDT 24
Peak memory 223128 kb
Host smart-9804191b-e802-4aca-8eab-462aa7fd8866
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3211026167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3211026167
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.4202084552
Short name T49
Test name
Test status
Simulation time 71867732 ps
CPU time 0.99 seconds
Started Jun 05 05:35:34 PM PDT 24
Finished Jun 05 05:35:35 PM PDT 24
Peak memory 235148 kb
Host smart-66f598a8-ff79-40c7-9564-98ac3b7d92af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202084552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4202084552
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.871798056
Short name T414
Test name
Test status
Simulation time 9350918556 ps
CPU time 71.39 seconds
Started Jun 05 05:35:19 PM PDT 24
Finished Jun 05 05:36:31 PM PDT 24
Peak memory 250380 kb
Host smart-fd5e0e9c-2be5-458d-b93c-407a190c9ecd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871798056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.871798056
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2364420980
Short name T459
Test name
Test status
Simulation time 1718887850 ps
CPU time 8.14 seconds
Started Jun 05 05:35:23 PM PDT 24
Finished Jun 05 05:35:32 PM PDT 24
Peak memory 216676 kb
Host smart-624dedcf-dc4c-4aa1-b254-ed4d8cdfcc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364420980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2364420980
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2446967721
Short name T651
Test name
Test status
Simulation time 1210210898 ps
CPU time 7.72 seconds
Started Jun 05 05:35:11 PM PDT 24
Finished Jun 05 05:35:20 PM PDT 24
Peak memory 216444 kb
Host smart-eefd23b4-b43c-42f5-b3d4-6050fefd5908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446967721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2446967721
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1920256615
Short name T455
Test name
Test status
Simulation time 247519639 ps
CPU time 0.93 seconds
Started Jun 05 05:35:19 PM PDT 24
Finished Jun 05 05:35:21 PM PDT 24
Peak memory 206612 kb
Host smart-3647d6f8-8501-4fa9-bb16-0e8417f6cf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920256615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1920256615
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.34294633
Short name T598
Test name
Test status
Simulation time 52809114 ps
CPU time 0.95 seconds
Started Jun 05 05:35:19 PM PDT 24
Finished Jun 05 05:35:21 PM PDT 24
Peak memory 206964 kb
Host smart-d339b290-2a60-4660-89af-7cf272a60848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34294633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.34294633
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4067368585
Short name T172
Test name
Test status
Simulation time 7794180929 ps
CPU time 14.3 seconds
Started Jun 05 05:35:19 PM PDT 24
Finished Jun 05 05:35:34 PM PDT 24
Peak memory 224676 kb
Host smart-8b72c547-959d-4274-9d17-9a16285f3160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067368585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4067368585
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.379907759
Short name T799
Test name
Test status
Simulation time 139845900 ps
CPU time 0.73 seconds
Started Jun 05 05:38:34 PM PDT 24
Finished Jun 05 05:38:35 PM PDT 24
Peak memory 205736 kb
Host smart-42bd933e-4578-46d8-a136-d4afaf84ea3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379907759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.379907759
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.470475055
Short name T236
Test name
Test status
Simulation time 36459788 ps
CPU time 2.57 seconds
Started Jun 05 05:38:31 PM PDT 24
Finished Jun 05 05:38:34 PM PDT 24
Peak memory 232832 kb
Host smart-8316f04c-3489-41c2-a63d-63a99a6b993e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470475055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.470475055
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2267130447
Short name T665
Test name
Test status
Simulation time 30327571 ps
CPU time 0.74 seconds
Started Jun 05 05:38:27 PM PDT 24
Finished Jun 05 05:38:28 PM PDT 24
Peak memory 205708 kb
Host smart-e64ae90a-929a-446d-aab7-5e96862ff436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267130447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2267130447
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3270595685
Short name T2
Test name
Test status
Simulation time 6894706146 ps
CPU time 39.41 seconds
Started Jun 05 05:38:34 PM PDT 24
Finished Jun 05 05:39:14 PM PDT 24
Peak memory 236644 kb
Host smart-1aa26665-169b-4676-b13d-98d27eec577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270595685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3270595685
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3166173635
Short name T222
Test name
Test status
Simulation time 65750367217 ps
CPU time 80.34 seconds
Started Jun 05 05:38:35 PM PDT 24
Finished Jun 05 05:39:56 PM PDT 24
Peak memory 249528 kb
Host smart-71e185b8-4ff3-4e21-9128-e921d2e0c297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166173635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3166173635
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1756121312
Short name T182
Test name
Test status
Simulation time 43913507762 ps
CPU time 150.61 seconds
Started Jun 05 05:38:35 PM PDT 24
Finished Jun 05 05:41:06 PM PDT 24
Peak memory 265732 kb
Host smart-3f3f7edb-a6b6-4824-b854-c87383ab7a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756121312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1756121312
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.657086064
Short name T32
Test name
Test status
Simulation time 93005116 ps
CPU time 4.23 seconds
Started Jun 05 05:38:35 PM PDT 24
Finished Jun 05 05:38:40 PM PDT 24
Peak memory 232848 kb
Host smart-917a2e2c-d18a-4116-b103-9ee514c941d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657086064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.657086064
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4121740676
Short name T802
Test name
Test status
Simulation time 316196034 ps
CPU time 6.68 seconds
Started Jun 05 05:38:27 PM PDT 24
Finished Jun 05 05:38:35 PM PDT 24
Peak memory 224648 kb
Host smart-acb28643-c242-4de3-82be-aca35e21eacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121740676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4121740676
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3497458250
Short name T735
Test name
Test status
Simulation time 147792267 ps
CPU time 3.63 seconds
Started Jun 05 05:38:24 PM PDT 24
Finished Jun 05 05:38:28 PM PDT 24
Peak memory 232832 kb
Host smart-0fd6432c-9176-4bbe-82fa-c51c90fb87c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497458250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3497458250
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3075759404
Short name T945
Test name
Test status
Simulation time 553904565 ps
CPU time 2.9 seconds
Started Jun 05 05:38:28 PM PDT 24
Finished Jun 05 05:38:32 PM PDT 24
Peak memory 232836 kb
Host smart-9b912359-9a39-4dd0-8c42-b7e51d64c1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075759404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3075759404
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1559604966
Short name T261
Test name
Test status
Simulation time 15457206226 ps
CPU time 17.08 seconds
Started Jun 05 05:38:26 PM PDT 24
Finished Jun 05 05:38:44 PM PDT 24
Peak memory 232844 kb
Host smart-fd08885e-3ff5-4281-ae3d-ba9980d0c682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559604966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1559604966
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1463847535
Short name T754
Test name
Test status
Simulation time 397950900 ps
CPU time 5.5 seconds
Started Jun 05 05:38:30 PM PDT 24
Finished Jun 05 05:38:36 PM PDT 24
Peak memory 223200 kb
Host smart-15de2ece-4eea-4bab-bf36-3eb3a5e243e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1463847535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1463847535
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3936387317
Short name T58
Test name
Test status
Simulation time 3167129898 ps
CPU time 15.35 seconds
Started Jun 05 05:38:36 PM PDT 24
Finished Jun 05 05:38:52 PM PDT 24
Peak memory 223708 kb
Host smart-fcd60481-d1a1-4f40-83fe-6d4e3c266245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936387317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3936387317
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.207269619
Short name T413
Test name
Test status
Simulation time 58565363 ps
CPU time 0.73 seconds
Started Jun 05 05:38:26 PM PDT 24
Finished Jun 05 05:38:28 PM PDT 24
Peak memory 205768 kb
Host smart-7571d4d0-3327-4690-8135-ce2589ac5463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207269619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.207269619
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.4162951058
Short name T428
Test name
Test status
Simulation time 6813812815 ps
CPU time 20.99 seconds
Started Jun 05 05:38:26 PM PDT 24
Finished Jun 05 05:38:47 PM PDT 24
Peak memory 216508 kb
Host smart-aabce606-7274-4b11-b478-63c76dbfb0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162951058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.4162951058
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.430731561
Short name T491
Test name
Test status
Simulation time 51521075 ps
CPU time 0.69 seconds
Started Jun 05 05:38:29 PM PDT 24
Finished Jun 05 05:38:30 PM PDT 24
Peak memory 205704 kb
Host smart-fe20639d-7a36-4c1b-be9e-ed1cdc00e2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430731561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.430731561
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1167802351
Short name T718
Test name
Test status
Simulation time 209188332 ps
CPU time 0.84 seconds
Started Jun 05 05:38:25 PM PDT 24
Finished Jun 05 05:38:27 PM PDT 24
Peak memory 205964 kb
Host smart-f6c0b8b5-bf57-49b3-ab76-ef606eaaaf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167802351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1167802351
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2855125486
Short name T699
Test name
Test status
Simulation time 8664075598 ps
CPU time 8.42 seconds
Started Jun 05 05:38:27 PM PDT 24
Finished Jun 05 05:38:36 PM PDT 24
Peak memory 232888 kb
Host smart-69fd59f4-d0a6-4c75-a574-541bb1f451c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855125486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2855125486
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4037893671
Short name T514
Test name
Test status
Simulation time 129987951 ps
CPU time 0.73 seconds
Started Jun 05 05:38:34 PM PDT 24
Finished Jun 05 05:38:36 PM PDT 24
Peak memory 205484 kb
Host smart-6f329547-f1b6-48f0-a7ba-a0269d0a7291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037893671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4037893671
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2974183777
Short name T512
Test name
Test status
Simulation time 1798074125 ps
CPU time 6.28 seconds
Started Jun 05 05:38:34 PM PDT 24
Finished Jun 05 05:38:41 PM PDT 24
Peak memory 224644 kb
Host smart-757b1aab-965b-4df8-a1cc-9e611820816d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974183777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2974183777
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1354664936
Short name T849
Test name
Test status
Simulation time 15160626 ps
CPU time 0.76 seconds
Started Jun 05 05:38:33 PM PDT 24
Finished Jun 05 05:38:35 PM PDT 24
Peak memory 205720 kb
Host smart-992013d6-418e-4610-8eec-3306cf8547ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354664936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1354664936
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3223966058
Short name T180
Test name
Test status
Simulation time 44063480223 ps
CPU time 322.11 seconds
Started Jun 05 05:38:35 PM PDT 24
Finished Jun 05 05:43:57 PM PDT 24
Peak memory 263768 kb
Host smart-4f1e292f-1f12-4e72-881c-94fbe675156f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223966058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3223966058
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3871181216
Short name T571
Test name
Test status
Simulation time 3541387023 ps
CPU time 22.36 seconds
Started Jun 05 05:38:34 PM PDT 24
Finished Jun 05 05:38:57 PM PDT 24
Peak memory 217808 kb
Host smart-30c2526c-cc9f-44ec-aeec-2597433aaa6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871181216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3871181216
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1029381773
Short name T214
Test name
Test status
Simulation time 6024238074 ps
CPU time 59.15 seconds
Started Jun 05 05:38:34 PM PDT 24
Finished Jun 05 05:39:33 PM PDT 24
Peak memory 249292 kb
Host smart-b419db8e-5bf8-46bd-ac6c-b37520996443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029381773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1029381773
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3060290705
Short name T580
Test name
Test status
Simulation time 2462046543 ps
CPU time 10.5 seconds
Started Jun 05 05:38:34 PM PDT 24
Finished Jun 05 05:38:45 PM PDT 24
Peak memory 234576 kb
Host smart-c9b4bc6d-e13a-4d96-89e7-15fb2a616dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060290705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3060290705
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.133810302
Short name T921
Test name
Test status
Simulation time 2605314813 ps
CPU time 4.95 seconds
Started Jun 05 05:38:33 PM PDT 24
Finished Jun 05 05:38:39 PM PDT 24
Peak memory 224680 kb
Host smart-b95a2048-0fac-4ab8-a24c-055909739233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133810302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.133810302
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2960434647
Short name T823
Test name
Test status
Simulation time 955442793 ps
CPU time 14.38 seconds
Started Jun 05 05:38:33 PM PDT 24
Finished Jun 05 05:38:48 PM PDT 24
Peak memory 224580 kb
Host smart-a4ecf78b-b412-430f-8bb7-039ab53c7756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960434647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2960434647
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4164358882
Short name T452
Test name
Test status
Simulation time 783025156 ps
CPU time 2.6 seconds
Started Jun 05 05:38:35 PM PDT 24
Finished Jun 05 05:38:38 PM PDT 24
Peak memory 224592 kb
Host smart-64483965-3758-4012-81ff-2ae65800853e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164358882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4164358882
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2288116098
Short name T624
Test name
Test status
Simulation time 120026142 ps
CPU time 2.58 seconds
Started Jun 05 05:38:32 PM PDT 24
Finished Jun 05 05:38:35 PM PDT 24
Peak memory 232680 kb
Host smart-e7ab5e74-37a6-4aee-8bb9-a17f86279b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288116098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2288116098
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3261502590
Short name T461
Test name
Test status
Simulation time 1499614041 ps
CPU time 4.65 seconds
Started Jun 05 05:38:32 PM PDT 24
Finished Jun 05 05:38:37 PM PDT 24
Peak memory 219072 kb
Host smart-596a9370-6aa0-41ba-a938-e5f5088124dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3261502590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3261502590
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.301579000
Short name T141
Test name
Test status
Simulation time 40127801295 ps
CPU time 229.85 seconds
Started Jun 05 05:38:34 PM PDT 24
Finished Jun 05 05:42:24 PM PDT 24
Peak memory 254612 kb
Host smart-d677b016-c3b3-4122-bdff-f2c47b0e9c8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301579000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.301579000
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2442515022
Short name T824
Test name
Test status
Simulation time 9912576625 ps
CPU time 29.24 seconds
Started Jun 05 05:38:35 PM PDT 24
Finished Jun 05 05:39:05 PM PDT 24
Peak memory 216572 kb
Host smart-356339ee-4543-4b46-8324-8e75e4146f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442515022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2442515022
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.711320406
Short name T685
Test name
Test status
Simulation time 9134201797 ps
CPU time 9.3 seconds
Started Jun 05 05:38:33 PM PDT 24
Finished Jun 05 05:38:42 PM PDT 24
Peak memory 216540 kb
Host smart-ccc6ce5e-8608-4e9a-8db4-8bba01c2eedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711320406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.711320406
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1325192173
Short name T422
Test name
Test status
Simulation time 141707012 ps
CPU time 2.24 seconds
Started Jun 05 05:38:32 PM PDT 24
Finished Jun 05 05:38:34 PM PDT 24
Peak memory 216384 kb
Host smart-2ee719c3-d82a-4f58-9766-86c83c32f9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325192173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1325192173
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2322387234
Short name T793
Test name
Test status
Simulation time 25036321 ps
CPU time 0.78 seconds
Started Jun 05 05:38:33 PM PDT 24
Finished Jun 05 05:38:35 PM PDT 24
Peak memory 205944 kb
Host smart-54954b80-310d-4037-9c48-bb24c401e03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322387234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2322387234
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3050714486
Short name T848
Test name
Test status
Simulation time 15224649667 ps
CPU time 15.25 seconds
Started Jun 05 05:38:31 PM PDT 24
Finished Jun 05 05:38:47 PM PDT 24
Peak memory 232840 kb
Host smart-4edbd211-8410-46b5-8d9a-d20856c601f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050714486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3050714486
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1388944133
Short name T575
Test name
Test status
Simulation time 14267694 ps
CPU time 0.7 seconds
Started Jun 05 05:38:40 PM PDT 24
Finished Jun 05 05:38:41 PM PDT 24
Peak memory 204916 kb
Host smart-abb7466c-524b-45bb-987c-2582b5b53074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388944133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1388944133
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3205301342
Short name T887
Test name
Test status
Simulation time 73937442 ps
CPU time 2.5 seconds
Started Jun 05 05:38:46 PM PDT 24
Finished Jun 05 05:38:49 PM PDT 24
Peak memory 232676 kb
Host smart-8b503a79-7af9-49cd-b499-52f21060df9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205301342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3205301342
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2046160284
Short name T405
Test name
Test status
Simulation time 13775222 ps
CPU time 0.76 seconds
Started Jun 05 05:38:32 PM PDT 24
Finished Jun 05 05:38:33 PM PDT 24
Peak memory 205728 kb
Host smart-bee066f7-d172-4c6c-933a-460d70d6cd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046160284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2046160284
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1417149135
Short name T31
Test name
Test status
Simulation time 17498223476 ps
CPU time 175.05 seconds
Started Jun 05 05:38:48 PM PDT 24
Finished Jun 05 05:41:43 PM PDT 24
Peak memory 265684 kb
Host smart-ab88c547-6e15-4800-a8b1-eee584b2df42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417149135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1417149135
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.204063322
Short name T748
Test name
Test status
Simulation time 4453487092 ps
CPU time 60.54 seconds
Started Jun 05 05:38:41 PM PDT 24
Finished Jun 05 05:39:42 PM PDT 24
Peak memory 249376 kb
Host smart-96b8ec48-8825-4149-b6dc-fc4629968153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204063322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.204063322
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2749648782
Short name T853
Test name
Test status
Simulation time 1001453776 ps
CPU time 15.62 seconds
Started Jun 05 05:38:41 PM PDT 24
Finished Jun 05 05:38:57 PM PDT 24
Peak memory 237144 kb
Host smart-da02de2b-cf22-43ea-9e3b-80ab9939202c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749648782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2749648782
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.873378451
Short name T877
Test name
Test status
Simulation time 273362894 ps
CPU time 4.22 seconds
Started Jun 05 05:38:46 PM PDT 24
Finished Jun 05 05:38:50 PM PDT 24
Peak memory 224580 kb
Host smart-1a4ba52d-6077-4f40-8bbc-b4391b474077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873378451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.873378451
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1272319619
Short name T265
Test name
Test status
Simulation time 111560150717 ps
CPU time 52.92 seconds
Started Jun 05 05:38:41 PM PDT 24
Finished Jun 05 05:39:34 PM PDT 24
Peak memory 233996 kb
Host smart-2776dc64-6316-4e52-afb6-1f03294014ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272319619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1272319619
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2495122239
Short name T676
Test name
Test status
Simulation time 248845128 ps
CPU time 4.55 seconds
Started Jun 05 05:38:42 PM PDT 24
Finished Jun 05 05:38:48 PM PDT 24
Peak memory 240468 kb
Host smart-dacfcd6e-d352-49df-b1c4-498d21e08ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495122239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2495122239
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3070062043
Short name T187
Test name
Test status
Simulation time 3945014371 ps
CPU time 10.15 seconds
Started Jun 05 05:38:42 PM PDT 24
Finished Jun 05 05:38:53 PM PDT 24
Peak memory 232940 kb
Host smart-ece23f0b-5770-4657-b2c9-61bf2d2792ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070062043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3070062043
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.82673118
Short name T590
Test name
Test status
Simulation time 2374588519 ps
CPU time 6.6 seconds
Started Jun 05 05:38:44 PM PDT 24
Finished Jun 05 05:38:51 PM PDT 24
Peak memory 223236 kb
Host smart-7d021cb5-fa35-48dc-a591-50aeb1ceba85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=82673118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direc
t.82673118
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3493350264
Short name T751
Test name
Test status
Simulation time 121386569 ps
CPU time 1.11 seconds
Started Jun 05 05:38:41 PM PDT 24
Finished Jun 05 05:38:43 PM PDT 24
Peak memory 207312 kb
Host smart-6a11b598-8ad8-4ea9-8619-8a25d0639dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493350264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3493350264
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3885217473
Short name T578
Test name
Test status
Simulation time 7054624178 ps
CPU time 8.64 seconds
Started Jun 05 05:38:35 PM PDT 24
Finished Jun 05 05:38:44 PM PDT 24
Peak memory 216492 kb
Host smart-f5540947-e2a3-42fb-b6a3-5bc0783ff0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885217473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3885217473
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.451983543
Short name T863
Test name
Test status
Simulation time 1543847383 ps
CPU time 3.25 seconds
Started Jun 05 05:38:32 PM PDT 24
Finished Jun 05 05:38:36 PM PDT 24
Peak memory 216444 kb
Host smart-067f8e24-8e0d-4ac8-9fec-754b5fc7be26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451983543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.451983543
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2117634685
Short name T639
Test name
Test status
Simulation time 75086874 ps
CPU time 1.07 seconds
Started Jun 05 05:38:34 PM PDT 24
Finished Jun 05 05:38:36 PM PDT 24
Peak memory 207176 kb
Host smart-bb044a98-0444-40d5-9cfc-7fbaa7eef0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117634685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2117634685
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.422835004
Short name T371
Test name
Test status
Simulation time 24712160 ps
CPU time 0.78 seconds
Started Jun 05 05:38:36 PM PDT 24
Finished Jun 05 05:38:37 PM PDT 24
Peak memory 206012 kb
Host smart-e6b2eaee-ba54-4cb9-b66d-b7740ed2b3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422835004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.422835004
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1071404156
Short name T549
Test name
Test status
Simulation time 586847816 ps
CPU time 7.21 seconds
Started Jun 05 05:38:41 PM PDT 24
Finished Jun 05 05:38:49 PM PDT 24
Peak memory 241052 kb
Host smart-80960332-a309-4d19-9b8e-c083d63b89d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071404156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1071404156
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.4273617337
Short name T705
Test name
Test status
Simulation time 42312864 ps
CPU time 0.71 seconds
Started Jun 05 05:38:47 PM PDT 24
Finished Jun 05 05:38:48 PM PDT 24
Peak memory 204992 kb
Host smart-8ff78c32-1892-4738-a057-ee6724822a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273617337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
4273617337
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2018165984
Short name T552
Test name
Test status
Simulation time 1234277950 ps
CPU time 5.66 seconds
Started Jun 05 05:38:40 PM PDT 24
Finished Jun 05 05:38:46 PM PDT 24
Peak memory 224648 kb
Host smart-591e9246-9671-4265-bfb9-8b899e95ed46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018165984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2018165984
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4128499499
Short name T447
Test name
Test status
Simulation time 23617924 ps
CPU time 0.8 seconds
Started Jun 05 05:38:41 PM PDT 24
Finished Jun 05 05:38:43 PM PDT 24
Peak memory 206728 kb
Host smart-802cfe07-e650-45b5-82f7-a49a8d7c1f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128499499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4128499499
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2803739655
Short name T734
Test name
Test status
Simulation time 28491547271 ps
CPU time 46.66 seconds
Started Jun 05 05:38:49 PM PDT 24
Finished Jun 05 05:39:36 PM PDT 24
Peak memory 249308 kb
Host smart-d4700dd6-2858-422e-9b3c-30ad71625fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803739655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2803739655
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3832996321
Short name T760
Test name
Test status
Simulation time 23471689377 ps
CPU time 14.4 seconds
Started Jun 05 05:38:46 PM PDT 24
Finished Jun 05 05:39:00 PM PDT 24
Peak memory 217872 kb
Host smart-edbd8c0f-fb21-49c3-b8e2-708fd34ac294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832996321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3832996321
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.74534599
Short name T123
Test name
Test status
Simulation time 3911953119 ps
CPU time 79.8 seconds
Started Jun 05 05:38:50 PM PDT 24
Finished Jun 05 05:40:10 PM PDT 24
Peak memory 255068 kb
Host smart-f71f23fb-5b39-4f06-8c73-33d29d3858f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74534599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.74534599
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2561745725
Short name T762
Test name
Test status
Simulation time 311439433 ps
CPU time 3.54 seconds
Started Jun 05 05:38:39 PM PDT 24
Finished Jun 05 05:38:43 PM PDT 24
Peak memory 224572 kb
Host smart-74e3dccf-b4c9-4e1c-9544-c0e120ec2fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561745725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2561745725
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2059059952
Short name T505
Test name
Test status
Simulation time 955840600 ps
CPU time 9.79 seconds
Started Jun 05 05:38:42 PM PDT 24
Finished Jun 05 05:38:53 PM PDT 24
Peak memory 224692 kb
Host smart-15bf5cb5-5dff-45c6-bed0-c037b70f38ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059059952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2059059952
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3717995486
Short name T465
Test name
Test status
Simulation time 1078403911 ps
CPU time 6.48 seconds
Started Jun 05 05:38:45 PM PDT 24
Finished Jun 05 05:38:52 PM PDT 24
Peak memory 224792 kb
Host smart-ed6eb00a-aa3f-42ee-94bf-28836cd51010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717995486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3717995486
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1301690271
Short name T18
Test name
Test status
Simulation time 400377257 ps
CPU time 4.32 seconds
Started Jun 05 05:38:52 PM PDT 24
Finished Jun 05 05:38:57 PM PDT 24
Peak memory 232788 kb
Host smart-e466a2bf-9053-42ee-95c4-419a9086fb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301690271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1301690271
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.4011271294
Short name T630
Test name
Test status
Simulation time 1714939204 ps
CPU time 6.54 seconds
Started Jun 05 05:38:45 PM PDT 24
Finished Jun 05 05:38:52 PM PDT 24
Peak memory 232868 kb
Host smart-a51674cc-bcc7-427e-8b66-82d876268bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011271294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.4011271294
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1963464549
Short name T486
Test name
Test status
Simulation time 7647634098 ps
CPU time 21.12 seconds
Started Jun 05 05:38:38 PM PDT 24
Finished Jun 05 05:38:59 PM PDT 24
Peak memory 223056 kb
Host smart-e4e62e32-2055-4e17-9496-eb3ec4891b81
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1963464549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1963464549
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2614870268
Short name T672
Test name
Test status
Simulation time 7976492124 ps
CPU time 18.33 seconds
Started Jun 05 05:38:38 PM PDT 24
Finished Jun 05 05:38:57 PM PDT 24
Peak memory 216524 kb
Host smart-fb85b4ed-a2ac-46a8-a672-2f5ecadab297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614870268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2614870268
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1889424335
Short name T819
Test name
Test status
Simulation time 274991679 ps
CPU time 1.05 seconds
Started Jun 05 05:38:42 PM PDT 24
Finished Jun 05 05:38:44 PM PDT 24
Peak memory 207100 kb
Host smart-c4b521e6-21ca-4ddf-96e5-e4389232faa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889424335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1889424335
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.292101147
Short name T805
Test name
Test status
Simulation time 47451671 ps
CPU time 0.72 seconds
Started Jun 05 05:38:41 PM PDT 24
Finished Jun 05 05:38:42 PM PDT 24
Peak memory 206004 kb
Host smart-e1ebbaff-b3d0-4295-b727-734fa7591426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292101147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.292101147
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3828427479
Short name T304
Test name
Test status
Simulation time 67204677 ps
CPU time 0.85 seconds
Started Jun 05 05:38:42 PM PDT 24
Finished Jun 05 05:38:43 PM PDT 24
Peak memory 205948 kb
Host smart-04e4ca2d-95b2-4c0e-a52b-46ad36833b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828427479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3828427479
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.4221323707
Short name T693
Test name
Test status
Simulation time 66030708991 ps
CPU time 49.4 seconds
Started Jun 05 05:38:41 PM PDT 24
Finished Jun 05 05:39:31 PM PDT 24
Peak memory 235528 kb
Host smart-9cc45e3e-a857-47f3-bb9f-4ec10979e333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221323707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.4221323707
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4050538222
Short name T606
Test name
Test status
Simulation time 12533985 ps
CPU time 0.74 seconds
Started Jun 05 05:38:48 PM PDT 24
Finished Jun 05 05:38:49 PM PDT 24
Peak memory 205552 kb
Host smart-0fa6f90c-fd15-4738-8dd1-4796ec4fdf3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050538222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4050538222
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.4069710002
Short name T71
Test name
Test status
Simulation time 2415192592 ps
CPU time 4.84 seconds
Started Jun 05 05:38:49 PM PDT 24
Finished Jun 05 05:38:55 PM PDT 24
Peak memory 232952 kb
Host smart-e52c3d1e-7b8c-4973-a6dc-efaf134bd303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069710002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.4069710002
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2363226625
Short name T747
Test name
Test status
Simulation time 79734742 ps
CPU time 0.72 seconds
Started Jun 05 05:38:49 PM PDT 24
Finished Jun 05 05:38:50 PM PDT 24
Peak memory 206704 kb
Host smart-64f69b5f-cd36-4974-8096-1f741f4deb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363226625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2363226625
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2096802745
Short name T767
Test name
Test status
Simulation time 3130773398 ps
CPU time 16.03 seconds
Started Jun 05 05:38:47 PM PDT 24
Finished Jun 05 05:39:04 PM PDT 24
Peak memory 235872 kb
Host smart-55223699-9537-4545-9c4c-9178cb341fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096802745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2096802745
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2764315167
Short name T219
Test name
Test status
Simulation time 196395431898 ps
CPU time 306.29 seconds
Started Jun 05 05:38:50 PM PDT 24
Finished Jun 05 05:43:57 PM PDT 24
Peak memory 252352 kb
Host smart-bb94bf8b-bb03-46c7-8fcf-970f733ef6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764315167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2764315167
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3092738244
Short name T489
Test name
Test status
Simulation time 28490970549 ps
CPU time 46.2 seconds
Started Jun 05 05:38:47 PM PDT 24
Finished Jun 05 05:39:33 PM PDT 24
Peak memory 241436 kb
Host smart-67b6f63b-5f38-4687-863f-10d1875a03ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092738244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3092738244
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1158188766
Short name T757
Test name
Test status
Simulation time 1392281192 ps
CPU time 10.69 seconds
Started Jun 05 05:38:48 PM PDT 24
Finished Jun 05 05:38:59 PM PDT 24
Peak memory 233040 kb
Host smart-2a865f0f-b23c-4b67-b783-07c4687b5520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158188766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1158188766
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3991116142
Short name T380
Test name
Test status
Simulation time 147203693 ps
CPU time 2.59 seconds
Started Jun 05 05:38:47 PM PDT 24
Finished Jun 05 05:38:50 PM PDT 24
Peak memory 232892 kb
Host smart-01f70194-9fd6-4292-b8b8-32441db5acd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991116142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3991116142
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.178266419
Short name T116
Test name
Test status
Simulation time 569585693 ps
CPU time 3.63 seconds
Started Jun 05 05:38:47 PM PDT 24
Finished Jun 05 05:38:51 PM PDT 24
Peak memory 224560 kb
Host smart-029f4491-561f-4e8a-b265-9f600b34b52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178266419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.178266419
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3541554366
Short name T173
Test name
Test status
Simulation time 1523433204 ps
CPU time 7.93 seconds
Started Jun 05 05:38:49 PM PDT 24
Finished Jun 05 05:38:58 PM PDT 24
Peak memory 241024 kb
Host smart-01adba8f-4bae-4af6-b8cf-7ef123f67df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541554366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3541554366
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1994272018
Short name T858
Test name
Test status
Simulation time 4355473777 ps
CPU time 9.81 seconds
Started Jun 05 05:38:50 PM PDT 24
Finished Jun 05 05:39:00 PM PDT 24
Peak memory 248664 kb
Host smart-0c76d854-b952-4edc-8f35-5686a1659380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994272018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1994272018
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1153242045
Short name T402
Test name
Test status
Simulation time 4520991809 ps
CPU time 12.97 seconds
Started Jun 05 05:38:47 PM PDT 24
Finished Jun 05 05:39:00 PM PDT 24
Peak memory 222680 kb
Host smart-87041e8d-696c-4428-af8e-073ba82148bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1153242045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1153242045
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.436065671
Short name T126
Test name
Test status
Simulation time 91916006250 ps
CPU time 115.94 seconds
Started Jun 05 05:38:50 PM PDT 24
Finished Jun 05 05:40:46 PM PDT 24
Peak memory 257532 kb
Host smart-f6b9eb11-e8aa-4788-82c7-93911f2f4f1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436065671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.436065671
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2556853614
Short name T885
Test name
Test status
Simulation time 5378592289 ps
CPU time 34.13 seconds
Started Jun 05 05:38:48 PM PDT 24
Finished Jun 05 05:39:23 PM PDT 24
Peak memory 216628 kb
Host smart-41e03e7e-1670-469e-93ba-207efeecfb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556853614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2556853614
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1578312493
Short name T845
Test name
Test status
Simulation time 36158532 ps
CPU time 0.74 seconds
Started Jun 05 05:38:50 PM PDT 24
Finished Jun 05 05:38:51 PM PDT 24
Peak memory 205768 kb
Host smart-680534b7-62da-4436-add1-57c39cddab3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578312493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1578312493
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2508534195
Short name T553
Test name
Test status
Simulation time 66823705 ps
CPU time 1.18 seconds
Started Jun 05 05:38:46 PM PDT 24
Finished Jun 05 05:38:48 PM PDT 24
Peak memory 215424 kb
Host smart-b761018c-c99b-41d9-8e69-a78a2e9c55b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508534195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2508534195
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3137054263
Short name T390
Test name
Test status
Simulation time 121007533 ps
CPU time 0.9 seconds
Started Jun 05 05:38:48 PM PDT 24
Finished Jun 05 05:38:50 PM PDT 24
Peak memory 207000 kb
Host smart-5b17cf7d-7b7a-4d72-b766-75250bf1bb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137054263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3137054263
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.803753114
Short name T927
Test name
Test status
Simulation time 95134856 ps
CPU time 2.25 seconds
Started Jun 05 05:38:48 PM PDT 24
Finished Jun 05 05:38:51 PM PDT 24
Peak memory 223060 kb
Host smart-2bb7f2fb-98c6-4558-b133-87c3b22d9273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803753114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.803753114
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2121876182
Short name T854
Test name
Test status
Simulation time 14857820 ps
CPU time 0.79 seconds
Started Jun 05 05:38:53 PM PDT 24
Finished Jun 05 05:38:55 PM PDT 24
Peak memory 204932 kb
Host smart-a06a06c0-325a-4e7a-a8be-447e2b65a65b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121876182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2121876182
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.759029398
Short name T536
Test name
Test status
Simulation time 91546588 ps
CPU time 2.1 seconds
Started Jun 05 05:38:47 PM PDT 24
Finished Jun 05 05:38:49 PM PDT 24
Peak memory 223180 kb
Host smart-dfaf9d2b-f9bd-45f8-a085-a9fe1dedce4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759029398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.759029398
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3761437672
Short name T916
Test name
Test status
Simulation time 56518250 ps
CPU time 0.76 seconds
Started Jun 05 05:38:51 PM PDT 24
Finished Jun 05 05:38:52 PM PDT 24
Peak memory 206260 kb
Host smart-2a92cc98-090b-4153-b98a-0a704db0e3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761437672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3761437672
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2582694862
Short name T300
Test name
Test status
Simulation time 32124585 ps
CPU time 0.78 seconds
Started Jun 05 05:38:53 PM PDT 24
Finished Jun 05 05:38:54 PM PDT 24
Peak memory 216076 kb
Host smart-66086505-effd-482d-8115-4de652392a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582694862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2582694862
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.748349109
Short name T704
Test name
Test status
Simulation time 92029138190 ps
CPU time 185.19 seconds
Started Jun 05 05:38:55 PM PDT 24
Finished Jun 05 05:42:00 PM PDT 24
Peak memory 252316 kb
Host smart-9b87f466-8927-4b79-adc7-0feeaa6d1c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748349109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.748349109
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.834889490
Short name T14
Test name
Test status
Simulation time 93208148186 ps
CPU time 211.92 seconds
Started Jun 05 05:38:52 PM PDT 24
Finished Jun 05 05:42:25 PM PDT 24
Peak memory 256536 kb
Host smart-d1d0183d-20e6-42b6-bfd8-2ed9e8afb44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834889490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.834889490
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.4018680974
Short name T460
Test name
Test status
Simulation time 183861698 ps
CPU time 4.78 seconds
Started Jun 05 05:38:45 PM PDT 24
Finished Jun 05 05:38:50 PM PDT 24
Peak memory 224600 kb
Host smart-883051d3-7d8d-4c3e-804f-4140192f360a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018680974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4018680974
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.4122335347
Short name T944
Test name
Test status
Simulation time 351783911 ps
CPU time 4.76 seconds
Started Jun 05 05:38:47 PM PDT 24
Finished Jun 05 05:38:52 PM PDT 24
Peak memory 224608 kb
Host smart-ce032a73-c2b9-4ee9-83e7-627daccb7d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122335347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.4122335347
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4055319241
Short name T257
Test name
Test status
Simulation time 11439843597 ps
CPU time 95.85 seconds
Started Jun 05 05:38:46 PM PDT 24
Finished Jun 05 05:40:23 PM PDT 24
Peak memory 233816 kb
Host smart-1bb669a7-14b7-4714-b007-a0a0c2674ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055319241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4055319241
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3648761730
Short name T535
Test name
Test status
Simulation time 1454007501 ps
CPU time 5.06 seconds
Started Jun 05 05:38:52 PM PDT 24
Finished Jun 05 05:38:57 PM PDT 24
Peak memory 232836 kb
Host smart-bf604cad-51d8-4173-a35d-cf9b1c6f0728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648761730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3648761730
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.552295457
Short name T750
Test name
Test status
Simulation time 341599503 ps
CPU time 2.22 seconds
Started Jun 05 05:38:45 PM PDT 24
Finished Jun 05 05:38:48 PM PDT 24
Peak memory 232640 kb
Host smart-1d26514b-135d-4a4c-b679-70100f2010ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552295457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.552295457
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2119395403
Short name T686
Test name
Test status
Simulation time 1477280470 ps
CPU time 16.75 seconds
Started Jun 05 05:38:47 PM PDT 24
Finished Jun 05 05:39:04 PM PDT 24
Peak memory 223072 kb
Host smart-1084696a-3ac4-41ff-9dfb-1f442ef0b98a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2119395403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2119395403
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2482737265
Short name T194
Test name
Test status
Simulation time 113607934963 ps
CPU time 238.3 seconds
Started Jun 05 05:38:52 PM PDT 24
Finished Jun 05 05:42:51 PM PDT 24
Peak memory 252408 kb
Host smart-81209e13-68bd-413f-bb9f-f960e2439815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482737265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2482737265
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2847034113
Short name T508
Test name
Test status
Simulation time 13642322 ps
CPU time 0.71 seconds
Started Jun 05 05:38:47 PM PDT 24
Finished Jun 05 05:38:48 PM PDT 24
Peak memory 205816 kb
Host smart-0c3ee5d0-f918-4d6a-971d-affe3ba6bde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847034113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2847034113
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1805568361
Short name T669
Test name
Test status
Simulation time 2926649282 ps
CPU time 6.65 seconds
Started Jun 05 05:38:48 PM PDT 24
Finished Jun 05 05:38:55 PM PDT 24
Peak memory 216508 kb
Host smart-ee41c008-8824-48f8-ae41-a8b69bf95005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805568361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1805568361
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1065240605
Short name T457
Test name
Test status
Simulation time 56432055 ps
CPU time 1.15 seconds
Started Jun 05 05:38:48 PM PDT 24
Finished Jun 05 05:38:49 PM PDT 24
Peak memory 208012 kb
Host smart-264bdfc3-0246-4c58-93c1-b2a110603508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065240605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1065240605
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1518294590
Short name T451
Test name
Test status
Simulation time 247534084 ps
CPU time 0.89 seconds
Started Jun 05 05:38:49 PM PDT 24
Finished Jun 05 05:38:51 PM PDT 24
Peak memory 205980 kb
Host smart-5cce47e6-3fb7-4b60-98d9-84ce995cf0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518294590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1518294590
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2860098204
Short name T629
Test name
Test status
Simulation time 218962004 ps
CPU time 2.44 seconds
Started Jun 05 05:38:48 PM PDT 24
Finished Jun 05 05:38:51 PM PDT 24
Peak memory 224404 kb
Host smart-afdbd1da-5cde-45fd-b13d-371c18d6e314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860098204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2860098204
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.763310104
Short name T312
Test name
Test status
Simulation time 14428912 ps
CPU time 0.74 seconds
Started Jun 05 05:38:52 PM PDT 24
Finished Jun 05 05:38:54 PM PDT 24
Peak memory 205568 kb
Host smart-fb46c18e-801d-4b06-8542-3197379b20cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763310104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.763310104
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2809384763
Short name T653
Test name
Test status
Simulation time 1330550581 ps
CPU time 3.21 seconds
Started Jun 05 05:38:54 PM PDT 24
Finished Jun 05 05:38:58 PM PDT 24
Peak memory 232856 kb
Host smart-4d99856a-5266-4a3f-895e-b257847daef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809384763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2809384763
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2495121379
Short name T739
Test name
Test status
Simulation time 39102097 ps
CPU time 0.72 seconds
Started Jun 05 05:38:52 PM PDT 24
Finished Jun 05 05:38:53 PM PDT 24
Peak memory 205724 kb
Host smart-f3d01019-0b8a-48c3-a3ef-5ab26e167e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495121379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2495121379
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1796385926
Short name T370
Test name
Test status
Simulation time 5955810167 ps
CPU time 42.99 seconds
Started Jun 05 05:38:53 PM PDT 24
Finished Jun 05 05:39:36 PM PDT 24
Peak memory 224712 kb
Host smart-f5e78c9e-29d4-4091-96d3-0e5e079cbd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796385926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1796385926
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1056812783
Short name T396
Test name
Test status
Simulation time 5210940667 ps
CPU time 12.25 seconds
Started Jun 05 05:38:54 PM PDT 24
Finished Jun 05 05:39:07 PM PDT 24
Peak memory 241076 kb
Host smart-f53afae7-a4cc-49bf-bf2c-df0eb6f96b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056812783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1056812783
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2684722686
Short name T149
Test name
Test status
Simulation time 1342222048548 ps
CPU time 679.21 seconds
Started Jun 05 05:38:53 PM PDT 24
Finished Jun 05 05:50:13 PM PDT 24
Peak memory 257500 kb
Host smart-35f611bc-e26a-412f-9122-d86566a76952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684722686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2684722686
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1330869255
Short name T796
Test name
Test status
Simulation time 5896147793 ps
CPU time 12.15 seconds
Started Jun 05 05:38:54 PM PDT 24
Finished Jun 05 05:39:07 PM PDT 24
Peak memory 224740 kb
Host smart-605a9f70-944e-4b49-96b3-5e8d0106b8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330869255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1330869255
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3231964088
Short name T99
Test name
Test status
Simulation time 206805597 ps
CPU time 4.84 seconds
Started Jun 05 05:38:54 PM PDT 24
Finished Jun 05 05:39:00 PM PDT 24
Peak memory 232900 kb
Host smart-5453f59e-d13a-4561-a5ff-f6e8b21baef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231964088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3231964088
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3640026827
Short name T880
Test name
Test status
Simulation time 1501298709 ps
CPU time 11.62 seconds
Started Jun 05 05:38:51 PM PDT 24
Finished Jun 05 05:39:03 PM PDT 24
Peak memory 232788 kb
Host smart-1eb11f96-92dd-4767-bf94-e9941cd98ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640026827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3640026827
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1245633706
Short name T941
Test name
Test status
Simulation time 481395699 ps
CPU time 2.48 seconds
Started Jun 05 05:38:54 PM PDT 24
Finished Jun 05 05:38:57 PM PDT 24
Peak memory 232828 kb
Host smart-c220d6bd-1e00-4335-aa08-db9ef66a2009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245633706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1245633706
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.160598687
Short name T755
Test name
Test status
Simulation time 826262234 ps
CPU time 2.3 seconds
Started Jun 05 05:38:53 PM PDT 24
Finished Jun 05 05:38:56 PM PDT 24
Peak memory 222940 kb
Host smart-5245c31e-7b61-43f6-b661-863411a5d4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160598687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.160598687
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2898114529
Short name T874
Test name
Test status
Simulation time 5681222449 ps
CPU time 15.34 seconds
Started Jun 05 05:38:56 PM PDT 24
Finished Jun 05 05:39:12 PM PDT 24
Peak memory 223232 kb
Host smart-5d013524-7d89-4bdc-853a-ceabb93e1d05
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2898114529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2898114529
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.349932431
Short name T889
Test name
Test status
Simulation time 3507172085 ps
CPU time 8.41 seconds
Started Jun 05 05:38:53 PM PDT 24
Finished Jun 05 05:39:02 PM PDT 24
Peak memory 216684 kb
Host smart-bb26e614-1a2e-4ff6-a987-77db73a36044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349932431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.349932431
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2532580360
Short name T334
Test name
Test status
Simulation time 4679195316 ps
CPU time 14.41 seconds
Started Jun 05 05:38:52 PM PDT 24
Finished Jun 05 05:39:07 PM PDT 24
Peak memory 216456 kb
Host smart-9e1f3b43-50d9-488f-9bc6-3ba121c33607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532580360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2532580360
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2997606354
Short name T576
Test name
Test status
Simulation time 282437800 ps
CPU time 2.56 seconds
Started Jun 05 05:38:59 PM PDT 24
Finished Jun 05 05:39:02 PM PDT 24
Peak memory 216484 kb
Host smart-52ea1506-e693-47ef-a922-c158e68c43c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997606354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2997606354
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2171120400
Short name T520
Test name
Test status
Simulation time 10859914 ps
CPU time 0.72 seconds
Started Jun 05 05:38:53 PM PDT 24
Finished Jun 05 05:38:54 PM PDT 24
Peak memory 205748 kb
Host smart-2f4cb726-eff1-43da-a103-293750594515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171120400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2171120400
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.4183355501
Short name T899
Test name
Test status
Simulation time 6541437709 ps
CPU time 7.22 seconds
Started Jun 05 05:38:53 PM PDT 24
Finished Jun 05 05:39:01 PM PDT 24
Peak memory 224688 kb
Host smart-e2858652-d904-4068-918b-193038f390c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183355501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4183355501
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3237521228
Short name T348
Test name
Test status
Simulation time 61153893 ps
CPU time 0.79 seconds
Started Jun 05 05:39:01 PM PDT 24
Finished Jun 05 05:39:02 PM PDT 24
Peak memory 205500 kb
Host smart-6c2f1576-2820-44bb-a07c-fc89ab137c39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237521228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3237521228
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3839733214
Short name T530
Test name
Test status
Simulation time 71408733 ps
CPU time 2.59 seconds
Started Jun 05 05:39:03 PM PDT 24
Finished Jun 05 05:39:06 PM PDT 24
Peak memory 232772 kb
Host smart-ba2c8b13-1c1c-419c-92b1-a676e947bb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839733214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3839733214
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.49915978
Short name T812
Test name
Test status
Simulation time 158533740 ps
CPU time 0.74 seconds
Started Jun 05 05:38:54 PM PDT 24
Finished Jun 05 05:38:55 PM PDT 24
Peak memory 206220 kb
Host smart-2cce12cf-df98-4160-9087-c5cd1f510383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49915978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.49915978
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.635082705
Short name T930
Test name
Test status
Simulation time 1440467476 ps
CPU time 10.5 seconds
Started Jun 05 05:39:01 PM PDT 24
Finished Jun 05 05:39:12 PM PDT 24
Peak memory 249428 kb
Host smart-3ffd8f62-02cd-492b-a447-44f04de9f723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635082705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.635082705
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.280254190
Short name T281
Test name
Test status
Simulation time 23605476671 ps
CPU time 97.21 seconds
Started Jun 05 05:39:02 PM PDT 24
Finished Jun 05 05:40:40 PM PDT 24
Peak memory 241172 kb
Host smart-6198d9d6-8f4c-4fbf-a667-8536596276ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280254190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.280254190
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.755224670
Short name T713
Test name
Test status
Simulation time 4333122155 ps
CPU time 70.32 seconds
Started Jun 05 05:39:03 PM PDT 24
Finished Jun 05 05:40:14 PM PDT 24
Peak memory 252644 kb
Host smart-1c1b3079-fac3-437f-8395-48aa1734826c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755224670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.755224670
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3729430639
Short name T364
Test name
Test status
Simulation time 1075011413 ps
CPU time 11.16 seconds
Started Jun 05 05:39:01 PM PDT 24
Finished Jun 05 05:39:12 PM PDT 24
Peak memory 232792 kb
Host smart-de0e0451-7cdf-434f-8470-da89afab095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729430639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3729430639
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3570067181
Short name T119
Test name
Test status
Simulation time 1189178545 ps
CPU time 11.44 seconds
Started Jun 05 05:39:02 PM PDT 24
Finished Jun 05 05:39:14 PM PDT 24
Peak memory 232900 kb
Host smart-90b16ff7-5ce4-42cb-8b26-6520c24485fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570067181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3570067181
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3539519290
Short name T424
Test name
Test status
Simulation time 2143627180 ps
CPU time 6.42 seconds
Started Jun 05 05:39:02 PM PDT 24
Finished Jun 05 05:39:10 PM PDT 24
Peak memory 224616 kb
Host smart-2470a120-3689-4489-ab09-c940a964dbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539519290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3539519290
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.86745563
Short name T555
Test name
Test status
Simulation time 47094292 ps
CPU time 2.65 seconds
Started Jun 05 05:38:53 PM PDT 24
Finished Jun 05 05:38:57 PM PDT 24
Peak memory 232880 kb
Host smart-33635246-c800-4d85-b40b-5932a3be6793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86745563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.86745563
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3911681864
Short name T775
Test name
Test status
Simulation time 596183199 ps
CPU time 3.81 seconds
Started Jun 05 05:38:52 PM PDT 24
Finished Jun 05 05:38:57 PM PDT 24
Peak memory 224648 kb
Host smart-bde4a9a8-3964-4e18-b07d-68c5732815bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911681864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3911681864
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1187214188
Short name T623
Test name
Test status
Simulation time 148729275 ps
CPU time 3.75 seconds
Started Jun 05 05:39:03 PM PDT 24
Finished Jun 05 05:39:07 PM PDT 24
Peak memory 222536 kb
Host smart-bcf9fdce-bf9b-4323-9834-ac9529ab022f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1187214188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1187214188
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1617721274
Short name T740
Test name
Test status
Simulation time 7507256105 ps
CPU time 23.41 seconds
Started Jun 05 05:38:53 PM PDT 24
Finished Jun 05 05:39:17 PM PDT 24
Peak memory 216520 kb
Host smart-888c30dc-f7d1-4f13-accf-05b35088aab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617721274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1617721274
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1633365956
Short name T920
Test name
Test status
Simulation time 602010996 ps
CPU time 5.04 seconds
Started Jun 05 05:38:56 PM PDT 24
Finished Jun 05 05:39:02 PM PDT 24
Peak memory 216356 kb
Host smart-6e7b3bd8-7fec-4baf-a5c5-88128900e548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633365956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1633365956
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2537714715
Short name T677
Test name
Test status
Simulation time 137510634 ps
CPU time 1.11 seconds
Started Jun 05 05:38:54 PM PDT 24
Finished Jun 05 05:38:56 PM PDT 24
Peak memory 216200 kb
Host smart-c5c02f88-d3e9-4b68-9c65-1999a763b349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537714715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2537714715
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1185340168
Short name T338
Test name
Test status
Simulation time 417636606 ps
CPU time 0.99 seconds
Started Jun 05 05:38:54 PM PDT 24
Finished Jun 05 05:38:56 PM PDT 24
Peak memory 207000 kb
Host smart-075b2cc6-cf6f-43ba-8cac-5f8747b31622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185340168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1185340168
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.852456973
Short name T923
Test name
Test status
Simulation time 34587725720 ps
CPU time 30.67 seconds
Started Jun 05 05:39:03 PM PDT 24
Finished Jun 05 05:39:35 PM PDT 24
Peak memory 240656 kb
Host smart-069527b4-ac27-428e-8882-aa052aa595ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852456973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.852456973
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.705887788
Short name T560
Test name
Test status
Simulation time 26635228 ps
CPU time 0.74 seconds
Started Jun 05 05:39:05 PM PDT 24
Finished Jun 05 05:39:06 PM PDT 24
Peak memory 204968 kb
Host smart-42823d13-1937-4622-9f8c-52d653bf8a25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705887788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.705887788
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2924281750
Short name T766
Test name
Test status
Simulation time 1257395981 ps
CPU time 5.22 seconds
Started Jun 05 05:39:01 PM PDT 24
Finished Jun 05 05:39:07 PM PDT 24
Peak memory 232792 kb
Host smart-9abc465e-d369-4b5d-8f9c-a2d9d1bcc8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924281750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2924281750
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3183482351
Short name T387
Test name
Test status
Simulation time 43120458 ps
CPU time 0.78 seconds
Started Jun 05 05:39:04 PM PDT 24
Finished Jun 05 05:39:05 PM PDT 24
Peak memory 207048 kb
Host smart-1f2d970f-17db-471b-9e07-cb1c5f22ee44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183482351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3183482351
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1514272510
Short name T201
Test name
Test status
Simulation time 34149361997 ps
CPU time 270.68 seconds
Started Jun 05 05:39:02 PM PDT 24
Finished Jun 05 05:43:34 PM PDT 24
Peak memory 263488 kb
Host smart-c732760c-93ad-4ceb-973f-018205a19358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514272510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1514272510
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3695556777
Short name T411
Test name
Test status
Simulation time 345929391775 ps
CPU time 386.37 seconds
Started Jun 05 05:39:08 PM PDT 24
Finished Jun 05 05:45:35 PM PDT 24
Peak memory 249320 kb
Host smart-5616c787-d9cc-487b-977b-fd27172f7f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695556777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3695556777
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2992878729
Short name T890
Test name
Test status
Simulation time 366273280015 ps
CPU time 164.93 seconds
Started Jun 05 05:39:12 PM PDT 24
Finished Jun 05 05:41:58 PM PDT 24
Peak memory 249352 kb
Host smart-92ebaa01-e05a-42d0-b3c0-ae666f69839c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992878729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2992878729
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1666168637
Short name T329
Test name
Test status
Simulation time 1581533520 ps
CPU time 7.76 seconds
Started Jun 05 05:39:03 PM PDT 24
Finished Jun 05 05:39:12 PM PDT 24
Peak memory 224636 kb
Host smart-2a09bf16-03ef-474a-9066-a890f0d4be9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666168637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1666168637
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3216286787
Short name T925
Test name
Test status
Simulation time 1380836383 ps
CPU time 4.31 seconds
Started Jun 05 05:39:02 PM PDT 24
Finished Jun 05 05:39:07 PM PDT 24
Peak memory 232824 kb
Host smart-2f771b0a-50c9-4dfc-ba87-b444fa08da46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216286787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3216286787
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.71874987
Short name T360
Test name
Test status
Simulation time 3536139733 ps
CPU time 6.7 seconds
Started Jun 05 05:39:02 PM PDT 24
Finished Jun 05 05:39:09 PM PDT 24
Peak memory 224632 kb
Host smart-fd296a27-15ea-4dc0-a30e-462e1756874d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71874987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.71874987
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.790291984
Short name T216
Test name
Test status
Simulation time 356948228 ps
CPU time 4.33 seconds
Started Jun 05 05:39:03 PM PDT 24
Finished Jun 05 05:39:08 PM PDT 24
Peak memory 232828 kb
Host smart-40ff8c7e-79e5-4bd4-81ce-e31bdf1a93c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790291984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.790291984
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3491011380
Short name T168
Test name
Test status
Simulation time 111673123685 ps
CPU time 33.1 seconds
Started Jun 05 05:39:01 PM PDT 24
Finished Jun 05 05:39:35 PM PDT 24
Peak memory 232856 kb
Host smart-e2104816-bb9d-4855-9636-056ee842530c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491011380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3491011380
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4249959887
Short name T373
Test name
Test status
Simulation time 4232037969 ps
CPU time 15.32 seconds
Started Jun 05 05:39:03 PM PDT 24
Finished Jun 05 05:39:19 PM PDT 24
Peak memory 219536 kb
Host smart-86f2e68a-40f1-4b7d-b094-98522909a651
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4249959887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4249959887
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1924079373
Short name T855
Test name
Test status
Simulation time 9284990443 ps
CPU time 76.89 seconds
Started Jun 05 05:39:09 PM PDT 24
Finished Jun 05 05:40:26 PM PDT 24
Peak memory 249196 kb
Host smart-55239219-5150-4864-b5a3-9d2463916558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924079373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1924079373
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.231796478
Short name T65
Test name
Test status
Simulation time 4315371479 ps
CPU time 15.8 seconds
Started Jun 05 05:39:03 PM PDT 24
Finished Jun 05 05:39:20 PM PDT 24
Peak memory 216616 kb
Host smart-74f88b42-efe9-4c48-a6be-c899eeb59361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231796478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.231796478
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.839398533
Short name T891
Test name
Test status
Simulation time 6216692578 ps
CPU time 8 seconds
Started Jun 05 05:39:07 PM PDT 24
Finished Jun 05 05:39:15 PM PDT 24
Peak memory 216472 kb
Host smart-c632a931-a18e-4294-af4b-7aa9bdaf6031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839398533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.839398533
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.291499500
Short name T888
Test name
Test status
Simulation time 189808929 ps
CPU time 2.35 seconds
Started Jun 05 05:39:00 PM PDT 24
Finished Jun 05 05:39:03 PM PDT 24
Peak memory 216472 kb
Host smart-a2d147c3-7a37-4f66-924c-5c59b9f953e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291499500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.291499500
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2741803930
Short name T681
Test name
Test status
Simulation time 44443259 ps
CPU time 0.82 seconds
Started Jun 05 05:39:02 PM PDT 24
Finished Jun 05 05:39:03 PM PDT 24
Peak memory 206004 kb
Host smart-29a9de80-0f0b-4b57-91d1-a295d57313e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741803930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2741803930
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2845923319
Short name T477
Test name
Test status
Simulation time 739922003 ps
CPU time 3.56 seconds
Started Jun 05 05:39:03 PM PDT 24
Finished Jun 05 05:39:07 PM PDT 24
Peak memory 224680 kb
Host smart-432b507d-ddf0-43fa-b9e9-801df0573816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845923319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2845923319
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.4006093713
Short name T504
Test name
Test status
Simulation time 39092775 ps
CPU time 0.71 seconds
Started Jun 05 05:39:13 PM PDT 24
Finished Jun 05 05:39:14 PM PDT 24
Peak memory 205536 kb
Host smart-ab373eae-1c03-4897-ad25-d0762e1c72ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006093713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
4006093713
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2781659062
Short name T879
Test name
Test status
Simulation time 3942651781 ps
CPU time 8.85 seconds
Started Jun 05 05:39:15 PM PDT 24
Finished Jun 05 05:39:25 PM PDT 24
Peak memory 232836 kb
Host smart-21c7cc9b-364b-49a3-a4ab-9e84e8d95681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781659062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2781659062
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.4044131059
Short name T427
Test name
Test status
Simulation time 96551881 ps
CPU time 0.8 seconds
Started Jun 05 05:39:10 PM PDT 24
Finished Jun 05 05:39:11 PM PDT 24
Peak memory 206748 kb
Host smart-b0a1b965-3d38-46e8-937c-0e5935df4d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044131059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4044131059
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2664030150
Short name T386
Test name
Test status
Simulation time 902112054 ps
CPU time 20.43 seconds
Started Jun 05 05:39:09 PM PDT 24
Finished Jun 05 05:39:30 PM PDT 24
Peak memory 249280 kb
Host smart-0e585fa2-e02f-4e61-bb12-d7e398c4e570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664030150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2664030150
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.322930413
Short name T725
Test name
Test status
Simulation time 51483668036 ps
CPU time 129.34 seconds
Started Jun 05 05:39:09 PM PDT 24
Finished Jun 05 05:41:18 PM PDT 24
Peak memory 234708 kb
Host smart-979a94fb-ad23-4ffd-b580-c3cd0aa7706f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322930413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.322930413
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1600635287
Short name T587
Test name
Test status
Simulation time 9758049499 ps
CPU time 55.53 seconds
Started Jun 05 05:39:05 PM PDT 24
Finished Jun 05 05:40:01 PM PDT 24
Peak memory 249788 kb
Host smart-c90118fd-060e-4577-9624-5d9e6076f50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600635287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1600635287
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2846775713
Short name T829
Test name
Test status
Simulation time 5482334491 ps
CPU time 33.17 seconds
Started Jun 05 05:39:11 PM PDT 24
Finished Jun 05 05:39:45 PM PDT 24
Peak memory 249160 kb
Host smart-8822a0f3-ea33-4624-975f-223ca7f72641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846775713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2846775713
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3037406197
Short name T54
Test name
Test status
Simulation time 260536125 ps
CPU time 6.64 seconds
Started Jun 05 05:39:07 PM PDT 24
Finished Jun 05 05:39:14 PM PDT 24
Peak memory 224600 kb
Host smart-223b8b11-714b-4d87-b1b9-1cad4973a17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037406197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3037406197
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3634390915
Short name T781
Test name
Test status
Simulation time 53231353 ps
CPU time 2.56 seconds
Started Jun 05 05:39:13 PM PDT 24
Finished Jun 05 05:39:16 PM PDT 24
Peak memory 232836 kb
Host smart-ad054336-e96e-4294-8fb2-9e6b5298af1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634390915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3634390915
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.560445247
Short name T631
Test name
Test status
Simulation time 7024216378 ps
CPU time 6.1 seconds
Started Jun 05 05:39:10 PM PDT 24
Finished Jun 05 05:39:16 PM PDT 24
Peak memory 233080 kb
Host smart-14411029-efd3-409e-8cb4-c8b88a2f4f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560445247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.560445247
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3265154586
Short name T691
Test name
Test status
Simulation time 3466275122 ps
CPU time 7.19 seconds
Started Jun 05 05:39:10 PM PDT 24
Finished Jun 05 05:39:18 PM PDT 24
Peak memory 232932 kb
Host smart-5aea9ec9-f644-4ae2-8f4d-f4e7f1de7a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265154586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3265154586
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3908384668
Short name T800
Test name
Test status
Simulation time 2397394100 ps
CPU time 3.85 seconds
Started Jun 05 05:39:10 PM PDT 24
Finished Jun 05 05:39:14 PM PDT 24
Peak memory 222840 kb
Host smart-84ed797e-7d1e-442c-8979-edaa6ef67dd5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3908384668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3908384668
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2034578341
Short name T814
Test name
Test status
Simulation time 2164632645 ps
CPU time 3.63 seconds
Started Jun 05 05:39:07 PM PDT 24
Finished Jun 05 05:39:11 PM PDT 24
Peak memory 216492 kb
Host smart-237cd139-59c8-4682-9d67-9c1d0df4aec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034578341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2034578341
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.930271992
Short name T423
Test name
Test status
Simulation time 13698482301 ps
CPU time 3.46 seconds
Started Jun 05 05:39:11 PM PDT 24
Finished Jun 05 05:39:15 PM PDT 24
Peak memory 216472 kb
Host smart-aa57dc90-ab18-4c57-8f4a-fbabfa401b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930271992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.930271992
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.481036399
Short name T496
Test name
Test status
Simulation time 88329770 ps
CPU time 0.89 seconds
Started Jun 05 05:39:12 PM PDT 24
Finished Jun 05 05:39:13 PM PDT 24
Peak memory 207060 kb
Host smart-2b892dce-bfa4-4dfb-a62b-5d48816c8d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481036399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.481036399
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1542353848
Short name T490
Test name
Test status
Simulation time 219313642 ps
CPU time 0.8 seconds
Started Jun 05 05:39:13 PM PDT 24
Finished Jun 05 05:39:14 PM PDT 24
Peak memory 205980 kb
Host smart-9cc0eb2c-3442-42ce-b179-20e87206c6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542353848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1542353848
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3507232168
Short name T733
Test name
Test status
Simulation time 6038855187 ps
CPU time 15.13 seconds
Started Jun 05 05:39:07 PM PDT 24
Finished Jun 05 05:39:23 PM PDT 24
Peak memory 232892 kb
Host smart-cbedf1b1-3e0a-4845-81b3-6863aadf314d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507232168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3507232168
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2138080875
Short name T25
Test name
Test status
Simulation time 13001517 ps
CPU time 0.73 seconds
Started Jun 05 05:35:30 PM PDT 24
Finished Jun 05 05:35:31 PM PDT 24
Peak memory 205872 kb
Host smart-d092abb2-a9cd-40dd-bf43-2a25ce7ac08b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138080875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
138080875
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3515242525
Short name T237
Test name
Test status
Simulation time 209288221 ps
CPU time 2.29 seconds
Started Jun 05 05:35:28 PM PDT 24
Finished Jun 05 05:35:31 PM PDT 24
Peak memory 224592 kb
Host smart-88fbf9f9-d4b5-4de9-a920-5979e22a77d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515242525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3515242525
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3966600650
Short name T350
Test name
Test status
Simulation time 49821573 ps
CPU time 0.76 seconds
Started Jun 05 05:35:28 PM PDT 24
Finished Jun 05 05:35:30 PM PDT 24
Peak memory 205708 kb
Host smart-a962f90f-e845-4bed-af78-78df1a5563a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966600650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3966600650
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2632953116
Short name T262
Test name
Test status
Simulation time 14435378363 ps
CPU time 49.76 seconds
Started Jun 05 05:35:29 PM PDT 24
Finished Jun 05 05:36:19 PM PDT 24
Peak memory 249636 kb
Host smart-cae71640-408f-4dcc-8591-457856c2bbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632953116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2632953116
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4130210471
Short name T202
Test name
Test status
Simulation time 61098244036 ps
CPU time 183.94 seconds
Started Jun 05 05:35:29 PM PDT 24
Finished Jun 05 05:38:34 PM PDT 24
Peak memory 252660 kb
Host smart-35ce3b1b-fec5-458c-a3df-6a14e5c62e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130210471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4130210471
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3856639751
Short name T280
Test name
Test status
Simulation time 14759837314 ps
CPU time 35.47 seconds
Started Jun 05 05:35:29 PM PDT 24
Finished Jun 05 05:36:05 PM PDT 24
Peak memory 217820 kb
Host smart-ce81d3af-92a0-4601-82e4-57a966fd762a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856639751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3856639751
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1825436962
Short name T341
Test name
Test status
Simulation time 1876671270 ps
CPU time 18 seconds
Started Jun 05 05:35:26 PM PDT 24
Finished Jun 05 05:35:45 PM PDT 24
Peak memory 232852 kb
Host smart-f5374b94-d91f-4446-b0b7-fce18f1ba828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825436962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1825436962
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3762386585
Short name T349
Test name
Test status
Simulation time 72329350 ps
CPU time 2.28 seconds
Started Jun 05 05:35:30 PM PDT 24
Finished Jun 05 05:35:33 PM PDT 24
Peak memory 223260 kb
Host smart-f4397e82-9a05-4a93-b4b0-4919e97c7223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762386585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3762386585
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3763435659
Short name T846
Test name
Test status
Simulation time 444306074 ps
CPU time 10.08 seconds
Started Jun 05 05:35:36 PM PDT 24
Finished Jun 05 05:35:46 PM PDT 24
Peak memory 232828 kb
Host smart-89262d83-292e-4860-a169-03517df58955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763435659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3763435659
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2787640651
Short name T244
Test name
Test status
Simulation time 2421185030 ps
CPU time 5.1 seconds
Started Jun 05 05:35:30 PM PDT 24
Finished Jun 05 05:35:35 PM PDT 24
Peak memory 224712 kb
Host smart-85c3e7c8-0a97-4be6-bcc1-14b3ac9711c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787640651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2787640651
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3276765843
Short name T59
Test name
Test status
Simulation time 136567934 ps
CPU time 2.43 seconds
Started Jun 05 05:35:31 PM PDT 24
Finished Jun 05 05:35:34 PM PDT 24
Peak memory 232876 kb
Host smart-6bd80fc6-40a6-44e8-a2f7-f1503d31ddae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276765843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3276765843
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3958470981
Short name T318
Test name
Test status
Simulation time 749338444 ps
CPU time 4.87 seconds
Started Jun 05 05:35:29 PM PDT 24
Finished Jun 05 05:35:34 PM PDT 24
Peak memory 223076 kb
Host smart-c01e7d82-feb7-4249-8f87-a27c15485443
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3958470981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3958470981
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2576904236
Short name T450
Test name
Test status
Simulation time 6532794448 ps
CPU time 16.98 seconds
Started Jun 05 05:35:35 PM PDT 24
Finished Jun 05 05:35:53 PM PDT 24
Peak memory 216616 kb
Host smart-39510700-efb5-4fa5-8e72-da7cfbe957f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576904236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2576904236
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2411259461
Short name T379
Test name
Test status
Simulation time 4602246079 ps
CPU time 7.92 seconds
Started Jun 05 05:35:30 PM PDT 24
Finished Jun 05 05:35:39 PM PDT 24
Peak memory 216548 kb
Host smart-12538927-b941-429e-85d7-f7c6bb115cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411259461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2411259461
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2654071951
Short name T731
Test name
Test status
Simulation time 425862784 ps
CPU time 1.16 seconds
Started Jun 05 05:35:29 PM PDT 24
Finished Jun 05 05:35:31 PM PDT 24
Peak memory 207268 kb
Host smart-c7c61f57-544a-4afe-9a11-33e20c567c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654071951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2654071951
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2603932529
Short name T577
Test name
Test status
Simulation time 143633607 ps
CPU time 0.81 seconds
Started Jun 05 05:35:28 PM PDT 24
Finished Jun 05 05:35:29 PM PDT 24
Peak memory 205984 kb
Host smart-6c35f8a0-46eb-4a8c-969b-4e08d97b1ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603932529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2603932529
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1042350007
Short name T247
Test name
Test status
Simulation time 518773164 ps
CPU time 4.4 seconds
Started Jun 05 05:35:27 PM PDT 24
Finished Jun 05 05:35:32 PM PDT 24
Peak memory 232824 kb
Host smart-e23135c3-e2a7-46eb-ac31-3cbb1d79a14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042350007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1042350007
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.469291601
Short name T467
Test name
Test status
Simulation time 17258605 ps
CPU time 0.75 seconds
Started Jun 05 05:35:35 PM PDT 24
Finished Jun 05 05:35:37 PM PDT 24
Peak memory 205564 kb
Host smart-b7a71db6-47bc-488c-9d93-3169ba809ca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469291601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.469291601
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3579028615
Short name T618
Test name
Test status
Simulation time 4285013579 ps
CPU time 6.35 seconds
Started Jun 05 05:35:36 PM PDT 24
Finished Jun 05 05:35:43 PM PDT 24
Peak memory 224660 kb
Host smart-6912b202-78f4-42f8-8b63-2ed4366be8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579028615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3579028615
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.361882515
Short name T337
Test name
Test status
Simulation time 55795087 ps
CPU time 0.77 seconds
Started Jun 05 05:35:33 PM PDT 24
Finished Jun 05 05:35:34 PM PDT 24
Peak memory 206780 kb
Host smart-6e33836b-38a6-42e2-a825-1f2b4e0695f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361882515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.361882515
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.829889390
Short name T151
Test name
Test status
Simulation time 240141723163 ps
CPU time 136.69 seconds
Started Jun 05 05:35:36 PM PDT 24
Finished Jun 05 05:37:54 PM PDT 24
Peak memory 238816 kb
Host smart-696a43e6-1230-4c45-a8a3-e08565de7e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829889390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.829889390
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1593635145
Short name T730
Test name
Test status
Simulation time 1536778243 ps
CPU time 39.78 seconds
Started Jun 05 05:35:39 PM PDT 24
Finished Jun 05 05:36:20 PM PDT 24
Peak memory 236856 kb
Host smart-2c5cb605-a847-45c2-ba91-1351a3213abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593635145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1593635145
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.36238289
Short name T124
Test name
Test status
Simulation time 333215301274 ps
CPU time 437.45 seconds
Started Jun 05 05:35:35 PM PDT 24
Finished Jun 05 05:42:53 PM PDT 24
Peak memory 255108 kb
Host smart-cb618478-4e79-45f1-af56-90c368c5a20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36238289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.36238289
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3866212284
Short name T150
Test name
Test status
Simulation time 863255895 ps
CPU time 4.1 seconds
Started Jun 05 05:35:35 PM PDT 24
Finished Jun 05 05:35:40 PM PDT 24
Peak memory 224708 kb
Host smart-cd33e828-4f8f-4f93-9210-090adf5621e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866212284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3866212284
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2065359500
Short name T473
Test name
Test status
Simulation time 4795282458 ps
CPU time 26.97 seconds
Started Jun 05 05:35:35 PM PDT 24
Finished Jun 05 05:36:03 PM PDT 24
Peak memory 224592 kb
Host smart-228592f3-12a3-4f10-a6bf-46ab90bc9144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065359500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2065359500
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4169169186
Short name T908
Test name
Test status
Simulation time 116984392 ps
CPU time 2.89 seconds
Started Jun 05 05:35:36 PM PDT 24
Finished Jun 05 05:35:40 PM PDT 24
Peak memory 232796 kb
Host smart-c5c5a04f-9a53-41e0-9078-d2a31a61d57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169169186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4169169186
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1472110993
Short name T240
Test name
Test status
Simulation time 3417897365 ps
CPU time 7.41 seconds
Started Jun 05 05:35:35 PM PDT 24
Finished Jun 05 05:35:43 PM PDT 24
Peak memory 224708 kb
Host smart-29049608-0bff-4929-9f2d-fb5ddd8e03a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472110993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1472110993
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2798803334
Short name T934
Test name
Test status
Simulation time 5292306917 ps
CPU time 7.89 seconds
Started Jun 05 05:35:37 PM PDT 24
Finished Jun 05 05:35:45 PM PDT 24
Peak memory 220156 kb
Host smart-c6666900-2db5-4d29-9871-50adecec2e1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2798803334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2798803334
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1587332481
Short name T203
Test name
Test status
Simulation time 462993753329 ps
CPU time 773 seconds
Started Jun 05 05:35:36 PM PDT 24
Finished Jun 05 05:48:30 PM PDT 24
Peak memory 282120 kb
Host smart-b7945ce0-0995-4228-ae4d-21c385fb34d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587332481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1587332481
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1143170543
Short name T292
Test name
Test status
Simulation time 110046377146 ps
CPU time 28.68 seconds
Started Jun 05 05:35:34 PM PDT 24
Finished Jun 05 05:36:03 PM PDT 24
Peak memory 216528 kb
Host smart-e2737e3b-7985-4cf6-8452-7e461f5b929f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143170543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1143170543
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1740227025
Short name T636
Test name
Test status
Simulation time 5402075394 ps
CPU time 15.55 seconds
Started Jun 05 05:35:29 PM PDT 24
Finished Jun 05 05:35:45 PM PDT 24
Peak memory 216408 kb
Host smart-ad39b703-3bb4-405a-8329-564801e28714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740227025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1740227025
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1625334205
Short name T324
Test name
Test status
Simulation time 304112727 ps
CPU time 6.95 seconds
Started Jun 05 05:35:36 PM PDT 24
Finished Jun 05 05:35:44 PM PDT 24
Peak memory 216376 kb
Host smart-fda79bf6-cc89-43e5-818c-89eaa172a47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625334205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1625334205
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1330119497
Short name T342
Test name
Test status
Simulation time 110584846 ps
CPU time 0.92 seconds
Started Jun 05 05:35:33 PM PDT 24
Finished Jun 05 05:35:35 PM PDT 24
Peak memory 207028 kb
Host smart-92319910-783d-40b4-8a89-99ae404323cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330119497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1330119497
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3635770738
Short name T548
Test name
Test status
Simulation time 716136615 ps
CPU time 4.51 seconds
Started Jun 05 05:35:36 PM PDT 24
Finished Jun 05 05:35:41 PM PDT 24
Peak memory 224628 kb
Host smart-7e95b9de-a813-4d5b-8894-f0155e30203a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635770738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3635770738
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.99942415
Short name T404
Test name
Test status
Simulation time 15211875 ps
CPU time 0.74 seconds
Started Jun 05 05:35:44 PM PDT 24
Finished Jun 05 05:35:45 PM PDT 24
Peak memory 204948 kb
Host smart-44d04699-6f2e-4247-aea2-07b7e8dcd7de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99942415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.99942415
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1984215627
Short name T307
Test name
Test status
Simulation time 1072477642 ps
CPU time 4.73 seconds
Started Jun 05 05:35:43 PM PDT 24
Finished Jun 05 05:35:48 PM PDT 24
Peak memory 224604 kb
Host smart-ae213a1d-a52c-48c6-9dd1-031248a1b7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984215627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1984215627
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2998729697
Short name T557
Test name
Test status
Simulation time 17133032 ps
CPU time 0.76 seconds
Started Jun 05 05:35:36 PM PDT 24
Finished Jun 05 05:35:37 PM PDT 24
Peak memory 205700 kb
Host smart-cd693c9f-ba6d-4def-a598-7fb930236cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998729697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2998729697
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3532576922
Short name T761
Test name
Test status
Simulation time 1525835050 ps
CPU time 13.18 seconds
Started Jun 05 05:35:47 PM PDT 24
Finished Jun 05 05:36:01 PM PDT 24
Peak memory 224644 kb
Host smart-d43aab97-f3ec-4cd1-ade6-b651499a0089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532576922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3532576922
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3267284107
Short name T808
Test name
Test status
Simulation time 64392260136 ps
CPU time 134.3 seconds
Started Jun 05 05:35:44 PM PDT 24
Finished Jun 05 05:37:59 PM PDT 24
Peak memory 234136 kb
Host smart-0ae64956-a7c0-4e10-9641-ff1b0218e394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267284107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3267284107
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1421527265
Short name T55
Test name
Test status
Simulation time 2992111101 ps
CPU time 9.66 seconds
Started Jun 05 05:35:45 PM PDT 24
Finished Jun 05 05:35:56 PM PDT 24
Peak memory 237740 kb
Host smart-e5ee5750-f47b-409a-8449-d8dffc3c468b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421527265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1421527265
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4115099334
Short name T641
Test name
Test status
Simulation time 420086773 ps
CPU time 3.74 seconds
Started Jun 05 05:35:37 PM PDT 24
Finished Jun 05 05:35:41 PM PDT 24
Peak memory 224632 kb
Host smart-51c7f513-c8ec-49ba-814d-e0b174e9374b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115099334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4115099334
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2160012879
Short name T181
Test name
Test status
Simulation time 784746298 ps
CPU time 6.61 seconds
Started Jun 05 05:35:33 PM PDT 24
Finished Jun 05 05:35:40 PM PDT 24
Peak memory 232820 kb
Host smart-3164f03f-c102-4805-b529-f5c662f2a2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160012879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2160012879
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3807146973
Short name T946
Test name
Test status
Simulation time 276457348 ps
CPU time 4.83 seconds
Started Jun 05 05:35:36 PM PDT 24
Finished Jun 05 05:35:42 PM PDT 24
Peak memory 236064 kb
Host smart-4480a628-1164-4020-a43a-00025bfe6a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807146973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3807146973
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.28012626
Short name T867
Test name
Test status
Simulation time 7085071719 ps
CPU time 18.49 seconds
Started Jun 05 05:35:35 PM PDT 24
Finished Jun 05 05:35:54 PM PDT 24
Peak memory 232800 kb
Host smart-d4a68548-0ca0-4bbe-bec5-810d78925ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28012626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.28012626
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2530687997
Short name T539
Test name
Test status
Simulation time 1407787236 ps
CPU time 8.7 seconds
Started Jun 05 05:35:42 PM PDT 24
Finished Jun 05 05:35:52 PM PDT 24
Peak memory 223160 kb
Host smart-f32a9268-91cf-4e77-be64-a1730b6b7cba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2530687997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2530687997
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4281674249
Short name T562
Test name
Test status
Simulation time 42338040 ps
CPU time 0.71 seconds
Started Jun 05 05:35:35 PM PDT 24
Finished Jun 05 05:35:37 PM PDT 24
Peak memory 205736 kb
Host smart-5b57db33-62f7-416f-af42-9ef323e858f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281674249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4281674249
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2631153640
Short name T673
Test name
Test status
Simulation time 852608428 ps
CPU time 3.18 seconds
Started Jun 05 05:35:35 PM PDT 24
Finished Jun 05 05:35:39 PM PDT 24
Peak memory 216416 kb
Host smart-ce5dfcd5-2738-484d-a337-19a303844de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631153640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2631153640
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3178696644
Short name T611
Test name
Test status
Simulation time 149240252 ps
CPU time 2.35 seconds
Started Jun 05 05:35:39 PM PDT 24
Finished Jun 05 05:35:42 PM PDT 24
Peak memory 216452 kb
Host smart-5a4ef756-c149-499a-990a-39afcc4c6a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178696644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3178696644
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2880576446
Short name T852
Test name
Test status
Simulation time 76961900 ps
CPU time 0.91 seconds
Started Jun 05 05:35:36 PM PDT 24
Finished Jun 05 05:35:37 PM PDT 24
Peak memory 206012 kb
Host smart-87e76f15-d3fe-4349-8f2b-27854b992e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880576446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2880576446
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3653893153
Short name T482
Test name
Test status
Simulation time 7892590853 ps
CPU time 6.15 seconds
Started Jun 05 05:35:39 PM PDT 24
Finished Jun 05 05:35:46 PM PDT 24
Peak memory 224644 kb
Host smart-16c38f57-d1d9-4b7a-b81a-f7a199022570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653893153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3653893153
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2639058521
Short name T667
Test name
Test status
Simulation time 23708874 ps
CPU time 0.73 seconds
Started Jun 05 05:35:50 PM PDT 24
Finished Jun 05 05:35:51 PM PDT 24
Peak memory 205620 kb
Host smart-326c9537-0d76-4eb2-ac02-8abc3ca82a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639058521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
639058521
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1195847315
Short name T706
Test name
Test status
Simulation time 202943742 ps
CPU time 3.77 seconds
Started Jun 05 05:35:46 PM PDT 24
Finished Jun 05 05:35:50 PM PDT 24
Peak memory 232836 kb
Host smart-b6c57f77-c74e-4015-9a4b-71852a1aa88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195847315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1195847315
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.951018426
Short name T642
Test name
Test status
Simulation time 55104882 ps
CPU time 0.74 seconds
Started Jun 05 05:35:42 PM PDT 24
Finished Jun 05 05:35:44 PM PDT 24
Peak memory 206064 kb
Host smart-2b3eb1d6-6138-4a99-ae68-16e06c16c98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951018426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.951018426
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.683625475
Short name T541
Test name
Test status
Simulation time 5499463265 ps
CPU time 49.2 seconds
Started Jun 05 05:35:44 PM PDT 24
Finished Jun 05 05:36:34 PM PDT 24
Peak memory 255416 kb
Host smart-052a39d7-ca30-48cc-ab28-679058ddbdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683625475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.683625475
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1942300337
Short name T198
Test name
Test status
Simulation time 6755452258 ps
CPU time 72.01 seconds
Started Jun 05 05:35:45 PM PDT 24
Finished Jun 05 05:36:58 PM PDT 24
Peak memory 264812 kb
Host smart-cb8e6d9b-d470-4dec-b0eb-071308283db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942300337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1942300337
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3813831432
Short name T881
Test name
Test status
Simulation time 68207100715 ps
CPU time 143.58 seconds
Started Jun 05 05:35:51 PM PDT 24
Finished Jun 05 05:38:15 PM PDT 24
Peak memory 249356 kb
Host smart-33b75680-8e47-4eab-8fbe-6825c09f9a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813831432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3813831432
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1688285381
Short name T301
Test name
Test status
Simulation time 185523899 ps
CPU time 4.69 seconds
Started Jun 05 05:35:44 PM PDT 24
Finished Jun 05 05:35:49 PM PDT 24
Peak memory 232812 kb
Host smart-8a177501-64c2-4e30-beb8-8025683449f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688285381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1688285381
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2717417293
Short name T780
Test name
Test status
Simulation time 2991527532 ps
CPU time 23.4 seconds
Started Jun 05 05:35:45 PM PDT 24
Finished Jun 05 05:36:10 PM PDT 24
Peak memory 224620 kb
Host smart-5d9db08e-537f-4a6d-b404-4daa68682543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717417293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2717417293
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1925239888
Short name T769
Test name
Test status
Simulation time 49008353760 ps
CPU time 131.82 seconds
Started Jun 05 05:35:45 PM PDT 24
Finished Jun 05 05:37:58 PM PDT 24
Peak memory 227132 kb
Host smart-c81f5379-eb71-48dc-b7c1-93f395dcb797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925239888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1925239888
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4208960716
Short name T638
Test name
Test status
Simulation time 8337852475 ps
CPU time 9.26 seconds
Started Jun 05 05:35:45 PM PDT 24
Finished Jun 05 05:35:55 PM PDT 24
Peak memory 232892 kb
Host smart-822566be-9faf-4c66-9d8c-f05f11d45f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208960716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4208960716
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2890432232
Short name T61
Test name
Test status
Simulation time 148957736 ps
CPU time 3.07 seconds
Started Jun 05 05:35:44 PM PDT 24
Finished Jun 05 05:35:49 PM PDT 24
Peak memory 227068 kb
Host smart-478f9904-408c-4356-a0dc-9e6d9826d933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890432232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2890432232
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.587445485
Short name T442
Test name
Test status
Simulation time 347663798 ps
CPU time 4.6 seconds
Started Jun 05 05:35:45 PM PDT 24
Finished Jun 05 05:35:51 PM PDT 24
Peak memory 219316 kb
Host smart-d5f8a0d0-5c95-4ef0-8b90-587759ac290b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=587445485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.587445485
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2521820925
Short name T625
Test name
Test status
Simulation time 36319522 ps
CPU time 0.95 seconds
Started Jun 05 05:35:52 PM PDT 24
Finished Jun 05 05:35:53 PM PDT 24
Peak memory 206952 kb
Host smart-944a598b-b1f9-46e6-abae-95a18854c09a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521820925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2521820925
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.784536355
Short name T581
Test name
Test status
Simulation time 93128540 ps
CPU time 2.15 seconds
Started Jun 05 05:35:42 PM PDT 24
Finished Jun 05 05:35:45 PM PDT 24
Peak memory 216660 kb
Host smart-e5d3bc8e-d04d-4c31-8e26-143621ee2472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784536355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.784536355
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2433781826
Short name T322
Test name
Test status
Simulation time 1162347473 ps
CPU time 7.58 seconds
Started Jun 05 05:35:45 PM PDT 24
Finished Jun 05 05:35:53 PM PDT 24
Peak memory 216348 kb
Host smart-5735c279-7735-4f49-b52a-25c3db196f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433781826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2433781826
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.632756701
Short name T910
Test name
Test status
Simulation time 54780083 ps
CPU time 1.46 seconds
Started Jun 05 05:35:42 PM PDT 24
Finished Jun 05 05:35:44 PM PDT 24
Peak memory 216432 kb
Host smart-dff07614-6479-4623-b356-177d31dfafb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632756701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.632756701
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.4123318329
Short name T294
Test name
Test status
Simulation time 114392162 ps
CPU time 0.78 seconds
Started Jun 05 05:35:44 PM PDT 24
Finished Jun 05 05:35:45 PM PDT 24
Peak memory 205984 kb
Host smart-ae09041e-fba4-4f29-b90d-d6c7bb995ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123318329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.4123318329
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4088780967
Short name T6
Test name
Test status
Simulation time 3607015100 ps
CPU time 6.87 seconds
Started Jun 05 05:35:44 PM PDT 24
Finished Jun 05 05:35:52 PM PDT 24
Peak memory 224672 kb
Host smart-a0f2d9bc-bc19-4756-af05-583455819080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088780967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4088780967
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1178754610
Short name T564
Test name
Test status
Simulation time 40681067 ps
CPU time 0.71 seconds
Started Jun 05 05:35:57 PM PDT 24
Finished Jun 05 05:35:58 PM PDT 24
Peak memory 205484 kb
Host smart-e079630a-bec3-441a-af39-74fff14aeeea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178754610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
178754610
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.370776963
Short name T267
Test name
Test status
Simulation time 51506520 ps
CPU time 2.62 seconds
Started Jun 05 05:35:50 PM PDT 24
Finished Jun 05 05:35:53 PM PDT 24
Peak memory 224640 kb
Host smart-fc19fc48-1af5-4926-92e9-2dc4a5400156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370776963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.370776963
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.499176232
Short name T680
Test name
Test status
Simulation time 16196243 ps
CPU time 0.74 seconds
Started Jun 05 05:35:49 PM PDT 24
Finished Jun 05 05:35:50 PM PDT 24
Peak memory 205660 kb
Host smart-3360de9e-f428-4f86-857b-73f941221893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499176232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.499176232
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.431824451
Short name T773
Test name
Test status
Simulation time 22307645846 ps
CPU time 34.3 seconds
Started Jun 05 05:35:50 PM PDT 24
Finished Jun 05 05:36:24 PM PDT 24
Peak memory 223056 kb
Host smart-4455c67f-3d48-4065-ae0d-c5f0145a650e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431824451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.431824451
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3500349203
Short name T911
Test name
Test status
Simulation time 7805308127 ps
CPU time 79.75 seconds
Started Jun 05 05:35:51 PM PDT 24
Finished Jun 05 05:37:11 PM PDT 24
Peak memory 256984 kb
Host smart-991ad294-c799-4457-9bef-b83ad3e9806c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500349203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3500349203
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1187710718
Short name T254
Test name
Test status
Simulation time 9537086520 ps
CPU time 30.96 seconds
Started Jun 05 05:35:49 PM PDT 24
Finished Jun 05 05:36:21 PM PDT 24
Peak memory 224652 kb
Host smart-35af9405-a91b-4607-9336-13961efb4180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187710718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1187710718
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1137296828
Short name T632
Test name
Test status
Simulation time 2613416098 ps
CPU time 22.63 seconds
Started Jun 05 05:35:49 PM PDT 24
Finished Jun 05 05:36:12 PM PDT 24
Peak memory 224692 kb
Host smart-940a208a-ee25-434b-85de-21984a0ecc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137296828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1137296828
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.586456695
Short name T12
Test name
Test status
Simulation time 6620441307 ps
CPU time 9.19 seconds
Started Jun 05 05:35:53 PM PDT 24
Finished Jun 05 05:36:03 PM PDT 24
Peak memory 240984 kb
Host smart-f103f0c3-9290-45bb-83da-768828d2fec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586456695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.586456695
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1302086369
Short name T188
Test name
Test status
Simulation time 615327353 ps
CPU time 3.25 seconds
Started Jun 05 05:35:54 PM PDT 24
Finished Jun 05 05:35:57 PM PDT 24
Peak memory 232800 kb
Host smart-bfb880b4-2286-4862-9c61-43346c87fefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302086369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1302086369
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.837794419
Short name T511
Test name
Test status
Simulation time 4003217264 ps
CPU time 9.59 seconds
Started Jun 05 05:35:52 PM PDT 24
Finished Jun 05 05:36:02 PM PDT 24
Peak memory 240556 kb
Host smart-4287d7c0-cf05-4566-8351-243043afa118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837794419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.837794419
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3515075845
Short name T597
Test name
Test status
Simulation time 236872716 ps
CPU time 5.12 seconds
Started Jun 05 05:35:50 PM PDT 24
Finished Jun 05 05:35:56 PM PDT 24
Peak memory 222624 kb
Host smart-a39658dd-0ba2-4959-913b-42d15d920f4b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3515075845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3515075845
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2029772911
Short name T903
Test name
Test status
Simulation time 97292501779 ps
CPU time 952.03 seconds
Started Jun 05 05:35:59 PM PDT 24
Finished Jun 05 05:51:52 PM PDT 24
Peak memory 283172 kb
Host smart-a25f917e-6ffb-4d42-8796-5c6c0bc50cc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029772911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2029772911
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.808551261
Short name T917
Test name
Test status
Simulation time 6789383028 ps
CPU time 17.75 seconds
Started Jun 05 05:35:53 PM PDT 24
Finished Jun 05 05:36:11 PM PDT 24
Peak memory 216764 kb
Host smart-0c59ea6f-2a2f-4d4c-9f53-d6a30c0d8ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808551261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.808551261
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.804811129
Short name T771
Test name
Test status
Simulation time 2679683712 ps
CPU time 4.52 seconds
Started Jun 05 05:35:52 PM PDT 24
Finished Jun 05 05:35:58 PM PDT 24
Peak memory 216408 kb
Host smart-5e0547c5-d913-436f-a36b-efaee5dd5c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804811129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.804811129
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3066583286
Short name T331
Test name
Test status
Simulation time 27264822 ps
CPU time 1.22 seconds
Started Jun 05 05:35:51 PM PDT 24
Finished Jun 05 05:35:53 PM PDT 24
Peak memory 216080 kb
Host smart-b8d03a73-7f0e-451e-afaf-3cb9f31e4753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066583286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3066583286
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3975486812
Short name T321
Test name
Test status
Simulation time 20103288 ps
CPU time 0.72 seconds
Started Jun 05 05:35:50 PM PDT 24
Finished Jun 05 05:35:52 PM PDT 24
Peak memory 206044 kb
Host smart-ba3f02ad-e13f-4aa3-814b-6a4a036be34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975486812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3975486812
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.506850514
Short name T558
Test name
Test status
Simulation time 7797829136 ps
CPU time 14.48 seconds
Started Jun 05 05:35:51 PM PDT 24
Finished Jun 05 05:36:07 PM PDT 24
Peak memory 232844 kb
Host smart-cd8f0762-260e-4e48-9f00-8860eeec24d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506850514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.506850514
Directory /workspace/9.spi_device_upload/latest
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