Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3189197	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3694814

1

T1

15083

T2

896

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3859577	1			T1	17051		T2	6		T3	1
values[0x0]	1512581	1			T1	7716		T2	448		T3	2
values[0x1]	1511853	1			T1	7699		T2	444		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2270506	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4613505

1

T1

20446

T2

897

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28625	1			T1	145		T4	59		T5	3
valid_sources[0x01]	25526	1			T1	126		T2	6		T4	56
valid_sources[0x02]	24095	1			T1	164		T2	3		T4	65
valid_sources[0x03]	27853	1			T1	126		T2	4		T4	66
valid_sources[0x04]	24084	1			T1	176		T2	11		T4	82
valid_sources[0x05]	26627	1			T1	148		T2	2		T4	61
valid_sources[0x06]	26514	1			T1	72		T2	1		T4	68
valid_sources[0x07]	30676	1			T1	125		T2	8		T4	68
valid_sources[0x08]	26804	1			T1	116		T2	1		T4	78
valid_sources[0x09]	24754	1			T1	132		T2	2		T4	78
valid_sources[0x0a]	27662	1			T1	105		T2	4		T4	72
valid_sources[0x0b]	27858	1			T1	126		T2	8		T4	73
valid_sources[0x0c]	25023	1			T1	118		T2	3		T4	80
valid_sources[0x0d]	24715	1			T1	104		T2	2		T4	68
valid_sources[0x0e]	24830	1			T1	128		T2	4		T4	81
valid_sources[0x0f]	28338	1			T1	157		T2	1		T4	79
valid_sources[0x10]	24775	1			T1	84		T2	1		T4	60
valid_sources[0x11]	24797	1			T1	101		T2	7		T4	74
valid_sources[0x12]	27884	1			T1	98		T2	4		T4	65
valid_sources[0x13]	28194	1			T1	119		T2	2		T4	77
valid_sources[0x14]	23903	1			T1	104		T2	3		T4	67
valid_sources[0x15]	31462	1			T1	117		T2	1		T4	74
valid_sources[0x16]	25996	1			T1	168		T2	2		T4	56
valid_sources[0x17]	24390	1			T1	135		T2	3		T4	69
valid_sources[0x18]	31591	1			T1	143		T2	8		T4	62
valid_sources[0x19]	24424	1			T1	132		T4	78		T5	2
valid_sources[0x1a]	29787	1			T1	111		T2	5		T4	71
valid_sources[0x1b]	25186	1			T1	146		T2	2		T4	62
valid_sources[0x1c]	24521	1			T1	88		T2	2		T4	65
valid_sources[0x1d]	29879	1			T1	107		T2	1		T4	56
valid_sources[0x1e]	26163	1			T1	107		T2	1		T4	65
valid_sources[0x1f]	32450	1			T1	125		T2	1		T4	60
valid_sources[0x20]	24721	1			T1	133		T2	1		T4	59
valid_sources[0x21]	24748	1			T1	108		T4	66		T7	44
valid_sources[0x22]	25548	1			T1	109		T2	2		T4	54
valid_sources[0x23]	25718	1			T1	144		T2	9		T4	67
valid_sources[0x24]	27057	1			T1	141		T2	4		T4	74
valid_sources[0x25]	26585	1			T1	151		T2	7		T4	85
valid_sources[0x26]	31170	1			T1	95		T2	5		T4	75
valid_sources[0x27]	26117	1			T1	131		T4	68		T5	12
valid_sources[0x28]	27899	1			T1	120		T2	2		T4	58
valid_sources[0x29]	24093	1			T1	106		T2	3		T4	74
valid_sources[0x2a]	26701	1			T1	95		T2	9		T4	71
valid_sources[0x2b]	25145	1			T1	170		T2	1		T4	77
valid_sources[0x2c]	25782	1			T1	122		T2	1		T4	63
valid_sources[0x2d]	23357	1			T1	131		T2	4		T4	59
valid_sources[0x2e]	24271	1			T1	155		T2	1		T4	86
valid_sources[0x2f]	29713	1			T1	91		T2	4		T4	68
valid_sources[0x30]	28857	1			T1	160		T2	2		T4	52
valid_sources[0x31]	22335	1			T1	155		T2	7		T4	76
valid_sources[0x32]	31694	1			T1	139		T2	9		T4	70
valid_sources[0x33]	26159	1			T1	163		T2	1		T4	75
valid_sources[0x34]	24499	1			T1	120		T2	4		T4	69
valid_sources[0x35]	26836	1			T1	145		T2	1		T4	75
valid_sources[0x36]	23253	1			T1	133		T2	4		T4	49
valid_sources[0x37]	22122	1			T1	121		T2	2		T4	75
valid_sources[0x38]	28074	1			T1	113		T2	5		T4	74
valid_sources[0x39]	26138	1			T1	118		T4	76		T5	12
valid_sources[0x3a]	27111	1			T1	123		T2	4		T4	66
valid_sources[0x3b]	24853	1			T1	120		T4	67		T5	2
valid_sources[0x3c]	26922	1			T1	153		T2	3		T4	62
valid_sources[0x3d]	26558	1			T1	124		T2	11		T4	60
valid_sources[0x3e]	28686	1			T1	142		T2	5		T4	70
valid_sources[0x3f]	25554	1			T1	121		T2	4		T4	75
valid_sources[0x40]	25572	1			T1	91		T2	7		T4	83
valid_sources[0x41]	24774	1			T1	116		T4	57		T5	2
valid_sources[0x42]	25240	1			T1	138		T2	16		T4	75
valid_sources[0x43]	27124	1			T1	106		T2	11		T4	56
valid_sources[0x44]	26516	1			T1	124		T2	9		T4	73
valid_sources[0x45]	25453	1			T1	146		T2	1		T4	60
valid_sources[0x46]	26017	1			T1	99		T2	1		T4	70
valid_sources[0x47]	28204	1			T1	114		T2	2		T4	81
valid_sources[0x48]	24018	1			T1	194		T2	6		T4	64
valid_sources[0x49]	40127	1			T1	97		T2	5		T4	57
valid_sources[0x4a]	25633	1			T1	93		T2	1		T4	58
valid_sources[0x4b]	25007	1			T1	136		T2	2		T4	64
valid_sources[0x4c]	23821	1			T1	129		T2	8		T4	71
valid_sources[0x4d]	26355	1			T1	130		T2	3		T4	73
valid_sources[0x4e]	24389	1			T1	98		T2	7		T4	65
valid_sources[0x4f]	27316	1			T1	136		T2	4		T4	70
valid_sources[0x50]	26772	1			T1	120		T4	71		T5	2
valid_sources[0x51]	24801	1			T1	118		T2	3		T4	65
valid_sources[0x52]	25161	1			T1	99		T2	7		T4	53
valid_sources[0x53]	26302	1			T1	142		T2	6		T4	77
valid_sources[0x54]	24491	1			T1	80		T2	7		T4	74
valid_sources[0x55]	38963	1			T1	133		T2	7		T4	55
valid_sources[0x56]	24336	1			T1	155		T2	5		T4	64
valid_sources[0x57]	25537	1			T1	129		T2	2		T4	59
valid_sources[0x58]	25224	1			T1	121		T2	8		T4	70
valid_sources[0x59]	29540	1			T1	120		T2	3		T4	57
valid_sources[0x5a]	25071	1			T1	122		T2	2		T4	66
valid_sources[0x5b]	25580	1			T1	123		T2	3		T4	68
valid_sources[0x5c]	24747	1			T1	115		T2	4		T4	59
valid_sources[0x5d]	26987	1			T1	140		T2	3		T4	64
valid_sources[0x5e]	25634	1			T1	174		T2	4		T4	66
valid_sources[0x5f]	24054	1			T1	141		T2	12		T4	61
valid_sources[0x60]	23186	1			T1	129		T2	1		T4	80
valid_sources[0x61]	41666	1			T1	136		T2	3		T4	78
valid_sources[0x62]	24020	1			T1	109		T4	66		T7	37
valid_sources[0x63]	24013	1			T1	127		T2	5		T4	57
valid_sources[0x64]	24377	1			T1	119		T4	73		T7	31
valid_sources[0x65]	22712	1			T1	92		T2	2		T4	49
valid_sources[0x66]	30314	1			T1	158		T4	61		T5	12
valid_sources[0x67]	24933	1			T1	134		T2	6		T4	61
valid_sources[0x68]	24502	1			T1	128		T2	1		T4	80
valid_sources[0x69]	25699	1			T1	157		T2	1		T4	52
valid_sources[0x6a]	25140	1			T1	105		T2	1		T4	72
valid_sources[0x6b]	88484	1			T1	137		T2	11		T4	62
valid_sources[0x6c]	28267	1			T1	131		T4	56		T7	20
valid_sources[0x6d]	25097	1			T1	160		T2	2		T4	57
valid_sources[0x6e]	25683	1			T1	120		T2	4		T4	76
valid_sources[0x6f]	22859	1			T1	143		T2	6		T4	79
valid_sources[0x70]	23648	1			T1	123		T4	79		T5	1
valid_sources[0x71]	26599	1			T1	87		T2	2		T4	66
valid_sources[0x72]	30244	1			T1	128		T2	6		T4	71
valid_sources[0x73]	27972	1			T1	105		T2	5		T4	66
valid_sources[0x74]	25784	1			T1	113		T2	5		T4	61
valid_sources[0x75]	26063	1			T1	122		T4	61		T7	39
valid_sources[0x76]	29362	1			T1	164		T4	61		T5	7
valid_sources[0x77]	28810	1			T1	133		T2	3		T4	64
valid_sources[0x78]	26232	1			T1	117		T2	4		T4	79
valid_sources[0x79]	25433	1			T1	158		T2	7		T4	72
valid_sources[0x7a]	25171	1			T1	104		T2	9		T4	68
valid_sources[0x7b]	27223	1			T1	140		T2	4		T4	77
valid_sources[0x7c]	22855	1			T1	116		T2	4		T4	55
valid_sources[0x7d]	28430	1			T1	101		T2	4		T4	54
valid_sources[0x7e]	26863	1			T1	67		T2	3		T4	60
valid_sources[0x7f]	23746	1			T1	139		T2	5		T4	74
valid_sources[0x80]	26681	1			T1	121		T2	1		T4	52

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

970343

1

T1

1912

T2

6

T3

1

values[0x0]

all_enables

biggest_size

1374347

1

T1

6695

T2

447

T3

1

values[0x1]

all_enables

biggest_size

1350124

1

T1

6476

T2

443

T4

1772