Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3207119

1

T1

17383

T2

2

T3

4

full_word

3695835

1

T1

15083

T2

896

T3

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6902594	1			T1	32466		T2	898		T3	6
auto[TlIntgErrCmd]	137	1			T90	4		T92	11		T94	6
auto[TlIntgErrData]	107	1			T90	1		T92	9		T94	8
auto[TlIntgErrBoth]	116	1			T90	5		T92	10		T94	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3862352

1

T1

17051

T2

6

T3

1

auto[1]

3040602

1

T1

15415

T2

892

T3

5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2891608	1			T1	15139		T4	11412		T5	46
auto[TlIntgErrNone]	partial	auto[1]	315191	1			T1	2244		T2	2		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	970579	1			T1	1912		T2	6		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	2725216	1			T1	13171		T2	890		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T90	1		T92	2		T94	4
auto[TlIntgErrCmd]	partial	auto[1]	74	1			T90	3		T92	9		T94	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T275	1		T278	1		T103	2
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T94	1		T276	1		T278	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T92	5		T94	5		T109	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T92	2		T94	2		T109	3
auto[TlIntgErrData]	full_word	auto[0]	10	1			T92	2		T94	1		T279	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T90	1		T275	1		T276	2
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T90	2		T92	3		T94	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T90	1		T92	5		T94	4
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T90	2		T94	1		T109	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T92	2		T275	1		T280	1