Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	481009664	2625797	0	0
gen_wmask[1].MaskCheckPortA_A	481009664	2625797	0	0
gen_wmask[2].MaskCheckPortA_A	481009664	2625797	0	0
gen_wmask[3].MaskCheckPortA_A	481009664	2625797	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481009664	2625797	0	0
T1	739254	10853	0	0
T2	137768	832	0	0
T3	1361	0	0	0
T4	1061764	5524	0	0
T5	10419	832	0	0
T6	20954	73	0	0
T7	416171	7183	0	0
T8	1345	0	0	0
T9	44259	0	0	0
T10	11455	832	0	0
T11	13989	832	0	0
T12	26850	832	0	0
T14	0	1344	0	0
T16	0	6715	0	0
T20	0	2910	0	0
T25	0	1040	0	0
T26	0	46	0	0
T27	0	6004	0	0
T39	0	2	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481009664	2625797	0	0
T1	739254	10853	0	0
T2	137768	832	0	0
T3	1361	0	0	0
T4	1061764	5524	0	0
T5	10419	832	0	0
T6	20954	73	0	0
T7	416171	7183	0	0
T8	1345	0	0	0
T9	44259	0	0	0
T10	11455	832	0	0
T11	13989	832	0	0
T12	26850	832	0	0
T14	0	1344	0	0
T16	0	6715	0	0
T20	0	2910	0	0
T25	0	1040	0	0
T26	0	46	0	0
T27	0	6004	0	0
T39	0	2	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481009664	2625797	0	0
T1	739254	10853	0	0
T2	137768	832	0	0
T3	1361	0	0	0
T4	1061764	5524	0	0
T5	10419	832	0	0
T6	20954	73	0	0
T7	416171	7183	0	0
T8	1345	0	0	0
T9	44259	0	0	0
T10	11455	832	0	0
T11	13989	832	0	0
T12	26850	832	0	0
T14	0	1344	0	0
T16	0	6715	0	0
T20	0	2910	0	0
T25	0	1040	0	0
T26	0	46	0	0
T27	0	6004	0	0
T39	0	2	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481009664	2625797	0	0
T1	739254	10853	0	0
T2	137768	832	0	0
T3	1361	0	0	0
T4	1061764	5524	0	0
T5	10419	832	0	0
T6	20954	73	0	0
T7	416171	7183	0	0
T8	1345	0	0	0
T9	44259	0	0	0
T10	11455	832	0	0
T11	13989	832	0	0
T12	26850	832	0	0
T14	0	1344	0	0
T16	0	6715	0	0
T20	0	2910	0	0
T25	0	1040	0	0
T26	0	46	0	0
T27	0	6004	0	0
T39	0	2	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	355171785	1772462	0	0
gen_wmask[1].MaskCheckPortA_A	355171785	1772462	0	0
gen_wmask[2].MaskCheckPortA_A	355171785	1772462	0	0
gen_wmask[3].MaskCheckPortA_A	355171785	1772462	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	1772462	0	0
T1	126620	6932	0	0
T2	31398	832	0	0
T3	1361	0	0	0
T4	932156	1934	0	0
T5	10065	832	0	0
T6	18450	57	0	0
T7	174272	6656	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T14	0	1344	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	1772462	0	0
T1	126620	6932	0	0
T2	31398	832	0	0
T3	1361	0	0	0
T4	932156	1934	0	0
T5	10065	832	0	0
T6	18450	57	0	0
T7	174272	6656	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T14	0	1344	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	1772462	0	0
T1	126620	6932	0	0
T2	31398	832	0	0
T3	1361	0	0	0
T4	932156	1934	0	0
T5	10065	832	0	0
T6	18450	57	0	0
T7	174272	6656	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T14	0	1344	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	1772462	0	0
T1	126620	6932	0	0
T2	31398	832	0	0
T3	1361	0	0	0
T4	932156	1934	0	0
T5	10065	832	0	0
T6	18450	57	0	0
T7	174272	6656	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T14	0	1344	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T6
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	125837879	853335	0	0
gen_wmask[1].MaskCheckPortA_A	125837879	853335	0	0
gen_wmask[2].MaskCheckPortA_A	125837879	853335	0	0
gen_wmask[3].MaskCheckPortA_A	125837879	853335	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	853335	0	0
T1	612634	3921	0	0
T2	106370	0	0	0
T4	129608	3590	0	0
T5	354	0	0	0
T6	2504	16	0	0
T7	241899	527	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	6715	0	0
T20	0	2910	0	0
T25	0	1040	0	0
T26	0	46	0	0
T27	0	6004	0	0
T39	0	2	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	853335	0	0
T1	612634	3921	0	0
T2	106370	0	0	0
T4	129608	3590	0	0
T5	354	0	0	0
T6	2504	16	0	0
T7	241899	527	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	6715	0	0
T20	0	2910	0	0
T25	0	1040	0	0
T26	0	46	0	0
T27	0	6004	0	0
T39	0	2	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	853335	0	0
T1	612634	3921	0	0
T2	106370	0	0	0
T4	129608	3590	0	0
T5	354	0	0	0
T6	2504	16	0	0
T7	241899	527	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	6715	0	0
T20	0	2910	0	0
T25	0	1040	0	0
T26	0	46	0	0
T27	0	6004	0	0
T39	0	2	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	853335	0	0
T1	612634	3921	0	0
T2	106370	0	0	0
T4	129608	3590	0	0
T5	354	0	0	0
T6	2504	16	0	0
T7	241899	527	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	6715	0	0
T20	0	2910	0	0
T25	0	1040	0	0
T26	0	46	0	0
T27	0	6004	0	0
T39	0	2	0	0