Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.62	93.89	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.62	93.89	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T7,T14
1	0	Covered	T1,T7,T14
1	1	Covered	T1,T7,T14

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T14
1	0	Covered	T1,T7,T14
1	1	Covered	T1,T7,T14

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1065515355	2070	0	0
SrcPulseCheck_M	377513637	2070	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1065515355	2070	0	0
T1	126620	5	0	0
T2	31398	0	0	0
T3	1361	0	0	0
T4	932156	0	0	0
T5	10065	0	0	0
T6	18450	0	0	0
T7	174272	8	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	0	0	0
T14	446114	4	0	0
T15	1165148	0	0	0
T16	1221632	23	0	0
T17	2128	0	0	0
T18	7112	0	0	0
T25	571310	8	0	0
T27	0	13	0	0
T28	0	9	0	0
T30	0	17	0	0
T37	157924	7	0	0
T38	0	7	0	0
T39	0	1	0	0
T42	0	2	0	0
T55	0	8	0	0
T56	1932	0	0	0
T63	12144	0	0	0
T68	248914	0	0	0
T136	0	7	0	0
T137	0	7	0	0
T138	0	7	0	0
T139	0	7	0	0
T140	0	7	0	0
T141	0	7	0	0
T142	0	7	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	377513637	2070	0	0
T1	612634	5	0	0
T2	106370	0	0	0
T4	129608	0	0	0
T5	354	0	0	0
T6	2504	0	0	0
T7	241899	8	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T14	55024	4	0	0
T15	143124	0	0	0
T16	296842	23	0	0
T18	2016	0	0	0
T25	707702	8	0	0
T27	0	13	0	0
T28	0	9	0	0
T29	154784	0	0	0
T30	0	17	0	0
T37	50272	7	0	0
T38	0	7	0	0
T39	0	1	0	0
T42	0	2	0	0
T55	0	8	0	0
T63	8556	0	0	0
T68	354820	0	0	0
T136	0	7	0	0
T137	0	7	0	0
T138	0	7	0	0
T139	0	7	0	0
T140	0	7	0	0
T141	0	7	0	0
T142	0	7	0	0
T143	1818	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T14,T37,T38
1	0	Covered	T14,T37,T38
1	1	Covered	T14,T37,T38

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T37,T38
1	0	Covered	T14,T37,T38
1	1	Covered	T14,T37,T38

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	355171785	152	0	0
SrcPulseCheck_M	125837879	152	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	152	0	0
T14	223057	2	0	0
T15	582574	0	0	0
T16	610816	0	0	0
T17	1064	0	0	0
T18	3556	0	0	0
T25	285655	0	0	0
T37	78962	2	0	0
T38	0	2	0	0
T56	966	0	0	0
T63	6072	0	0	0
T68	124457	0	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	2	0	0
T140	0	2	0	0
T141	0	2	0	0
T142	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	152	0	0
T14	27512	2	0	0
T15	71562	0	0	0
T16	148421	0	0	0
T18	1008	0	0	0
T25	353851	0	0	0
T29	77392	0	0	0
T37	25136	2	0	0
T38	0	2	0	0
T63	4278	0	0	0
T68	177410	0	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	2	0	0
T140	0	2	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	909	0	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T14,T37,T38
1	0	Covered	T14,T37,T38
1	1	Covered	T14,T37,T38

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T37,T38
1	0	Covered	T14,T37,T38
1	1	Covered	T14,T37,T38

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	355171785	295	0	0
SrcPulseCheck_M	125837879	295	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	295	0	0
T14	223057	2	0	0
T15	582574	0	0	0
T16	610816	0	0	0
T17	1064	0	0	0
T18	3556	0	0	0
T25	285655	0	0	0
T37	78962	5	0	0
T38	0	5	0	0
T56	966	0	0	0
T63	6072	0	0	0
T68	124457	0	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	5	0	0
T139	0	5	0	0
T140	0	5	0	0
T141	0	5	0	0
T142	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	295	0	0
T14	27512	2	0	0
T15	71562	0	0	0
T16	148421	0	0	0
T18	1008	0	0	0
T25	353851	0	0	0
T29	77392	0	0	0
T37	25136	5	0	0
T38	0	5	0	0
T63	4278	0	0	0
T68	177410	0	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	5	0	0
T139	0	5	0	0
T140	0	5	0	0
T141	0	5	0	0
T142	0	5	0	0
T143	909	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T7,T16
1	0	Covered	T1,T7,T16
1	1	Covered	T1,T7,T16

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T16
1	0	Covered	T1,T7,T16
1	1	Covered	T1,T7,T16

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	355171785	1623	0	0
SrcPulseCheck_M	125837879	1623	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	1623	0	0
T1	126620	5	0	0
T2	31398	0	0	0
T3	1361	0	0	0
T4	932156	0	0	0
T5	10065	0	0	0
T6	18450	0	0	0
T7	174272	8	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	0	0	0
T16	0	23	0	0
T25	0	8	0	0
T27	0	13	0	0
T28	0	9	0	0
T30	0	17	0	0
T39	0	1	0	0
T42	0	2	0	0
T55	0	8	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	1623	0	0
T1	612634	5	0	0
T2	106370	0	0	0
T4	129608	0	0	0
T5	354	0	0	0
T6	2504	0	0	0
T7	241899	8	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	23	0	0
T25	0	8	0	0
T27	0	13	0	0
T28	0	9	0	0
T30	0	17	0	0
T39	0	1	0	0
T42	0	2	0	0
T55	0	8	0	0