Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	357383041	2401557	0	0
DepthKnown_A	357383041	357260474	0	0
RvalidKnown_A	357383041	357260474	0	0
WreadyKnown_A	357383041	357260474	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2401557	0	0
T1	126620	7486	0	0
T2	31398	832	0	0
T3	1361	0	0	0
T4	932156	0	0	0
T5	10065	832	0	0
T6	18450	0	0	0
T7	174272	9996	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	1663	0	0
T11	0	1666	0	0
T12	0	1667	0	0
T14	0	1854	0	0
T15	0	832	0	0
T16	0	30773	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	357383041	2675896	0	0
DepthKnown_A	357383041	357260474	0	0
RvalidKnown_A	357383041	357260474	0	0
WreadyKnown_A	357383041	357260474	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2675896	0	0
T1	126620	5824	0	0
T2	31398	832	0	0
T3	1361	0	0	0
T4	932156	0	0	0
T5	10065	2576	0	0
T6	18450	0	0	0
T7	174272	18340	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	832	0	0
T11	0	835	0	0
T12	0	836	0	0
T14	0	1344	0	0
T15	0	3609	0	0
T16	0	21632	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	357383041	152736	0	0
DepthKnown_A	357383041	357260474	0	0
RvalidKnown_A	357383041	357260474	0	0
WreadyKnown_A	357383041	357260474	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	152736	0	0
T1	126620	945	0	0
T2	31398	0	0	0
T3	1361	0	0	0
T4	932156	932	0	0
T5	10065	0	0	0
T6	18450	4	0	0
T7	174272	64	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	0	0	0
T16	0	1127	0	0
T20	0	756	0	0
T25	0	257	0	0
T26	0	12	0	0
T27	0	692	0	0
T28	0	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	357383041	351990	0	0
DepthKnown_A	357383041	357260474	0	0
RvalidKnown_A	357383041	357260474	0	0
WreadyKnown_A	357383041	357260474	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	351990	0	0
T1	126620	945	0	0
T2	31398	0	0	0
T3	1361	0	0	0
T4	932156	932	0	0
T5	10065	0	0	0
T6	18450	4	0	0
T7	174272	257	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	0	0	0
T16	0	1127	0	0
T20	0	3466	0	0
T25	0	257	0	0
T26	0	12	0	0
T27	0	692	0	0
T28	0	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	357383041	5523755	0	0
DepthKnown_A	357383041	357260474	0	0
RvalidKnown_A	357383041	357260474	0	0
WreadyKnown_A	357383041	357260474	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	5523755	0	0
T1	126620	25826	0	0
T2	31398	66	0	0
T3	1361	6	0	0
T4	932156	16399	0	0
T5	10065	128	0	0
T6	18450	625	0	0
T7	174272	2973	0	0
T8	1345	75	0	0
T9	20692	128	0	0
T10	7343	265	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	357383041	12149261	0	0
DepthKnown_A	357383041	357260474	0	0
RvalidKnown_A	357383041	357260474	0	0
WreadyKnown_A	357383041	357260474	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	12149261	0	0
T1	126620	25697	0	0
T2	31398	66	0	0
T3	1361	6	0	0
T4	932156	16304	0	0
T5	10065	337	0	0
T6	18450	625	0	0
T7	174272	13115	0	0
T8	1345	75	0	0
T9	20692	128	0	0
T10	7343	265	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	357260474	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0