Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T4,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Unreachable
1	1	Covered	T1,T4,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T16
1	0	Covered	T1,T7,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T1,T7,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	606847543	479666105	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	606847543	2981744	0	0
GntImpliesValid_A	606847543	2981744	0	0
GrantKnown_A	606847543	479666105	0	0
IdxKnown_A	606847543	479666105	0	0
IndexIsCorrect_A	606847543	2981744	0	0
LockArbDecision_A	606847543	0	0	0
NoReadyValidNoGrant_A	606847543	0	0	0
ReadyAndValidImplyGrant_A	606847543	2981744	0	0
ReqAndReadyImplyGrant_A	606847543	2981744	0	0
ReqImpliesValid_A	606847543	2981744	0	0
ReqStaysHighUntilGranted0_M	606847543	0	0	0
RoundRobin_A	606847543	3	0	906
ValidKnown_A	606847543	479666105	0	0
gen_data_port_assertion.DataFlow_A	606847543	2981744	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606847543	479666105	0	0
T1	1351888	730683	0	0
T2	244138	136716	0	0
T3	1361	1287	0	0
T4	1191372	1055969	0	0
T5	10773	10082	0	0
T6	23458	20887	0	0
T7	658070	415328	0	0
T8	1345	1291	0	0
T9	67826	42646	0	0
T10	15567	11369	0	0
T11	27978	13989	0	0
T12	53700	26850	0	0
T13	0	50240	0	0
T14	0	27512	0	0
T15	0	71562	0	0
T16	0	292013	0	0
T18	0	1008	0	0
T20	0	120960	0	0
T26	0	7104	0	0
T27	0	78000	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606847543	2981744	0	0
T1	1351888	13012	0	0
T2	244138	832	0	0
T3	1361	0	0	0
T4	1191372	8592	0	0
T5	10773	832	0	0
T6	23458	138	0	0
T7	658070	7262	0	0
T8	1345	0	0	0
T9	67826	0	0	0
T10	15567	832	0	0
T11	27978	832	0	0
T12	53700	832	0	0
T14	0	1344	0	0
T16	0	8535	0	0
T20	0	4523	0	0
T21	0	850	0	0
T25	0	1040	0	0
T26	0	105	0	0
T27	0	7230	0	0
T28	0	2184	0	0
T39	0	2	0	0
T40	0	1921	0	0
T41	0	1377	0	0
T42	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606847543	2981744	0	0
T1	1351888	13012	0	0
T2	244138	832	0	0
T3	1361	0	0	0
T4	1191372	8592	0	0
T5	10773	832	0	0
T6	23458	138	0	0
T7	658070	7262	0	0
T8	1345	0	0	0
T9	67826	0	0	0
T10	15567	832	0	0
T11	27978	832	0	0
T12	53700	832	0	0
T14	0	1344	0	0
T16	0	8535	0	0
T20	0	4523	0	0
T21	0	850	0	0
T25	0	1040	0	0
T26	0	105	0	0
T27	0	7230	0	0
T28	0	2184	0	0
T39	0	2	0	0
T40	0	1921	0	0
T41	0	1377	0	0
T42	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606847543	479666105	0	0
T1	1351888	730683	0	0
T2	244138	136716	0	0
T3	1361	1287	0	0
T4	1191372	1055969	0	0
T5	10773	10082	0	0
T6	23458	20887	0	0
T7	658070	415328	0	0
T8	1345	1291	0	0
T9	67826	42646	0	0
T10	15567	11369	0	0
T11	27978	13989	0	0
T12	53700	26850	0	0
T13	0	50240	0	0
T14	0	27512	0	0
T15	0	71562	0	0
T16	0	292013	0	0
T18	0	1008	0	0
T20	0	120960	0	0
T26	0	7104	0	0
T27	0	78000	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606847543	479666105	0	0
T1	1351888	730683	0	0
T2	244138	136716	0	0
T3	1361	1287	0	0
T4	1191372	1055969	0	0
T5	10773	10082	0	0
T6	23458	20887	0	0
T7	658070	415328	0	0
T8	1345	1291	0	0
T9	67826	42646	0	0
T10	15567	11369	0	0
T11	27978	13989	0	0
T12	53700	26850	0	0
T13	0	50240	0	0
T14	0	27512	0	0
T15	0	71562	0	0
T16	0	292013	0	0
T18	0	1008	0	0
T20	0	120960	0	0
T26	0	7104	0	0
T27	0	78000	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606847543	2981744	0	0
T1	1351888	13012	0	0
T2	244138	832	0	0
T3	1361	0	0	0
T4	1191372	8592	0	0
T5	10773	832	0	0
T6	23458	138	0	0
T7	658070	7262	0	0
T8	1345	0	0	0
T9	67826	0	0	0
T10	15567	832	0	0
T11	27978	832	0	0
T12	53700	832	0	0
T14	0	1344	0	0
T16	0	8535	0	0
T20	0	4523	0	0
T21	0	850	0	0
T25	0	1040	0	0
T26	0	105	0	0
T27	0	7230	0	0
T28	0	2184	0	0
T39	0	2	0	0
T40	0	1921	0	0
T41	0	1377	0	0
T42	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606847543	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606847543	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606847543	2981744	0	0
T1	1351888	13012	0	0
T2	244138	832	0	0
T3	1361	0	0	0
T4	1191372	8592	0	0
T5	10773	832	0	0
T6	23458	138	0	0
T7	658070	7262	0	0
T8	1345	0	0	0
T9	67826	0	0	0
T10	15567	832	0	0
T11	27978	832	0	0
T12	53700	832	0	0
T14	0	1344	0	0
T16	0	8535	0	0
T20	0	4523	0	0
T21	0	850	0	0
T25	0	1040	0	0
T26	0	105	0	0
T27	0	7230	0	0
T28	0	2184	0	0
T39	0	2	0	0
T40	0	1921	0	0
T41	0	1377	0	0
T42	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606847543	2981744	0	0
T1	1351888	13012	0	0
T2	244138	832	0	0
T3	1361	0	0	0
T4	1191372	8592	0	0
T5	10773	832	0	0
T6	23458	138	0	0
T7	658070	7262	0	0
T8	1345	0	0	0
T9	67826	0	0	0
T10	15567	832	0	0
T11	27978	832	0	0
T12	53700	832	0	0
T14	0	1344	0	0
T16	0	8535	0	0
T20	0	4523	0	0
T21	0	850	0	0
T25	0	1040	0	0
T26	0	105	0	0
T27	0	7230	0	0
T28	0	2184	0	0
T39	0	2	0	0
T40	0	1921	0	0
T41	0	1377	0	0
T42	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606847543	2981744	0	0
T1	1351888	13012	0	0
T2	244138	832	0	0
T3	1361	0	0	0
T4	1191372	8592	0	0
T5	10773	832	0	0
T6	23458	138	0	0
T7	658070	7262	0	0
T8	1345	0	0	0
T9	67826	0	0	0
T10	15567	832	0	0
T11	27978	832	0	0
T12	53700	832	0	0
T14	0	1344	0	0
T16	0	8535	0	0
T20	0	4523	0	0
T21	0	850	0	0
T25	0	1040	0	0
T26	0	105	0	0
T27	0	7230	0	0
T28	0	2184	0	0
T39	0	2	0	0
T40	0	1921	0	0
T41	0	1377	0	0
T42	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	606847543	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606847543	3	0	906
T43	356226	1	0	1
T44	0	1	0	0
T45	0	1	0	0
T46	164940	0	0	1
T47	231808	0	0	1
T48	8858	0	0	1
T49	3582	0	0	1
T50	166839	0	0	1
T51	1396	0	0	1
T52	9952	0	0	1
T53	912	0	0	1
T54	1288	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606847543	479666105	0	0
T1	1351888	730683	0	0
T2	244138	136716	0	0
T3	1361	1287	0	0
T4	1191372	1055969	0	0
T5	10773	10082	0	0
T6	23458	20887	0	0
T7	658070	415328	0	0
T8	1345	1291	0	0
T9	67826	42646	0	0
T10	15567	11369	0	0
T11	27978	13989	0	0
T12	53700	26850	0	0
T13	0	50240	0	0
T14	0	27512	0	0
T15	0	71562	0	0
T16	0	292013	0	0
T18	0	1008	0	0
T20	0	120960	0	0
T26	0	7104	0	0
T27	0	78000	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	606847543	2981744	0	0
T1	1351888	13012	0	0
T2	244138	832	0	0
T3	1361	0	0	0
T4	1191372	8592	0	0
T5	10773	832	0	0
T6	23458	138	0	0
T7	658070	7262	0	0
T8	1345	0	0	0
T9	67826	0	0	0
T10	15567	832	0	0
T11	27978	832	0	0
T12	53700	832	0	0
T14	0	1344	0	0
T16	0	8535	0	0
T20	0	4523	0	0
T21	0	850	0	0
T25	0	1040	0	0
T26	0	105	0	0
T27	0	7230	0	0
T28	0	2184	0	0
T39	0	2	0	0
T40	0	1921	0	0
T41	0	1377	0	0
T42	0	4	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T4,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Unreachable
1	1	Covered	T1,T4,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	125837879	28734159	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	125837879	641188	0	0
GntImpliesValid_A	125837879	641188	0	0
GrantKnown_A	125837879	28734159	0	0
IdxKnown_A	125837879	28734159	0	0
IndexIsCorrect_A	125837879	641188	0	0
LockArbDecision_A	125837879	0	0	0
NoReadyValidNoGrant_A	125837879	0	0	0
ReadyAndValidImplyGrant_A	125837879	641188	0	0
ReqAndReadyImplyGrant_A	125837879	641188	0	0
ReqImpliesValid_A	125837879	641188	0	0
ReqStaysHighUntilGranted0_M	125837879	0	0	0
RoundRobin_A	125837879	0	0	0
ValidKnown_A	125837879	28734159	0	0
gen_data_port_assertion.DataFlow_A	125837879	641188	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	28734159	0	0
T1	612634	128472	0	0
T2	106370	0	0	0
T4	129608	123880	0	0
T5	354	0	0	0
T6	2504	2504	0	0
T7	241899	0	0	0
T9	23567	22048	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T13	0	50240	0	0
T16	0	161400	0	0
T18	0	1008	0	0
T20	0	120960	0	0
T26	0	7104	0	0
T27	0	78000	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	641188	0	0
T1	612634	4474	0	0
T2	106370	0	0	0
T4	129608	5726	0	0
T5	354	0	0	0
T6	2504	77	0	0
T7	241899	0	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	5052	0	0
T20	0	4523	0	0
T21	0	850	0	0
T26	0	105	0	0
T27	0	3420	0	0
T40	0	1921	0	0
T41	0	1377	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	641188	0	0
T1	612634	4474	0	0
T2	106370	0	0	0
T4	129608	5726	0	0
T5	354	0	0	0
T6	2504	77	0	0
T7	241899	0	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	5052	0	0
T20	0	4523	0	0
T21	0	850	0	0
T26	0	105	0	0
T27	0	3420	0	0
T40	0	1921	0	0
T41	0	1377	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	28734159	0	0
T1	612634	128472	0	0
T2	106370	0	0	0
T4	129608	123880	0	0
T5	354	0	0	0
T6	2504	2504	0	0
T7	241899	0	0	0
T9	23567	22048	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T13	0	50240	0	0
T16	0	161400	0	0
T18	0	1008	0	0
T20	0	120960	0	0
T26	0	7104	0	0
T27	0	78000	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	28734159	0	0
T1	612634	128472	0	0
T2	106370	0	0	0
T4	129608	123880	0	0
T5	354	0	0	0
T6	2504	2504	0	0
T7	241899	0	0	0
T9	23567	22048	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T13	0	50240	0	0
T16	0	161400	0	0
T18	0	1008	0	0
T20	0	120960	0	0
T26	0	7104	0	0
T27	0	78000	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	641188	0	0
T1	612634	4474	0	0
T2	106370	0	0	0
T4	129608	5726	0	0
T5	354	0	0	0
T6	2504	77	0	0
T7	241899	0	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	5052	0	0
T20	0	4523	0	0
T21	0	850	0	0
T26	0	105	0	0
T27	0	3420	0	0
T40	0	1921	0	0
T41	0	1377	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	641188	0	0
T1	612634	4474	0	0
T2	106370	0	0	0
T4	129608	5726	0	0
T5	354	0	0	0
T6	2504	77	0	0
T7	241899	0	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	5052	0	0
T20	0	4523	0	0
T21	0	850	0	0
T26	0	105	0	0
T27	0	3420	0	0
T40	0	1921	0	0
T41	0	1377	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	641188	0	0
T1	612634	4474	0	0
T2	106370	0	0	0
T4	129608	5726	0	0
T5	354	0	0	0
T6	2504	77	0	0
T7	241899	0	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	5052	0	0
T20	0	4523	0	0
T21	0	850	0	0
T26	0	105	0	0
T27	0	3420	0	0
T40	0	1921	0	0
T41	0	1377	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	641188	0	0
T1	612634	4474	0	0
T2	106370	0	0	0
T4	129608	5726	0	0
T5	354	0	0	0
T6	2504	77	0	0
T7	241899	0	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	5052	0	0
T20	0	4523	0	0
T21	0	850	0	0
T26	0	105	0	0
T27	0	3420	0	0
T40	0	1921	0	0
T41	0	1377	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	28734159	0	0
T1	612634	128472	0	0
T2	106370	0	0	0
T4	129608	123880	0	0
T5	354	0	0	0
T6	2504	2504	0	0
T7	241899	0	0	0
T9	23567	22048	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T13	0	50240	0	0
T16	0	161400	0	0
T18	0	1008	0	0
T20	0	120960	0	0
T26	0	7104	0	0
T27	0	78000	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	641188	0	0
T1	612634	4474	0	0
T2	106370	0	0	0
T4	129608	5726	0	0
T5	354	0	0	0
T6	2504	77	0	0
T7	241899	0	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	5052	0	0
T20	0	4523	0	0
T21	0	850	0	0
T26	0	105	0	0
T27	0	3420	0	0
T40	0	1921	0	0
T41	0	1377	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T16
1	0	Covered	T1,T7,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T1,T7,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T7,T16
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	125837879	95840515	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	125837879	421263	0	0
GntImpliesValid_A	125837879	421263	0	0
GrantKnown_A	125837879	95840515	0	0
IdxKnown_A	125837879	95840515	0	0
IndexIsCorrect_A	125837879	421263	0	0
LockArbDecision_A	125837879	0	0	0
NoReadyValidNoGrant_A	125837879	0	0	0
ReadyAndValidImplyGrant_A	125837879	421263	0	0
ReqAndReadyImplyGrant_A	125837879	421263	0	0
ReqImpliesValid_A	125837879	421263	0	0
ReqStaysHighUntilGranted0_M	125837879	0	0	0
RoundRobin_A	125837879	0	0	0
ValidKnown_A	125837879	95840515	0	0
gen_data_port_assertion.DataFlow_A	125837879	421263	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	95840515	0	0
T1	612634	475618	0	0
T2	106370	105376	0	0
T4	129608	0	0	0
T5	354	80	0	0
T6	2504	0	0	0
T7	241899	241065	0	0
T9	23567	0	0	0
T10	4112	4112	0	0
T11	13989	13989	0	0
T12	26850	26850	0	0
T14	0	27512	0	0
T15	0	71562	0	0
T16	0	130613	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	421263	0	0
T1	612634	653	0	0
T2	106370	0	0	0
T4	129608	0	0	0
T5	354	0	0	0
T6	2504	0	0	0
T7	241899	527	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	3483	0	0
T25	0	1040	0	0
T27	0	3810	0	0
T28	0	2184	0	0
T30	0	10856	0	0
T39	0	2	0	0
T42	0	4	0	0
T55	0	3078	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	421263	0	0
T1	612634	653	0	0
T2	106370	0	0	0
T4	129608	0	0	0
T5	354	0	0	0
T6	2504	0	0	0
T7	241899	527	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	3483	0	0
T25	0	1040	0	0
T27	0	3810	0	0
T28	0	2184	0	0
T30	0	10856	0	0
T39	0	2	0	0
T42	0	4	0	0
T55	0	3078	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	95840515	0	0
T1	612634	475618	0	0
T2	106370	105376	0	0
T4	129608	0	0	0
T5	354	80	0	0
T6	2504	0	0	0
T7	241899	241065	0	0
T9	23567	0	0	0
T10	4112	4112	0	0
T11	13989	13989	0	0
T12	26850	26850	0	0
T14	0	27512	0	0
T15	0	71562	0	0
T16	0	130613	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	95840515	0	0
T1	612634	475618	0	0
T2	106370	105376	0	0
T4	129608	0	0	0
T5	354	80	0	0
T6	2504	0	0	0
T7	241899	241065	0	0
T9	23567	0	0	0
T10	4112	4112	0	0
T11	13989	13989	0	0
T12	26850	26850	0	0
T14	0	27512	0	0
T15	0	71562	0	0
T16	0	130613	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	421263	0	0
T1	612634	653	0	0
T2	106370	0	0	0
T4	129608	0	0	0
T5	354	0	0	0
T6	2504	0	0	0
T7	241899	527	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	3483	0	0
T25	0	1040	0	0
T27	0	3810	0	0
T28	0	2184	0	0
T30	0	10856	0	0
T39	0	2	0	0
T42	0	4	0	0
T55	0	3078	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	421263	0	0
T1	612634	653	0	0
T2	106370	0	0	0
T4	129608	0	0	0
T5	354	0	0	0
T6	2504	0	0	0
T7	241899	527	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	3483	0	0
T25	0	1040	0	0
T27	0	3810	0	0
T28	0	2184	0	0
T30	0	10856	0	0
T39	0	2	0	0
T42	0	4	0	0
T55	0	3078	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	421263	0	0
T1	612634	653	0	0
T2	106370	0	0	0
T4	129608	0	0	0
T5	354	0	0	0
T6	2504	0	0	0
T7	241899	527	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	3483	0	0
T25	0	1040	0	0
T27	0	3810	0	0
T28	0	2184	0	0
T30	0	10856	0	0
T39	0	2	0	0
T42	0	4	0	0
T55	0	3078	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	421263	0	0
T1	612634	653	0	0
T2	106370	0	0	0
T4	129608	0	0	0
T5	354	0	0	0
T6	2504	0	0	0
T7	241899	527	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	3483	0	0
T25	0	1040	0	0
T27	0	3810	0	0
T28	0	2184	0	0
T30	0	10856	0	0
T39	0	2	0	0
T42	0	4	0	0
T55	0	3078	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	95840515	0	0
T1	612634	475618	0	0
T2	106370	105376	0	0
T4	129608	0	0	0
T5	354	80	0	0
T6	2504	0	0	0
T7	241899	241065	0	0
T9	23567	0	0	0
T10	4112	4112	0	0
T11	13989	13989	0	0
T12	26850	26850	0	0
T14	0	27512	0	0
T15	0	71562	0	0
T16	0	130613	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125837879	421263	0	0
T1	612634	653	0	0
T2	106370	0	0	0
T4	129608	0	0	0
T5	354	0	0	0
T6	2504	0	0	0
T7	241899	527	0	0
T9	23567	0	0	0
T10	4112	0	0	0
T11	13989	0	0	0
T12	26850	0	0	0
T16	0	3483	0	0
T25	0	1040	0	0
T27	0	3810	0	0
T28	0	2184	0	0
T30	0	10856	0	0
T39	0	2	0	0
T42	0	4	0	0
T55	0	3078	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	355171785	355091431	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	355171785	1919293	0	0
GntImpliesValid_A	355171785	1919293	0	0
GrantKnown_A	355171785	355091431	0	0
IdxKnown_A	355171785	355091431	0	0
IndexIsCorrect_A	355171785	1919293	0	0
LockArbDecision_A	355171785	0	0	0
NoReadyValidNoGrant_A	355171785	0	0	0
ReadyAndValidImplyGrant_A	355171785	1919293	0	0
ReqAndReadyImplyGrant_A	355171785	1919293	0	0
ReqImpliesValid_A	355171785	1919293	0	0
ReqStaysHighUntilGranted0_M	355171785	0	0	0
RoundRobin_A	355171785	3	0	906
ValidKnown_A	355171785	355091431	0	0
gen_data_port_assertion.DataFlow_A	355171785	1919293	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	355091431	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	1919293	0	0
T1	126620	7885	0	0
T2	31398	832	0	0
T3	1361	0	0	0
T4	932156	2866	0	0
T5	10065	832	0	0
T6	18450	61	0	0
T7	174272	6735	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T14	0	1344	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	1919293	0	0
T1	126620	7885	0	0
T2	31398	832	0	0
T3	1361	0	0	0
T4	932156	2866	0	0
T5	10065	832	0	0
T6	18450	61	0	0
T7	174272	6735	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T14	0	1344	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	355091431	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	355091431	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	1919293	0	0
T1	126620	7885	0	0
T2	31398	832	0	0
T3	1361	0	0	0
T4	932156	2866	0	0
T5	10065	832	0	0
T6	18450	61	0	0
T7	174272	6735	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T14	0	1344	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	1919293	0	0
T1	126620	7885	0	0
T2	31398	832	0	0
T3	1361	0	0	0
T4	932156	2866	0	0
T5	10065	832	0	0
T6	18450	61	0	0
T7	174272	6735	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T14	0	1344	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	1919293	0	0
T1	126620	7885	0	0
T2	31398	832	0	0
T3	1361	0	0	0
T4	932156	2866	0	0
T5	10065	832	0	0
T6	18450	61	0	0
T7	174272	6735	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T14	0	1344	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	1919293	0	0
T1	126620	7885	0	0
T2	31398	832	0	0
T3	1361	0	0	0
T4	932156	2866	0	0
T5	10065	832	0	0
T6	18450	61	0	0
T7	174272	6735	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T14	0	1344	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	3	0	906
T43	356226	1	0	1
T44	0	1	0	0
T45	0	1	0	0
T46	164940	0	0	1
T47	231808	0	0	1
T48	8858	0	0	1
T49	3582	0	0	1
T50	166839	0	0	1
T51	1396	0	0	1
T52	9952	0	0	1
T53	912	0	0	1
T54	1288	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	355091431	0	0
T1	126620	126593	0	0
T2	31398	31340	0	0
T3	1361	1287	0	0
T4	932156	932089	0	0
T5	10065	10002	0	0
T6	18450	18383	0	0
T7	174272	174263	0	0
T8	1345	1291	0	0
T9	20692	20598	0	0
T10	7343	7257	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	355171785	1919293	0	0
T1	126620	7885	0	0
T2	31398	832	0	0
T3	1361	0	0	0
T4	932156	2866	0	0
T5	10065	832	0	0
T6	18450	61	0	0
T7	174272	6735	0	0
T8	1345	0	0	0
T9	20692	0	0	0
T10	7343	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T14	0	1344	0	0