Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.62	93.89	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	357383041	2998	0	0
addr_swap_data_rd_A	357383041	2177	0	0
addr_swap_mask_rd_A	357383041	2189	0	0
cfg_rd_A	357383041	2522	0	0
cmd_filter_0_rd_A	357383041	5641	0	0
cmd_filter_1_rd_A	357383041	5728	0	0
cmd_filter_2_rd_A	357383041	5969	0	0
cmd_filter_3_rd_A	357383041	5756	0	0
cmd_filter_4_rd_A	357383041	5170	0	0
cmd_filter_5_rd_A	357383041	5682	0	0
cmd_filter_6_rd_A	357383041	5531	0	0
cmd_filter_7_rd_A	357383041	4561	0	0
cmd_info_0_rd_A	357383041	3640	0	0
cmd_info_10_rd_A	357383041	3513	0	0
cmd_info_11_rd_A	357383041	3589	0	0
cmd_info_12_rd_A	357383041	3980	0	0
cmd_info_13_rd_A	357383041	3723	0	0
cmd_info_14_rd_A	357383041	3567	0	0
cmd_info_15_rd_A	357383041	3528	0	0
cmd_info_16_rd_A	357383041	3679	0	0
cmd_info_17_rd_A	357383041	3796	0	0
cmd_info_18_rd_A	357383041	3806	0	0
cmd_info_19_rd_A	357383041	3626	0	0
cmd_info_1_rd_A	357383041	3482	0	0
cmd_info_20_rd_A	357383041	3632	0	0
cmd_info_21_rd_A	357383041	3593	0	0
cmd_info_22_rd_A	357383041	3725	0	0
cmd_info_23_rd_A	357383041	3632	0	0
cmd_info_2_rd_A	357383041	3014	0	0
cmd_info_3_rd_A	357383041	3525	0	0
cmd_info_4_rd_A	357383041	3184	0	0
cmd_info_5_rd_A	357383041	3687	0	0
cmd_info_6_rd_A	357383041	3633	0	0
cmd_info_7_rd_A	357383041	3697	0	0
cmd_info_8_rd_A	357383041	3790	0	0
cmd_info_9_rd_A	357383041	3648	0	0
cmd_info_en4b_rd_A	357383041	2333	0	0
cmd_info_ex4b_rd_A	357383041	2183	0	0
cmd_info_wrdi_rd_A	357383041	2278	0	0
cmd_info_wren_rd_A	357383041	2388	0	0
intercept_en_rd_A	357383041	2743	0	0
intr_enable_rd_A	357383041	3849	0	0
jedec_cc_rd_A	357383041	2387	0	0
jedec_id_rd_A	357383041	2262	0	0
mailbox_addr_rd_A	357383041	2317	0	0
payload_swap_data_rd_A	357383041	2283	0	0
payload_swap_mask_rd_A	357383041	2161	0	0
read_threshold_rd_A	357383041	2238	0	0
tpm_access_0_rd_A	357383041	2482	0	0
tpm_access_1_rd_A	357383041	2177	0	0
tpm_cfg_rd_A	357383041	2775	0	0
tpm_did_vid_rd_A	357383041	2329	0	0
tpm_int_enable_rd_A	357383041	2313	0	0
tpm_int_status_rd_A	357383041	2223	0	0
tpm_int_vector_rd_A	357383041	2132	0	0
tpm_intf_capability_rd_A	357383041	2363	0	0
tpm_rid_rd_A	357383041	2223	0	0
tpm_sts_rd_A	357383041	2243	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2998	0	0
T59	6233	335	0	0
T60	2425	6	0	0
T61	3978	12	0	0
T90	28527	2	0	0
T91	10003	129	0	0
T92	80739	3	0	0
T93	19803	278	0	0
T105	11173	4	0	0
T107	5292	1	0	0
T108	8142	5	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2177	0	0
T105	11173	23	0	0
T106	10611	22	0	0
T107	5292	7	0	0
T114	9529	2	0	0
T115	10492	8	0	0
T117	90098	200	0	0
T144	16447	17	0	0
T145	4611	3	0	0
T146	14328	60	0	0
T147	6019	3	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2189	0	0
T105	11173	19	0	0
T106	10611	16	0	0
T107	5292	4	0	0
T114	9529	9	0	0
T115	10492	13	0	0
T117	90098	235	0	0
T144	16447	25	0	0
T145	4611	6	0	0
T146	14328	31	0	0
T147	6019	4	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2522	0	0
T105	11173	24	0	0
T106	10611	23	0	0
T107	5292	17	0	0
T114	9529	2	0	0
T115	10492	13	0	0
T117	90098	248	0	0
T144	16447	69	0	0
T145	4611	1	0	0
T146	14328	29	0	0
T147	6019	10	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	5641	0	0
T105	11173	7	0	0
T106	10611	122	0	0
T107	5292	12	0	0
T114	9529	161	0	0
T115	10492	252	0	0
T117	90098	219	0	0
T144	16447	37	0	0
T145	4611	129	0	0
T146	14328	35	0	0
T147	6019	137	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	5728	0	0
T105	11173	277	0	0
T106	10611	250	0	0
T107	5292	5	0	0
T115	10492	126	0	0
T117	90098	213	0	0
T144	16447	13	0	0
T145	4611	122	0	0
T146	14328	53	0	0
T147	6019	10	0	0
T148	6022	105	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	5969	0	0
T105	11173	130	0	0
T106	10611	119	0	0
T107	5292	123	0	0
T114	9529	179	0	0
T115	10492	149	0	0
T117	90098	221	0	0
T144	16447	26	0	0
T145	4611	8	0	0
T146	14328	48	0	0
T147	6019	133	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	5756	0	0
T105	11173	19	0	0
T106	10611	248	0	0
T107	5292	117	0	0
T114	9529	42	0	0
T115	10492	149	0	0
T117	90098	214	0	0
T144	16447	28	0	0
T145	4611	125	0	0
T146	14328	81	0	0
T147	6019	13	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	5170	0	0
T105	11173	145	0	0
T106	10611	102	0	0
T107	5292	5	0	0
T114	9529	86	0	0
T115	10492	134	0	0
T117	90098	209	0	0
T144	16447	32	0	0
T145	4611	117	0	0
T146	14328	45	0	0
T147	6019	132	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	5682	0	0
T105	11173	148	0	0
T106	10611	137	0	0
T107	5292	11	0	0
T114	9529	24	0	0
T115	10492	310	0	0
T117	90098	223	0	0
T144	16447	38	0	0
T145	4611	114	0	0
T146	14328	46	0	0
T147	6019	3	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	5531	0	0
T105	11173	156	0	0
T106	10611	129	0	0
T107	5292	16	0	0
T114	9529	73	0	0
T115	10492	141	0	0
T117	90098	235	0	0
T144	16447	15	0	0
T145	4611	3	0	0
T146	14328	43	0	0
T147	6019	147	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	4561	0	0
T105	11173	145	0	0
T106	10611	6	0	0
T107	5292	12	0	0
T114	9529	51	0	0
T115	10492	225	0	0
T117	90098	236	0	0
T144	16447	40	0	0
T145	4611	3	0	0
T146	14328	39	0	0
T147	6019	6	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3640	0	0
T105	11173	55	0	0
T106	10611	70	0	0
T107	5292	9	0	0
T114	9529	37	0	0
T115	10492	15	0	0
T117	90098	219	0	0
T144	16447	77	0	0
T145	4611	57	0	0
T146	14328	2	0	0
T147	6019	5	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3513	0	0
T105	11173	78	0	0
T106	10611	15	0	0
T107	5292	7	0	0
T114	9529	80	0	0
T115	10492	102	0	0
T117	90098	256	0	0
T144	16447	25	0	0
T145	4611	1	0	0
T146	14328	40	0	0
T147	6019	47	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3589	0	0
T105	11173	10	0	0
T106	10611	93	0	0
T107	5292	17	0	0
T114	9529	46	0	0
T115	10492	106	0	0
T117	90098	211	0	0
T144	16447	29	0	0
T146	14328	28	0	0
T147	6019	64	0	0
T148	6022	53	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3980	0	0
T105	11173	10	0	0
T106	10611	116	0	0
T107	5292	52	0	0
T114	9529	80	0	0
T115	10492	58	0	0
T117	90098	225	0	0
T144	16447	43	0	0
T145	4611	2	0	0
T146	14328	67	0	0
T147	6019	66	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3723	0	0
T93	19803	2	0	0
T105	11173	72	0	0
T106	10611	87	0	0
T107	5292	10	0	0
T114	9529	54	0	0
T115	10492	10	0	0
T117	90098	223	0	0
T144	16447	19	0	0
T145	4611	53	0	0
T146	14328	52	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3567	0	0
T105	11173	111	0	0
T106	10611	4	0	0
T107	5292	6	0	0
T114	9529	28	0	0
T115	10492	51	0	0
T117	90098	226	0	0
T144	16447	40	0	0
T145	4611	43	0	0
T146	14328	108	0	0
T147	6019	47	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3528	0	0
T105	11173	119	0	0
T106	10611	45	0	0
T107	5292	61	0	0
T114	9529	62	0	0
T115	10492	60	0	0
T117	90098	237	0	0
T144	16447	15	0	0
T145	4611	65	0	0
T146	14328	19	0	0
T147	6019	7	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3679	0	0
T105	11173	93	0	0
T106	10611	11	0	0
T107	5292	8	0	0
T114	9529	57	0	0
T115	10492	117	0	0
T117	90098	244	0	0
T144	16447	37	0	0
T145	4611	58	0	0
T146	14328	61	0	0
T147	6019	59	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3796	0	0
T105	11173	69	0	0
T106	10611	64	0	0
T107	5292	61	0	0
T114	9529	40	0	0
T115	10492	98	0	0
T117	90098	215	0	0
T144	16447	70	0	0
T145	4611	41	0	0
T146	14328	40	0	0
T147	6019	6	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3806	0	0
T105	11173	121	0	0
T106	10611	110	0	0
T107	5292	47	0	0
T114	9529	15	0	0
T115	10492	100	0	0
T117	90098	240	0	0
T144	16447	44	0	0
T145	4611	9	0	0
T146	14328	63	0	0
T147	6019	54	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3626	0	0
T105	11173	138	0	0
T106	10611	19	0	0
T107	5292	52	0	0
T114	9529	61	0	0
T115	10492	62	0	0
T117	90098	215	0	0
T144	16447	14	0	0
T145	4611	46	0	0
T146	14328	14	0	0
T147	6019	6	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3482	0	0
T105	11173	63	0	0
T106	10611	54	0	0
T107	5292	9	0	0
T114	9529	47	0	0
T115	10492	36	0	0
T117	90098	221	0	0
T144	16447	32	0	0
T145	4611	6	0	0
T146	14328	27	0	0
T147	6019	14	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3632	0	0
T105	11173	10	0	0
T106	10611	18	0	0
T107	5292	68	0	0
T114	9529	58	0	0
T115	10492	68	0	0
T117	90098	249	0	0
T144	16447	40	0	0
T145	4611	55	0	0
T146	14328	28	0	0
T147	6019	3	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3593	0	0
T105	11173	53	0	0
T106	10611	123	0	0
T107	5292	8	0	0
T114	9529	35	0	0
T115	10492	90	0	0
T117	90098	222	0	0
T144	16447	18	0	0
T145	4611	45	0	0
T146	14328	36	0	0
T147	6019	1	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3725	0	0
T105	11173	100	0	0
T106	10611	16	0	0
T107	5292	13	0	0
T115	10492	59	0	0
T117	90098	221	0	0
T144	16447	59	0	0
T145	4611	64	0	0
T146	14328	46	0	0
T147	6019	7	0	0
T148	6022	4	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3632	0	0
T104	6853	5	0	0
T105	11173	105	0	0
T106	10611	120	0	0
T107	5292	62	0	0
T115	10492	154	0	0
T117	90098	223	0	0
T144	16447	50	0	0
T145	4611	63	0	0
T146	14328	20	0	0
T147	6019	4	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3014	0	0
T105	11173	27	0	0
T106	10611	83	0	0
T107	5292	5	0	0
T114	9529	37	0	0
T115	10492	105	0	0
T117	90098	180	0	0
T144	16447	25	0	0
T145	4611	9	0	0
T146	14328	12	0	0
T147	6019	2	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3525	0	0
T105	11173	16	0	0
T106	10611	69	0	0
T107	5292	61	0	0
T114	9529	38	0	0
T115	10492	13	0	0
T117	90098	211	0	0
T144	16447	28	0	0
T145	4611	48	0	0
T146	14328	68	0	0
T147	6019	7	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3184	0	0
T105	11173	12	0	0
T106	10611	39	0	0
T107	5292	8	0	0
T114	9529	8	0	0
T115	10492	111	0	0
T117	90098	224	0	0
T144	16447	36	0	0
T145	4611	8	0	0
T146	14328	28	0	0
T147	6019	37	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3687	0	0
T105	11173	67	0	0
T106	10611	74	0	0
T107	5292	3	0	0
T114	9529	47	0	0
T115	10492	69	0	0
T117	90098	202	0	0
T144	16447	27	0	0
T145	4611	10	0	0
T146	14328	17	0	0
T147	6019	62	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3633	0	0
T105	11173	16	0	0
T106	10611	117	0	0
T107	5292	61	0	0
T114	9529	59	0	0
T115	10492	180	0	0
T117	90098	219	0	0
T144	16447	16	0	0
T145	4611	6	0	0
T146	14328	61	0	0
T147	6019	4	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3697	0	0
T105	11173	14	0	0
T106	10611	79	0	0
T107	5292	72	0	0
T114	9529	30	0	0
T115	10492	116	0	0
T117	90098	216	0	0
T144	16447	27	0	0
T145	4611	39	0	0
T146	14328	52	0	0
T147	6019	50	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3790	0	0
T105	11173	93	0	0
T106	10611	60	0	0
T107	5292	6	0	0
T114	9529	31	0	0
T115	10492	53	0	0
T117	90098	240	0	0
T144	16447	62	0	0
T145	4611	9	0	0
T146	14328	35	0	0
T147	6019	8	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3648	0	0
T105	11173	89	0	0
T106	10611	65	0	0
T107	5292	8	0	0
T114	9529	86	0	0
T115	10492	68	0	0
T117	90098	237	0	0
T144	16447	25	0	0
T145	4611	54	0	0
T146	14328	54	0	0
T147	6019	4	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2333	0	0
T105	11173	20	0	0
T106	10611	23	0	0
T107	5292	10	0	0
T114	9529	13	0	0
T115	10492	16	0	0
T117	90098	213	0	0
T144	16447	68	0	0
T145	4611	9	0	0
T146	14328	18	0	0
T147	6019	6	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2183	0	0
T105	11173	2	0	0
T106	10611	20	0	0
T107	5292	8	0	0
T114	9529	8	0	0
T115	10492	28	0	0
T117	90098	200	0	0
T144	16447	13	0	0
T145	4611	6	0	0
T146	14328	23	0	0
T147	6019	11	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2278	0	0
T93	19803	3	0	0
T105	11173	12	0	0
T106	10611	14	0	0
T107	5292	4	0	0
T114	9529	10	0	0
T115	10492	23	0	0
T117	90098	229	0	0
T144	16447	33	0	0
T145	4611	7	0	0
T146	14328	38	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2388	0	0
T105	11173	15	0	0
T106	10611	29	0	0
T107	5292	9	0	0
T114	9529	8	0	0
T115	10492	3	0	0
T117	90098	202	0	0
T144	16447	8	0	0
T145	4611	9	0	0
T146	14328	45	0	0
T147	6019	3	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2743	0	0
T105	11173	37	0	0
T106	10611	25	0	0
T107	5292	19	0	0
T114	9529	13	0	0
T115	10492	54	0	0
T117	90098	225	0	0
T144	16447	52	0	0
T145	4611	14	0	0
T146	14328	56	0	0
T147	6019	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	3849	0	0
T74	0	71	0	0
T132	0	29	0	0
T149	860596	30	0	0
T150	0	23	0	0
T151	0	24	0	0
T152	0	51	0	0
T153	0	18	0	0
T154	0	49	0	0
T155	0	37	0	0
T156	0	25	0	0
T157	10960	0	0	0
T158	11785	0	0	0
T159	907	0	0	0
T160	218050	0	0	0
T161	1161	0	0	0
T162	186273	0	0	0
T163	973	0	0	0
T164	264234	0	0	0
T165	82369	0	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2387	0	0
T105	11173	15	0	0
T106	10611	18	0	0
T107	5292	25	0	0
T114	9529	11	0	0
T115	10492	9	0	0
T117	90098	244	0	0
T144	16447	34	0	0
T145	4611	5	0	0
T146	14328	7	0	0
T147	6019	13	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2262	0	0
T105	11173	16	0	0
T106	10611	20	0	0
T107	5292	13	0	0
T114	9529	9	0	0
T115	10492	16	0	0
T117	90098	225	0	0
T144	16447	27	0	0
T146	14328	30	0	0
T147	6019	8	0	0
T148	6022	18	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2317	0	0
T105	11173	13	0	0
T106	10611	14	0	0
T107	5292	5	0	0
T114	9529	3	0	0
T115	10492	11	0	0
T117	90098	222	0	0
T144	16447	15	0	0
T146	14328	77	0	0
T147	6019	5	0	0
T148	6022	12	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2283	0	0
T105	11173	30	0	0
T106	10611	18	0	0
T107	5292	2	0	0
T114	9529	3	0	0
T115	10492	13	0	0
T117	90098	236	0	0
T144	16447	40	0	0
T145	4611	5	0	0
T146	14328	61	0	0
T147	6019	1	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2161	0	0
T105	11173	13	0	0
T106	10611	14	0	0
T107	5292	6	0	0
T114	9529	12	0	0
T115	10492	1	0	0
T117	90098	231	0	0
T144	16447	41	0	0
T145	4611	1	0	0
T146	14328	16	0	0
T148	6022	3	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2238	0	0
T105	11173	13	0	0
T106	10611	19	0	0
T107	5292	9	0	0
T115	10492	6	0	0
T117	90098	182	0	0
T144	16447	35	0	0
T145	4611	6	0	0
T146	14328	81	0	0
T147	6019	5	0	0
T148	6022	1	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2482	0	0
T105	11173	50	0	0
T106	10611	25	0	0
T107	5292	6	0	0
T114	9529	13	0	0
T115	10492	31	0	0
T117	90098	248	0	0
T144	16447	18	0	0
T145	4611	12	0	0
T146	14328	29	0	0
T147	6019	1	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2177	0	0
T105	11173	13	0	0
T106	10611	9	0	0
T107	5292	12	0	0
T114	9529	4	0	0
T115	10492	21	0	0
T117	90098	217	0	0
T144	16447	28	0	0
T145	4611	9	0	0
T146	14328	44	0	0
T147	6019	6	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2775	0	0
T105	11173	42	0	0
T106	10611	11	0	0
T107	5292	22	0	0
T114	9529	21	0	0
T115	10492	35	0	0
T117	90098	192	0	0
T144	16447	35	0	0
T145	4611	12	0	0
T146	14328	39	0	0
T147	6019	8	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2329	0	0
T105	11173	14	0	0
T106	10611	19	0	0
T107	5292	5	0	0
T114	9529	4	0	0
T115	10492	22	0	0
T117	90098	238	0	0
T144	16447	11	0	0
T145	4611	3	0	0
T146	14328	59	0	0
T147	6019	12	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2313	0	0
T105	11173	7	0	0
T106	10611	6	0	0
T107	5292	6	0	0
T115	10492	21	0	0
T117	90098	222	0	0
T144	16447	63	0	0
T145	4611	2	0	0
T146	14328	48	0	0
T147	6019	4	0	0
T148	6022	15	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2223	0	0
T93	19803	5	0	0
T105	11173	23	0	0
T106	10611	19	0	0
T107	5292	9	0	0
T114	9529	7	0	0
T115	10492	13	0	0
T117	90098	199	0	0
T144	16447	39	0	0
T145	4611	3	0	0
T146	14328	38	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2132	0	0
T105	11173	15	0	0
T106	10611	21	0	0
T107	5292	10	0	0
T114	9529	1	0	0
T115	10492	11	0	0
T117	90098	215	0	0
T144	16447	36	0	0
T145	4611	5	0	0
T146	14328	20	0	0
T147	6019	15	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2363	0	0
T105	11173	21	0	0
T106	10611	15	0	0
T107	5292	11	0	0
T114	9529	10	0	0
T115	10492	11	0	0
T117	90098	234	0	0
T144	16447	30	0	0
T145	4611	6	0	0
T146	14328	82	0	0
T147	6019	1	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2223	0	0
T105	11173	24	0	0
T106	10611	15	0	0
T107	5292	10	0	0
T114	9529	14	0	0
T115	10492	10	0	0
T117	90098	191	0	0
T144	16447	24	0	0
T145	4611	9	0	0
T146	14328	59	0	0
T147	6019	5	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357383041	2243	0	0
T91	10003	6	0	0
T105	11173	10	0	0
T106	10611	13	0	0
T107	5292	4	0	0
T115	10492	17	0	0
T117	90098	224	0	0
T144	16447	33	0	0
T145	4611	1	0	0
T146	14328	15	0	0
T147	6019	8	0	0