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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.30 94.12 98.61 89.36 97.14 95.84 99.10


Total test records in report: 1081
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T1010 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2463114669 Jun 06 01:53:56 PM PDT 24 Jun 06 01:53:57 PM PDT 24 26529122 ps
T1011 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1629824763 Jun 06 01:53:16 PM PDT 24 Jun 06 01:53:21 PM PDT 24 157100485 ps
T277 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3320288787 Jun 06 01:53:20 PM PDT 24 Jun 06 01:53:36 PM PDT 24 567343816 ps
T1012 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3610566812 Jun 06 01:53:13 PM PDT 24 Jun 06 01:53:23 PM PDT 24 353005651 ps
T1013 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2296919323 Jun 06 01:53:18 PM PDT 24 Jun 06 01:53:24 PM PDT 24 3581691679 ps
T1014 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1062387066 Jun 06 01:53:39 PM PDT 24 Jun 06 01:53:40 PM PDT 24 11925101 ps
T1015 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.926066067 Jun 06 01:53:22 PM PDT 24 Jun 06 01:53:25 PM PDT 24 81053923 ps
T124 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2743205503 Jun 06 01:53:17 PM PDT 24 Jun 06 01:53:19 PM PDT 24 32138323 ps
T1016 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3533887052 Jun 06 01:53:28 PM PDT 24 Jun 06 01:53:29 PM PDT 24 28715133 ps
T280 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.653455937 Jun 06 01:53:37 PM PDT 24 Jun 06 01:53:45 PM PDT 24 2188368324 ps
T125 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4066373166 Jun 06 01:53:22 PM PDT 24 Jun 06 01:53:24 PM PDT 24 124782397 ps
T126 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.394990589 Jun 06 01:53:24 PM PDT 24 Jun 06 01:53:49 PM PDT 24 374374442 ps
T127 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4144144656 Jun 06 01:53:41 PM PDT 24 Jun 06 01:53:44 PM PDT 24 1622816769 ps
T1017 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3233189196 Jun 06 01:53:37 PM PDT 24 Jun 06 01:53:40 PM PDT 24 321520013 ps
T1018 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3227651590 Jun 06 01:53:25 PM PDT 24 Jun 06 01:53:31 PM PDT 24 287944599 ps
T1019 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.498258693 Jun 06 01:53:47 PM PDT 24 Jun 06 01:53:50 PM PDT 24 104958871 ps
T1020 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1029853058 Jun 06 01:53:56 PM PDT 24 Jun 06 01:53:59 PM PDT 24 48573060 ps
T1021 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.83187514 Jun 06 01:53:15 PM PDT 24 Jun 06 01:53:19 PM PDT 24 271389110 ps
T1022 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1962115602 Jun 06 01:53:31 PM PDT 24 Jun 06 01:53:35 PM PDT 24 153017303 ps
T273 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.384249291 Jun 06 01:53:40 PM PDT 24 Jun 06 01:53:48 PM PDT 24 552286188 ps
T1023 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2123750965 Jun 06 01:53:38 PM PDT 24 Jun 06 01:53:41 PM PDT 24 139559815 ps
T1024 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1429304286 Jun 06 01:53:36 PM PDT 24 Jun 06 01:53:38 PM PDT 24 270862331 ps
T1025 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3137580636 Jun 06 01:53:26 PM PDT 24 Jun 06 01:53:28 PM PDT 24 78752439 ps
T1026 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2629375342 Jun 06 01:53:13 PM PDT 24 Jun 06 01:53:17 PM PDT 24 120442453 ps
T78 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3803894195 Jun 06 01:53:16 PM PDT 24 Jun 06 01:53:19 PM PDT 24 79481295 ps
T1027 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2592112058 Jun 06 01:53:48 PM PDT 24 Jun 06 01:53:52 PM PDT 24 132777702 ps
T1028 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.740134702 Jun 06 01:53:41 PM PDT 24 Jun 06 01:53:44 PM PDT 24 73391341 ps
T1029 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3055096493 Jun 06 01:53:36 PM PDT 24 Jun 06 01:53:38 PM PDT 24 54844799 ps
T1030 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1754974104 Jun 06 01:53:56 PM PDT 24 Jun 06 01:53:58 PM PDT 24 13101831 ps
T1031 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3111529105 Jun 06 01:53:16 PM PDT 24 Jun 06 01:53:20 PM PDT 24 105730719 ps
T1032 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3192415672 Jun 06 01:53:46 PM PDT 24 Jun 06 01:53:48 PM PDT 24 15722626 ps
T1033 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1007591314 Jun 06 01:53:29 PM PDT 24 Jun 06 01:53:32 PM PDT 24 60374135 ps
T1034 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.879579136 Jun 06 01:53:40 PM PDT 24 Jun 06 01:53:42 PM PDT 24 41617714 ps
T1035 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1685920108 Jun 06 01:53:55 PM PDT 24 Jun 06 01:53:56 PM PDT 24 35498798 ps
T1036 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3165468353 Jun 06 01:53:15 PM PDT 24 Jun 06 01:53:21 PM PDT 24 218877674 ps
T1037 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.555644740 Jun 06 01:53:20 PM PDT 24 Jun 06 01:53:24 PM PDT 24 59066631 ps
T1038 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3611092080 Jun 06 01:53:50 PM PDT 24 Jun 06 01:53:52 PM PDT 24 42088072 ps
T1039 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2901436272 Jun 06 01:53:23 PM PDT 24 Jun 06 01:53:25 PM PDT 24 12163522 ps
T1040 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.860967401 Jun 06 01:53:48 PM PDT 24 Jun 06 01:53:50 PM PDT 24 16722988 ps
T1041 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1068568888 Jun 06 01:53:59 PM PDT 24 Jun 06 01:54:01 PM PDT 24 25769133 ps
T1042 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2058487875 Jun 06 01:53:46 PM PDT 24 Jun 06 01:53:48 PM PDT 24 52890666 ps
T1043 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3596044537 Jun 06 01:53:49 PM PDT 24 Jun 06 01:53:53 PM PDT 24 564575309 ps
T1044 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.796105960 Jun 06 01:53:20 PM PDT 24 Jun 06 01:53:55 PM PDT 24 2616758554 ps
T1045 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1417174208 Jun 06 01:53:47 PM PDT 24 Jun 06 01:53:50 PM PDT 24 224640651 ps
T1046 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3779789501 Jun 06 01:53:16 PM PDT 24 Jun 06 01:53:18 PM PDT 24 21744156 ps
T1047 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3396729934 Jun 06 01:53:55 PM PDT 24 Jun 06 01:53:57 PM PDT 24 13731180 ps
T1048 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3411303556 Jun 06 01:53:24 PM PDT 24 Jun 06 01:53:27 PM PDT 24 163901606 ps
T1049 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1538983918 Jun 06 01:53:36 PM PDT 24 Jun 06 01:53:39 PM PDT 24 962410642 ps
T1050 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3259330670 Jun 06 01:53:45 PM PDT 24 Jun 06 01:53:52 PM PDT 24 115019456 ps
T1051 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1353824603 Jun 06 01:53:45 PM PDT 24 Jun 06 01:53:47 PM PDT 24 13115275 ps
T1052 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1181434200 Jun 06 01:53:38 PM PDT 24 Jun 06 01:53:39 PM PDT 24 38544452 ps
T1053 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1477088063 Jun 06 01:53:38 PM PDT 24 Jun 06 01:53:41 PM PDT 24 30135498 ps
T1054 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2416170462 Jun 06 01:53:38 PM PDT 24 Jun 06 01:53:40 PM PDT 24 35174779 ps
T1055 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1233156964 Jun 06 01:53:47 PM PDT 24 Jun 06 01:53:51 PM PDT 24 52386843 ps
T1056 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.707580788 Jun 06 01:53:16 PM PDT 24 Jun 06 01:53:19 PM PDT 24 39825039 ps
T1057 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2092104914 Jun 06 01:53:24 PM PDT 24 Jun 06 01:53:32 PM PDT 24 922329983 ps
T1058 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.117324848 Jun 06 01:53:24 PM PDT 24 Jun 06 01:53:25 PM PDT 24 13150089 ps
T1059 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1682899736 Jun 06 01:53:24 PM PDT 24 Jun 06 01:54:01 PM PDT 24 1841264011 ps
T1060 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1886944607 Jun 06 01:53:52 PM PDT 24 Jun 06 01:53:57 PM PDT 24 216288593 ps
T1061 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2933326351 Jun 06 01:54:02 PM PDT 24 Jun 06 01:54:04 PM PDT 24 35372676 ps
T1062 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1040737562 Jun 06 01:53:28 PM PDT 24 Jun 06 01:53:41 PM PDT 24 410246099 ps
T1063 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4092139051 Jun 06 01:53:50 PM PDT 24 Jun 06 01:53:52 PM PDT 24 14142703 ps
T1064 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2475195633 Jun 06 01:53:49 PM PDT 24 Jun 06 01:53:51 PM PDT 24 16751931 ps
T1065 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1435389411 Jun 06 01:53:55 PM PDT 24 Jun 06 01:53:57 PM PDT 24 704583753 ps
T1066 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2298156097 Jun 06 01:53:46 PM PDT 24 Jun 06 01:54:09 PM PDT 24 3919361557 ps
T1067 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4124064663 Jun 06 01:53:24 PM PDT 24 Jun 06 01:53:41 PM PDT 24 817342225 ps
T1068 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2799146063 Jun 06 01:53:46 PM PDT 24 Jun 06 01:53:51 PM PDT 24 437888546 ps
T1069 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1189784216 Jun 06 01:53:47 PM PDT 24 Jun 06 01:53:51 PM PDT 24 34566929 ps
T1070 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1023138950 Jun 06 01:53:22 PM PDT 24 Jun 06 01:53:28 PM PDT 24 199845340 ps
T1071 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1149437837 Jun 06 01:53:15 PM PDT 24 Jun 06 01:53:18 PM PDT 24 20717112 ps
T1072 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3978511015 Jun 06 01:53:40 PM PDT 24 Jun 06 01:53:44 PM PDT 24 161393279 ps
T1073 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.198844496 Jun 06 01:53:50 PM PDT 24 Jun 06 01:53:53 PM PDT 24 26918824 ps
T1074 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1410675328 Jun 06 01:53:14 PM PDT 24 Jun 06 01:53:16 PM PDT 24 13768924 ps
T274 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.575574141 Jun 06 01:53:35 PM PDT 24 Jun 06 01:53:43 PM PDT 24 336867809 ps
T1075 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1639385925 Jun 06 01:53:41 PM PDT 24 Jun 06 01:53:46 PM PDT 24 199799534 ps
T1076 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1089520573 Jun 06 01:53:51 PM PDT 24 Jun 06 01:53:55 PM PDT 24 39544024 ps
T1077 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2944402861 Jun 06 01:53:14 PM PDT 24 Jun 06 01:53:17 PM PDT 24 77402378 ps
T1078 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3575964047 Jun 06 01:53:51 PM PDT 24 Jun 06 01:53:53 PM PDT 24 63952475 ps
T1079 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1103815960 Jun 06 01:53:18 PM PDT 24 Jun 06 01:53:45 PM PDT 24 1277059123 ps
T1080 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2897736078 Jun 06 01:53:13 PM PDT 24 Jun 06 01:53:15 PM PDT 24 17684819 ps
T1081 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2630729486 Jun 06 01:53:43 PM PDT 24 Jun 06 01:53:58 PM PDT 24 2161682847 ps

Test location /workspace/coverage/default/1.spi_device_stress_all.2018644232
Short name T1
Test name
Test status
Simulation time 23448838908 ps
CPU time 167.23 seconds
Started Jun 06 01:57:08 PM PDT 24
Finished Jun 06 01:59:56 PM PDT 24
Peak memory 258084 kb
Host smart-d019ba37-bcf2-47ba-98b2-54f43d2941dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018644232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2018644232
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3532026087
Short name T16
Test name
Test status
Simulation time 61081681392 ps
CPU time 646.2 seconds
Started Jun 06 01:59:18 PM PDT 24
Finished Jun 06 02:10:06 PM PDT 24
Peak memory 273784 kb
Host smart-39544437-ed5c-4aa5-b6e1-2d5d256ce7a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532026087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3532026087
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3908221986
Short name T68
Test name
Test status
Simulation time 54111672955 ps
CPU time 128.68 seconds
Started Jun 06 01:57:55 PM PDT 24
Finished Jun 06 02:00:06 PM PDT 24
Peak memory 241612 kb
Host smart-d87577c1-ecfb-4515-9fbe-dfa8d9e1edfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908221986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3908221986
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.798168477
Short name T69
Test name
Test status
Simulation time 12839919724 ps
CPU time 160.08 seconds
Started Jun 06 01:59:03 PM PDT 24
Finished Jun 06 02:01:44 PM PDT 24
Peak memory 265960 kb
Host smart-170fff39-0401-4a98-86b6-2c3961f5b6de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798168477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.798168477
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.576279562
Short name T105
Test name
Test status
Simulation time 116414260 ps
CPU time 2.84 seconds
Started Jun 06 01:53:47 PM PDT 24
Finished Jun 06 01:53:51 PM PDT 24
Peak memory 216960 kb
Host smart-abafaf60-437e-4cc2-88f9-8f2822ad8462
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576279562 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.576279562
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1341796751
Short name T30
Test name
Test status
Simulation time 106461659273 ps
CPU time 351.88 seconds
Started Jun 06 01:57:03 PM PDT 24
Finished Jun 06 02:02:56 PM PDT 24
Peak memory 266308 kb
Host smart-759edfb9-ee6f-46a7-ab80-bac3124574bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341796751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1341796751
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.276838801
Short name T62
Test name
Test status
Simulation time 16772781 ps
CPU time 0.74 seconds
Started Jun 06 01:56:56 PM PDT 24
Finished Jun 06 01:56:58 PM PDT 24
Peak memory 216828 kb
Host smart-eb71e4da-0837-48eb-947f-0633df92d61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276838801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.276838801
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2018763342
Short name T31
Test name
Test status
Simulation time 66758807695 ps
CPU time 331.8 seconds
Started Jun 06 01:57:19 PM PDT 24
Finished Jun 06 02:02:52 PM PDT 24
Peak memory 256960 kb
Host smart-3233d4cd-2362-4003-b4e6-39053a66c9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018763342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2018763342
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1351183522
Short name T71
Test name
Test status
Simulation time 19107793897 ps
CPU time 231.26 seconds
Started Jun 06 01:58:45 PM PDT 24
Finished Jun 06 02:02:37 PM PDT 24
Peak memory 265284 kb
Host smart-0a875097-7b5d-4fd7-b34b-f8cb5e01e9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351183522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1351183522
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1775608888
Short name T58
Test name
Test status
Simulation time 123618413 ps
CPU time 0.95 seconds
Started Jun 06 01:57:06 PM PDT 24
Finished Jun 06 01:57:08 PM PDT 24
Peak memory 236188 kb
Host smart-8af43271-b886-46c4-a899-5a4d84ae85e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775608888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1775608888
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1267364074
Short name T232
Test name
Test status
Simulation time 107289485863 ps
CPU time 503.74 seconds
Started Jun 06 01:57:02 PM PDT 24
Finished Jun 06 02:05:27 PM PDT 24
Peak memory 283704 kb
Host smart-2f72332e-05df-491c-a86b-97c35fe770ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267364074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1267364074
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3390920636
Short name T14
Test name
Test status
Simulation time 2230601147 ps
CPU time 39.89 seconds
Started Jun 06 01:58:06 PM PDT 24
Finished Jun 06 01:58:47 PM PDT 24
Peak memory 228224 kb
Host smart-0d9614af-66f7-4fba-8b14-802c69bb79a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390920636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3390920636
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2967047487
Short name T266
Test name
Test status
Simulation time 60046876287 ps
CPU time 544.53 seconds
Started Jun 06 01:59:13 PM PDT 24
Finished Jun 06 02:08:19 PM PDT 24
Peak memory 250996 kb
Host smart-bb456111-8dff-463d-bb35-d6c626ffd34f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967047487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2967047487
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3733524305
Short name T153
Test name
Test status
Simulation time 29738714091 ps
CPU time 202.3 seconds
Started Jun 06 01:57:42 PM PDT 24
Finished Jun 06 02:01:07 PM PDT 24
Peak memory 274444 kb
Host smart-8886f7a0-763e-4e1c-962f-6385b5f6bd58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733524305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3733524305
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.619732746
Short name T278
Test name
Test status
Simulation time 761249625 ps
CPU time 12.08 seconds
Started Jun 06 01:53:50 PM PDT 24
Finished Jun 06 01:54:03 PM PDT 24
Peak memory 215408 kb
Host smart-20acd297-3705-4ee8-8ce0-32c0d9a2809c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619732746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.619732746
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2609878045
Short name T93
Test name
Test status
Simulation time 825230277 ps
CPU time 4.86 seconds
Started Jun 06 01:53:50 PM PDT 24
Finished Jun 06 01:53:57 PM PDT 24
Peak memory 215248 kb
Host smart-15dc3f41-be85-4d34-becf-e7e2b67d08cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609878045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2609878045
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4011202199
Short name T76
Test name
Test status
Simulation time 23855351 ps
CPU time 1.38 seconds
Started Jun 06 01:53:25 PM PDT 24
Finished Jun 06 01:53:27 PM PDT 24
Peak memory 216120 kb
Host smart-2c1dea26-28ad-4526-8325-1570ea7c530d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011202199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4011202199
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3472170966
Short name T239
Test name
Test status
Simulation time 110802698825 ps
CPU time 513.79 seconds
Started Jun 06 01:57:49 PM PDT 24
Finished Jun 06 02:06:25 PM PDT 24
Peak memory 266268 kb
Host smart-d8fd6dd2-70a6-4f57-8c2c-f0cccb184d34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472170966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3472170966
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.906782440
Short name T173
Test name
Test status
Simulation time 145579580193 ps
CPU time 672.91 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 02:08:36 PM PDT 24
Peak memory 265492 kb
Host smart-7c70576e-c0a2-418c-a42a-71291bfa0cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906782440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.906782440
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.920976058
Short name T81
Test name
Test status
Simulation time 8299555958 ps
CPU time 48.68 seconds
Started Jun 06 01:57:14 PM PDT 24
Finished Jun 06 01:58:04 PM PDT 24
Peak memory 241704 kb
Host smart-265db96e-72d2-41de-8d4b-d24f4abaa59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920976058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.920976058
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3614970447
Short name T198
Test name
Test status
Simulation time 27858124768 ps
CPU time 132.82 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:59:35 PM PDT 24
Peak memory 267320 kb
Host smart-c7e1a529-6fc6-4f8f-aa93-0aa7e0e3a73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614970447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3614970447
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1000039527
Short name T245
Test name
Test status
Simulation time 48195500095 ps
CPU time 202.37 seconds
Started Jun 06 01:59:17 PM PDT 24
Finished Jun 06 02:02:40 PM PDT 24
Peak memory 268332 kb
Host smart-01a0fca6-f6ef-4405-b654-7a80e4cd61ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000039527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1000039527
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2176310808
Short name T483
Test name
Test status
Simulation time 7270231934 ps
CPU time 71.67 seconds
Started Jun 06 01:58:26 PM PDT 24
Finished Jun 06 01:59:38 PM PDT 24
Peak memory 251540 kb
Host smart-b321fde6-1fce-4497-bb44-e47272e00f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176310808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2176310808
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1817640899
Short name T233
Test name
Test status
Simulation time 9066198581 ps
CPU time 83.16 seconds
Started Jun 06 01:57:43 PM PDT 24
Finished Jun 06 01:59:07 PM PDT 24
Peak memory 255072 kb
Host smart-9d18a62a-30ac-4bdc-9e89-1b3a48b8c1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817640899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1817640899
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.633092606
Short name T13
Test name
Test status
Simulation time 2904736630 ps
CPU time 9.58 seconds
Started Jun 06 01:59:10 PM PDT 24
Finished Jun 06 01:59:21 PM PDT 24
Peak memory 217052 kb
Host smart-28ccb471-9338-4fbe-a54a-90a8fcd8211b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633092606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.633092606
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.305019772
Short name T350
Test name
Test status
Simulation time 114033340 ps
CPU time 0.75 seconds
Started Jun 06 01:57:51 PM PDT 24
Finished Jun 06 01:57:53 PM PDT 24
Peak memory 206088 kb
Host smart-5f2509ba-ab44-415e-a47f-8e16ebfb40a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305019772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.305019772
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.198104039
Short name T128
Test name
Test status
Simulation time 17359412818 ps
CPU time 171.28 seconds
Started Jun 06 01:57:47 PM PDT 24
Finished Jun 06 02:00:39 PM PDT 24
Peak memory 265264 kb
Host smart-fa5810a2-9607-4725-8d45-820dfb6f484e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198104039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.198104039
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.104836694
Short name T73
Test name
Test status
Simulation time 15992335077 ps
CPU time 264.39 seconds
Started Jun 06 01:58:17 PM PDT 24
Finished Jun 06 02:02:43 PM PDT 24
Peak memory 289592 kb
Host smart-7c6196ae-5a41-48c6-887c-9b33274f3cac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104836694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.104836694
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.898179563
Short name T234
Test name
Test status
Simulation time 32735558971 ps
CPU time 165.94 seconds
Started Jun 06 01:58:17 PM PDT 24
Finished Jun 06 02:01:05 PM PDT 24
Peak memory 266288 kb
Host smart-cdaca557-2be0-4de6-8720-35111b219e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898179563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.898179563
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1773568097
Short name T227
Test name
Test status
Simulation time 7351584129 ps
CPU time 113.94 seconds
Started Jun 06 01:57:42 PM PDT 24
Finished Jun 06 01:59:38 PM PDT 24
Peak memory 258076 kb
Host smart-c2ce3a9b-5888-400a-9067-88618dd3dce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773568097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1773568097
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1057017434
Short name T242
Test name
Test status
Simulation time 88208413922 ps
CPU time 154.82 seconds
Started Jun 06 01:59:08 PM PDT 24
Finished Jun 06 02:01:44 PM PDT 24
Peak memory 267492 kb
Host smart-95cb5081-ecef-40c1-a489-e102935b2803
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057017434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1057017434
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2095750175
Short name T43
Test name
Test status
Simulation time 131935572927 ps
CPU time 392.22 seconds
Started Jun 06 01:57:52 PM PDT 24
Finished Jun 06 02:04:26 PM PDT 24
Peak memory 258060 kb
Host smart-cde4e20a-04a2-41bd-9ad3-8995ed8b4876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095750175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2095750175
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.871145300
Short name T133
Test name
Test status
Simulation time 127892739296 ps
CPU time 298.78 seconds
Started Jun 06 01:57:12 PM PDT 24
Finished Jun 06 02:02:12 PM PDT 24
Peak memory 254040 kb
Host smart-a69decd6-93ba-4550-9580-a6b26b147b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871145300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.871145300
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3453051782
Short name T248
Test name
Test status
Simulation time 10569599968 ps
CPU time 169.96 seconds
Started Jun 06 01:57:41 PM PDT 24
Finished Jun 06 02:00:34 PM PDT 24
Peak memory 263940 kb
Host smart-27d56c12-169a-4163-bf60-7cc70218478b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453051782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3453051782
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2793745470
Short name T22
Test name
Test status
Simulation time 27565746191 ps
CPU time 273.19 seconds
Started Jun 06 01:57:13 PM PDT 24
Finished Jun 06 02:01:47 PM PDT 24
Peak memory 249984 kb
Host smart-be365fdb-efdd-4a3c-90cb-96885bb62853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793745470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2793745470
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4114427947
Short name T275
Test name
Test status
Simulation time 1628915118 ps
CPU time 22.11 seconds
Started Jun 06 01:53:12 PM PDT 24
Finished Jun 06 01:53:35 PM PDT 24
Peak memory 215276 kb
Host smart-625fa091-fd53-4c03-949d-a0e0a8b2f748
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114427947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4114427947
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3201167419
Short name T333
Test name
Test status
Simulation time 1347495984 ps
CPU time 19.03 seconds
Started Jun 06 01:57:15 PM PDT 24
Finished Jun 06 01:57:35 PM PDT 24
Peak memory 225172 kb
Host smart-051d5259-700e-4eaf-b60d-4c08e8a026f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201167419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3201167419
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3395347235
Short name T183
Test name
Test status
Simulation time 144180795629 ps
CPU time 391.65 seconds
Started Jun 06 01:57:56 PM PDT 24
Finished Jun 06 02:04:29 PM PDT 24
Peak memory 250944 kb
Host smart-bde967d3-0b3f-43a2-9fe3-781960b6c23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395347235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3395347235
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3680145032
Short name T202
Test name
Test status
Simulation time 5102544055 ps
CPU time 52.9 seconds
Started Jun 06 01:57:14 PM PDT 24
Finished Jun 06 01:58:08 PM PDT 24
Peak memory 238124 kb
Host smart-735eb5bc-ff79-45a4-a943-51afc5ad5e29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680145032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3680145032
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3907649160
Short name T70
Test name
Test status
Simulation time 86829251686 ps
CPU time 84.04 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 02:00:04 PM PDT 24
Peak memory 249884 kb
Host smart-98aa68f5-b721-4260-8822-1fac6a91a7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907649160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3907649160
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2305492586
Short name T331
Test name
Test status
Simulation time 347507885 ps
CPU time 5.67 seconds
Started Jun 06 01:58:55 PM PDT 24
Finished Jun 06 01:59:01 PM PDT 24
Peak memory 236304 kb
Host smart-fd8a573e-c578-4ece-8917-bc35c676f40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305492586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2305492586
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.19491037
Short name T82
Test name
Test status
Simulation time 212884222 ps
CPU time 4.07 seconds
Started Jun 06 01:58:20 PM PDT 24
Finished Jun 06 01:58:25 PM PDT 24
Peak memory 233412 kb
Host smart-0c342f04-ef5c-4b43-a849-662239c9704f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19491037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.19491037
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2929412168
Short name T101
Test name
Test status
Simulation time 995687674 ps
CPU time 5.77 seconds
Started Jun 06 01:53:37 PM PDT 24
Finished Jun 06 01:53:43 PM PDT 24
Peak memory 215368 kb
Host smart-a9a0f17f-2489-4077-b331-ca00c88a56fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929412168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2929412168
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2408884021
Short name T90
Test name
Test status
Simulation time 297195361 ps
CPU time 7.99 seconds
Started Jun 06 01:53:12 PM PDT 24
Finished Jun 06 01:53:21 PM PDT 24
Peak memory 215472 kb
Host smart-a45b8611-3465-47e1-9d7a-3fc6dd8123ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408884021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2408884021
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.575574141
Short name T274
Test name
Test status
Simulation time 336867809 ps
CPU time 7.49 seconds
Started Jun 06 01:53:35 PM PDT 24
Finished Jun 06 01:53:43 PM PDT 24
Peak memory 215152 kb
Host smart-8aa01de8-6b67-4fe6-baef-b6930dd4eb65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575574141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.575574141
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1135121047
Short name T257
Test name
Test status
Simulation time 6463810170 ps
CPU time 25.62 seconds
Started Jun 06 01:57:49 PM PDT 24
Finished Jun 06 01:58:16 PM PDT 24
Peak memory 249128 kb
Host smart-406c1277-44ab-4d4b-9af7-49bc82bcb2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135121047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1135121047
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2671198613
Short name T212
Test name
Test status
Simulation time 2482419915 ps
CPU time 14.92 seconds
Started Jun 06 01:58:06 PM PDT 24
Finished Jun 06 01:58:22 PM PDT 24
Peak memory 241672 kb
Host smart-31f02a17-f8e3-45ce-9bd1-fb33dd1207f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671198613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2671198613
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1178960431
Short name T255
Test name
Test status
Simulation time 2255334642 ps
CPU time 30.36 seconds
Started Jun 06 01:57:55 PM PDT 24
Finished Jun 06 01:58:27 PM PDT 24
Peak memory 249904 kb
Host smart-9674e180-7e8d-4e86-9d1c-5afd8c3d016c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178960431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1178960431
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3963796434
Short name T328
Test name
Test status
Simulation time 1851267115 ps
CPU time 10.65 seconds
Started Jun 06 01:57:56 PM PDT 24
Finished Jun 06 01:58:09 PM PDT 24
Peak memory 225216 kb
Host smart-ee026a0c-32d0-4983-abe1-098d5a10c394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963796434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3963796434
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.4078601099
Short name T282
Test name
Test status
Simulation time 1393163857 ps
CPU time 6.08 seconds
Started Jun 06 01:57:55 PM PDT 24
Finished Jun 06 01:58:02 PM PDT 24
Peak memory 225176 kb
Host smart-58e7dd09-0354-40c0-a761-fdc03fb93f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078601099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.4078601099
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2974290703
Short name T883
Test name
Test status
Simulation time 123190339 ps
CPU time 3.39 seconds
Started Jun 06 01:58:09 PM PDT 24
Finished Jun 06 01:58:13 PM PDT 24
Peak memory 233428 kb
Host smart-ae76bf76-e974-48ef-abcb-8521be3c79fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974290703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2974290703
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2816875393
Short name T254
Test name
Test status
Simulation time 1814918271 ps
CPU time 5.59 seconds
Started Jun 06 01:58:12 PM PDT 24
Finished Jun 06 01:58:19 PM PDT 24
Peak memory 233424 kb
Host smart-35a96357-a16a-4e74-a910-9223825dd752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816875393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2816875393
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2602265392
Short name T246
Test name
Test status
Simulation time 3778614582 ps
CPU time 94.92 seconds
Started Jun 06 01:58:09 PM PDT 24
Finished Jun 06 01:59:45 PM PDT 24
Peak memory 266264 kb
Host smart-ed6482c3-b7f6-4d6f-8ab1-194182597e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602265392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2602265392
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.201514994
Short name T244
Test name
Test status
Simulation time 38625769103 ps
CPU time 391.15 seconds
Started Jun 06 01:58:39 PM PDT 24
Finished Jun 06 02:05:12 PM PDT 24
Peak memory 257056 kb
Host smart-1b5f91ff-a773-430d-b77e-c53b88c7f61b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201514994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.201514994
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2029007209
Short name T74
Test name
Test status
Simulation time 21305490462 ps
CPU time 105.85 seconds
Started Jun 06 01:58:44 PM PDT 24
Finished Jun 06 02:00:31 PM PDT 24
Peak memory 271972 kb
Host smart-0b9c7cfb-3768-4ba2-be15-e583efa7a8d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029007209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2029007209
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3186664571
Short name T35
Test name
Test status
Simulation time 45962148242 ps
CPU time 247.27 seconds
Started Jun 06 01:58:46 PM PDT 24
Finished Jun 06 02:02:54 PM PDT 24
Peak memory 249860 kb
Host smart-8f427f85-c989-479f-9f46-07132b0d0985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186664571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3186664571
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4197614718
Short name T267
Test name
Test status
Simulation time 18786623139 ps
CPU time 177.3 seconds
Started Jun 06 01:59:41 PM PDT 24
Finished Jun 06 02:02:39 PM PDT 24
Peak memory 249832 kb
Host smart-02a1206d-ce8e-4886-b3ac-8a0d7b574f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197614718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4197614718
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.174851706
Short name T215
Test name
Test status
Simulation time 41948239863 ps
CPU time 186.62 seconds
Started Jun 06 01:57:18 PM PDT 24
Finished Jun 06 02:00:26 PM PDT 24
Peak memory 256136 kb
Host smart-b9033e1a-fbf9-4b9b-b9ae-09b63bad5361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174851706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.174851706
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1664076799
Short name T85
Test name
Test status
Simulation time 215341636 ps
CPU time 2.4 seconds
Started Jun 06 01:58:16 PM PDT 24
Finished Jun 06 01:58:20 PM PDT 24
Peak memory 225224 kb
Host smart-d4a857db-77ac-453c-8e48-810e02f537ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664076799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1664076799
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3022978090
Short name T75
Test name
Test status
Simulation time 32127201 ps
CPU time 1.22 seconds
Started Jun 06 01:53:20 PM PDT 24
Finished Jun 06 01:53:22 PM PDT 24
Peak memory 206804 kb
Host smart-0f4b1dfd-2eb8-4bde-b1ef-53f66a36a131
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022978090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3022978090
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1576537347
Short name T103
Test name
Test status
Simulation time 819928162 ps
CPU time 12.59 seconds
Started Jun 06 01:53:47 PM PDT 24
Finished Jun 06 01:54:01 PM PDT 24
Peak memory 215120 kb
Host smart-a80718c4-b1bb-4e51-971d-68f54368efa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576537347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1576537347
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1721608744
Short name T123
Test name
Test status
Simulation time 1513951351 ps
CPU time 17.22 seconds
Started Jun 06 01:53:16 PM PDT 24
Finished Jun 06 01:53:34 PM PDT 24
Peak memory 214968 kb
Host smart-6103caed-247d-4130-9f5a-c7aeb9921801
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721608744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1721608744
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.796105960
Short name T1044
Test name
Test status
Simulation time 2616758554 ps
CPU time 33.34 seconds
Started Jun 06 01:53:20 PM PDT 24
Finished Jun 06 01:53:55 PM PDT 24
Peak memory 206920 kb
Host smart-7b55ecf2-aee3-4213-a6d6-a4f116e84bcf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796105960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.796105960
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1629824763
Short name T1011
Test name
Test status
Simulation time 157100485 ps
CPU time 3.43 seconds
Started Jun 06 01:53:16 PM PDT 24
Finished Jun 06 01:53:21 PM PDT 24
Peak memory 217404 kb
Host smart-18714115-1964-4d2a-8795-9aea72fa1fc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629824763 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1629824763
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.83187514
Short name T1021
Test name
Test status
Simulation time 271389110 ps
CPU time 2.03 seconds
Started Jun 06 01:53:15 PM PDT 24
Finished Jun 06 01:53:19 PM PDT 24
Peak memory 214968 kb
Host smart-5a24c9f2-ec05-44db-9e90-2c08c005f0d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83187514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.83187514
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2897736078
Short name T1080
Test name
Test status
Simulation time 17684819 ps
CPU time 0.7 seconds
Started Jun 06 01:53:13 PM PDT 24
Finished Jun 06 01:53:15 PM PDT 24
Peak memory 203908 kb
Host smart-2b3f0057-77c1-47fd-9bac-ccec9c8c47ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897736078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
897736078
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4048543951
Short name T118
Test name
Test status
Simulation time 236537520 ps
CPU time 2.24 seconds
Started Jun 06 01:53:20 PM PDT 24
Finished Jun 06 01:53:23 PM PDT 24
Peak memory 215168 kb
Host smart-1a47a8ce-1512-4101-9e12-db061dc2a847
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048543951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.4048543951
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1021802763
Short name T988
Test name
Test status
Simulation time 34014522 ps
CPU time 0.63 seconds
Started Jun 06 01:53:12 PM PDT 24
Finished Jun 06 01:53:13 PM PDT 24
Peak memory 203484 kb
Host smart-68306981-16db-460e-8d3a-9e751cdf2948
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021802763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1021802763
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3165468353
Short name T1036
Test name
Test status
Simulation time 218877674 ps
CPU time 4.3 seconds
Started Jun 06 01:53:15 PM PDT 24
Finished Jun 06 01:53:21 PM PDT 24
Peak memory 215124 kb
Host smart-3d093075-1b63-48fd-8d13-cc6a8859ecc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165468353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3165468353
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.462920257
Short name T100
Test name
Test status
Simulation time 178649471 ps
CPU time 4.49 seconds
Started Jun 06 01:53:15 PM PDT 24
Finished Jun 06 01:53:21 PM PDT 24
Peak memory 215160 kb
Host smart-c4bf1e26-6b07-4244-9db1-68a702f163b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462920257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.462920257
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3610566812
Short name T1012
Test name
Test status
Simulation time 353005651 ps
CPU time 8.23 seconds
Started Jun 06 01:53:13 PM PDT 24
Finished Jun 06 01:53:23 PM PDT 24
Peak memory 215028 kb
Host smart-25f906b3-169f-48b3-9f63-2672126e3ce5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610566812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3610566812
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1664357594
Short name T117
Test name
Test status
Simulation time 4742150565 ps
CPU time 13.8 seconds
Started Jun 06 01:53:17 PM PDT 24
Finished Jun 06 01:53:32 PM PDT 24
Peak memory 214964 kb
Host smart-59969695-40dc-4af7-9289-3f5f969ec14e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664357594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1664357594
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3803894195
Short name T78
Test name
Test status
Simulation time 79481295 ps
CPU time 1.37 seconds
Started Jun 06 01:53:16 PM PDT 24
Finished Jun 06 01:53:19 PM PDT 24
Peak memory 206776 kb
Host smart-3300b270-64c9-463f-afb3-1d06489b858f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803894195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3803894195
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2692998520
Short name T147
Test name
Test status
Simulation time 60215151 ps
CPU time 1.74 seconds
Started Jun 06 01:53:14 PM PDT 24
Finished Jun 06 01:53:17 PM PDT 24
Peak memory 215240 kb
Host smart-b9072744-ab2e-4c1f-afff-e0a505f726db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692998520 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2692998520
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1149437837
Short name T1071
Test name
Test status
Simulation time 20717112 ps
CPU time 1.26 seconds
Started Jun 06 01:53:15 PM PDT 24
Finished Jun 06 01:53:18 PM PDT 24
Peak memory 215048 kb
Host smart-0a5d1013-cf01-44f2-9b61-855d541bca15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149437837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
149437837
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2872058177
Short name T965
Test name
Test status
Simulation time 53669590 ps
CPU time 0.72 seconds
Started Jun 06 01:53:17 PM PDT 24
Finished Jun 06 01:53:20 PM PDT 24
Peak memory 203848 kb
Host smart-2e36c963-2d8f-401e-990e-c397b3c16332
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872058177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
872058177
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2629375342
Short name T1026
Test name
Test status
Simulation time 120442453 ps
CPU time 2.14 seconds
Started Jun 06 01:53:13 PM PDT 24
Finished Jun 06 01:53:17 PM PDT 24
Peak memory 215188 kb
Host smart-8fc4d905-7f9c-48b5-9cd1-946cbbf8f401
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629375342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2629375342
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4091611058
Short name T1006
Test name
Test status
Simulation time 12923799 ps
CPU time 0.66 seconds
Started Jun 06 01:53:22 PM PDT 24
Finished Jun 06 01:53:24 PM PDT 24
Peak memory 203428 kb
Host smart-a104a5ee-f516-4d74-9acb-c5964c22209d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091611058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4091611058
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3111529105
Short name T1031
Test name
Test status
Simulation time 105730719 ps
CPU time 2.98 seconds
Started Jun 06 01:53:16 PM PDT 24
Finished Jun 06 01:53:20 PM PDT 24
Peak memory 215072 kb
Host smart-f271a15a-ebdd-4d0e-85de-abffb7741ad8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111529105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3111529105
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.707580788
Short name T1056
Test name
Test status
Simulation time 39825039 ps
CPU time 1.32 seconds
Started Jun 06 01:53:16 PM PDT 24
Finished Jun 06 01:53:19 PM PDT 24
Peak memory 215224 kb
Host smart-81c949cf-04e2-4ffa-b714-f87741275d5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707580788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.707580788
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.740134702
Short name T1028
Test name
Test status
Simulation time 73391341 ps
CPU time 2 seconds
Started Jun 06 01:53:41 PM PDT 24
Finished Jun 06 01:53:44 PM PDT 24
Peak memory 215200 kb
Host smart-b2d42c4f-9d9b-449f-8538-d13dc2efcd96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740134702 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.740134702
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2782205909
Short name T119
Test name
Test status
Simulation time 72265199 ps
CPU time 2.22 seconds
Started Jun 06 01:53:38 PM PDT 24
Finished Jun 06 01:53:41 PM PDT 24
Peak memory 215000 kb
Host smart-6eae91d3-e6a9-4100-9cb7-6273ef751c7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782205909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2782205909
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3593462042
Short name T970
Test name
Test status
Simulation time 82324600 ps
CPU time 0.74 seconds
Started Jun 06 01:53:36 PM PDT 24
Finished Jun 06 01:53:38 PM PDT 24
Peak memory 203568 kb
Host smart-8b2e3673-8e5a-40a3-840f-2810e8897c0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593462042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3593462042
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1639385925
Short name T1075
Test name
Test status
Simulation time 199799534 ps
CPU time 4.19 seconds
Started Jun 06 01:53:41 PM PDT 24
Finished Jun 06 01:53:46 PM PDT 24
Peak memory 215108 kb
Host smart-2f962bba-78c8-4d0e-8fbb-d7d30d4b54cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639385925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1639385925
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1231383521
Short name T279
Test name
Test status
Simulation time 547188003 ps
CPU time 15.18 seconds
Started Jun 06 01:53:37 PM PDT 24
Finished Jun 06 01:53:53 PM PDT 24
Peak memory 223328 kb
Host smart-b50bb589-cda7-4ef2-a980-c82a96ce841f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231383521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1231383521
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2172652762
Short name T60
Test name
Test status
Simulation time 80854957 ps
CPU time 1.79 seconds
Started Jun 06 01:53:40 PM PDT 24
Finished Jun 06 01:53:42 PM PDT 24
Peak memory 215232 kb
Host smart-283ccaab-81de-46c5-95dd-91b1a8c20379
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172652762 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2172652762
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.922779903
Short name T121
Test name
Test status
Simulation time 56111947 ps
CPU time 1.97 seconds
Started Jun 06 01:53:39 PM PDT 24
Finished Jun 06 01:53:42 PM PDT 24
Peak memory 215076 kb
Host smart-0c66d33f-18c6-455c-9c48-68b72085efe0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922779903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.922779903
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1181434200
Short name T1052
Test name
Test status
Simulation time 38544452 ps
CPU time 0.68 seconds
Started Jun 06 01:53:38 PM PDT 24
Finished Jun 06 01:53:39 PM PDT 24
Peak memory 203552 kb
Host smart-c65ef378-5853-4f6d-a887-15aaa5ac304f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181434200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1181434200
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3206483262
Short name T985
Test name
Test status
Simulation time 279151546 ps
CPU time 3.15 seconds
Started Jun 06 01:53:37 PM PDT 24
Finished Jun 06 01:53:41 PM PDT 24
Peak memory 215084 kb
Host smart-84c3cf4e-b9d5-4557-9534-72572e13c121
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206483262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3206483262
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1429304286
Short name T1024
Test name
Test status
Simulation time 270862331 ps
CPU time 1.85 seconds
Started Jun 06 01:53:36 PM PDT 24
Finished Jun 06 01:53:38 PM PDT 24
Peak memory 215412 kb
Host smart-55cb22e8-11d0-4e09-9c59-acfce6d52731
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429304286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1429304286
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.653455937
Short name T280
Test name
Test status
Simulation time 2188368324 ps
CPU time 7.51 seconds
Started Jun 06 01:53:37 PM PDT 24
Finished Jun 06 01:53:45 PM PDT 24
Peak memory 215380 kb
Host smart-d909635c-9ce7-4c07-9a78-70cb5d6ce95f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653455937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.653455937
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3071820763
Short name T1002
Test name
Test status
Simulation time 1661111696 ps
CPU time 3.76 seconds
Started Jun 06 01:53:36 PM PDT 24
Finished Jun 06 01:53:40 PM PDT 24
Peak memory 217248 kb
Host smart-501e493e-9a5b-4e84-aff6-37135ff2cb00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071820763 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3071820763
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4144144656
Short name T127
Test name
Test status
Simulation time 1622816769 ps
CPU time 2.72 seconds
Started Jun 06 01:53:41 PM PDT 24
Finished Jun 06 01:53:44 PM PDT 24
Peak memory 215028 kb
Host smart-4e01d441-c9d7-48b8-b417-564074680040
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144144656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4144144656
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1062387066
Short name T1014
Test name
Test status
Simulation time 11925101 ps
CPU time 0.76 seconds
Started Jun 06 01:53:39 PM PDT 24
Finished Jun 06 01:53:40 PM PDT 24
Peak memory 203868 kb
Host smart-72ad5df8-8985-48bb-8196-528cd529b961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062387066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1062387066
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.198844496
Short name T1073
Test name
Test status
Simulation time 26918824 ps
CPU time 1.83 seconds
Started Jun 06 01:53:50 PM PDT 24
Finished Jun 06 01:53:53 PM PDT 24
Peak memory 206888 kb
Host smart-f1261d31-1842-42d7-a56a-7400f55176a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198844496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.198844496
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.879579136
Short name T1034
Test name
Test status
Simulation time 41617714 ps
CPU time 1.67 seconds
Started Jun 06 01:53:40 PM PDT 24
Finished Jun 06 01:53:42 PM PDT 24
Peak memory 215392 kb
Host smart-ee45b84b-b955-4d2e-9ce8-a81f861211cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879579136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.879579136
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.802394773
Short name T107
Test name
Test status
Simulation time 55161262 ps
CPU time 1.61 seconds
Started Jun 06 01:53:37 PM PDT 24
Finished Jun 06 01:53:40 PM PDT 24
Peak memory 215208 kb
Host smart-c8fafd10-7ff9-4c13-8239-4526c7e3669f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802394773 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.802394773
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.61888229
Short name T973
Test name
Test status
Simulation time 113033658 ps
CPU time 2.06 seconds
Started Jun 06 01:53:37 PM PDT 24
Finished Jun 06 01:53:40 PM PDT 24
Peak memory 214984 kb
Host smart-f51329df-447c-4a42-9f98-cecb6a4eba25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61888229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.61888229
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.412916150
Short name T996
Test name
Test status
Simulation time 194395119 ps
CPU time 0.76 seconds
Started Jun 06 01:53:38 PM PDT 24
Finished Jun 06 01:53:39 PM PDT 24
Peak memory 203908 kb
Host smart-e68ce09f-6238-4803-b8b3-23ac5d82b95d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412916150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.412916150
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1477088063
Short name T1053
Test name
Test status
Simulation time 30135498 ps
CPU time 1.94 seconds
Started Jun 06 01:53:38 PM PDT 24
Finished Jun 06 01:53:41 PM PDT 24
Peak memory 215104 kb
Host smart-11c5af9e-5e23-4dbd-a1a1-63beff109fb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477088063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1477088063
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.629791231
Short name T99
Test name
Test status
Simulation time 166594238 ps
CPU time 2.24 seconds
Started Jun 06 01:53:37 PM PDT 24
Finished Jun 06 01:53:41 PM PDT 24
Peak memory 216200 kb
Host smart-3a740051-56c9-4a42-9d22-fed464a73a91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629791231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.629791231
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3019913618
Short name T92
Test name
Test status
Simulation time 849881437 ps
CPU time 20.33 seconds
Started Jun 06 01:53:39 PM PDT 24
Finished Jun 06 01:54:00 PM PDT 24
Peak memory 215248 kb
Host smart-87322ed7-799a-4493-9a9f-0e43e75e25d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019913618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3019913618
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.782094157
Short name T148
Test name
Test status
Simulation time 77237737 ps
CPU time 1.79 seconds
Started Jun 06 01:53:50 PM PDT 24
Finished Jun 06 01:53:52 PM PDT 24
Peak memory 216280 kb
Host smart-f189450e-7565-4871-a699-ac13b94b20ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782094157 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.782094157
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2123750965
Short name T1023
Test name
Test status
Simulation time 139559815 ps
CPU time 2.58 seconds
Started Jun 06 01:53:38 PM PDT 24
Finished Jun 06 01:53:41 PM PDT 24
Peak memory 215092 kb
Host smart-c1f015ca-9842-4e7f-abb3-85da6a5f450f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123750965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2123750965
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1989643506
Short name T974
Test name
Test status
Simulation time 13082524 ps
CPU time 0.7 seconds
Started Jun 06 01:53:41 PM PDT 24
Finished Jun 06 01:53:42 PM PDT 24
Peak memory 203572 kb
Host smart-eb118537-222f-455a-99a4-d6893b2b9a13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989643506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1989643506
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.99271474
Short name T144
Test name
Test status
Simulation time 609168807 ps
CPU time 3.56 seconds
Started Jun 06 01:53:48 PM PDT 24
Finished Jun 06 01:53:53 PM PDT 24
Peak memory 215088 kb
Host smart-166a534b-c23b-4a1b-bbc7-4c756e7ba308
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99271474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sp
i_device_same_csr_outstanding.99271474
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3655031122
Short name T109
Test name
Test status
Simulation time 535178463 ps
CPU time 14.88 seconds
Started Jun 06 01:53:41 PM PDT 24
Finished Jun 06 01:53:57 PM PDT 24
Peak memory 215880 kb
Host smart-c7d1a639-6364-4b29-96dd-b1afa39b31fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655031122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3655031122
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.498258693
Short name T1019
Test name
Test status
Simulation time 104958871 ps
CPU time 1.9 seconds
Started Jun 06 01:53:47 PM PDT 24
Finished Jun 06 01:53:50 PM PDT 24
Peak memory 206904 kb
Host smart-6a706b48-ef7f-4e0c-bbd4-b038dcff5097
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498258693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.498258693
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3611092080
Short name T1038
Test name
Test status
Simulation time 42088072 ps
CPU time 0.7 seconds
Started Jun 06 01:53:50 PM PDT 24
Finished Jun 06 01:53:52 PM PDT 24
Peak memory 203608 kb
Host smart-00a682bf-7eb3-4e67-94ea-8cf173977fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611092080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3611092080
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4187025186
Short name T979
Test name
Test status
Simulation time 378804970 ps
CPU time 2.88 seconds
Started Jun 06 01:53:48 PM PDT 24
Finished Jun 06 01:53:52 PM PDT 24
Peak memory 215120 kb
Host smart-530fd570-a71c-43b0-b8b9-80eb11fb95f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187025186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4187025186
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1417174208
Short name T1045
Test name
Test status
Simulation time 224640651 ps
CPU time 1.83 seconds
Started Jun 06 01:53:47 PM PDT 24
Finished Jun 06 01:53:50 PM PDT 24
Peak memory 215252 kb
Host smart-a58d018d-ffc0-4a3d-9bbe-5d652e3e18a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417174208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1417174208
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3259330670
Short name T1050
Test name
Test status
Simulation time 115019456 ps
CPU time 6.68 seconds
Started Jun 06 01:53:45 PM PDT 24
Finished Jun 06 01:53:52 PM PDT 24
Peak memory 215016 kb
Host smart-f2618015-41cb-4059-a5c1-788b1bac8c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259330670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3259330670
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3596044537
Short name T1043
Test name
Test status
Simulation time 564575309 ps
CPU time 3.65 seconds
Started Jun 06 01:53:49 PM PDT 24
Finished Jun 06 01:53:53 PM PDT 24
Peak memory 216928 kb
Host smart-5a7f4d8d-1f38-48f1-a87d-d81040cec809
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596044537 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3596044537
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3547198447
Short name T113
Test name
Test status
Simulation time 26849853 ps
CPU time 1.81 seconds
Started Jun 06 01:53:48 PM PDT 24
Finished Jun 06 01:53:51 PM PDT 24
Peak memory 214976 kb
Host smart-5165ebcd-0429-412d-a1a9-0b588e32cd1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547198447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3547198447
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3192415672
Short name T1032
Test name
Test status
Simulation time 15722626 ps
CPU time 0.74 seconds
Started Jun 06 01:53:46 PM PDT 24
Finished Jun 06 01:53:48 PM PDT 24
Peak memory 203880 kb
Host smart-acc1a0fd-b161-496d-9a30-cf579852aa2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192415672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3192415672
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1189784216
Short name T1069
Test name
Test status
Simulation time 34566929 ps
CPU time 1.96 seconds
Started Jun 06 01:53:47 PM PDT 24
Finished Jun 06 01:53:51 PM PDT 24
Peak memory 206776 kb
Host smart-92810244-c272-42c1-9c7d-9747d6821336
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189784216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1189784216
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3685226312
Short name T1008
Test name
Test status
Simulation time 1644583553 ps
CPU time 4.59 seconds
Started Jun 06 01:53:46 PM PDT 24
Finished Jun 06 01:53:52 PM PDT 24
Peak memory 215108 kb
Host smart-4419b48e-bb40-4f94-b307-1810ce6ea553
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685226312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3685226312
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1089520573
Short name T1076
Test name
Test status
Simulation time 39544024 ps
CPU time 2.7 seconds
Started Jun 06 01:53:51 PM PDT 24
Finished Jun 06 01:53:55 PM PDT 24
Peak memory 216952 kb
Host smart-4c0a72cc-ff46-418f-ab05-907443078454
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089520573 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1089520573
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3678271385
Short name T115
Test name
Test status
Simulation time 437215202 ps
CPU time 2.82 seconds
Started Jun 06 01:53:47 PM PDT 24
Finished Jun 06 01:53:51 PM PDT 24
Peak memory 215052 kb
Host smart-902f6797-5b20-4d45-96d9-a7fe3c6f00f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678271385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3678271385
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.576422521
Short name T983
Test name
Test status
Simulation time 51185807 ps
CPU time 0.74 seconds
Started Jun 06 01:53:48 PM PDT 24
Finished Jun 06 01:53:50 PM PDT 24
Peak memory 203600 kb
Host smart-c82a88bb-2b4c-41b2-a4ec-d0647d5a8dfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576422521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.576422521
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2592112058
Short name T1027
Test name
Test status
Simulation time 132777702 ps
CPU time 3.14 seconds
Started Jun 06 01:53:48 PM PDT 24
Finished Jun 06 01:53:52 PM PDT 24
Peak memory 215116 kb
Host smart-44ea5c87-41d9-42bc-847d-85da0c8fdcf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592112058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2592112058
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3613928250
Short name T999
Test name
Test status
Simulation time 68221981 ps
CPU time 2.16 seconds
Started Jun 06 01:53:48 PM PDT 24
Finished Jun 06 01:53:51 PM PDT 24
Peak memory 216236 kb
Host smart-0fdfda51-777d-4bd8-888a-a6e9ab96fb8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613928250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3613928250
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2942092692
Short name T984
Test name
Test status
Simulation time 212706502 ps
CPU time 12.88 seconds
Started Jun 06 01:53:48 PM PDT 24
Finished Jun 06 01:54:02 PM PDT 24
Peak memory 215604 kb
Host smart-f32096f9-07c9-4e80-b868-aea044e05c78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942092692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2942092692
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3634452594
Short name T1000
Test name
Test status
Simulation time 400748980 ps
CPU time 2.69 seconds
Started Jun 06 01:53:49 PM PDT 24
Finished Jun 06 01:53:52 PM PDT 24
Peak memory 216640 kb
Host smart-3e7ad49b-9d1a-42a1-97d4-2be5e166c64f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634452594 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3634452594
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1435389411
Short name T1065
Test name
Test status
Simulation time 704583753 ps
CPU time 1.34 seconds
Started Jun 06 01:53:55 PM PDT 24
Finished Jun 06 01:53:57 PM PDT 24
Peak memory 206828 kb
Host smart-d442e20e-8464-49d2-aa65-aa350f40eb39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435389411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1435389411
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2058487875
Short name T1042
Test name
Test status
Simulation time 52890666 ps
CPU time 0.74 seconds
Started Jun 06 01:53:46 PM PDT 24
Finished Jun 06 01:53:48 PM PDT 24
Peak memory 203556 kb
Host smart-f0fabc7b-e2f5-413a-8185-e017a7d0ccca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058487875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2058487875
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2169400188
Short name T990
Test name
Test status
Simulation time 62223507 ps
CPU time 1.85 seconds
Started Jun 06 01:53:50 PM PDT 24
Finished Jun 06 01:53:54 PM PDT 24
Peak memory 215108 kb
Host smart-ed87fec5-9265-4585-ada0-e7661dac00c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169400188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2169400188
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1647089494
Short name T91
Test name
Test status
Simulation time 104236373 ps
CPU time 2.73 seconds
Started Jun 06 01:53:46 PM PDT 24
Finished Jun 06 01:53:50 PM PDT 24
Peak memory 216220 kb
Host smart-57b6f858-9f3f-4376-9f5b-9aed200672d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647089494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1647089494
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2298156097
Short name T1066
Test name
Test status
Simulation time 3919361557 ps
CPU time 22.28 seconds
Started Jun 06 01:53:46 PM PDT 24
Finished Jun 06 01:54:09 PM PDT 24
Peak memory 215232 kb
Host smart-d0c7fa8a-4af2-4cfd-9783-2204a4b424ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298156097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2298156097
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.192080990
Short name T1007
Test name
Test status
Simulation time 60907975 ps
CPU time 4.13 seconds
Started Jun 06 01:53:50 PM PDT 24
Finished Jun 06 01:53:56 PM PDT 24
Peak memory 217388 kb
Host smart-2234facb-56a7-4dcc-8681-534c907ed5d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192080990 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.192080990
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.382108436
Short name T135
Test name
Test status
Simulation time 92656956 ps
CPU time 2.53 seconds
Started Jun 06 01:53:49 PM PDT 24
Finished Jun 06 01:53:52 PM PDT 24
Peak memory 215088 kb
Host smart-80c32602-12fa-45de-83fc-097ca53797e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382108436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.382108436
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1645129669
Short name T993
Test name
Test status
Simulation time 37706196 ps
CPU time 0.72 seconds
Started Jun 06 01:53:49 PM PDT 24
Finished Jun 06 01:53:50 PM PDT 24
Peak memory 203920 kb
Host smart-d8aecb33-46cb-497d-8713-f70c1167994e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645129669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1645129669
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1886944607
Short name T1060
Test name
Test status
Simulation time 216288593 ps
CPU time 3.92 seconds
Started Jun 06 01:53:52 PM PDT 24
Finished Jun 06 01:53:57 PM PDT 24
Peak memory 215096 kb
Host smart-1bdab2da-5777-407a-83c6-e40af3ac649a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886944607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1886944607
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2799146063
Short name T1068
Test name
Test status
Simulation time 437888546 ps
CPU time 3.83 seconds
Started Jun 06 01:53:46 PM PDT 24
Finished Jun 06 01:53:51 PM PDT 24
Peak memory 215156 kb
Host smart-89107ab7-8442-478d-8ed2-3a4507629a47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799146063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2799146063
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3630456139
Short name T94
Test name
Test status
Simulation time 568603353 ps
CPU time 14.03 seconds
Started Jun 06 01:53:50 PM PDT 24
Finished Jun 06 01:54:06 PM PDT 24
Peak memory 215172 kb
Host smart-681dc2c4-43f2-4554-ab3c-7d002721849a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630456139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3630456139
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1103815960
Short name T1079
Test name
Test status
Simulation time 1277059123 ps
CPU time 25.79 seconds
Started Jun 06 01:53:18 PM PDT 24
Finished Jun 06 01:53:45 PM PDT 24
Peak memory 206824 kb
Host smart-cccc807c-6212-41ed-b63c-5c2ceb6bc1d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103815960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1103815960
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1682899736
Short name T1059
Test name
Test status
Simulation time 1841264011 ps
CPU time 35.81 seconds
Started Jun 06 01:53:24 PM PDT 24
Finished Jun 06 01:54:01 PM PDT 24
Peak memory 206896 kb
Host smart-7f5ce051-0338-4dee-85cd-6993ca9a247f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682899736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1682899736
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2944402861
Short name T1077
Test name
Test status
Simulation time 77402378 ps
CPU time 1.36 seconds
Started Jun 06 01:53:14 PM PDT 24
Finished Jun 06 01:53:17 PM PDT 24
Peak memory 206784 kb
Host smart-fd66fd0e-c104-4ffc-9976-acf35286a71d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944402861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2944402861
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3411303556
Short name T1048
Test name
Test status
Simulation time 163901606 ps
CPU time 1.83 seconds
Started Jun 06 01:53:24 PM PDT 24
Finished Jun 06 01:53:27 PM PDT 24
Peak memory 216232 kb
Host smart-87cd4331-a923-4bb5-b207-4735409998ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411303556 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3411303556
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3899953888
Short name T120
Test name
Test status
Simulation time 42925998 ps
CPU time 1.43 seconds
Started Jun 06 01:53:20 PM PDT 24
Finished Jun 06 01:53:23 PM PDT 24
Peak memory 206884 kb
Host smart-da2b5e5d-1191-42ba-9e3a-5aa530779179
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899953888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
899953888
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3779789501
Short name T1046
Test name
Test status
Simulation time 21744156 ps
CPU time 0.73 seconds
Started Jun 06 01:53:16 PM PDT 24
Finished Jun 06 01:53:18 PM PDT 24
Peak memory 203600 kb
Host smart-3350fc09-6d22-4224-9a67-df91db3153ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779789501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
779789501
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3476075564
Short name T116
Test name
Test status
Simulation time 213570838 ps
CPU time 2.01 seconds
Started Jun 06 01:53:11 PM PDT 24
Finished Jun 06 01:53:14 PM PDT 24
Peak memory 215232 kb
Host smart-3a70a456-58a3-4ab6-b8b0-88592415ef46
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476075564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3476075564
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1410675328
Short name T1074
Test name
Test status
Simulation time 13768924 ps
CPU time 0.65 seconds
Started Jun 06 01:53:14 PM PDT 24
Finished Jun 06 01:53:16 PM PDT 24
Peak memory 203492 kb
Host smart-1573f05b-d376-49eb-913c-611c56db0803
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410675328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1410675328
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3260582742
Short name T987
Test name
Test status
Simulation time 439206668 ps
CPU time 3.64 seconds
Started Jun 06 01:53:18 PM PDT 24
Finished Jun 06 01:53:24 PM PDT 24
Peak memory 215124 kb
Host smart-794a1546-e96b-4ad8-98d5-83736914167c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260582742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3260582742
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.504523073
Short name T102
Test name
Test status
Simulation time 281735237 ps
CPU time 2.35 seconds
Started Jun 06 01:53:14 PM PDT 24
Finished Jun 06 01:53:18 PM PDT 24
Peak memory 215340 kb
Host smart-03a87d87-332b-47a6-ae6e-d44ed5f8ff21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504523073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.504523073
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3320288787
Short name T277
Test name
Test status
Simulation time 567343816 ps
CPU time 14.77 seconds
Started Jun 06 01:53:20 PM PDT 24
Finished Jun 06 01:53:36 PM PDT 24
Peak memory 215152 kb
Host smart-45de8d11-507c-4513-9891-599e83f8371c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320288787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3320288787
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2475195633
Short name T1064
Test name
Test status
Simulation time 16751931 ps
CPU time 0.77 seconds
Started Jun 06 01:53:49 PM PDT 24
Finished Jun 06 01:53:51 PM PDT 24
Peak memory 203560 kb
Host smart-95ed45a3-7f6a-434a-b73e-711ae164b391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475195633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2475195633
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2803821691
Short name T977
Test name
Test status
Simulation time 28802691 ps
CPU time 0.68 seconds
Started Jun 06 01:53:51 PM PDT 24
Finished Jun 06 01:53:53 PM PDT 24
Peak memory 203576 kb
Host smart-3181cfa0-3f78-441b-8b93-cde38435a133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803821691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2803821691
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2602913869
Short name T998
Test name
Test status
Simulation time 10840241 ps
CPU time 0.72 seconds
Started Jun 06 01:53:50 PM PDT 24
Finished Jun 06 01:53:52 PM PDT 24
Peak memory 203608 kb
Host smart-c939f563-80b8-4d83-8a5d-af0e907308ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602913869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2602913869
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.860967401
Short name T1040
Test name
Test status
Simulation time 16722988 ps
CPU time 0.74 seconds
Started Jun 06 01:53:48 PM PDT 24
Finished Jun 06 01:53:50 PM PDT 24
Peak memory 203812 kb
Host smart-de60892f-1950-4e58-9467-10cea6682116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860967401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.860967401
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1403741148
Short name T975
Test name
Test status
Simulation time 12915576 ps
CPU time 0.76 seconds
Started Jun 06 01:53:47 PM PDT 24
Finished Jun 06 01:53:49 PM PDT 24
Peak memory 203556 kb
Host smart-eff0acc2-4cea-421f-af20-02d554344b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403741148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1403741148
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1353824603
Short name T1051
Test name
Test status
Simulation time 13115275 ps
CPU time 0.66 seconds
Started Jun 06 01:53:45 PM PDT 24
Finished Jun 06 01:53:47 PM PDT 24
Peak memory 203912 kb
Host smart-ed6a26f1-e0b8-4be5-b17a-679e0d38b414
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353824603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1353824603
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4092139051
Short name T1063
Test name
Test status
Simulation time 14142703 ps
CPU time 0.73 seconds
Started Jun 06 01:53:50 PM PDT 24
Finished Jun 06 01:53:52 PM PDT 24
Peak memory 203528 kb
Host smart-20c3103d-a450-4933-b0b3-e0b7b3ce805d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092139051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
4092139051
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2200779654
Short name T964
Test name
Test status
Simulation time 16311863 ps
CPU time 0.72 seconds
Started Jun 06 01:53:50 PM PDT 24
Finished Jun 06 01:53:52 PM PDT 24
Peak memory 203532 kb
Host smart-a8394a17-15c8-4108-8b88-0c5a17af1456
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200779654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2200779654
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2456029518
Short name T982
Test name
Test status
Simulation time 12479072 ps
CPU time 0.72 seconds
Started Jun 06 01:53:51 PM PDT 24
Finished Jun 06 01:53:53 PM PDT 24
Peak memory 203608 kb
Host smart-058908e2-98e8-400a-9442-d02aed8da0e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456029518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2456029518
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2070683372
Short name T981
Test name
Test status
Simulation time 23794043 ps
CPU time 0.79 seconds
Started Jun 06 01:53:54 PM PDT 24
Finished Jun 06 01:53:55 PM PDT 24
Peak memory 203512 kb
Host smart-ec40aa38-1f1a-4516-afbe-a07b9e06e9ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070683372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2070683372
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2092104914
Short name T1057
Test name
Test status
Simulation time 922329983 ps
CPU time 7.36 seconds
Started Jun 06 01:53:24 PM PDT 24
Finished Jun 06 01:53:32 PM PDT 24
Peak memory 206704 kb
Host smart-8dd6b187-d823-47ca-aa43-4c4c652ddf6a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092104914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2092104914
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.394990589
Short name T126
Test name
Test status
Simulation time 374374442 ps
CPU time 23.45 seconds
Started Jun 06 01:53:24 PM PDT 24
Finished Jun 06 01:53:49 PM PDT 24
Peak memory 206656 kb
Host smart-b3cc3f10-c17e-4840-9025-339089727af4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394990589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.394990589
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1023138950
Short name T1070
Test name
Test status
Simulation time 199845340 ps
CPU time 3.75 seconds
Started Jun 06 01:53:22 PM PDT 24
Finished Jun 06 01:53:28 PM PDT 24
Peak memory 216780 kb
Host smart-8290565b-c94b-45c7-aaa1-fcdc2a1109dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023138950 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1023138950
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3485857067
Short name T112
Test name
Test status
Simulation time 149546196 ps
CPU time 2.65 seconds
Started Jun 06 01:53:24 PM PDT 24
Finished Jun 06 01:53:28 PM PDT 24
Peak memory 215024 kb
Host smart-6045d93b-1168-4130-a862-3b13c810ada9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485857067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
485857067
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3226540790
Short name T1005
Test name
Test status
Simulation time 59758358 ps
CPU time 0.78 seconds
Started Jun 06 01:53:17 PM PDT 24
Finished Jun 06 01:53:20 PM PDT 24
Peak memory 203768 kb
Host smart-8431f69e-33d7-49e7-9db5-b2821644431f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226540790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
226540790
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4066373166
Short name T125
Test name
Test status
Simulation time 124782397 ps
CPU time 1.27 seconds
Started Jun 06 01:53:22 PM PDT 24
Finished Jun 06 01:53:24 PM PDT 24
Peak memory 215180 kb
Host smart-1d306653-ce4a-4175-ae9c-929467cc5938
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066373166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4066373166
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2901436272
Short name T1039
Test name
Test status
Simulation time 12163522 ps
CPU time 0.67 seconds
Started Jun 06 01:53:23 PM PDT 24
Finished Jun 06 01:53:25 PM PDT 24
Peak memory 203408 kb
Host smart-880f7ed5-a072-44ac-95a4-9aeb1940cd06
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901436272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2901436272
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3227651590
Short name T1018
Test name
Test status
Simulation time 287944599 ps
CPU time 4.82 seconds
Started Jun 06 01:53:25 PM PDT 24
Finished Jun 06 01:53:31 PM PDT 24
Peak memory 215140 kb
Host smart-6a37cf44-16dc-4c2d-bc14-a14df984b4c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227651590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3227651590
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1711931561
Short name T98
Test name
Test status
Simulation time 88887218 ps
CPU time 3.95 seconds
Started Jun 06 01:53:23 PM PDT 24
Finished Jun 06 01:53:29 PM PDT 24
Peak memory 215180 kb
Host smart-a5f0ce60-b952-488f-834c-2479bb7619cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711931561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
711931561
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3720798776
Short name T995
Test name
Test status
Simulation time 727784124 ps
CPU time 8.11 seconds
Started Jun 06 01:53:21 PM PDT 24
Finished Jun 06 01:53:31 PM PDT 24
Peak memory 215140 kb
Host smart-5125c4a2-5b1c-4d2c-bd59-762fe0469bcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720798776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3720798776
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1579805304
Short name T1009
Test name
Test status
Simulation time 15177936 ps
CPU time 0.78 seconds
Started Jun 06 01:53:54 PM PDT 24
Finished Jun 06 01:53:55 PM PDT 24
Peak memory 203512 kb
Host smart-7c23b2ca-89ff-4796-a4f8-1fdf932cab86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579805304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1579805304
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3575964047
Short name T1078
Test name
Test status
Simulation time 63952475 ps
CPU time 0.73 seconds
Started Jun 06 01:53:51 PM PDT 24
Finished Jun 06 01:53:53 PM PDT 24
Peak memory 203584 kb
Host smart-08c285a2-506b-4b20-8126-6de7cd4641d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575964047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3575964047
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2567561399
Short name T980
Test name
Test status
Simulation time 21597272 ps
CPU time 0.79 seconds
Started Jun 06 01:54:02 PM PDT 24
Finished Jun 06 01:54:04 PM PDT 24
Peak memory 203568 kb
Host smart-b28a3414-d18a-43ca-bbf4-99c4b29c4f75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567561399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2567561399
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2486943599
Short name T966
Test name
Test status
Simulation time 20850715 ps
CPU time 0.78 seconds
Started Jun 06 01:53:57 PM PDT 24
Finished Jun 06 01:53:59 PM PDT 24
Peak memory 203556 kb
Host smart-a2d303e7-07b2-45b1-accb-839d0d2fcf5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486943599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2486943599
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1620346176
Short name T968
Test name
Test status
Simulation time 45853575 ps
CPU time 0.75 seconds
Started Jun 06 01:53:56 PM PDT 24
Finished Jun 06 01:53:58 PM PDT 24
Peak memory 203624 kb
Host smart-2cacff6f-fa06-4fe3-8d0a-bd0d58f62f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620346176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1620346176
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3396729934
Short name T1047
Test name
Test status
Simulation time 13731180 ps
CPU time 0.81 seconds
Started Jun 06 01:53:55 PM PDT 24
Finished Jun 06 01:53:57 PM PDT 24
Peak memory 203912 kb
Host smart-ceeaf7d2-6d9f-4297-9f88-cfea274918a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396729934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3396729934
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1508817133
Short name T963
Test name
Test status
Simulation time 18767004 ps
CPU time 0.71 seconds
Started Jun 06 01:53:55 PM PDT 24
Finished Jun 06 01:53:56 PM PDT 24
Peak memory 203588 kb
Host smart-a08695ec-6703-4ccc-a156-66c72f9b8c58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508817133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1508817133
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1957293501
Short name T971
Test name
Test status
Simulation time 37912064 ps
CPU time 0.72 seconds
Started Jun 06 01:53:52 PM PDT 24
Finished Jun 06 01:53:54 PM PDT 24
Peak memory 203844 kb
Host smart-c4e848b3-0d39-4e18-bd35-0a01513a2dd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957293501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1957293501
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.698255770
Short name T972
Test name
Test status
Simulation time 198343516 ps
CPU time 0.73 seconds
Started Jun 06 01:53:56 PM PDT 24
Finished Jun 06 01:53:57 PM PDT 24
Peak memory 203868 kb
Host smart-d2f90ef5-31c1-4385-8b28-1657d3768d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698255770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.698255770
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1029853058
Short name T1020
Test name
Test status
Simulation time 48573060 ps
CPU time 0.77 seconds
Started Jun 06 01:53:56 PM PDT 24
Finished Jun 06 01:53:59 PM PDT 24
Peak memory 203568 kb
Host smart-229eb6e5-9cb3-42bf-adf7-d17199b30974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029853058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1029853058
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4124064663
Short name T1067
Test name
Test status
Simulation time 817342225 ps
CPU time 14.91 seconds
Started Jun 06 01:53:24 PM PDT 24
Finished Jun 06 01:53:41 PM PDT 24
Peak memory 215044 kb
Host smart-0345d8c0-0e39-484c-ba49-d95ac4cb0bd9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124064663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4124064663
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2978843565
Short name T961
Test name
Test status
Simulation time 823678379 ps
CPU time 12.43 seconds
Started Jun 06 01:53:18 PM PDT 24
Finished Jun 06 01:53:32 PM PDT 24
Peak memory 206784 kb
Host smart-dee9f6b5-634a-49d2-b41e-9c733e9e5d51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978843565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2978843565
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1189803186
Short name T77
Test name
Test status
Simulation time 51688842 ps
CPU time 1.21 seconds
Started Jun 06 01:53:21 PM PDT 24
Finished Jun 06 01:53:23 PM PDT 24
Peak memory 206776 kb
Host smart-cc0891be-cebd-4ca6-bd0c-c7ed03523e71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189803186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1189803186
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1567803217
Short name T108
Test name
Test status
Simulation time 339312352 ps
CPU time 2.69 seconds
Started Jun 06 01:53:25 PM PDT 24
Finished Jun 06 01:53:29 PM PDT 24
Peak memory 216340 kb
Host smart-2463473b-6162-48ca-94bf-9b74ca2f98d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567803217 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1567803217
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2743205503
Short name T124
Test name
Test status
Simulation time 32138323 ps
CPU time 1.11 seconds
Started Jun 06 01:53:17 PM PDT 24
Finished Jun 06 01:53:19 PM PDT 24
Peak memory 206852 kb
Host smart-37e49e68-1a83-4bca-8d2b-c9ace28579a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743205503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
743205503
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.117324848
Short name T1058
Test name
Test status
Simulation time 13150089 ps
CPU time 0.73 seconds
Started Jun 06 01:53:24 PM PDT 24
Finished Jun 06 01:53:25 PM PDT 24
Peak memory 203504 kb
Host smart-2538e369-d7ac-48b1-932c-12508d75e8e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117324848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.117324848
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.555644740
Short name T1037
Test name
Test status
Simulation time 59066631 ps
CPU time 2.28 seconds
Started Jun 06 01:53:20 PM PDT 24
Finished Jun 06 01:53:24 PM PDT 24
Peak memory 215152 kb
Host smart-5f020253-698d-44b3-a5e4-2644bfad0f2b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555644740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.555644740
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3834595679
Short name T997
Test name
Test status
Simulation time 40137088 ps
CPU time 0.71 seconds
Started Jun 06 01:53:24 PM PDT 24
Finished Jun 06 01:53:25 PM PDT 24
Peak memory 203468 kb
Host smart-2095ce93-ac24-47db-8811-7db89c937b83
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834595679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3834595679
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2296919323
Short name T1013
Test name
Test status
Simulation time 3581691679 ps
CPU time 4.09 seconds
Started Jun 06 01:53:18 PM PDT 24
Finished Jun 06 01:53:24 PM PDT 24
Peak memory 215196 kb
Host smart-e942afce-2198-4b58-a340-62f25063273c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296919323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2296919323
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2858458917
Short name T1004
Test name
Test status
Simulation time 402170825 ps
CPU time 2.79 seconds
Started Jun 06 01:53:24 PM PDT 24
Finished Jun 06 01:53:28 PM PDT 24
Peak memory 215192 kb
Host smart-7c20b6e5-6b81-4ec3-8218-9b9312a8888f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858458917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
858458917
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2469699685
Short name T1001
Test name
Test status
Simulation time 109846315 ps
CPU time 7.11 seconds
Started Jun 06 01:53:24 PM PDT 24
Finished Jun 06 01:53:32 PM PDT 24
Peak memory 215056 kb
Host smart-139d867a-e9e1-4854-a97d-b6090af67d76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469699685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2469699685
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2463114669
Short name T1010
Test name
Test status
Simulation time 26529122 ps
CPU time 0.77 seconds
Started Jun 06 01:53:56 PM PDT 24
Finished Jun 06 01:53:57 PM PDT 24
Peak memory 203588 kb
Host smart-949f2e02-66bb-48cb-9b83-deab696d04bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463114669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2463114669
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3230504894
Short name T994
Test name
Test status
Simulation time 35220243 ps
CPU time 0.8 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:01 PM PDT 24
Peak memory 203576 kb
Host smart-b4cfcfda-e10b-4ab5-bf95-d98cee143254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230504894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3230504894
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2738545011
Short name T989
Test name
Test status
Simulation time 30183556 ps
CPU time 0.74 seconds
Started Jun 06 01:53:56 PM PDT 24
Finished Jun 06 01:53:58 PM PDT 24
Peak memory 203564 kb
Host smart-ea40006d-a98b-4424-a168-72dc9d3394c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738545011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2738545011
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4274388721
Short name T962
Test name
Test status
Simulation time 11693706 ps
CPU time 0.74 seconds
Started Jun 06 01:53:58 PM PDT 24
Finished Jun 06 01:54:01 PM PDT 24
Peak memory 203596 kb
Host smart-69613efe-a4ee-4390-b6c3-f31cda14b88f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274388721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4274388721
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2477461924
Short name T991
Test name
Test status
Simulation time 12996379 ps
CPU time 0.74 seconds
Started Jun 06 01:53:56 PM PDT 24
Finished Jun 06 01:53:58 PM PDT 24
Peak memory 203548 kb
Host smart-a81b2252-fee6-44b8-8923-1d9328637d74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477461924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2477461924
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1754974104
Short name T1030
Test name
Test status
Simulation time 13101831 ps
CPU time 0.7 seconds
Started Jun 06 01:53:56 PM PDT 24
Finished Jun 06 01:53:58 PM PDT 24
Peak memory 203564 kb
Host smart-11946083-069e-44a8-8405-689d8f75da87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754974104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1754974104
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2933326351
Short name T1061
Test name
Test status
Simulation time 35372676 ps
CPU time 0.72 seconds
Started Jun 06 01:54:02 PM PDT 24
Finished Jun 06 01:54:04 PM PDT 24
Peak memory 203576 kb
Host smart-d78b3b75-276b-49c6-b7f2-204417d586e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933326351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2933326351
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1068568888
Short name T1041
Test name
Test status
Simulation time 25769133 ps
CPU time 0.78 seconds
Started Jun 06 01:53:59 PM PDT 24
Finished Jun 06 01:54:01 PM PDT 24
Peak memory 203904 kb
Host smart-1e9a4e73-b1ff-48b0-8232-250f95df3e16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068568888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1068568888
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.258048842
Short name T992
Test name
Test status
Simulation time 24459127 ps
CPU time 0.73 seconds
Started Jun 06 01:53:56 PM PDT 24
Finished Jun 06 01:53:58 PM PDT 24
Peak memory 203560 kb
Host smart-cbaea1b2-1eb7-44a0-ae2d-5d016ca718d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258048842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.258048842
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1685920108
Short name T1035
Test name
Test status
Simulation time 35498798 ps
CPU time 0.78 seconds
Started Jun 06 01:53:55 PM PDT 24
Finished Jun 06 01:53:56 PM PDT 24
Peak memory 203576 kb
Host smart-b929471f-db0b-481d-8fe0-94ded4c70696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685920108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1685920108
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.667433618
Short name T106
Test name
Test status
Simulation time 106139260 ps
CPU time 2.99 seconds
Started Jun 06 01:53:28 PM PDT 24
Finished Jun 06 01:53:32 PM PDT 24
Peak memory 216512 kb
Host smart-f2b45c60-55ec-4a65-9597-fcc29266078e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667433618 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.667433618
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3137580636
Short name T1025
Test name
Test status
Simulation time 78752439 ps
CPU time 1.31 seconds
Started Jun 06 01:53:26 PM PDT 24
Finished Jun 06 01:53:28 PM PDT 24
Peak memory 206856 kb
Host smart-fd280df5-5248-4778-a69e-0c3b0a747a68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137580636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
137580636
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2254237495
Short name T978
Test name
Test status
Simulation time 44947812 ps
CPU time 0.74 seconds
Started Jun 06 01:53:20 PM PDT 24
Finished Jun 06 01:53:23 PM PDT 24
Peak memory 203904 kb
Host smart-5519aa8a-b105-4cb9-9666-5ddfa289fc3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254237495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
254237495
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.116780950
Short name T146
Test name
Test status
Simulation time 146219693 ps
CPU time 3 seconds
Started Jun 06 01:53:31 PM PDT 24
Finished Jun 06 01:53:35 PM PDT 24
Peak memory 215152 kb
Host smart-1d2c114c-f489-4a50-950f-ed554209bbb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116780950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.116780950
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.926066067
Short name T1015
Test name
Test status
Simulation time 81053923 ps
CPU time 2.32 seconds
Started Jun 06 01:53:22 PM PDT 24
Finished Jun 06 01:53:25 PM PDT 24
Peak memory 215216 kb
Host smart-9dee585d-f9da-4212-b932-57de267a262b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926066067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.926066067
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3159404968
Short name T276
Test name
Test status
Simulation time 767404828 ps
CPU time 16.21 seconds
Started Jun 06 01:53:24 PM PDT 24
Finished Jun 06 01:53:41 PM PDT 24
Peak memory 215040 kb
Host smart-b9480d89-6ea8-45c9-bfb7-996845b83dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159404968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3159404968
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1007591314
Short name T1033
Test name
Test status
Simulation time 60374135 ps
CPU time 1.74 seconds
Started Jun 06 01:53:29 PM PDT 24
Finished Jun 06 01:53:32 PM PDT 24
Peak memory 215228 kb
Host smart-7768d1ef-4336-460e-8f9c-4dae7da0552c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007591314 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1007591314
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1930477594
Short name T114
Test name
Test status
Simulation time 96275823 ps
CPU time 2.5 seconds
Started Jun 06 01:53:26 PM PDT 24
Finished Jun 06 01:53:29 PM PDT 24
Peak memory 215000 kb
Host smart-254250cd-f2c3-45df-8559-1feb5762abb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930477594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
930477594
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2934116165
Short name T969
Test name
Test status
Simulation time 43198449 ps
CPU time 0.73 seconds
Started Jun 06 01:53:30 PM PDT 24
Finished Jun 06 01:53:31 PM PDT 24
Peak memory 203920 kb
Host smart-4b62647b-071b-4e6f-81e7-68cdd073fc77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934116165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
934116165
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1962115602
Short name T1022
Test name
Test status
Simulation time 153017303 ps
CPU time 3.4 seconds
Started Jun 06 01:53:31 PM PDT 24
Finished Jun 06 01:53:35 PM PDT 24
Peak memory 215072 kb
Host smart-79cc197d-7a76-4643-b8aa-fe973d0cfa09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962115602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1962115602
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.255910329
Short name T1003
Test name
Test status
Simulation time 102729468 ps
CPU time 1.91 seconds
Started Jun 06 01:53:36 PM PDT 24
Finished Jun 06 01:53:39 PM PDT 24
Peak memory 215148 kb
Host smart-f98a5a5a-1a14-461c-9464-ccabbf18513a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255910329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.255910329
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1040737562
Short name T1062
Test name
Test status
Simulation time 410246099 ps
CPU time 11.97 seconds
Started Jun 06 01:53:28 PM PDT 24
Finished Jun 06 01:53:41 PM PDT 24
Peak memory 215440 kb
Host smart-83e76bc6-3d6c-44ed-9822-d545b282030f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040737562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1040737562
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2171356834
Short name T61
Test name
Test status
Simulation time 153068823 ps
CPU time 2.97 seconds
Started Jun 06 01:53:31 PM PDT 24
Finished Jun 06 01:53:35 PM PDT 24
Peak memory 216620 kb
Host smart-18ec65e0-dc39-4fd4-9f49-66d36669f943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171356834 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2171356834
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2765115121
Short name T145
Test name
Test status
Simulation time 768776257 ps
CPU time 1.45 seconds
Started Jun 06 01:53:28 PM PDT 24
Finished Jun 06 01:53:31 PM PDT 24
Peak memory 206884 kb
Host smart-341766ef-8761-446b-babf-c10d1cf0959a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765115121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
765115121
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3533887052
Short name T1016
Test name
Test status
Simulation time 28715133 ps
CPU time 0.72 seconds
Started Jun 06 01:53:28 PM PDT 24
Finished Jun 06 01:53:29 PM PDT 24
Peak memory 203580 kb
Host smart-b9dd56d1-0207-4432-9625-534b46441d1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533887052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
533887052
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1538983918
Short name T1049
Test name
Test status
Simulation time 962410642 ps
CPU time 1.84 seconds
Started Jun 06 01:53:36 PM PDT 24
Finished Jun 06 01:53:39 PM PDT 24
Peak memory 215036 kb
Host smart-24bc60c1-60e7-4ad8-b28c-f0d15e047f43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538983918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1538983918
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.50338270
Short name T59
Test name
Test status
Simulation time 194844741 ps
CPU time 4.52 seconds
Started Jun 06 01:53:37 PM PDT 24
Finished Jun 06 01:53:43 PM PDT 24
Peak memory 215272 kb
Host smart-5ba2e318-775d-40ff-8fef-39739bb74725
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50338270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.50338270
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3978511015
Short name T1072
Test name
Test status
Simulation time 161393279 ps
CPU time 2.68 seconds
Started Jun 06 01:53:40 PM PDT 24
Finished Jun 06 01:53:44 PM PDT 24
Peak memory 216968 kb
Host smart-12045bae-05d5-49bc-9024-a590e5ed90af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978511015 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3978511015
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1233156964
Short name T1055
Test name
Test status
Simulation time 52386843 ps
CPU time 1.76 seconds
Started Jun 06 01:53:47 PM PDT 24
Finished Jun 06 01:53:51 PM PDT 24
Peak memory 215096 kb
Host smart-7b46a6b8-a4be-430c-87dd-7c8c67e11019
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233156964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
233156964
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3055096493
Short name T1029
Test name
Test status
Simulation time 54844799 ps
CPU time 0.76 seconds
Started Jun 06 01:53:36 PM PDT 24
Finished Jun 06 01:53:38 PM PDT 24
Peak memory 203552 kb
Host smart-1ddc42d1-3346-4477-bc68-9bd50c624469
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055096493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
055096493
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1630726423
Short name T967
Test name
Test status
Simulation time 52754792 ps
CPU time 1.6 seconds
Started Jun 06 01:53:40 PM PDT 24
Finished Jun 06 01:53:43 PM PDT 24
Peak memory 215088 kb
Host smart-599a8cfb-c52e-4353-92e5-3f7accd98756
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630726423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1630726423
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.103594936
Short name T104
Test name
Test status
Simulation time 142778433 ps
CPU time 2.06 seconds
Started Jun 06 01:53:37 PM PDT 24
Finished Jun 06 01:53:40 PM PDT 24
Peak memory 215256 kb
Host smart-867fc6e5-8858-407a-937e-030ff5b65e2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103594936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.103594936
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.384249291
Short name T273
Test name
Test status
Simulation time 552286188 ps
CPU time 7.21 seconds
Started Jun 06 01:53:40 PM PDT 24
Finished Jun 06 01:53:48 PM PDT 24
Peak memory 215100 kb
Host smart-9100d446-ecf4-4885-833e-d4bdf90c65a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384249291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.384249291
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2302447933
Short name T976
Test name
Test status
Simulation time 28536380 ps
CPU time 1.86 seconds
Started Jun 06 01:53:36 PM PDT 24
Finished Jun 06 01:53:39 PM PDT 24
Peak memory 215256 kb
Host smart-931eccae-1b34-41f3-b787-9632c7508535
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302447933 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2302447933
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2486630063
Short name T122
Test name
Test status
Simulation time 102331952 ps
CPU time 1.64 seconds
Started Jun 06 01:53:35 PM PDT 24
Finished Jun 06 01:53:37 PM PDT 24
Peak memory 206816 kb
Host smart-f6a2052b-aaf2-4793-9787-3d7e31a80f86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486630063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
486630063
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2416170462
Short name T1054
Test name
Test status
Simulation time 35174779 ps
CPU time 0.72 seconds
Started Jun 06 01:53:38 PM PDT 24
Finished Jun 06 01:53:40 PM PDT 24
Peak memory 203560 kb
Host smart-7a3db6dc-271d-47e5-a42c-e42b21ca481a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416170462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
416170462
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3738689049
Short name T986
Test name
Test status
Simulation time 231697308 ps
CPU time 3.01 seconds
Started Jun 06 01:53:39 PM PDT 24
Finished Jun 06 01:53:43 PM PDT 24
Peak memory 215112 kb
Host smart-4822bbf8-fcd2-45bf-8f4d-ffc380cf4fab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738689049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3738689049
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3233189196
Short name T1017
Test name
Test status
Simulation time 321520013 ps
CPU time 2.21 seconds
Started Jun 06 01:53:37 PM PDT 24
Finished Jun 06 01:53:40 PM PDT 24
Peak memory 215288 kb
Host smart-bcf5ebba-6679-4d57-9ad7-ed9d127d4a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233189196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
233189196
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2630729486
Short name T1081
Test name
Test status
Simulation time 2161682847 ps
CPU time 14.64 seconds
Started Jun 06 01:53:43 PM PDT 24
Finished Jun 06 01:53:58 PM PDT 24
Peak memory 216700 kb
Host smart-464067c8-d205-4ff8-bac6-0992d637e447
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630729486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2630729486
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2297184444
Short name T810
Test name
Test status
Simulation time 57626191 ps
CPU time 0.74 seconds
Started Jun 06 01:57:04 PM PDT 24
Finished Jun 06 01:57:06 PM PDT 24
Peak memory 205540 kb
Host smart-300a27fa-ec07-4d0b-a858-95fef9e422aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297184444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
297184444
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3450427732
Short name T5
Test name
Test status
Simulation time 419466779 ps
CPU time 2.55 seconds
Started Jun 06 01:57:10 PM PDT 24
Finished Jun 06 01:57:14 PM PDT 24
Peak memory 225116 kb
Host smart-060f2113-28ff-4e11-a86c-78dcb5ad7ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450427732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3450427732
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3426244978
Short name T912
Test name
Test status
Simulation time 53643498 ps
CPU time 0.78 seconds
Started Jun 06 01:57:05 PM PDT 24
Finished Jun 06 01:57:07 PM PDT 24
Peak memory 207260 kb
Host smart-df4c216c-adf8-4fea-9e8f-d348d56cb992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426244978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3426244978
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1225996356
Short name T602
Test name
Test status
Simulation time 162715414810 ps
CPU time 291.03 seconds
Started Jun 06 01:57:06 PM PDT 24
Finished Jun 06 02:01:58 PM PDT 24
Peak memory 249880 kb
Host smart-bc226e08-a4e4-4fba-951f-1703cf0cd831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225996356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1225996356
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2009303371
Short name T252
Test name
Test status
Simulation time 16000200896 ps
CPU time 56.32 seconds
Started Jun 06 01:56:56 PM PDT 24
Finished Jun 06 01:57:54 PM PDT 24
Peak memory 241732 kb
Host smart-9a3b5727-825b-4893-9475-7a89923fed37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009303371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2009303371
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2354160175
Short name T910
Test name
Test status
Simulation time 186353998 ps
CPU time 2.84 seconds
Started Jun 06 01:57:05 PM PDT 24
Finished Jun 06 01:57:09 PM PDT 24
Peak memory 228304 kb
Host smart-d9ce3cdb-7447-4bf7-a942-039bc24b6acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354160175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2354160175
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1242147084
Short name T775
Test name
Test status
Simulation time 99255943334 ps
CPU time 105.53 seconds
Started Jun 06 01:57:03 PM PDT 24
Finished Jun 06 01:58:50 PM PDT 24
Peak memory 235188 kb
Host smart-0e84dc45-6813-438e-9d1a-15bc17d1c8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242147084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1242147084
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1265092068
Short name T709
Test name
Test status
Simulation time 1032629711 ps
CPU time 5.33 seconds
Started Jun 06 01:56:56 PM PDT 24
Finished Jun 06 01:57:02 PM PDT 24
Peak memory 225216 kb
Host smart-bb246e99-1bea-476e-9f8f-e96aced14f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265092068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1265092068
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.292760773
Short name T182
Test name
Test status
Simulation time 59528480007 ps
CPU time 38.96 seconds
Started Jun 06 01:57:06 PM PDT 24
Finished Jun 06 01:57:46 PM PDT 24
Peak memory 225516 kb
Host smart-bb3173e9-d029-4881-acff-c775ffb2b8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292760773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.292760773
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2334669521
Short name T745
Test name
Test status
Simulation time 920267119 ps
CPU time 6.26 seconds
Started Jun 06 01:57:04 PM PDT 24
Finished Jun 06 01:57:11 PM PDT 24
Peak memory 220624 kb
Host smart-d2270cd4-a1a5-43a9-b847-0c1efaaf2db2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2334669521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2334669521
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2489711015
Short name T65
Test name
Test status
Simulation time 150909354 ps
CPU time 1.03 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:24 PM PDT 24
Peak memory 236224 kb
Host smart-f216b965-67e6-4c13-9517-b5ea4374e7af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489711015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2489711015
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1944348636
Short name T386
Test name
Test status
Simulation time 5009975416 ps
CPU time 6.56 seconds
Started Jun 06 01:56:58 PM PDT 24
Finished Jun 06 01:57:06 PM PDT 24
Peak memory 217076 kb
Host smart-28b4146a-5ade-4118-9b65-7d03a751d4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944348636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1944348636
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1829210917
Short name T461
Test name
Test status
Simulation time 7119509593 ps
CPU time 20.06 seconds
Started Jun 06 01:57:01 PM PDT 24
Finished Jun 06 01:57:22 PM PDT 24
Peak memory 217028 kb
Host smart-9025b490-4a7b-492d-be83-dc6bfc6ae3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829210917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1829210917
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.670131801
Short name T565
Test name
Test status
Simulation time 182052740 ps
CPU time 1.4 seconds
Started Jun 06 01:57:02 PM PDT 24
Finished Jun 06 01:57:04 PM PDT 24
Peak memory 217032 kb
Host smart-843e0020-f841-4b1a-a5a6-79b6730176d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670131801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.670131801
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2293589118
Short name T352
Test name
Test status
Simulation time 16388627 ps
CPU time 0.73 seconds
Started Jun 06 01:56:56 PM PDT 24
Finished Jun 06 01:56:58 PM PDT 24
Peak memory 206532 kb
Host smart-900bb23e-efec-4940-a85b-dc8729987cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293589118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2293589118
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3357522853
Short name T171
Test name
Test status
Simulation time 8935034721 ps
CPU time 15.88 seconds
Started Jun 06 01:56:59 PM PDT 24
Finished Jun 06 01:57:17 PM PDT 24
Peak memory 249884 kb
Host smart-b5ece012-82a6-4c8a-ad52-6d1cad72b76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357522853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3357522853
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1820315359
Short name T619
Test name
Test status
Simulation time 13694221 ps
CPU time 0.7 seconds
Started Jun 06 01:57:12 PM PDT 24
Finished Jun 06 01:57:13 PM PDT 24
Peak memory 206100 kb
Host smart-0db0fc09-3694-4eb3-9ccf-658748539ebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820315359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
820315359
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.28374836
Short name T283
Test name
Test status
Simulation time 801469622 ps
CPU time 4.63 seconds
Started Jun 06 01:57:01 PM PDT 24
Finished Jun 06 01:57:06 PM PDT 24
Peak memory 233420 kb
Host smart-48b88e2e-029f-4657-93b3-a497a881c505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28374836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.28374836
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3584841446
Short name T439
Test name
Test status
Simulation time 44118396 ps
CPU time 0.77 seconds
Started Jun 06 01:57:00 PM PDT 24
Finished Jun 06 01:57:02 PM PDT 24
Peak memory 206536 kb
Host smart-0658eeb0-1068-473e-a4f1-78f9acd0812a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584841446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3584841446
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.4291051326
Short name T661
Test name
Test status
Simulation time 19177227 ps
CPU time 0.75 seconds
Started Jun 06 01:56:57 PM PDT 24
Finished Jun 06 01:57:00 PM PDT 24
Peak memory 216556 kb
Host smart-71fad470-6ddf-48f0-98a8-131be4fc8454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291051326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4291051326
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1388479734
Short name T466
Test name
Test status
Simulation time 46816077712 ps
CPU time 446.11 seconds
Started Jun 06 01:57:03 PM PDT 24
Finished Jun 06 02:04:31 PM PDT 24
Peak memory 258076 kb
Host smart-1abb5a72-1898-4ee7-bf4f-f03680656f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388479734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1388479734
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1139488247
Short name T220
Test name
Test status
Simulation time 8317784638 ps
CPU time 47.5 seconds
Started Jun 06 01:57:03 PM PDT 24
Finished Jun 06 01:57:51 PM PDT 24
Peak memory 241700 kb
Host smart-986f1ef9-1738-4959-8608-816ab40e5da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139488247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1139488247
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3429550312
Short name T714
Test name
Test status
Simulation time 453898416 ps
CPU time 8.93 seconds
Started Jun 06 01:56:57 PM PDT 24
Finished Jun 06 01:57:08 PM PDT 24
Peak memory 225228 kb
Host smart-10f50ca0-2192-4c7c-9ac1-228b149ff38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429550312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3429550312
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1003183770
Short name T211
Test name
Test status
Simulation time 235617319 ps
CPU time 4.44 seconds
Started Jun 06 01:57:09 PM PDT 24
Finished Jun 06 01:57:15 PM PDT 24
Peak memory 229672 kb
Host smart-ac0eaeba-6e87-4fa4-9d9f-f0381cb7fde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003183770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1003183770
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1918685723
Short name T825
Test name
Test status
Simulation time 38782549539 ps
CPU time 32.36 seconds
Started Jun 06 01:57:05 PM PDT 24
Finished Jun 06 01:57:38 PM PDT 24
Peak memory 233412 kb
Host smart-6d0c7230-c816-4133-9686-591ed9a10178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918685723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1918685723
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.99585877
Short name T927
Test name
Test status
Simulation time 25454620278 ps
CPU time 14.25 seconds
Started Jun 06 01:56:59 PM PDT 24
Finished Jun 06 01:57:14 PM PDT 24
Peak memory 241484 kb
Host smart-0f21e4ac-3dc0-42f9-827a-2a1de4c2017d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99585877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.99585877
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.236998919
Short name T684
Test name
Test status
Simulation time 1000978513 ps
CPU time 8.1 seconds
Started Jun 06 01:56:57 PM PDT 24
Finished Jun 06 01:57:07 PM PDT 24
Peak memory 233376 kb
Host smart-f20124b8-33d3-4a49-a2f6-65ce94618b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236998919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.236998919
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1685753167
Short name T140
Test name
Test status
Simulation time 1161035371 ps
CPU time 14.13 seconds
Started Jun 06 01:57:12 PM PDT 24
Finished Jun 06 01:57:27 PM PDT 24
Peak memory 223600 kb
Host smart-6088ccc0-2947-4dbb-bbc3-044fb2640732
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1685753167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1685753167
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2021159495
Short name T338
Test name
Test status
Simulation time 33952527963 ps
CPU time 43.96 seconds
Started Jun 06 01:57:00 PM PDT 24
Finished Jun 06 01:57:46 PM PDT 24
Peak memory 217000 kb
Host smart-f85c3c18-5f95-4047-bbad-83f54267378b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021159495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2021159495
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3892072817
Short name T522
Test name
Test status
Simulation time 3159397151 ps
CPU time 11.79 seconds
Started Jun 06 01:57:01 PM PDT 24
Finished Jun 06 01:57:14 PM PDT 24
Peak memory 216988 kb
Host smart-aad25525-4491-4f80-8f70-74ac47fd34bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892072817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3892072817
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2435031453
Short name T652
Test name
Test status
Simulation time 14499559 ps
CPU time 0.83 seconds
Started Jun 06 01:57:00 PM PDT 24
Finished Jun 06 01:57:02 PM PDT 24
Peak memory 207232 kb
Host smart-e6d9a3ed-50f9-46ca-a2d2-17688a917e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435031453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2435031453
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2669436118
Short name T685
Test name
Test status
Simulation time 16633625 ps
CPU time 0.7 seconds
Started Jun 06 01:56:56 PM PDT 24
Finished Jun 06 01:56:58 PM PDT 24
Peak memory 206508 kb
Host smart-43f2d6aa-7cee-4692-af54-b94d80b372b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669436118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2669436118
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2004709396
Short name T563
Test name
Test status
Simulation time 1754980082 ps
CPU time 9.07 seconds
Started Jun 06 01:57:07 PM PDT 24
Finished Jun 06 01:57:17 PM PDT 24
Peak memory 241600 kb
Host smart-0fa767b8-148e-44bf-b9b5-3334912b9c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004709396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2004709396
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1230381813
Short name T468
Test name
Test status
Simulation time 14217992 ps
CPU time 0.79 seconds
Started Jun 06 01:57:41 PM PDT 24
Finished Jun 06 01:57:44 PM PDT 24
Peak memory 206436 kb
Host smart-208a39dd-0b0b-41ae-8aa8-9fcf11134edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230381813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1230381813
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.517128503
Short name T372
Test name
Test status
Simulation time 538057026 ps
CPU time 5.99 seconds
Started Jun 06 01:57:19 PM PDT 24
Finished Jun 06 01:57:27 PM PDT 24
Peak memory 225204 kb
Host smart-7dff6259-5334-493b-9487-bd98983d6e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517128503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.517128503
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1158119613
Short name T396
Test name
Test status
Simulation time 13781002 ps
CPU time 0.77 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:23 PM PDT 24
Peak memory 207276 kb
Host smart-da1f3c55-b04a-4e82-9120-46227beb95e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158119613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1158119613
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.845645780
Short name T420
Test name
Test status
Simulation time 15494404252 ps
CPU time 122.83 seconds
Started Jun 06 01:57:23 PM PDT 24
Finished Jun 06 01:59:27 PM PDT 24
Peak memory 238724 kb
Host smart-148cb75f-f6c5-4658-b2d5-0dc5a255ec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845645780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.845645780
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.663271071
Short name T753
Test name
Test status
Simulation time 15611144417 ps
CPU time 175.93 seconds
Started Jun 06 01:57:45 PM PDT 24
Finished Jun 06 02:00:42 PM PDT 24
Peak memory 250916 kb
Host smart-3564fcff-4b2d-404b-95f1-5bf3dd0243b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663271071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.663271071
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1137924176
Short name T777
Test name
Test status
Simulation time 6397218015 ps
CPU time 103.9 seconds
Started Jun 06 01:57:24 PM PDT 24
Finished Jun 06 01:59:09 PM PDT 24
Peak memory 258100 kb
Host smart-2294df04-ae98-42b9-af35-a2e008d73f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137924176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1137924176
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.496143388
Short name T516
Test name
Test status
Simulation time 1998887428 ps
CPU time 9.84 seconds
Started Jun 06 01:57:25 PM PDT 24
Finished Jun 06 01:57:36 PM PDT 24
Peak memory 225244 kb
Host smart-4235a989-e0ca-412d-b98b-896db430c8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496143388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.496143388
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2905680924
Short name T591
Test name
Test status
Simulation time 169200625 ps
CPU time 2.5 seconds
Started Jun 06 01:57:22 PM PDT 24
Finished Jun 06 01:57:26 PM PDT 24
Peak memory 225184 kb
Host smart-bf23cb0d-9b92-4fb7-b609-4592086a2959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905680924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2905680924
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.86181913
Short name T306
Test name
Test status
Simulation time 68420519878 ps
CPU time 86.34 seconds
Started Jun 06 01:57:27 PM PDT 24
Finished Jun 06 01:58:54 PM PDT 24
Peak memory 241552 kb
Host smart-b4609c11-6188-49d3-b22c-42b1a6da4121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86181913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.86181913
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.425228439
Short name T52
Test name
Test status
Simulation time 99551671 ps
CPU time 2.45 seconds
Started Jun 06 01:57:38 PM PDT 24
Finished Jun 06 01:57:42 PM PDT 24
Peak memory 224972 kb
Host smart-4a7fa680-abb4-43b2-aeea-0aa145516fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425228439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.425228439
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.602642081
Short name T931
Test name
Test status
Simulation time 25913702564 ps
CPU time 20.01 seconds
Started Jun 06 01:57:21 PM PDT 24
Finished Jun 06 01:57:43 PM PDT 24
Peak memory 233484 kb
Host smart-b8d604ed-f4cf-4175-adb4-060c05992fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602642081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.602642081
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3280394166
Short name T37
Test name
Test status
Simulation time 1611480148 ps
CPU time 8.43 seconds
Started Jun 06 01:57:25 PM PDT 24
Finished Jun 06 01:57:34 PM PDT 24
Peak memory 222960 kb
Host smart-8f85fa84-894d-4ae9-87da-f69133139f88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3280394166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3280394166
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2182810396
Short name T646
Test name
Test status
Simulation time 3222736776 ps
CPU time 52 seconds
Started Jun 06 01:57:21 PM PDT 24
Finished Jun 06 01:58:15 PM PDT 24
Peak memory 249912 kb
Host smart-8d57cd2e-a0cb-4861-9ffb-ec6dab997be6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182810396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2182810396
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1458240362
Short name T897
Test name
Test status
Simulation time 2849405574 ps
CPU time 26.84 seconds
Started Jun 06 01:57:39 PM PDT 24
Finished Jun 06 01:58:07 PM PDT 24
Peak memory 217048 kb
Host smart-83f99bec-f85a-4e9a-afcf-9367400edc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458240362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1458240362
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1587767170
Short name T423
Test name
Test status
Simulation time 303506311 ps
CPU time 2.83 seconds
Started Jun 06 01:57:41 PM PDT 24
Finished Jun 06 01:57:46 PM PDT 24
Peak memory 216984 kb
Host smart-d4817840-ccc3-4a55-b733-3bdd64b8ac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587767170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1587767170
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3358207163
Short name T637
Test name
Test status
Simulation time 211666725 ps
CPU time 1.71 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:24 PM PDT 24
Peak memory 216944 kb
Host smart-645bc0dc-d64c-4e4c-b694-7b82b7a34e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358207163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3358207163
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1649007433
Short name T561
Test name
Test status
Simulation time 254555151 ps
CPU time 0.71 seconds
Started Jun 06 01:57:26 PM PDT 24
Finished Jun 06 01:57:28 PM PDT 24
Peak memory 206536 kb
Host smart-a94b6dcc-6bf3-4c03-9831-2dfb3d4518e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649007433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1649007433
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3558675342
Short name T764
Test name
Test status
Simulation time 1033597166 ps
CPU time 5.35 seconds
Started Jun 06 01:57:26 PM PDT 24
Finished Jun 06 01:57:33 PM PDT 24
Peak memory 233184 kb
Host smart-5ffd97f7-f721-4bb7-a533-4da59c5dd8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558675342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3558675342
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1320166439
Short name T949
Test name
Test status
Simulation time 16381733 ps
CPU time 0.76 seconds
Started Jun 06 01:57:34 PM PDT 24
Finished Jun 06 01:57:35 PM PDT 24
Peak memory 206104 kb
Host smart-ab332958-5742-4e68-a8b3-59d95ad9fa78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320166439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1320166439
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2717730930
Short name T517
Test name
Test status
Simulation time 3619937961 ps
CPU time 12.11 seconds
Started Jun 06 01:57:22 PM PDT 24
Finished Jun 06 01:57:36 PM PDT 24
Peak memory 233428 kb
Host smart-86110e94-7fe4-4902-9689-812cd7257e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717730930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2717730930
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3547120858
Short name T366
Test name
Test status
Simulation time 194736482 ps
CPU time 0.76 seconds
Started Jun 06 01:57:40 PM PDT 24
Finished Jun 06 01:57:43 PM PDT 24
Peak memory 207592 kb
Host smart-14f650bc-8eba-4515-8a28-154d3b3383f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547120858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3547120858
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1796282422
Short name T46
Test name
Test status
Simulation time 149945333157 ps
CPU time 151.03 seconds
Started Jun 06 01:57:22 PM PDT 24
Finished Jun 06 01:59:55 PM PDT 24
Peak memory 255964 kb
Host smart-6513ef34-2f14-484e-8d99-2c7e4f4f4a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796282422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1796282422
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2150225386
Short name T355
Test name
Test status
Simulation time 13285576858 ps
CPU time 23.9 seconds
Started Jun 06 01:57:24 PM PDT 24
Finished Jun 06 01:57:49 PM PDT 24
Peak memory 233452 kb
Host smart-68d7a054-825d-44b4-8a18-d374684c204b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150225386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2150225386
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1266757401
Short name T662
Test name
Test status
Simulation time 1052503955 ps
CPU time 10.6 seconds
Started Jun 06 01:57:23 PM PDT 24
Finished Jun 06 01:57:35 PM PDT 24
Peak memory 225136 kb
Host smart-e22d690c-f324-4430-92f8-29c03c29212f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266757401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1266757401
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2447504583
Short name T840
Test name
Test status
Simulation time 49968902031 ps
CPU time 134.58 seconds
Started Jun 06 01:57:25 PM PDT 24
Finished Jun 06 01:59:41 PM PDT 24
Peak memory 238016 kb
Host smart-3e0813f5-1060-4431-91ad-b37c0a62970b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447504583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2447504583
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2377689428
Short name T323
Test name
Test status
Simulation time 928681901 ps
CPU time 3.45 seconds
Started Jun 06 01:57:29 PM PDT 24
Finished Jun 06 01:57:34 PM PDT 24
Peak memory 233364 kb
Host smart-48d5e346-2926-4941-9c1a-eaf9ebed8fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377689428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2377689428
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1495650508
Short name T32
Test name
Test status
Simulation time 1926626676 ps
CPU time 7.05 seconds
Started Jun 06 01:57:23 PM PDT 24
Finished Jun 06 01:57:32 PM PDT 24
Peak memory 233400 kb
Host smart-fd2c3362-30dc-4f5c-811f-c2ce2086d868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495650508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1495650508
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.445330350
Short name T870
Test name
Test status
Simulation time 781616945 ps
CPU time 5.35 seconds
Started Jun 06 01:57:38 PM PDT 24
Finished Jun 06 01:57:45 PM PDT 24
Peak memory 223804 kb
Host smart-98682fef-362a-4e6f-8075-c6a040940a11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=445330350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.445330350
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1100806835
Short name T455
Test name
Test status
Simulation time 23571900921 ps
CPU time 23.98 seconds
Started Jun 06 01:57:21 PM PDT 24
Finished Jun 06 01:57:47 PM PDT 24
Peak memory 217192 kb
Host smart-37866635-8c05-4867-89eb-e7560f8d14b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100806835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1100806835
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2348863739
Short name T367
Test name
Test status
Simulation time 16971378694 ps
CPU time 11.42 seconds
Started Jun 06 01:57:44 PM PDT 24
Finished Jun 06 01:57:57 PM PDT 24
Peak memory 217052 kb
Host smart-0cdfb0e7-6949-428a-89b4-e59ce13cad16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348863739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2348863739
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1880640054
Short name T707
Test name
Test status
Simulation time 37791673 ps
CPU time 1.16 seconds
Started Jun 06 01:57:25 PM PDT 24
Finished Jun 06 01:57:27 PM PDT 24
Peak memory 208528 kb
Host smart-09fb34d5-a7c2-4e46-895b-dddec89f160c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880640054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1880640054
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2909223888
Short name T936
Test name
Test status
Simulation time 31649871 ps
CPU time 0.71 seconds
Started Jun 06 01:57:19 PM PDT 24
Finished Jun 06 01:57:22 PM PDT 24
Peak memory 206520 kb
Host smart-97834e7a-a8ce-4ede-9e4e-26073ea7cb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909223888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2909223888
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.564311287
Short name T193
Test name
Test status
Simulation time 1419049841 ps
CPU time 3.25 seconds
Started Jun 06 01:57:35 PM PDT 24
Finished Jun 06 01:57:39 PM PDT 24
Peak memory 225176 kb
Host smart-0f217fb6-227a-44db-8edd-c5427cc48d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564311287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.564311287
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2894076251
Short name T873
Test name
Test status
Simulation time 39474595 ps
CPU time 0.72 seconds
Started Jun 06 01:57:40 PM PDT 24
Finished Jun 06 01:57:44 PM PDT 24
Peak memory 206140 kb
Host smart-01afdb00-67fe-4fc8-a449-37390be499b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894076251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2894076251
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.191275178
Short name T464
Test name
Test status
Simulation time 341010649 ps
CPU time 3.86 seconds
Started Jun 06 01:57:41 PM PDT 24
Finished Jun 06 01:57:47 PM PDT 24
Peak memory 233384 kb
Host smart-d05f5146-0548-4af3-9713-c2d2400ef2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191275178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.191275178
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3882210542
Short name T829
Test name
Test status
Simulation time 50685362 ps
CPU time 0.78 seconds
Started Jun 06 01:57:38 PM PDT 24
Finished Jun 06 01:57:40 PM PDT 24
Peak memory 207584 kb
Host smart-2a8f240a-fde4-4c39-99d6-df0c8a948d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882210542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3882210542
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3749765321
Short name T786
Test name
Test status
Simulation time 6991922907 ps
CPU time 110.98 seconds
Started Jun 06 01:57:42 PM PDT 24
Finished Jun 06 01:59:35 PM PDT 24
Peak memory 258072 kb
Host smart-8386b9b2-4499-49ac-9d3a-0f2138ccd38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749765321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3749765321
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.4053874687
Short name T471
Test name
Test status
Simulation time 2485290462 ps
CPU time 8.55 seconds
Started Jun 06 01:57:45 PM PDT 24
Finished Jun 06 01:57:54 PM PDT 24
Peak memory 235208 kb
Host smart-24d59d9a-59f4-4065-bcf9-6f2813d8605b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053874687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.4053874687
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3200774879
Short name T216
Test name
Test status
Simulation time 276559252 ps
CPU time 5.39 seconds
Started Jun 06 01:57:40 PM PDT 24
Finished Jun 06 01:57:48 PM PDT 24
Peak memory 219272 kb
Host smart-220e155e-3793-4ce9-9bc6-d147937c3d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200774879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3200774879
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.777434363
Short name T578
Test name
Test status
Simulation time 2475552654 ps
CPU time 6.41 seconds
Started Jun 06 01:57:41 PM PDT 24
Finished Jun 06 01:57:50 PM PDT 24
Peak memory 225220 kb
Host smart-1b25a032-a231-445a-aa3c-dd85eea4e891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777434363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.777434363
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1532638185
Short name T268
Test name
Test status
Simulation time 2519550815 ps
CPU time 9.37 seconds
Started Jun 06 01:57:38 PM PDT 24
Finished Jun 06 01:57:49 PM PDT 24
Peak memory 233488 kb
Host smart-afe726f2-4c40-409c-a335-910ce5f7ff71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532638185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1532638185
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3642987516
Short name T645
Test name
Test status
Simulation time 497028902 ps
CPU time 5.38 seconds
Started Jun 06 01:57:38 PM PDT 24
Finished Jun 06 01:57:45 PM PDT 24
Peak memory 233660 kb
Host smart-62613edb-b162-4228-9b78-221c46e2e7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642987516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3642987516
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3496025443
Short name T774
Test name
Test status
Simulation time 19855937557 ps
CPU time 13.73 seconds
Started Jun 06 01:57:37 PM PDT 24
Finished Jun 06 01:57:52 PM PDT 24
Peak memory 223708 kb
Host smart-bf9f473b-5368-4999-b16c-89188f051003
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3496025443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3496025443
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2437797917
Short name T299
Test name
Test status
Simulation time 5471105511 ps
CPU time 24.4 seconds
Started Jun 06 01:57:43 PM PDT 24
Finished Jun 06 01:58:09 PM PDT 24
Peak memory 225244 kb
Host smart-edd636fa-e2fa-45e5-a035-a2a7460a8b6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437797917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2437797917
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3325594855
Short name T21
Test name
Test status
Simulation time 2506384391 ps
CPU time 7.88 seconds
Started Jun 06 01:57:38 PM PDT 24
Finished Jun 06 01:57:48 PM PDT 24
Peak memory 217048 kb
Host smart-22a99628-82f6-45bf-9230-d43a14ce5e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325594855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3325594855
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2691063430
Short name T526
Test name
Test status
Simulation time 6368689875 ps
CPU time 14.21 seconds
Started Jun 06 01:57:37 PM PDT 24
Finished Jun 06 01:57:53 PM PDT 24
Peak memory 217068 kb
Host smart-f8f9697b-85b3-4e2c-9819-05189df3cce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691063430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2691063430
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1388277570
Short name T798
Test name
Test status
Simulation time 232026565 ps
CPU time 4.98 seconds
Started Jun 06 01:57:29 PM PDT 24
Finished Jun 06 01:57:35 PM PDT 24
Peak memory 217040 kb
Host smart-ce0745c0-fe80-47d1-9633-2a60580378ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388277570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1388277570
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.4062118805
Short name T353
Test name
Test status
Simulation time 156735614 ps
CPU time 0.85 seconds
Started Jun 06 01:57:43 PM PDT 24
Finished Jun 06 01:57:45 PM PDT 24
Peak memory 206536 kb
Host smart-8f187a31-4b52-4d98-a1ee-733de94ee85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062118805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.4062118805
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1656688487
Short name T479
Test name
Test status
Simulation time 61878682 ps
CPU time 2.51 seconds
Started Jun 06 01:57:40 PM PDT 24
Finished Jun 06 01:57:44 PM PDT 24
Peak memory 224980 kb
Host smart-ac01e216-c619-4514-b33c-9dfd422f9993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656688487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1656688487
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1108189165
Short name T943
Test name
Test status
Simulation time 137436237 ps
CPU time 3.38 seconds
Started Jun 06 01:57:47 PM PDT 24
Finished Jun 06 01:57:51 PM PDT 24
Peak memory 233412 kb
Host smart-040dcd0a-430a-4429-9c65-904b62ace69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108189165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1108189165
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.4237324423
Short name T345
Test name
Test status
Simulation time 43245355 ps
CPU time 0.77 seconds
Started Jun 06 01:57:40 PM PDT 24
Finished Jun 06 01:57:43 PM PDT 24
Peak memory 207504 kb
Host smart-9bc8478e-b40b-4c2e-ae0b-51153d3b9af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237324423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.4237324423
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3400883763
Short name T940
Test name
Test status
Simulation time 283851775293 ps
CPU time 224.74 seconds
Started Jun 06 01:57:45 PM PDT 24
Finished Jun 06 02:01:31 PM PDT 24
Peak memory 249848 kb
Host smart-1d7b60f7-e33b-45ce-b84e-f8ed725b2dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400883763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3400883763
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.4065161413
Short name T72
Test name
Test status
Simulation time 50339973871 ps
CPU time 447.18 seconds
Started Jun 06 01:57:49 PM PDT 24
Finished Jun 06 02:05:18 PM PDT 24
Peak memory 264056 kb
Host smart-b117c2ba-7bf5-437c-b8e9-4f9b2da61fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065161413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.4065161413
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.509171873
Short name T772
Test name
Test status
Simulation time 22770368124 ps
CPU time 47.94 seconds
Started Jun 06 01:57:46 PM PDT 24
Finished Jun 06 01:58:35 PM PDT 24
Peak memory 250952 kb
Host smart-83aac6e0-26c6-458a-879b-914ff7536671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509171873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.509171873
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.172742281
Short name T854
Test name
Test status
Simulation time 9470481277 ps
CPU time 67.51 seconds
Started Jun 06 01:57:43 PM PDT 24
Finished Jun 06 01:58:52 PM PDT 24
Peak memory 251260 kb
Host smart-2f81f11e-6ec0-4ac4-9be9-7ec34707924d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172742281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.172742281
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3104985435
Short name T879
Test name
Test status
Simulation time 584126847 ps
CPU time 4.81 seconds
Started Jun 06 01:57:40 PM PDT 24
Finished Jun 06 01:57:48 PM PDT 24
Peak memory 233452 kb
Host smart-c8162cf5-7cf0-4727-a3f0-5b22a14bf2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104985435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3104985435
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1681202586
Short name T800
Test name
Test status
Simulation time 110865964 ps
CPU time 2.62 seconds
Started Jun 06 01:57:42 PM PDT 24
Finished Jun 06 01:57:46 PM PDT 24
Peak memory 233272 kb
Host smart-30085bfa-0925-4954-9354-a045450d6ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681202586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1681202586
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.91285920
Short name T204
Test name
Test status
Simulation time 889076899 ps
CPU time 4.61 seconds
Started Jun 06 01:57:42 PM PDT 24
Finished Jun 06 01:57:48 PM PDT 24
Peak memory 225208 kb
Host smart-8b428067-6fdc-47b8-af31-05329810ba99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91285920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.91285920
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.189356205
Short name T668
Test name
Test status
Simulation time 76023739 ps
CPU time 2.18 seconds
Started Jun 06 01:57:48 PM PDT 24
Finished Jun 06 01:57:52 PM PDT 24
Peak memory 225228 kb
Host smart-d3b12e03-db3a-46fe-9809-c27fd68bc36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189356205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.189356205
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2171252245
Short name T826
Test name
Test status
Simulation time 482264737 ps
CPU time 6.59 seconds
Started Jun 06 01:57:38 PM PDT 24
Finished Jun 06 01:57:46 PM PDT 24
Peak memory 221116 kb
Host smart-5d003221-10be-499f-8e7a-34d8ada3f496
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2171252245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2171252245
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3517759852
Short name T241
Test name
Test status
Simulation time 109616665770 ps
CPU time 407.62 seconds
Started Jun 06 01:57:48 PM PDT 24
Finished Jun 06 02:04:37 PM PDT 24
Peak memory 258060 kb
Host smart-000e49bb-de64-47ff-b0d2-48505af8659a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517759852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3517759852
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1737740586
Short name T40
Test name
Test status
Simulation time 31652513596 ps
CPU time 11.66 seconds
Started Jun 06 01:57:41 PM PDT 24
Finished Jun 06 01:57:55 PM PDT 24
Peak memory 217100 kb
Host smart-1959fed0-90f9-4cb3-acf6-fb970611f647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737740586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1737740586
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3275849379
Short name T475
Test name
Test status
Simulation time 1876560168 ps
CPU time 2.51 seconds
Started Jun 06 01:57:42 PM PDT 24
Finished Jun 06 01:57:47 PM PDT 24
Peak memory 216768 kb
Host smart-3a4ee0b9-9bba-4ec8-8fac-e8082199a73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275849379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3275849379
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3142823369
Short name T728
Test name
Test status
Simulation time 1054939884 ps
CPU time 6.36 seconds
Started Jun 06 01:57:39 PM PDT 24
Finished Jun 06 01:57:47 PM PDT 24
Peak memory 217152 kb
Host smart-57e4a993-94d6-491e-b525-1fb15b5b1dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142823369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3142823369
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2321048362
Short name T448
Test name
Test status
Simulation time 58519102 ps
CPU time 0.84 seconds
Started Jun 06 01:57:37 PM PDT 24
Finished Jun 06 01:57:39 PM PDT 24
Peak memory 206540 kb
Host smart-7e7bc2cc-7f91-4dbc-a633-00e1e80b7d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321048362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2321048362
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3708262675
Short name T958
Test name
Test status
Simulation time 1032022457 ps
CPU time 3.7 seconds
Started Jun 06 01:57:40 PM PDT 24
Finished Jun 06 01:57:47 PM PDT 24
Peak memory 225232 kb
Host smart-7f5589ef-7327-4de6-9dc2-58eebd2e32d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708262675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3708262675
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2369254197
Short name T163
Test name
Test status
Simulation time 40661153 ps
CPU time 0.7 seconds
Started Jun 06 01:57:48 PM PDT 24
Finished Jun 06 01:57:50 PM PDT 24
Peak memory 206044 kb
Host smart-76bb104b-a017-4e42-af46-21656f52d65f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369254197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2369254197
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.828445746
Short name T315
Test name
Test status
Simulation time 577982239 ps
CPU time 5.8 seconds
Started Jun 06 01:57:48 PM PDT 24
Finished Jun 06 01:57:55 PM PDT 24
Peak memory 225160 kb
Host smart-954686a1-d0ed-4663-b236-1b050da0f75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828445746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.828445746
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3291783797
Short name T8
Test name
Test status
Simulation time 61193593 ps
CPU time 0.81 seconds
Started Jun 06 01:57:50 PM PDT 24
Finished Jun 06 01:57:53 PM PDT 24
Peak memory 207208 kb
Host smart-68b5f410-a89d-4aea-905f-fdce9da69e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291783797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3291783797
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.588342679
Short name T505
Test name
Test status
Simulation time 68739335 ps
CPU time 0.76 seconds
Started Jun 06 01:57:47 PM PDT 24
Finished Jun 06 01:57:49 PM PDT 24
Peak memory 216580 kb
Host smart-43073fc1-2888-42e3-ac2c-0eaf8c697cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588342679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.588342679
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1084105388
Short name T926
Test name
Test status
Simulation time 6301593508 ps
CPU time 29.14 seconds
Started Jun 06 01:57:47 PM PDT 24
Finished Jun 06 01:58:17 PM PDT 24
Peak memory 249860 kb
Host smart-f0cfc615-bef6-466f-8855-b5d0c2b9d3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084105388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1084105388
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2928038334
Short name T793
Test name
Test status
Simulation time 5481636538 ps
CPU time 59.83 seconds
Started Jun 06 01:57:47 PM PDT 24
Finished Jun 06 01:58:48 PM PDT 24
Peak memory 241188 kb
Host smart-ffdfb011-9948-4987-916a-4e91be6e79c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928038334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2928038334
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3405207234
Short name T538
Test name
Test status
Simulation time 107027113 ps
CPU time 2.09 seconds
Started Jun 06 01:57:43 PM PDT 24
Finished Jun 06 01:57:46 PM PDT 24
Peak memory 223728 kb
Host smart-baa812f2-ee0d-4741-999a-bb88e88b9ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405207234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3405207234
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3584559094
Short name T300
Test name
Test status
Simulation time 1852684408 ps
CPU time 25.89 seconds
Started Jun 06 01:57:47 PM PDT 24
Finished Jun 06 01:58:13 PM PDT 24
Peak memory 241220 kb
Host smart-e34c86b0-930b-4ba5-9975-6916b719f19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584559094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3584559094
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2344799025
Short name T321
Test name
Test status
Simulation time 293062403 ps
CPU time 2.22 seconds
Started Jun 06 01:57:44 PM PDT 24
Finished Jun 06 01:57:47 PM PDT 24
Peak memory 225216 kb
Host smart-1e93eceb-e9b6-4698-92ec-e48fd1ee286d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344799025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2344799025
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2069007444
Short name T314
Test name
Test status
Simulation time 1127917458 ps
CPU time 3.64 seconds
Started Jun 06 01:57:48 PM PDT 24
Finished Jun 06 01:57:53 PM PDT 24
Peak memory 219148 kb
Host smart-7fa48275-1ba0-4bad-a4f4-8c961226cbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069007444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2069007444
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.958095144
Short name T647
Test name
Test status
Simulation time 282724134 ps
CPU time 5.59 seconds
Started Jun 06 01:57:50 PM PDT 24
Finished Jun 06 01:57:57 PM PDT 24
Peak memory 223804 kb
Host smart-b1b89e28-fc70-481e-b436-a4f3b3bcf60a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=958095144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.958095144
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.487667516
Short name T417
Test name
Test status
Simulation time 2370490494 ps
CPU time 6.79 seconds
Started Jun 06 01:57:51 PM PDT 24
Finished Jun 06 01:57:59 PM PDT 24
Peak memory 217072 kb
Host smart-03244137-7dff-4f61-86eb-17d9617259e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487667516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.487667516
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.409837455
Short name T613
Test name
Test status
Simulation time 12246682 ps
CPU time 0.71 seconds
Started Jun 06 01:57:42 PM PDT 24
Finished Jun 06 01:57:45 PM PDT 24
Peak memory 206328 kb
Host smart-13faa413-e9fb-408a-98a0-e340aad3ff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409837455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.409837455
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2359777162
Short name T400
Test name
Test status
Simulation time 111653995 ps
CPU time 1.76 seconds
Started Jun 06 01:57:48 PM PDT 24
Finished Jun 06 01:57:52 PM PDT 24
Peak memory 208792 kb
Host smart-4aea40f5-1a17-4b60-9a06-8207325465c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359777162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2359777162
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2837432809
Short name T888
Test name
Test status
Simulation time 108764597 ps
CPU time 0.83 seconds
Started Jun 06 01:57:49 PM PDT 24
Finished Jun 06 01:57:52 PM PDT 24
Peak memory 206548 kb
Host smart-4a67759c-4c91-4060-8c11-8baee9c13837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837432809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2837432809
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2075990538
Short name T884
Test name
Test status
Simulation time 5755967626 ps
CPU time 7.63 seconds
Started Jun 06 01:57:51 PM PDT 24
Finished Jun 06 01:58:00 PM PDT 24
Peak memory 233488 kb
Host smart-94c9a91b-e110-4c14-8d30-b16fee0a8764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075990538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2075990538
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3859939065
Short name T415
Test name
Test status
Simulation time 12143742 ps
CPU time 0.72 seconds
Started Jun 06 01:57:45 PM PDT 24
Finished Jun 06 01:57:46 PM PDT 24
Peak memory 205548 kb
Host smart-d698c648-f5b8-484e-b75c-361ef5db6fae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859939065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3859939065
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2970905866
Short name T929
Test name
Test status
Simulation time 309131557 ps
CPU time 4.59 seconds
Started Jun 06 01:57:54 PM PDT 24
Finished Jun 06 01:58:00 PM PDT 24
Peak memory 225192 kb
Host smart-f4ac9a40-9e31-4eac-9a15-640ca1fbb3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970905866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2970905866
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2263981733
Short name T819
Test name
Test status
Simulation time 17005582 ps
CPU time 0.76 seconds
Started Jun 06 01:57:48 PM PDT 24
Finished Jun 06 01:57:50 PM PDT 24
Peak memory 207524 kb
Host smart-ecab07bf-e748-4e42-b76d-03ee7278c538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263981733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2263981733
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.4082900774
Short name T213
Test name
Test status
Simulation time 70435075604 ps
CPU time 507.22 seconds
Started Jun 06 01:57:50 PM PDT 24
Finished Jun 06 02:06:19 PM PDT 24
Peak memory 266492 kb
Host smart-1d0b7716-1b69-434e-aaaa-0f3509d53d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082900774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.4082900774
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2167088085
Short name T686
Test name
Test status
Simulation time 150171927919 ps
CPU time 552.11 seconds
Started Jun 06 01:57:51 PM PDT 24
Finished Jun 06 02:07:04 PM PDT 24
Peak memory 255608 kb
Host smart-8c1773b6-ec5f-4de7-9ef2-618a7a165a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167088085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2167088085
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3272565590
Short name T885
Test name
Test status
Simulation time 2885886949 ps
CPU time 21.29 seconds
Started Jun 06 01:57:51 PM PDT 24
Finished Jun 06 01:58:14 PM PDT 24
Peak memory 218148 kb
Host smart-f3f85bbd-742f-4a2b-a12a-4237e1489b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272565590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3272565590
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.512522183
Short name T937
Test name
Test status
Simulation time 5208991653 ps
CPU time 20.89 seconds
Started Jun 06 01:57:47 PM PDT 24
Finished Jun 06 01:58:09 PM PDT 24
Peak memory 225292 kb
Host smart-086c2607-9990-479d-afc8-ba912e9c115c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512522183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.512522183
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2785310059
Short name T164
Test name
Test status
Simulation time 11009913076 ps
CPU time 20.1 seconds
Started Jun 06 01:57:46 PM PDT 24
Finished Jun 06 01:58:07 PM PDT 24
Peak memory 233480 kb
Host smart-229b147c-e2d1-4355-a049-423f7d154d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785310059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2785310059
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2137148665
Short name T934
Test name
Test status
Simulation time 1098490115 ps
CPU time 9.16 seconds
Started Jun 06 01:57:48 PM PDT 24
Finished Jun 06 01:57:59 PM PDT 24
Peak memory 233300 kb
Host smart-54d73d1f-1877-437f-8d74-f15ef6685d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137148665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2137148665
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3456582385
Short name T622
Test name
Test status
Simulation time 2570418967 ps
CPU time 10.49 seconds
Started Jun 06 01:57:44 PM PDT 24
Finished Jun 06 01:57:55 PM PDT 24
Peak memory 234584 kb
Host smart-fbd75aba-9246-47c6-9d85-ea14a140ccc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456582385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3456582385
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.4278849238
Short name T307
Test name
Test status
Simulation time 126999022 ps
CPU time 2.56 seconds
Started Jun 06 01:57:45 PM PDT 24
Finished Jun 06 01:57:48 PM PDT 24
Peak memory 233420 kb
Host smart-795e08b6-cb9c-4293-a800-6a25d2994e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278849238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.4278849238
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.302410975
Short name T752
Test name
Test status
Simulation time 404233461 ps
CPU time 6.77 seconds
Started Jun 06 01:57:42 PM PDT 24
Finished Jun 06 01:57:51 PM PDT 24
Peak memory 220932 kb
Host smart-a4ac654e-6800-4601-bf7e-4900e368cc54
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=302410975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.302410975
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2334394175
Short name T911
Test name
Test status
Simulation time 74797253851 ps
CPU time 660.71 seconds
Started Jun 06 01:57:49 PM PDT 24
Finished Jun 06 02:08:52 PM PDT 24
Peak memory 282148 kb
Host smart-5add13e8-db39-4cae-b113-6bf5e3d1f63c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334394175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2334394175
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1250514783
Short name T540
Test name
Test status
Simulation time 7732737854 ps
CPU time 12.76 seconds
Started Jun 06 01:57:42 PM PDT 24
Finished Jun 06 01:57:57 PM PDT 24
Peak memory 217096 kb
Host smart-a5b6218c-0b55-457a-9c30-aa9d942fe28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250514783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1250514783
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.254300318
Short name T509
Test name
Test status
Simulation time 656963953 ps
CPU time 2.3 seconds
Started Jun 06 01:57:41 PM PDT 24
Finished Jun 06 01:57:46 PM PDT 24
Peak memory 216952 kb
Host smart-df5164ff-0a34-41f1-8931-5438a61dffa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254300318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.254300318
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3647226584
Short name T594
Test name
Test status
Simulation time 69816071 ps
CPU time 1.95 seconds
Started Jun 06 01:57:48 PM PDT 24
Finished Jun 06 01:57:52 PM PDT 24
Peak memory 208676 kb
Host smart-2c688c5c-102b-401b-867d-98a9e7e52c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647226584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3647226584
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.429638963
Short name T49
Test name
Test status
Simulation time 37719571 ps
CPU time 0.81 seconds
Started Jun 06 01:57:50 PM PDT 24
Finished Jun 06 01:57:52 PM PDT 24
Peak memory 206544 kb
Host smart-9909f8e9-fb26-4f9d-8435-86267995d8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429638963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.429638963
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.960438667
Short name T222
Test name
Test status
Simulation time 1979716917 ps
CPU time 7.35 seconds
Started Jun 06 01:57:48 PM PDT 24
Finished Jun 06 01:57:56 PM PDT 24
Peak memory 225200 kb
Host smart-123b694c-2095-48c5-ac6e-f0aea7728dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960438667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.960438667
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3133843172
Short name T411
Test name
Test status
Simulation time 10441596 ps
CPU time 0.71 seconds
Started Jun 06 01:57:55 PM PDT 24
Finished Jun 06 01:57:57 PM PDT 24
Peak memory 205512 kb
Host smart-a7080c9b-403b-4416-acc7-9e2ccb36ec00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133843172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3133843172
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4214062497
Short name T590
Test name
Test status
Simulation time 982120583 ps
CPU time 3.77 seconds
Started Jun 06 01:57:54 PM PDT 24
Finished Jun 06 01:57:59 PM PDT 24
Peak memory 225172 kb
Host smart-c57f72cc-96bf-45eb-9c5b-948de9a5db09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214062497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4214062497
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.4014404258
Short name T615
Test name
Test status
Simulation time 13345382 ps
CPU time 0.75 seconds
Started Jun 06 01:57:45 PM PDT 24
Finished Jun 06 01:57:47 PM PDT 24
Peak memory 206252 kb
Host smart-97d8c3ee-0842-4996-800e-d993190b57d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014404258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.4014404258
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.862292579
Short name T639
Test name
Test status
Simulation time 3157835508 ps
CPU time 58.47 seconds
Started Jun 06 01:57:56 PM PDT 24
Finished Jun 06 01:58:56 PM PDT 24
Peak memory 251256 kb
Host smart-959f4a13-208e-41a3-a656-3db52b1cb9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862292579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.862292579
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.244622304
Short name T174
Test name
Test status
Simulation time 2651635102 ps
CPU time 30.85 seconds
Started Jun 06 01:57:58 PM PDT 24
Finished Jun 06 01:58:30 PM PDT 24
Peak memory 249896 kb
Host smart-abb26916-080b-492e-969a-c1a651878d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244622304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.244622304
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.25015743
Short name T50
Test name
Test status
Simulation time 33368027512 ps
CPU time 168.14 seconds
Started Jun 06 01:57:53 PM PDT 24
Finished Jun 06 02:00:43 PM PDT 24
Peak memory 257052 kb
Host smart-5d746400-991d-4dc6-9b19-96e8750f9b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25015743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.25015743
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.324092080
Short name T11
Test name
Test status
Simulation time 215886427 ps
CPU time 4.33 seconds
Started Jun 06 01:57:56 PM PDT 24
Finished Jun 06 01:58:02 PM PDT 24
Peak memory 236404 kb
Host smart-6d5fcf26-e484-4008-ae7d-80990da7afc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324092080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.324092080
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2247689823
Short name T905
Test name
Test status
Simulation time 644702285 ps
CPU time 2.96 seconds
Started Jun 06 01:57:53 PM PDT 24
Finished Jun 06 01:57:58 PM PDT 24
Peak memory 219336 kb
Host smart-c6f7350e-3ff6-44e0-aea0-c7a4360e0c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247689823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2247689823
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2511264130
Short name T519
Test name
Test status
Simulation time 40521002784 ps
CPU time 28.87 seconds
Started Jun 06 01:57:50 PM PDT 24
Finished Jun 06 01:58:21 PM PDT 24
Peak memory 240948 kb
Host smart-6b8dbbd0-7b5e-4eb8-8081-948078c52cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511264130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2511264130
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1341200009
Short name T375
Test name
Test status
Simulation time 935029491 ps
CPU time 9.74 seconds
Started Jun 06 01:57:54 PM PDT 24
Finished Jun 06 01:58:05 PM PDT 24
Peak memory 223648 kb
Host smart-a05cd87c-fcc1-481c-9581-013833eb34c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1341200009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1341200009
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1939186338
Short name T759
Test name
Test status
Simulation time 61853623 ps
CPU time 1.08 seconds
Started Jun 06 01:57:51 PM PDT 24
Finished Jun 06 01:57:54 PM PDT 24
Peak memory 207820 kb
Host smart-7bf04677-eae2-4436-8acb-229c0c94afbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939186338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1939186338
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3190334002
Short name T909
Test name
Test status
Simulation time 5051199573 ps
CPU time 10.73 seconds
Started Jun 06 01:57:39 PM PDT 24
Finished Jun 06 01:57:52 PM PDT 24
Peak memory 216992 kb
Host smart-88be8c71-6e34-47af-ba20-b71f796c9f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190334002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3190334002
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1145951955
Short name T654
Test name
Test status
Simulation time 15250581743 ps
CPU time 18.96 seconds
Started Jun 06 01:57:49 PM PDT 24
Finished Jun 06 01:58:10 PM PDT 24
Peak memory 216988 kb
Host smart-85f0fa42-15b1-4ff2-9202-ae597e6695e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145951955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1145951955
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.707389717
Short name T529
Test name
Test status
Simulation time 256331909 ps
CPU time 1.53 seconds
Started Jun 06 01:57:44 PM PDT 24
Finished Jun 06 01:57:47 PM PDT 24
Peak memory 216936 kb
Host smart-7a091023-f03a-47bf-bafe-9cb385e2f467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707389717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.707389717
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3281963268
Short name T438
Test name
Test status
Simulation time 166198852 ps
CPU time 0.87 seconds
Started Jun 06 01:57:50 PM PDT 24
Finished Jun 06 01:57:52 PM PDT 24
Peak memory 206560 kb
Host smart-285291fe-6d6b-4259-b7db-fe5afd98221e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281963268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3281963268
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1740108702
Short name T898
Test name
Test status
Simulation time 1173897269 ps
CPU time 4.8 seconds
Started Jun 06 01:57:53 PM PDT 24
Finished Jun 06 01:57:59 PM PDT 24
Peak memory 225180 kb
Host smart-b2ef937a-1ee8-4015-8979-b0700af5031d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740108702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1740108702
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.619280830
Short name T159
Test name
Test status
Simulation time 33635640 ps
CPU time 0.75 seconds
Started Jun 06 01:57:57 PM PDT 24
Finished Jun 06 01:57:59 PM PDT 24
Peak memory 206464 kb
Host smart-86cdb6c0-8135-4662-8f55-1a12fc569b7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619280830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.619280830
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1096829462
Short name T570
Test name
Test status
Simulation time 60227235 ps
CPU time 2.32 seconds
Started Jun 06 01:58:04 PM PDT 24
Finished Jun 06 01:58:07 PM PDT 24
Peak memory 233256 kb
Host smart-8124c1b7-bd70-41f8-b5dc-b2b19a85a6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096829462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1096829462
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2688130306
Short name T849
Test name
Test status
Simulation time 15395885 ps
CPU time 0.76 seconds
Started Jun 06 01:57:51 PM PDT 24
Finished Jun 06 01:57:54 PM PDT 24
Peak memory 207224 kb
Host smart-813a5e41-2d0f-40ba-806f-f23b38aafed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688130306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2688130306
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.4162680849
Short name T576
Test name
Test status
Simulation time 2553249186 ps
CPU time 15.46 seconds
Started Jun 06 01:57:59 PM PDT 24
Finished Jun 06 01:58:16 PM PDT 24
Peak memory 239096 kb
Host smart-0fcdeb55-0958-400a-8cfc-c801dc63522b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162680849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.4162680849
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2574629287
Short name T335
Test name
Test status
Simulation time 568807346 ps
CPU time 6.45 seconds
Started Jun 06 01:57:56 PM PDT 24
Finished Jun 06 01:58:03 PM PDT 24
Peak memory 234768 kb
Host smart-8c1b2b9d-532d-477d-9a1c-ec8b2408a53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574629287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2574629287
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3989319483
Short name T915
Test name
Test status
Simulation time 135984028 ps
CPU time 3.33 seconds
Started Jun 06 01:57:57 PM PDT 24
Finished Jun 06 01:58:02 PM PDT 24
Peak memory 233332 kb
Host smart-93b34e10-4132-45ea-bbac-dcda858acb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989319483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3989319483
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1289309482
Short name T500
Test name
Test status
Simulation time 44310575 ps
CPU time 2.84 seconds
Started Jun 06 01:57:57 PM PDT 24
Finished Jun 06 01:58:01 PM PDT 24
Peak memory 233456 kb
Host smart-5f256296-ceb6-47dd-91e9-33dea34e7973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289309482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1289309482
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1633706133
Short name T813
Test name
Test status
Simulation time 47257439 ps
CPU time 2.78 seconds
Started Jun 06 01:57:57 PM PDT 24
Finished Jun 06 01:58:01 PM PDT 24
Peak memory 228088 kb
Host smart-704def2c-cfcd-48da-ada9-4dfd3e9ebbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633706133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1633706133
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1542055502
Short name T427
Test name
Test status
Simulation time 47540597367 ps
CPU time 28.63 seconds
Started Jun 06 01:57:57 PM PDT 24
Finished Jun 06 01:58:27 PM PDT 24
Peak memory 234416 kb
Host smart-bb14b500-897d-4a33-b166-a96ee6100174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542055502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1542055502
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3160833753
Short name T391
Test name
Test status
Simulation time 3990061248 ps
CPU time 10.67 seconds
Started Jun 06 01:57:59 PM PDT 24
Finished Jun 06 01:58:10 PM PDT 24
Peak memory 219748 kb
Host smart-0504bf8d-3cc8-4708-94dc-fd2a64f42edf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3160833753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3160833753
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.58574627
Short name T27
Test name
Test status
Simulation time 243731967489 ps
CPU time 530.1 seconds
Started Jun 06 01:58:00 PM PDT 24
Finished Jun 06 02:06:51 PM PDT 24
Peak memory 262364 kb
Host smart-dc7b01c4-1b78-4611-89a5-f6cbc332fe9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58574627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress
_all.58574627
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1514990464
Short name T339
Test name
Test status
Simulation time 16447201506 ps
CPU time 29.91 seconds
Started Jun 06 01:57:55 PM PDT 24
Finished Jun 06 01:58:26 PM PDT 24
Peak memory 217424 kb
Host smart-977fc392-87cf-4eb4-a66f-bb25b26c92c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514990464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1514990464
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2204867203
Short name T891
Test name
Test status
Simulation time 2887775858 ps
CPU time 4.49 seconds
Started Jun 06 01:57:51 PM PDT 24
Finished Jun 06 01:57:57 PM PDT 24
Peak memory 217060 kb
Host smart-ac3f411b-a99b-40dd-8e7b-6f59e9bc02b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204867203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2204867203
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1956969568
Short name T392
Test name
Test status
Simulation time 348927654 ps
CPU time 2.67 seconds
Started Jun 06 01:57:56 PM PDT 24
Finished Jun 06 01:58:00 PM PDT 24
Peak memory 216976 kb
Host smart-cb8533a6-c7cd-4517-952e-b3cd3349a5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956969568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1956969568
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.894315750
Short name T620
Test name
Test status
Simulation time 32596055 ps
CPU time 0.84 seconds
Started Jun 06 01:57:52 PM PDT 24
Finished Jun 06 01:57:54 PM PDT 24
Peak memory 206560 kb
Host smart-ed0e5da5-46c6-4a44-9eaa-96d4eaf53a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894315750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.894315750
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1842603875
Short name T922
Test name
Test status
Simulation time 11134639460 ps
CPU time 12.55 seconds
Started Jun 06 01:57:52 PM PDT 24
Finished Jun 06 01:58:06 PM PDT 24
Peak memory 233492 kb
Host smart-7f3131d7-9b52-4acb-9ab8-b2290d07cd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842603875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1842603875
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4099924476
Short name T476
Test name
Test status
Simulation time 11536914 ps
CPU time 0.71 seconds
Started Jun 06 01:57:54 PM PDT 24
Finished Jun 06 01:57:56 PM PDT 24
Peak memory 206428 kb
Host smart-57fcafb4-7175-49dd-a483-033d64dbae04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099924476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4099924476
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1808167256
Short name T802
Test name
Test status
Simulation time 1342683803 ps
CPU time 4.16 seconds
Started Jun 06 01:57:55 PM PDT 24
Finished Jun 06 01:58:01 PM PDT 24
Peak memory 233308 kb
Host smart-46dd2786-20a9-48e1-9a1f-59d9019a78bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808167256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1808167256
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2612053369
Short name T51
Test name
Test status
Simulation time 14573981 ps
CPU time 0.84 seconds
Started Jun 06 01:57:54 PM PDT 24
Finished Jun 06 01:57:57 PM PDT 24
Peak memory 207224 kb
Host smart-3955b774-9ffa-4f08-81dc-8ffc653290fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612053369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2612053369
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3308546952
Short name T236
Test name
Test status
Simulation time 189508649741 ps
CPU time 163.64 seconds
Started Jun 06 01:57:55 PM PDT 24
Finished Jun 06 02:00:40 PM PDT 24
Peak memory 257396 kb
Host smart-1c03919a-a413-4b91-9243-713336769f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308546952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3308546952
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.684968414
Short name T820
Test name
Test status
Simulation time 23603839932 ps
CPU time 95.17 seconds
Started Jun 06 01:58:06 PM PDT 24
Finished Jun 06 01:59:42 PM PDT 24
Peak memory 260420 kb
Host smart-ffae8153-a262-4175-b97d-c7a0a5198054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684968414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.684968414
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3342992774
Short name T369
Test name
Test status
Simulation time 1168606621 ps
CPU time 4.17 seconds
Started Jun 06 01:58:07 PM PDT 24
Finished Jun 06 01:58:12 PM PDT 24
Peak memory 225160 kb
Host smart-1a804eba-ef60-4a9e-957d-05f193d6cc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342992774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3342992774
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.51872132
Short name T445
Test name
Test status
Simulation time 75654529 ps
CPU time 2.1 seconds
Started Jun 06 01:57:55 PM PDT 24
Finished Jun 06 01:57:58 PM PDT 24
Peak memory 225096 kb
Host smart-68e2f08c-239e-4e4c-a548-898ab6457577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51872132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.51872132
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3974118922
Short name T676
Test name
Test status
Simulation time 1782200452 ps
CPU time 8.58 seconds
Started Jun 06 01:57:56 PM PDT 24
Finished Jun 06 01:58:06 PM PDT 24
Peak memory 233300 kb
Host smart-1027d30d-d556-4e85-927a-27d049fa56a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974118922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3974118922
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.751762549
Short name T581
Test name
Test status
Simulation time 702459006 ps
CPU time 4.79 seconds
Started Jun 06 01:57:56 PM PDT 24
Finished Jun 06 01:58:02 PM PDT 24
Peak memory 241036 kb
Host smart-7782cf4a-0c7a-4ea1-9bfa-2b1f6a13e59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751762549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.751762549
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3408023280
Short name T539
Test name
Test status
Simulation time 229158097 ps
CPU time 3.71 seconds
Started Jun 06 01:57:55 PM PDT 24
Finished Jun 06 01:58:01 PM PDT 24
Peak memory 223744 kb
Host smart-446f0b63-56f0-4181-932c-8accd6ab7772
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3408023280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3408023280
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1228592913
Short name T152
Test name
Test status
Simulation time 313781465 ps
CPU time 1.02 seconds
Started Jun 06 01:57:56 PM PDT 24
Finished Jun 06 01:57:58 PM PDT 24
Peak memory 207568 kb
Host smart-dce3c626-7342-4060-901d-77aa651bd8e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228592913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1228592913
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3980547118
Short name T770
Test name
Test status
Simulation time 416050147 ps
CPU time 5.86 seconds
Started Jun 06 01:57:50 PM PDT 24
Finished Jun 06 01:57:58 PM PDT 24
Peak memory 217040 kb
Host smart-7719e733-b0a7-4a1b-81f9-b30c0ea55a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980547118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3980547118
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3269678212
Short name T9
Test name
Test status
Simulation time 422305437 ps
CPU time 2.09 seconds
Started Jun 06 01:57:53 PM PDT 24
Finished Jun 06 01:57:57 PM PDT 24
Peak memory 216948 kb
Host smart-ce03c61c-19d3-4be8-ad72-a4f952551782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269678212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3269678212
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3719351379
Short name T399
Test name
Test status
Simulation time 37713135 ps
CPU time 0.73 seconds
Started Jun 06 01:57:54 PM PDT 24
Finished Jun 06 01:57:56 PM PDT 24
Peak memory 206276 kb
Host smart-beac31d7-be1a-4b22-a58b-b45afcc99c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719351379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3719351379
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2052221712
Short name T421
Test name
Test status
Simulation time 65588001 ps
CPU time 0.86 seconds
Started Jun 06 01:57:54 PM PDT 24
Finished Jun 06 01:57:57 PM PDT 24
Peak memory 206520 kb
Host smart-27843a9d-5c2c-4b02-b710-2816823d921d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052221712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2052221712
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3582748962
Short name T904
Test name
Test status
Simulation time 13040621988 ps
CPU time 24.79 seconds
Started Jun 06 01:57:57 PM PDT 24
Finished Jun 06 01:58:23 PM PDT 24
Peak memory 241260 kb
Host smart-f30a771a-6059-40f8-9c30-91fa79547e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582748962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3582748962
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.246061854
Short name T667
Test name
Test status
Simulation time 35080714 ps
CPU time 0.74 seconds
Started Jun 06 01:57:59 PM PDT 24
Finished Jun 06 01:58:00 PM PDT 24
Peak memory 206092 kb
Host smart-34e65bfe-cd28-46c8-8df9-071fe1ca36cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246061854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.246061854
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1779998466
Short name T467
Test name
Test status
Simulation time 44231776 ps
CPU time 0.78 seconds
Started Jun 06 01:57:54 PM PDT 24
Finished Jun 06 01:57:57 PM PDT 24
Peak memory 207564 kb
Host smart-92df61d4-4763-4285-8682-a1e821606439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779998466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1779998466
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2654488129
Short name T859
Test name
Test status
Simulation time 2415552977 ps
CPU time 57.83 seconds
Started Jun 06 01:57:56 PM PDT 24
Finished Jun 06 01:58:55 PM PDT 24
Peak memory 249408 kb
Host smart-994f890b-740f-4e4b-9cef-469d2174f913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654488129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2654488129
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3549800875
Short name T264
Test name
Test status
Simulation time 1104816545 ps
CPU time 29.09 seconds
Started Jun 06 01:58:05 PM PDT 24
Finished Jun 06 01:58:35 PM PDT 24
Peak memory 254624 kb
Host smart-7ce48f50-76f7-401c-8161-088ce9bad4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549800875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3549800875
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2714379607
Short name T867
Test name
Test status
Simulation time 26518098192 ps
CPU time 276.96 seconds
Started Jun 06 01:58:08 PM PDT 24
Finished Jun 06 02:02:45 PM PDT 24
Peak memory 253872 kb
Host smart-5602732e-1080-4ef0-b9a6-a3f1c987a0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714379607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2714379607
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4138949125
Short name T494
Test name
Test status
Simulation time 3504784821 ps
CPU time 16.35 seconds
Started Jun 06 01:57:52 PM PDT 24
Finished Jun 06 01:58:10 PM PDT 24
Peak memory 241600 kb
Host smart-03b70582-9f38-484c-ac5d-504769716283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138949125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4138949125
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4164571341
Short name T660
Test name
Test status
Simulation time 56445681 ps
CPU time 2.19 seconds
Started Jun 06 01:57:55 PM PDT 24
Finished Jun 06 01:57:59 PM PDT 24
Peak memory 233252 kb
Host smart-4faf827a-d048-4465-9e81-5534c9f22988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164571341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4164571341
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.682992023
Short name T95
Test name
Test status
Simulation time 2510680014 ps
CPU time 10.25 seconds
Started Jun 06 01:57:55 PM PDT 24
Finished Jun 06 01:58:07 PM PDT 24
Peak memory 225212 kb
Host smart-d570d567-f2b4-4e85-8df3-d7ed6ebbf8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682992023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.682992023
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1513578491
Short name T880
Test name
Test status
Simulation time 1004400699 ps
CPU time 3.19 seconds
Started Jun 06 01:58:03 PM PDT 24
Finished Jun 06 01:58:07 PM PDT 24
Peak memory 233380 kb
Host smart-d9f9a465-bc50-4cfd-8ad5-c4e0a5df697d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513578491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1513578491
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3546688047
Short name T925
Test name
Test status
Simulation time 32235027 ps
CPU time 2.41 seconds
Started Jun 06 01:57:52 PM PDT 24
Finished Jun 06 01:57:56 PM PDT 24
Peak memory 233436 kb
Host smart-37e85c9b-59e6-4b20-83e8-b347abca51cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546688047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3546688047
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.989048325
Short name T571
Test name
Test status
Simulation time 826773056 ps
CPU time 9.72 seconds
Started Jun 06 01:57:57 PM PDT 24
Finished Jun 06 01:58:08 PM PDT 24
Peak memory 222576 kb
Host smart-82b01f8d-ade0-4a84-bca1-cc7b6a697fc9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=989048325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.989048325
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.4007450541
Short name T150
Test name
Test status
Simulation time 560928000 ps
CPU time 4.74 seconds
Started Jun 06 01:58:02 PM PDT 24
Finished Jun 06 01:58:08 PM PDT 24
Peak memory 225128 kb
Host smart-30aff034-f7da-4a61-a83f-498232021205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007450541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.4007450541
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1490590081
Short name T20
Test name
Test status
Simulation time 4155194995 ps
CPU time 29.51 seconds
Started Jun 06 01:57:52 PM PDT 24
Finished Jun 06 01:58:23 PM PDT 24
Peak memory 217024 kb
Host smart-4e0210c2-424d-45b4-85a8-e368b736854a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490590081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1490590081
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1959422242
Short name T559
Test name
Test status
Simulation time 900023783 ps
CPU time 6.49 seconds
Started Jun 06 01:57:55 PM PDT 24
Finished Jun 06 01:58:03 PM PDT 24
Peak memory 217036 kb
Host smart-d3dc1ce6-a6b1-4382-b3c2-63d9a30cb6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959422242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1959422242
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1497521314
Short name T658
Test name
Test status
Simulation time 26360201 ps
CPU time 0.76 seconds
Started Jun 06 01:57:52 PM PDT 24
Finished Jun 06 01:57:55 PM PDT 24
Peak memory 206528 kb
Host smart-e5fc7f4f-819a-4aea-8279-7565c92bc22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497521314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1497521314
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2777369271
Short name T817
Test name
Test status
Simulation time 117442264 ps
CPU time 0.95 seconds
Started Jun 06 01:58:00 PM PDT 24
Finished Jun 06 01:58:02 PM PDT 24
Peak memory 206512 kb
Host smart-f9ef14ac-1b28-4829-a16c-fde89bf94dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777369271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2777369271
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.362109650
Short name T194
Test name
Test status
Simulation time 1605978060 ps
CPU time 12.62 seconds
Started Jun 06 01:57:58 PM PDT 24
Finished Jun 06 01:58:11 PM PDT 24
Peak memory 233352 kb
Host smart-5f7f4c04-ae3a-4a4e-b8a8-941349592b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362109650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.362109650
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2191038284
Short name T644
Test name
Test status
Simulation time 15021795 ps
CPU time 0.71 seconds
Started Jun 06 01:57:08 PM PDT 24
Finished Jun 06 01:57:10 PM PDT 24
Peak memory 206056 kb
Host smart-79a830d6-0ecc-45fd-8f73-c783bdcd60df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191038284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
191038284
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2834322417
Short name T110
Test name
Test status
Simulation time 90703728 ps
CPU time 3.89 seconds
Started Jun 06 01:57:08 PM PDT 24
Finished Jun 06 01:57:13 PM PDT 24
Peak memory 233432 kb
Host smart-07783a77-a349-4f6c-900c-6a44e75aff0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834322417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2834322417
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1902035767
Short name T804
Test name
Test status
Simulation time 17905711 ps
CPU time 0.8 seconds
Started Jun 06 01:57:09 PM PDT 24
Finished Jun 06 01:57:11 PM PDT 24
Peak memory 207552 kb
Host smart-218b2769-e50b-4d2c-8dd2-efdc1d42249b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902035767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1902035767
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1640164825
Short name T374
Test name
Test status
Simulation time 76622100 ps
CPU time 0.78 seconds
Started Jun 06 01:57:05 PM PDT 24
Finished Jun 06 01:57:07 PM PDT 24
Peak memory 216836 kb
Host smart-1e515e57-9ae3-44a6-99a1-b529097e6cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640164825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1640164825
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1695659196
Short name T45
Test name
Test status
Simulation time 14685265659 ps
CPU time 141.84 seconds
Started Jun 06 01:57:09 PM PDT 24
Finished Jun 06 01:59:32 PM PDT 24
Peak memory 251352 kb
Host smart-f4351c3a-c99a-4d46-8c30-692c92829a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695659196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1695659196
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.660001167
Short name T824
Test name
Test status
Simulation time 21490472042 ps
CPU time 180.84 seconds
Started Jun 06 01:57:14 PM PDT 24
Finished Jun 06 02:00:16 PM PDT 24
Peak memory 235712 kb
Host smart-251633e1-77d0-43f5-b4e1-bb2f1ed13f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660001167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
660001167
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2388332715
Short name T794
Test name
Test status
Simulation time 421350735 ps
CPU time 8.73 seconds
Started Jun 06 01:57:02 PM PDT 24
Finished Jun 06 01:57:12 PM PDT 24
Peak memory 233304 kb
Host smart-676e190d-9106-4ecf-b89c-7357321da7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388332715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2388332715
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1224673342
Short name T309
Test name
Test status
Simulation time 630160042 ps
CPU time 5.36 seconds
Started Jun 06 01:57:09 PM PDT 24
Finished Jun 06 01:57:15 PM PDT 24
Peak memory 225164 kb
Host smart-0e5fdd17-e4f2-42e5-a227-4a582a752d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224673342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1224673342
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3432911006
Short name T815
Test name
Test status
Simulation time 6074781792 ps
CPU time 37.62 seconds
Started Jun 06 01:57:08 PM PDT 24
Finished Jun 06 01:57:46 PM PDT 24
Peak memory 233484 kb
Host smart-e39bdf78-db0a-48df-9770-8f516fcd8c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432911006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3432911006
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3166106836
Short name T616
Test name
Test status
Simulation time 8366202527 ps
CPU time 15.37 seconds
Started Jun 06 01:57:09 PM PDT 24
Finished Jun 06 01:57:26 PM PDT 24
Peak memory 239008 kb
Host smart-cf6d69b1-de12-47af-80c9-fb6c80629902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166106836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3166106836
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.576582392
Short name T791
Test name
Test status
Simulation time 5180661301 ps
CPU time 8.78 seconds
Started Jun 06 01:56:59 PM PDT 24
Finished Jun 06 01:57:09 PM PDT 24
Peak memory 241440 kb
Host smart-9884476b-3e00-4dff-ab47-d0740227f4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576582392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.576582392
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.598419780
Short name T796
Test name
Test status
Simulation time 4897126763 ps
CPU time 8.21 seconds
Started Jun 06 01:57:09 PM PDT 24
Finished Jun 06 01:57:19 PM PDT 24
Peak memory 223684 kb
Host smart-94a1f5ee-e5a5-499b-8355-32828e83d09d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=598419780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.598419780
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3391509861
Short name T66
Test name
Test status
Simulation time 154681795 ps
CPU time 0.93 seconds
Started Jun 06 01:57:16 PM PDT 24
Finished Jun 06 01:57:19 PM PDT 24
Peak memory 235700 kb
Host smart-8b962be3-1e7c-4d2e-b055-cf7887e47e96
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391509861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3391509861
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.965367079
Short name T830
Test name
Test status
Simulation time 2173952924 ps
CPU time 27.6 seconds
Started Jun 06 01:57:10 PM PDT 24
Finished Jun 06 01:57:39 PM PDT 24
Peak memory 217084 kb
Host smart-2afc4742-eb1a-4a4a-8a14-634b8644b5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965367079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.965367079
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3948037035
Short name T768
Test name
Test status
Simulation time 30298972309 ps
CPU time 20.13 seconds
Started Jun 06 01:57:05 PM PDT 24
Finished Jun 06 01:57:26 PM PDT 24
Peak memory 217128 kb
Host smart-51475bb6-eedf-45ea-b46a-5ba74d8181bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948037035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3948037035
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1540164754
Short name T656
Test name
Test status
Simulation time 90684642 ps
CPU time 1.98 seconds
Started Jun 06 01:57:07 PM PDT 24
Finished Jun 06 01:57:10 PM PDT 24
Peak memory 216960 kb
Host smart-adbe5936-c4d4-41b1-b306-750d3f2d6fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540164754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1540164754
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1141673721
Short name T862
Test name
Test status
Simulation time 52056302 ps
CPU time 0.76 seconds
Started Jun 06 01:57:08 PM PDT 24
Finished Jun 06 01:57:09 PM PDT 24
Peak memory 206584 kb
Host smart-4f0d22c9-9fd9-4f70-aa9b-4d99271b8a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141673721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1141673721
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.762765578
Short name T621
Test name
Test status
Simulation time 16825680129 ps
CPU time 25.49 seconds
Started Jun 06 01:57:08 PM PDT 24
Finished Jun 06 01:57:34 PM PDT 24
Peak memory 233420 kb
Host smart-0f29a8f4-6176-410d-a8c3-0c9b77ede982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762765578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.762765578
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.4249721195
Short name T712
Test name
Test status
Simulation time 14709873 ps
CPU time 0.72 seconds
Started Jun 06 01:57:58 PM PDT 24
Finished Jun 06 01:58:00 PM PDT 24
Peak memory 205528 kb
Host smart-ea40e05f-d111-4c7f-8dfd-38047a99aa8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249721195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
4249721195
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.734157479
Short name T206
Test name
Test status
Simulation time 1029978355 ps
CPU time 3.44 seconds
Started Jun 06 01:58:00 PM PDT 24
Finished Jun 06 01:58:04 PM PDT 24
Peak memory 225236 kb
Host smart-74f221a9-fe2a-4871-821d-7d4594eb1d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734157479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.734157479
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.601508086
Short name T814
Test name
Test status
Simulation time 60529747 ps
CPU time 0.8 seconds
Started Jun 06 01:58:06 PM PDT 24
Finished Jun 06 01:58:08 PM PDT 24
Peak memory 207528 kb
Host smart-ba0541b7-294b-4c12-be0b-c7b3d96cda9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601508086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.601508086
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1489716627
Short name T175
Test name
Test status
Simulation time 1697709481 ps
CPU time 12.57 seconds
Started Jun 06 01:58:02 PM PDT 24
Finished Jun 06 01:58:16 PM PDT 24
Peak memory 239152 kb
Host smart-ce2b0557-3c94-488f-965f-ae5ce22e087b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489716627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1489716627
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.837056264
Short name T605
Test name
Test status
Simulation time 1652048147 ps
CPU time 8.98 seconds
Started Jun 06 01:58:04 PM PDT 24
Finished Jun 06 01:58:14 PM PDT 24
Peak memory 218176 kb
Host smart-aa078ea4-2420-4419-b311-8e6b3737a5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837056264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.837056264
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.585140556
Short name T440
Test name
Test status
Simulation time 6565059707 ps
CPU time 34.54 seconds
Started Jun 06 01:58:10 PM PDT 24
Finished Jun 06 01:58:46 PM PDT 24
Peak memory 256456 kb
Host smart-34ae1c19-527a-4d02-bcab-eb23ca644255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585140556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.585140556
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2628540522
Short name T642
Test name
Test status
Simulation time 348799258 ps
CPU time 4.23 seconds
Started Jun 06 01:57:59 PM PDT 24
Finished Jun 06 01:58:04 PM PDT 24
Peak memory 241520 kb
Host smart-ab9f3a2b-26cc-47b5-b873-2426ada1fd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628540522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2628540522
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.924922597
Short name T48
Test name
Test status
Simulation time 328113009 ps
CPU time 3.7 seconds
Started Jun 06 01:58:02 PM PDT 24
Finished Jun 06 01:58:07 PM PDT 24
Peak memory 233400 kb
Host smart-bc33e453-6e32-4fc2-93a6-920b2203e7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924922597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.924922597
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1745480505
Short name T88
Test name
Test status
Simulation time 1461792805 ps
CPU time 17.01 seconds
Started Jun 06 01:57:58 PM PDT 24
Finished Jun 06 01:58:17 PM PDT 24
Peak memory 233404 kb
Host smart-51803ae9-0bb9-4167-82ca-9bd8c386d310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745480505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1745480505
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1942810475
Short name T606
Test name
Test status
Simulation time 13244461173 ps
CPU time 11.48 seconds
Started Jun 06 01:58:06 PM PDT 24
Finished Jun 06 01:58:19 PM PDT 24
Peak memory 225180 kb
Host smart-6b0ac954-e473-4aed-84b8-870cdaa752dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942810475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1942810475
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1532227073
Short name T550
Test name
Test status
Simulation time 24222275303 ps
CPU time 15.89 seconds
Started Jun 06 01:58:01 PM PDT 24
Finished Jun 06 01:58:18 PM PDT 24
Peak memory 233440 kb
Host smart-e011e497-84ba-431f-ad6d-e65590ecb962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532227073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1532227073
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.4010527905
Short name T552
Test name
Test status
Simulation time 892560471 ps
CPU time 6.11 seconds
Started Jun 06 01:57:56 PM PDT 24
Finished Jun 06 01:58:04 PM PDT 24
Peak memory 222904 kb
Host smart-452617c3-6c5a-4098-bdc0-68f44dbe87dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4010527905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.4010527905
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.221373756
Short name T643
Test name
Test status
Simulation time 161725975 ps
CPU time 0.91 seconds
Started Jun 06 01:57:59 PM PDT 24
Finished Jun 06 01:58:01 PM PDT 24
Peak memory 207260 kb
Host smart-06ac011c-11ca-48d0-a12c-0046306f7c77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221373756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.221373756
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.440596533
Short name T340
Test name
Test status
Simulation time 11536045176 ps
CPU time 37.21 seconds
Started Jun 06 01:58:00 PM PDT 24
Finished Jun 06 01:58:38 PM PDT 24
Peak memory 217084 kb
Host smart-c6b0738c-1585-41cd-9a5b-c66b723c421c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440596533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.440596533
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3043256893
Short name T53
Test name
Test status
Simulation time 76127705 ps
CPU time 0.71 seconds
Started Jun 06 01:58:01 PM PDT 24
Finished Jun 06 01:58:02 PM PDT 24
Peak memory 206336 kb
Host smart-051d6052-23e3-44ba-b995-04ae1ad3d4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043256893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3043256893
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1542787858
Short name T585
Test name
Test status
Simulation time 1450346208 ps
CPU time 2.99 seconds
Started Jun 06 01:58:01 PM PDT 24
Finished Jun 06 01:58:04 PM PDT 24
Peak memory 216992 kb
Host smart-01fc2cf2-dfd4-4ed9-a569-b2f6f1ca1194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542787858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1542787858
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.36255726
Short name T583
Test name
Test status
Simulation time 64884780 ps
CPU time 0.9 seconds
Started Jun 06 01:57:55 PM PDT 24
Finished Jun 06 01:57:58 PM PDT 24
Peak memory 206532 kb
Host smart-ccbae135-2ad5-40af-abcb-4bbcf4b75ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36255726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.36255726
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1502328419
Short name T169
Test name
Test status
Simulation time 9500682757 ps
CPU time 10.43 seconds
Started Jun 06 01:58:00 PM PDT 24
Finished Jun 06 01:58:11 PM PDT 24
Peak memory 225464 kb
Host smart-deaf8ada-f577-4551-b15c-626773cd0da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502328419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1502328419
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3611327233
Short name T348
Test name
Test status
Simulation time 11689570 ps
CPU time 0.7 seconds
Started Jun 06 01:57:57 PM PDT 24
Finished Jun 06 01:57:59 PM PDT 24
Peak memory 206128 kb
Host smart-fc031c72-af11-458e-accf-dd97c4f29d9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611327233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3611327233
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.230339963
Short name T549
Test name
Test status
Simulation time 699423264 ps
CPU time 7.76 seconds
Started Jun 06 01:58:01 PM PDT 24
Finished Jun 06 01:58:09 PM PDT 24
Peak memory 225192 kb
Host smart-b8397d7a-d486-40cb-9d27-bd6bcc5fd8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230339963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.230339963
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1712049004
Short name T495
Test name
Test status
Simulation time 28754563 ps
CPU time 0.8 seconds
Started Jun 06 01:58:07 PM PDT 24
Finished Jun 06 01:58:09 PM PDT 24
Peak memory 207292 kb
Host smart-5af18e65-88bb-40ea-803e-0217caaa5159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712049004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1712049004
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.760607939
Short name T28
Test name
Test status
Simulation time 12489146035 ps
CPU time 101.8 seconds
Started Jun 06 01:57:59 PM PDT 24
Finished Jun 06 01:59:42 PM PDT 24
Peak memory 255688 kb
Host smart-0a1c2519-facc-4099-8525-6d242f1e8a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760607939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.760607939
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2457251247
Short name T821
Test name
Test status
Simulation time 29941816008 ps
CPU time 259.45 seconds
Started Jun 06 01:58:10 PM PDT 24
Finished Jun 06 02:02:31 PM PDT 24
Peak memory 251684 kb
Host smart-28cbe187-96d4-44a8-99ec-2a219e0a29a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457251247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2457251247
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3355572487
Short name T130
Test name
Test status
Simulation time 100064800855 ps
CPU time 252.48 seconds
Started Jun 06 01:58:11 PM PDT 24
Finished Jun 06 02:02:25 PM PDT 24
Peak memory 250888 kb
Host smart-f334174d-2d95-4b99-a21e-d5945a0b0ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355572487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3355572487
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.442605663
Short name T143
Test name
Test status
Simulation time 468234438 ps
CPU time 3.34 seconds
Started Jun 06 01:57:58 PM PDT 24
Finished Jun 06 01:58:02 PM PDT 24
Peak memory 233416 kb
Host smart-291510aa-2ddb-4d97-8447-4de7556952dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442605663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.442605663
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1283324735
Short name T816
Test name
Test status
Simulation time 1074729192 ps
CPU time 9.14 seconds
Started Jun 06 01:58:01 PM PDT 24
Finished Jun 06 01:58:11 PM PDT 24
Peak memory 233492 kb
Host smart-b34ce7a0-5f96-4890-8a5e-8d707760b9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283324735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1283324735
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.676274576
Short name T231
Test name
Test status
Simulation time 1518520274 ps
CPU time 9.72 seconds
Started Jun 06 01:58:11 PM PDT 24
Finished Jun 06 01:58:22 PM PDT 24
Peak memory 233428 kb
Host smart-faf87cee-1ef6-4ab2-801e-664aa3552254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676274576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.676274576
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1811999626
Short name T783
Test name
Test status
Simulation time 14787971695 ps
CPU time 7.01 seconds
Started Jun 06 01:57:57 PM PDT 24
Finished Jun 06 01:58:05 PM PDT 24
Peak memory 225304 kb
Host smart-0aeea8e4-755e-43da-bed2-8f5ab11c5464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811999626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1811999626
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1332467472
Short name T688
Test name
Test status
Simulation time 9114544857 ps
CPU time 17.81 seconds
Started Jun 06 01:57:58 PM PDT 24
Finished Jun 06 01:58:17 PM PDT 24
Peak memory 240104 kb
Host smart-30f3ef70-2143-4ee4-9fb0-7fa3d499062c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332467472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1332467472
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.770183471
Short name T141
Test name
Test status
Simulation time 1593531818 ps
CPU time 13.17 seconds
Started Jun 06 01:57:58 PM PDT 24
Finished Jun 06 01:58:12 PM PDT 24
Peak memory 221040 kb
Host smart-280d2a39-6418-4678-b26c-ebe34af61b35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=770183471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.770183471
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1367878891
Short name T192
Test name
Test status
Simulation time 9474460980 ps
CPU time 71.38 seconds
Started Jun 06 01:57:58 PM PDT 24
Finished Jun 06 01:59:10 PM PDT 24
Peak memory 251920 kb
Host smart-f254fbfa-c0e2-4ad9-96b7-595e73786236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367878891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1367878891
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2033341990
Short name T337
Test name
Test status
Simulation time 63717348215 ps
CPU time 44.35 seconds
Started Jun 06 01:58:07 PM PDT 24
Finished Jun 06 01:58:52 PM PDT 24
Peak memory 217120 kb
Host smart-4f13c0b5-4377-49d2-a372-febe3904233d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033341990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2033341990
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2723737339
Short name T596
Test name
Test status
Simulation time 1676417408 ps
CPU time 7.19 seconds
Started Jun 06 01:58:01 PM PDT 24
Finished Jun 06 01:58:09 PM PDT 24
Peak memory 216996 kb
Host smart-8d2f6ead-f8f6-41fa-8cb3-b167f387cd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723737339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2723737339
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3918424564
Short name T442
Test name
Test status
Simulation time 37978372 ps
CPU time 0.85 seconds
Started Jun 06 01:57:56 PM PDT 24
Finished Jun 06 01:57:58 PM PDT 24
Peak memory 206568 kb
Host smart-3080ac7a-df61-4470-84e6-6e6bbb95b2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918424564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3918424564
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.636942969
Short name T503
Test name
Test status
Simulation time 33789834 ps
CPU time 0.76 seconds
Started Jun 06 01:58:03 PM PDT 24
Finished Jun 06 01:58:04 PM PDT 24
Peak memory 206512 kb
Host smart-2e043c63-14cb-4724-856c-a8ed3a07a357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636942969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.636942969
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1967614766
Short name T225
Test name
Test status
Simulation time 5644021019 ps
CPU time 9.65 seconds
Started Jun 06 01:58:00 PM PDT 24
Finished Jun 06 01:58:10 PM PDT 24
Peak memory 225224 kb
Host smart-59effce0-7bb5-407a-8534-6abdcfa1b658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967614766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1967614766
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2024621940
Short name T823
Test name
Test status
Simulation time 11831916 ps
CPU time 0.74 seconds
Started Jun 06 01:58:10 PM PDT 24
Finished Jun 06 01:58:11 PM PDT 24
Peak memory 206108 kb
Host smart-e65fdf8a-578e-42e7-bd54-ba420f42f785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024621940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2024621940
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.309153772
Short name T811
Test name
Test status
Simulation time 31112154 ps
CPU time 2.54 seconds
Started Jun 06 01:58:13 PM PDT 24
Finished Jun 06 01:58:17 PM PDT 24
Peak memory 233216 kb
Host smart-761ce6e5-71ba-472a-aec7-401b0ea937b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309153772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.309153772
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3589459988
Short name T359
Test name
Test status
Simulation time 113079720 ps
CPU time 0.83 seconds
Started Jun 06 01:58:00 PM PDT 24
Finished Jun 06 01:58:02 PM PDT 24
Peak memory 207260 kb
Host smart-13a44521-ea9e-47ce-b998-e24f37b61dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589459988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3589459988
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3387580445
Short name T403
Test name
Test status
Simulation time 13802660054 ps
CPU time 85.81 seconds
Started Jun 06 01:58:10 PM PDT 24
Finished Jun 06 01:59:37 PM PDT 24
Peak memory 238376 kb
Host smart-2df5776a-1ada-47a8-8a84-492eab5314d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387580445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3387580445
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.575717905
Short name T446
Test name
Test status
Simulation time 11348053603 ps
CPU time 93.13 seconds
Started Jun 06 01:58:05 PM PDT 24
Finished Jun 06 01:59:39 PM PDT 24
Peak memory 233628 kb
Host smart-768bee67-773e-4f55-a430-72ce23542365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575717905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.575717905
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1085462068
Short name T256
Test name
Test status
Simulation time 12654447507 ps
CPU time 81.52 seconds
Started Jun 06 01:58:10 PM PDT 24
Finished Jun 06 01:59:33 PM PDT 24
Peak memory 265508 kb
Host smart-37aaa99d-bcf5-4096-9cd3-05354d0aaa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085462068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1085462068
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.4048952381
Short name T334
Test name
Test status
Simulation time 1001963266 ps
CPU time 7.02 seconds
Started Jun 06 01:58:13 PM PDT 24
Finished Jun 06 01:58:21 PM PDT 24
Peak memory 233392 kb
Host smart-7e841ad6-f389-4fe0-852e-f842f0aaf542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048952381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.4048952381
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.420528794
Short name T784
Test name
Test status
Simulation time 1406232479 ps
CPU time 6.17 seconds
Started Jun 06 01:58:09 PM PDT 24
Finished Jun 06 01:58:16 PM PDT 24
Peak memory 233384 kb
Host smart-c6df21aa-7a9e-468d-9550-155cd3fcbfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420528794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.420528794
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.783277750
Short name T541
Test name
Test status
Simulation time 16307224530 ps
CPU time 9.53 seconds
Started Jun 06 01:58:02 PM PDT 24
Finished Jun 06 01:58:12 PM PDT 24
Peak memory 225240 kb
Host smart-c1b3412a-6969-4a1d-94b6-115f35748265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783277750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.783277750
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.244160983
Short name T469
Test name
Test status
Simulation time 5799797023 ps
CPU time 14.81 seconds
Started Jun 06 01:58:13 PM PDT 24
Finished Jun 06 01:58:29 PM PDT 24
Peak memory 219624 kb
Host smart-0032300b-e4b3-471e-89d9-ff875ff825ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=244160983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.244160983
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2012660384
Short name T501
Test name
Test status
Simulation time 24809984942 ps
CPU time 106.58 seconds
Started Jun 06 01:58:13 PM PDT 24
Finished Jun 06 02:00:01 PM PDT 24
Peak memory 250312 kb
Host smart-ccbaf784-1b3c-4fce-adb4-0eb5c87905bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012660384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2012660384
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1012737339
Short name T534
Test name
Test status
Simulation time 1644106320 ps
CPU time 10.27 seconds
Started Jun 06 01:57:58 PM PDT 24
Finished Jun 06 01:58:09 PM PDT 24
Peak memory 217068 kb
Host smart-0343c141-5791-4bbc-9b43-41e4d3493537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012737339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1012737339
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.460129515
Short name T935
Test name
Test status
Simulation time 1271277822 ps
CPU time 3.89 seconds
Started Jun 06 01:58:04 PM PDT 24
Finished Jun 06 01:58:09 PM PDT 24
Peak memory 216940 kb
Host smart-23ed3c9a-1aaf-496a-8b7e-7e669c811fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460129515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.460129515
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1310677615
Short name T357
Test name
Test status
Simulation time 13827261 ps
CPU time 0.73 seconds
Started Jun 06 01:58:09 PM PDT 24
Finished Jun 06 01:58:10 PM PDT 24
Peak memory 206252 kb
Host smart-f9b42a54-359b-4e32-86c1-ce043c6291d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310677615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1310677615
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.535406110
Short name T557
Test name
Test status
Simulation time 253540167 ps
CPU time 1.01 seconds
Started Jun 06 01:58:05 PM PDT 24
Finished Jun 06 01:58:07 PM PDT 24
Peak memory 206512 kb
Host smart-087b5fab-d5d3-430c-930c-1cda1e518a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535406110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.535406110
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.137623331
Short name T312
Test name
Test status
Simulation time 42971139099 ps
CPU time 13.55 seconds
Started Jun 06 01:58:15 PM PDT 24
Finished Jun 06 01:58:29 PM PDT 24
Peak memory 233412 kb
Host smart-50c0f4e7-ec9d-4c66-8479-a8f18dc4e025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137623331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.137623331
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1310797041
Short name T451
Test name
Test status
Simulation time 88148901 ps
CPU time 0.71 seconds
Started Jun 06 01:58:09 PM PDT 24
Finished Jun 06 01:58:10 PM PDT 24
Peak memory 206472 kb
Host smart-d7ce0fcd-577f-48ce-85a9-0af593481117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310797041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1310797041
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1084884427
Short name T664
Test name
Test status
Simulation time 108329521 ps
CPU time 2.99 seconds
Started Jun 06 01:58:14 PM PDT 24
Finished Jun 06 01:58:18 PM PDT 24
Peak memory 233396 kb
Host smart-1507718f-78ff-4a1b-8438-a711872402c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084884427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1084884427
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2766403212
Short name T771
Test name
Test status
Simulation time 41633302 ps
CPU time 0.79 seconds
Started Jun 06 01:58:10 PM PDT 24
Finished Jun 06 01:58:12 PM PDT 24
Peak memory 207252 kb
Host smart-7aec9f81-00e2-4dd4-9342-50b863e182fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766403212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2766403212
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.857956486
Short name T190
Test name
Test status
Simulation time 76686990586 ps
CPU time 268.96 seconds
Started Jun 06 01:58:12 PM PDT 24
Finished Jun 06 02:02:43 PM PDT 24
Peak memory 238308 kb
Host smart-2db8d8b6-411e-45db-a59d-9fb0d4f62381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857956486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.857956486
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3045852835
Short name T450
Test name
Test status
Simulation time 9936069650 ps
CPU time 25.94 seconds
Started Jun 06 01:58:10 PM PDT 24
Finished Jun 06 01:58:37 PM PDT 24
Peak memory 220020 kb
Host smart-6f4cafb8-6786-441d-addf-bd52352a2665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045852835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3045852835
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2066302110
Short name T237
Test name
Test status
Simulation time 158153893120 ps
CPU time 378.66 seconds
Started Jun 06 01:58:10 PM PDT 24
Finished Jun 06 02:04:30 PM PDT 24
Peak memory 268304 kb
Host smart-95cbd418-50cc-4af6-b71a-c94190c24729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066302110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2066302110
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1571949132
Short name T901
Test name
Test status
Simulation time 72316774 ps
CPU time 3.25 seconds
Started Jun 06 01:58:08 PM PDT 24
Finished Jun 06 01:58:12 PM PDT 24
Peak memory 233368 kb
Host smart-1b4c9ee9-b0c1-401c-8ba4-aa7ce5fe1bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571949132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1571949132
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3761790276
Short name T97
Test name
Test status
Simulation time 4525991855 ps
CPU time 9.86 seconds
Started Jun 06 01:58:05 PM PDT 24
Finished Jun 06 01:58:16 PM PDT 24
Peak memory 229920 kb
Host smart-de142795-e2eb-4d83-b751-925c1df08a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761790276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3761790276
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2405839501
Short name T548
Test name
Test status
Simulation time 3292159529 ps
CPU time 18.59 seconds
Started Jun 06 01:58:08 PM PDT 24
Finished Jun 06 01:58:28 PM PDT 24
Peak memory 249844 kb
Host smart-5fe62980-8bef-4eeb-87ba-9b464eb51d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405839501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2405839501
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.485950155
Short name T769
Test name
Test status
Simulation time 2749107805 ps
CPU time 9.2 seconds
Started Jun 06 01:58:14 PM PDT 24
Finished Jun 06 01:58:24 PM PDT 24
Peak memory 233492 kb
Host smart-4ab3eb3d-197a-4e4c-be57-8956d9891d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485950155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.485950155
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.959414786
Short name T364
Test name
Test status
Simulation time 549992808 ps
CPU time 2.21 seconds
Started Jun 06 01:58:10 PM PDT 24
Finished Jun 06 01:58:13 PM PDT 24
Peak memory 223696 kb
Host smart-6eef2c72-d971-4c79-9c23-85f7664bc06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959414786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.959414786
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.532372143
Short name T805
Test name
Test status
Simulation time 988715757 ps
CPU time 5.7 seconds
Started Jun 06 01:58:04 PM PDT 24
Finished Jun 06 01:58:10 PM PDT 24
Peak memory 219768 kb
Host smart-d77daad8-5eeb-4bbc-a77a-1c2b479f0e95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=532372143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.532372143
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.823023236
Short name T887
Test name
Test status
Simulation time 9342589266 ps
CPU time 61.21 seconds
Started Jun 06 01:58:12 PM PDT 24
Finished Jun 06 01:59:14 PM PDT 24
Peak memory 250020 kb
Host smart-5f66f640-58d2-4777-875a-9f0059f3e788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823023236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.823023236
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3950501961
Short name T536
Test name
Test status
Simulation time 1912284783 ps
CPU time 25.83 seconds
Started Jun 06 01:58:06 PM PDT 24
Finished Jun 06 01:58:33 PM PDT 24
Peak memory 217104 kb
Host smart-b97e8efb-a8eb-498f-9f34-0504df6b407d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950501961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3950501961
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3670437243
Short name T354
Test name
Test status
Simulation time 782993218 ps
CPU time 3.77 seconds
Started Jun 06 01:58:09 PM PDT 24
Finished Jun 06 01:58:14 PM PDT 24
Peak memory 217060 kb
Host smart-396c4e6d-3d15-40c2-9dfe-8c6df9ee2762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670437243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3670437243
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1967290729
Short name T751
Test name
Test status
Simulation time 66629512 ps
CPU time 1.08 seconds
Started Jun 06 01:58:12 PM PDT 24
Finished Jun 06 01:58:15 PM PDT 24
Peak memory 208336 kb
Host smart-46ede74e-2d49-43fb-a540-6f834a8f2a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967290729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1967290729
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2353608577
Short name T544
Test name
Test status
Simulation time 29614300 ps
CPU time 0.68 seconds
Started Jun 06 01:58:12 PM PDT 24
Finished Jun 06 01:58:14 PM PDT 24
Peak memory 206288 kb
Host smart-d668119b-ec2c-44a6-bcee-99f8e4a663fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353608577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2353608577
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2412500501
Short name T761
Test name
Test status
Simulation time 19274075438 ps
CPU time 18.03 seconds
Started Jun 06 01:58:11 PM PDT 24
Finished Jun 06 01:58:30 PM PDT 24
Peak memory 233492 kb
Host smart-76d22c38-7708-44da-b109-8af71b263e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412500501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2412500501
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1423826317
Short name T511
Test name
Test status
Simulation time 14272922 ps
CPU time 0.71 seconds
Started Jun 06 01:58:06 PM PDT 24
Finished Jun 06 01:58:08 PM PDT 24
Peak memory 205560 kb
Host smart-7c25fc33-a367-44f7-900d-e6061f1ce78e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423826317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1423826317
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.890906387
Short name T523
Test name
Test status
Simulation time 1056223455 ps
CPU time 2.35 seconds
Started Jun 06 01:58:10 PM PDT 24
Finished Jun 06 01:58:13 PM PDT 24
Peak memory 225200 kb
Host smart-7b73d055-bcd7-494d-950f-f99ccd27df56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890906387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.890906387
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1013794053
Short name T844
Test name
Test status
Simulation time 37569725 ps
CPU time 0.81 seconds
Started Jun 06 01:58:08 PM PDT 24
Finished Jun 06 01:58:10 PM PDT 24
Peak memory 207232 kb
Host smart-1401bb53-af74-4b72-91e1-032af48b2715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013794053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1013794053
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2463601620
Short name T487
Test name
Test status
Simulation time 29059910911 ps
CPU time 199.79 seconds
Started Jun 06 01:58:13 PM PDT 24
Finished Jun 06 02:01:34 PM PDT 24
Peak memory 251512 kb
Host smart-8d4f79d8-523f-4ad8-9857-3afddc23ce65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463601620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2463601620
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3155592911
Short name T297
Test name
Test status
Simulation time 6339903490 ps
CPU time 96.41 seconds
Started Jun 06 01:58:13 PM PDT 24
Finished Jun 06 01:59:51 PM PDT 24
Peak memory 256900 kb
Host smart-19a1a077-dcc1-41e6-88fb-778852833f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155592911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3155592911
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.4243569802
Short name T329
Test name
Test status
Simulation time 1191079708 ps
CPU time 22.26 seconds
Started Jun 06 01:58:13 PM PDT 24
Finished Jun 06 01:58:36 PM PDT 24
Peak memory 225044 kb
Host smart-29368a05-82bf-499c-86d9-a094b757332c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243569802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.4243569802
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.808721534
Short name T381
Test name
Test status
Simulation time 187856831 ps
CPU time 4.28 seconds
Started Jun 06 01:58:06 PM PDT 24
Finished Jun 06 01:58:11 PM PDT 24
Peak memory 233660 kb
Host smart-1a541060-2615-4ce0-ac1d-1cf12e55e505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808721534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.808721534
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2327847883
Short name T855
Test name
Test status
Simulation time 15317403635 ps
CPU time 19.67 seconds
Started Jun 06 01:58:08 PM PDT 24
Finished Jun 06 01:58:28 PM PDT 24
Peak memory 237732 kb
Host smart-f5bba145-0910-4262-9ec6-1c38b082c482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327847883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2327847883
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3996230563
Short name T520
Test name
Test status
Simulation time 113051316 ps
CPU time 2.69 seconds
Started Jun 06 01:58:06 PM PDT 24
Finished Jun 06 01:58:10 PM PDT 24
Peak memory 233328 kb
Host smart-7dc1aa93-6ab8-4194-8a76-2803a97f16d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996230563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3996230563
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1847007981
Short name T2
Test name
Test status
Simulation time 1308378248 ps
CPU time 6.17 seconds
Started Jun 06 01:58:07 PM PDT 24
Finished Jun 06 01:58:14 PM PDT 24
Peak memory 225240 kb
Host smart-4fda5df9-1304-41cc-b91c-9ab4d6451568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847007981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1847007981
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3354685053
Short name T556
Test name
Test status
Simulation time 5043693681 ps
CPU time 8.6 seconds
Started Jun 06 01:58:11 PM PDT 24
Finished Jun 06 01:58:21 PM PDT 24
Peak memory 220156 kb
Host smart-c42b5b06-0111-4293-bdfd-d416fa00fa62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3354685053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3354685053
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.524767950
Short name T55
Test name
Test status
Simulation time 9258814180 ps
CPU time 43.63 seconds
Started Jun 06 01:58:10 PM PDT 24
Finished Jun 06 01:58:55 PM PDT 24
Peak memory 256928 kb
Host smart-0b9ce727-c877-4fd7-badb-5f3c6ce1ef6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524767950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.524767950
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3082191502
Short name T851
Test name
Test status
Simulation time 10604867286 ps
CPU time 38.21 seconds
Started Jun 06 01:58:05 PM PDT 24
Finished Jun 06 01:58:44 PM PDT 24
Peak memory 217040 kb
Host smart-6dac842b-7017-4d71-aaca-e00228b3cb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082191502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3082191502
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2432024955
Short name T669
Test name
Test status
Simulation time 7211195641 ps
CPU time 21.62 seconds
Started Jun 06 01:58:12 PM PDT 24
Finished Jun 06 01:58:35 PM PDT 24
Peak memory 217016 kb
Host smart-21da0c00-e782-4715-9b4a-7c6e90a7504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432024955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2432024955
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.762221582
Short name T6
Test name
Test status
Simulation time 2635925004 ps
CPU time 2.06 seconds
Started Jun 06 01:58:05 PM PDT 24
Finished Jun 06 01:58:08 PM PDT 24
Peak memory 217320 kb
Host smart-4328a5aa-d67f-4b1c-9545-03a31e99e352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762221582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.762221582
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3593757110
Short name T460
Test name
Test status
Simulation time 32550823 ps
CPU time 0.84 seconds
Started Jun 06 01:58:12 PM PDT 24
Finished Jun 06 01:58:13 PM PDT 24
Peak memory 206324 kb
Host smart-575c6034-8a9e-4f8a-bd86-bd00dbb968ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593757110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3593757110
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1314078054
Short name T502
Test name
Test status
Simulation time 4776174167 ps
CPU time 8.82 seconds
Started Jun 06 01:58:08 PM PDT 24
Finished Jun 06 01:58:18 PM PDT 24
Peak memory 233448 kb
Host smart-6ec3901f-e94e-43be-ae8c-e4f8419761b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314078054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1314078054
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3097850565
Short name T480
Test name
Test status
Simulation time 48365966 ps
CPU time 0.77 seconds
Started Jun 06 01:58:23 PM PDT 24
Finished Jun 06 01:58:25 PM PDT 24
Peak memory 205500 kb
Host smart-9a56695c-b1a7-4ad1-8660-b98bd5d8adfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097850565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3097850565
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3172666091
Short name T316
Test name
Test status
Simulation time 327782959 ps
CPU time 3.49 seconds
Started Jun 06 01:58:10 PM PDT 24
Finished Jun 06 01:58:14 PM PDT 24
Peak memory 233364 kb
Host smart-736032b5-b01f-4520-839c-238df7461afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172666091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3172666091
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1650936173
Short name T872
Test name
Test status
Simulation time 40595490 ps
CPU time 0.75 seconds
Started Jun 06 01:58:06 PM PDT 24
Finished Jun 06 01:58:08 PM PDT 24
Peak memory 206504 kb
Host smart-219085a9-ee36-400f-b872-0264e0a75c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650936173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1650936173
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2580897992
Short name T382
Test name
Test status
Simulation time 11035845 ps
CPU time 0.75 seconds
Started Jun 06 01:58:17 PM PDT 24
Finished Jun 06 01:58:20 PM PDT 24
Peak memory 216576 kb
Host smart-1da809c8-253d-49a1-b455-eb18747b8349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580897992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2580897992
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2680791862
Short name T313
Test name
Test status
Simulation time 14094243837 ps
CPU time 32.82 seconds
Started Jun 06 01:58:17 PM PDT 24
Finished Jun 06 01:58:51 PM PDT 24
Peak memory 241716 kb
Host smart-323b16d0-1c28-40cf-b79f-4e085306a84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680791862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2680791862
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.803643391
Short name T172
Test name
Test status
Simulation time 33426955483 ps
CPU time 190.3 seconds
Started Jun 06 01:58:21 PM PDT 24
Finished Jun 06 02:01:32 PM PDT 24
Peak memory 255160 kb
Host smart-187552b0-3b88-4631-90d8-dfc341fc51cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803643391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.803643391
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_intercept.173243602
Short name T443
Test name
Test status
Simulation time 8392633221 ps
CPU time 18.02 seconds
Started Jun 06 01:58:12 PM PDT 24
Finished Jun 06 01:58:31 PM PDT 24
Peak memory 233516 kb
Host smart-1013ad9c-b0c3-48b9-8def-cf4208113228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173243602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.173243602
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.318104047
Short name T809
Test name
Test status
Simulation time 1185426702 ps
CPU time 3.6 seconds
Started Jun 06 01:58:09 PM PDT 24
Finished Jun 06 01:58:14 PM PDT 24
Peak memory 233432 kb
Host smart-fee7e875-476b-4741-b58c-e29bff6681f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318104047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.318104047
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2641232807
Short name T875
Test name
Test status
Simulation time 5471416132 ps
CPU time 20.12 seconds
Started Jun 06 01:58:13 PM PDT 24
Finished Jun 06 01:58:34 PM PDT 24
Peak memory 233496 kb
Host smart-18fadccc-5c8e-4487-8aa2-f044f47a8d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641232807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2641232807
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3898631803
Short name T630
Test name
Test status
Simulation time 19320585970 ps
CPU time 18.05 seconds
Started Jun 06 01:58:13 PM PDT 24
Finished Jun 06 01:58:33 PM PDT 24
Peak memory 233444 kb
Host smart-3c2a4703-8fe1-4d11-822e-4a5583c21b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898631803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3898631803
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3668340215
Short name T649
Test name
Test status
Simulation time 2750805709 ps
CPU time 9.09 seconds
Started Jun 06 01:58:19 PM PDT 24
Finished Jun 06 01:58:29 PM PDT 24
Peak memory 222660 kb
Host smart-502ad636-0e00-44e8-9bb6-475658078a24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3668340215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3668340215
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2927710330
Short name T289
Test name
Test status
Simulation time 12333864916 ps
CPU time 106.69 seconds
Started Jun 06 01:58:16 PM PDT 24
Finished Jun 06 02:00:04 PM PDT 24
Peak memory 249892 kb
Host smart-4b927a67-799c-4995-b229-30087b0e3806
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927710330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2927710330
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.28691971
Short name T435
Test name
Test status
Simulation time 11234138449 ps
CPU time 26.7 seconds
Started Jun 06 01:58:10 PM PDT 24
Finished Jun 06 01:58:38 PM PDT 24
Peak memory 217012 kb
Host smart-bb460110-5ce1-42cf-9b84-d51d7c857fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28691971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.28691971
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1525708001
Short name T727
Test name
Test status
Simulation time 3857037808 ps
CPU time 3.95 seconds
Started Jun 06 01:58:09 PM PDT 24
Finished Jun 06 01:58:14 PM PDT 24
Peak memory 217024 kb
Host smart-6ec13879-ef2f-4c73-88b0-ff3d401e806d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525708001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1525708001
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.4105505390
Short name T553
Test name
Test status
Simulation time 289224731 ps
CPU time 2.97 seconds
Started Jun 06 01:58:06 PM PDT 24
Finished Jun 06 01:58:10 PM PDT 24
Peak memory 216968 kb
Host smart-514edc71-267a-4193-8249-49e2a7ba49db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105505390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.4105505390
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2307910061
Short name T692
Test name
Test status
Simulation time 369906006 ps
CPU time 0.93 seconds
Started Jun 06 01:58:07 PM PDT 24
Finished Jun 06 01:58:09 PM PDT 24
Peak memory 207560 kb
Host smart-be5fc264-3d8c-45a2-8cfb-737fd1fb27ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307910061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2307910061
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2032099679
Short name T184
Test name
Test status
Simulation time 211598015 ps
CPU time 3.5 seconds
Started Jun 06 01:58:12 PM PDT 24
Finished Jun 06 01:58:16 PM PDT 24
Peak memory 224980 kb
Host smart-2da45870-afe1-4be4-aa92-340030e1c92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032099679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2032099679
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3663271732
Short name T930
Test name
Test status
Simulation time 32403427 ps
CPU time 0.74 seconds
Started Jun 06 01:58:20 PM PDT 24
Finished Jun 06 01:58:21 PM PDT 24
Peak memory 206048 kb
Host smart-588fd127-2967-4402-95ee-82b384415f36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663271732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3663271732
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.521613014
Short name T363
Test name
Test status
Simulation time 29929499 ps
CPU time 0.79 seconds
Started Jun 06 01:58:19 PM PDT 24
Finished Jun 06 01:58:20 PM PDT 24
Peak memory 207268 kb
Host smart-0c4e6a8d-0f1a-4e33-8f32-aba834c3df2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521613014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.521613014
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.4166124916
Short name T25
Test name
Test status
Simulation time 59510610020 ps
CPU time 189.89 seconds
Started Jun 06 01:58:47 PM PDT 24
Finished Jun 06 02:01:58 PM PDT 24
Peak memory 249852 kb
Host smart-593dc35b-ba9c-4039-9f2d-2718816a10c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166124916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.4166124916
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3570137826
Short name T874
Test name
Test status
Simulation time 6384939656 ps
CPU time 66.89 seconds
Started Jun 06 01:58:20 PM PDT 24
Finished Jun 06 01:59:27 PM PDT 24
Peak memory 249300 kb
Host smart-06bb1b1f-fde3-4151-abc4-3f0513ef2973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570137826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3570137826
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.790910648
Short name T294
Test name
Test status
Simulation time 75020294123 ps
CPU time 179.3 seconds
Started Jun 06 01:58:20 PM PDT 24
Finished Jun 06 02:01:20 PM PDT 24
Peak memory 250016 kb
Host smart-6692ccf1-f4db-4af6-a565-b10c6598e52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790910648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.790910648
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2221507040
Short name T671
Test name
Test status
Simulation time 444651167 ps
CPU time 9.26 seconds
Started Jun 06 01:58:18 PM PDT 24
Finished Jun 06 01:58:28 PM PDT 24
Peak memory 234064 kb
Host smart-4f00b1db-0fd7-4554-970b-9031a6ad4ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221507040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2221507040
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1083918040
Short name T12
Test name
Test status
Simulation time 23938176678 ps
CPU time 17.22 seconds
Started Jun 06 01:58:15 PM PDT 24
Finished Jun 06 01:58:33 PM PDT 24
Peak memory 233440 kb
Host smart-3b03355e-8f86-4da1-affa-034d2d260571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083918040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1083918040
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1799565289
Short name T228
Test name
Test status
Simulation time 21610539340 ps
CPU time 66.36 seconds
Started Jun 06 01:58:23 PM PDT 24
Finished Jun 06 01:59:30 PM PDT 24
Peak memory 241520 kb
Host smart-3406f027-a31e-41a4-99e6-511e2d96175e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799565289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1799565289
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2886528487
Short name T419
Test name
Test status
Simulation time 784356738 ps
CPU time 4.58 seconds
Started Jun 06 01:58:22 PM PDT 24
Finished Jun 06 01:58:28 PM PDT 24
Peak memory 233400 kb
Host smart-e27326d4-4c5a-4a20-86ca-ed4203527ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886528487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2886528487
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.838446205
Short name T657
Test name
Test status
Simulation time 1905519557 ps
CPU time 7.78 seconds
Started Jun 06 01:58:15 PM PDT 24
Finished Jun 06 01:58:24 PM PDT 24
Peak memory 225236 kb
Host smart-3d1c88f9-4e8c-4b0a-8820-41b00932e6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838446205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.838446205
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3622491132
Short name T139
Test name
Test status
Simulation time 127427341 ps
CPU time 3.74 seconds
Started Jun 06 01:58:20 PM PDT 24
Finished Jun 06 01:58:25 PM PDT 24
Peak memory 219776 kb
Host smart-b81ba713-12bb-4c86-83fe-34b18b6d7ff4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3622491132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3622491132
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1599276006
Short name T486
Test name
Test status
Simulation time 15713476720 ps
CPU time 42.77 seconds
Started Jun 06 01:58:15 PM PDT 24
Finished Jun 06 01:58:59 PM PDT 24
Peak memory 217100 kb
Host smart-2aed5e4d-ec6e-4adc-bff0-da6e194fa955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599276006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1599276006
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1945153796
Short name T437
Test name
Test status
Simulation time 94252443 ps
CPU time 1.49 seconds
Started Jun 06 01:58:18 PM PDT 24
Finished Jun 06 01:58:20 PM PDT 24
Peak memory 208564 kb
Host smart-669a4b8c-2075-4e06-8eda-c590a7788e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945153796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1945153796
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3826152247
Short name T706
Test name
Test status
Simulation time 63972438 ps
CPU time 1.56 seconds
Started Jun 06 01:58:21 PM PDT 24
Finished Jun 06 01:58:24 PM PDT 24
Peak memory 216968 kb
Host smart-d62ea372-0f3b-4b63-b3e6-d517a68beb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826152247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3826152247
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.196707821
Short name T675
Test name
Test status
Simulation time 13654087 ps
CPU time 0.75 seconds
Started Jun 06 01:58:17 PM PDT 24
Finished Jun 06 01:58:19 PM PDT 24
Peak memory 206484 kb
Host smart-00ee771c-22ce-490a-94ca-f46a5faf4a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196707821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.196707821
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3521252398
Short name T393
Test name
Test status
Simulation time 1091774410 ps
CPU time 4.18 seconds
Started Jun 06 01:58:15 PM PDT 24
Finished Jun 06 01:58:21 PM PDT 24
Peak memory 225232 kb
Host smart-0fb68c29-9e90-40c8-9ac6-36b3731a81b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521252398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3521252398
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3727037958
Short name T409
Test name
Test status
Simulation time 35600604 ps
CPU time 0.74 seconds
Started Jun 06 01:58:18 PM PDT 24
Finished Jun 06 01:58:20 PM PDT 24
Peak memory 206148 kb
Host smart-821cabe2-4382-45cc-81ed-7124127264ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727037958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3727037958
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.717139657
Short name T908
Test name
Test status
Simulation time 14207275 ps
CPU time 0.75 seconds
Started Jun 06 01:58:21 PM PDT 24
Finished Jun 06 01:58:23 PM PDT 24
Peak memory 207280 kb
Host smart-3263d5ed-54e1-41c8-9d08-22c2b6434542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717139657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.717139657
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.4250084030
Short name T698
Test name
Test status
Simulation time 150765867 ps
CPU time 0.89 seconds
Started Jun 06 01:58:18 PM PDT 24
Finished Jun 06 01:58:20 PM PDT 24
Peak memory 216800 kb
Host smart-7c9013ff-69eb-45cf-8558-853ebaab9218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250084030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.4250084030
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1909389494
Short name T303
Test name
Test status
Simulation time 27816543870 ps
CPU time 132.64 seconds
Started Jun 06 01:58:24 PM PDT 24
Finished Jun 06 02:00:37 PM PDT 24
Peak memory 249940 kb
Host smart-84597983-f3f8-446e-9f89-33a1bb489e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909389494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1909389494
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3278885335
Short name T291
Test name
Test status
Simulation time 6463344107 ps
CPU time 128.15 seconds
Started Jun 06 01:58:21 PM PDT 24
Finished Jun 06 02:00:30 PM PDT 24
Peak memory 250888 kb
Host smart-d54a26c5-c9a2-4cbe-bead-ecddf7d726e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278885335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3278885335
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3896948901
Short name T846
Test name
Test status
Simulation time 460122878 ps
CPU time 5.24 seconds
Started Jun 06 01:58:22 PM PDT 24
Finished Jun 06 01:58:28 PM PDT 24
Peak memory 241116 kb
Host smart-a85744ca-77cf-4892-88e7-ee16b673e177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896948901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3896948901
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.315300344
Short name T63
Test name
Test status
Simulation time 63937425 ps
CPU time 2.97 seconds
Started Jun 06 01:58:20 PM PDT 24
Finished Jun 06 01:58:24 PM PDT 24
Peak memory 233480 kb
Host smart-7706fbdd-c488-41b0-9cf3-b8afc1276d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315300344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.315300344
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1208987426
Short name T181
Test name
Test status
Simulation time 19295007431 ps
CPU time 34.28 seconds
Started Jun 06 01:58:21 PM PDT 24
Finished Jun 06 01:58:56 PM PDT 24
Peak memory 241636 kb
Host smart-607514fb-2c50-401a-bc77-b694fff76a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208987426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1208987426
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1557870969
Short name T322
Test name
Test status
Simulation time 2561549195 ps
CPU time 5.77 seconds
Started Jun 06 01:58:18 PM PDT 24
Finished Jun 06 01:58:25 PM PDT 24
Peak memory 225184 kb
Host smart-138757da-1c92-460a-b349-ef2dbaba272e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557870969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1557870969
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3669947756
Short name T180
Test name
Test status
Simulation time 202938501 ps
CPU time 2.56 seconds
Started Jun 06 01:58:16 PM PDT 24
Finished Jun 06 01:58:19 PM PDT 24
Peak memory 225144 kb
Host smart-32d0dd7f-0eca-48ad-a183-6fdc6411c963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669947756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3669947756
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2255265020
Short name T530
Test name
Test status
Simulation time 3403439591 ps
CPU time 11.74 seconds
Started Jun 06 01:58:17 PM PDT 24
Finished Jun 06 01:58:30 PM PDT 24
Peak memory 219696 kb
Host smart-9bde267f-c340-4693-8dad-26692d0fb76e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2255265020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2255265020
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1875042523
Short name T154
Test name
Test status
Simulation time 64180130 ps
CPU time 1.1 seconds
Started Jun 06 01:58:20 PM PDT 24
Finished Jun 06 01:58:22 PM PDT 24
Peak memory 207716 kb
Host smart-e957777a-1a04-43a1-842d-ad7e178d7dbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875042523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1875042523
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3833899794
Short name T416
Test name
Test status
Simulation time 3097755829 ps
CPU time 19.7 seconds
Started Jun 06 01:58:24 PM PDT 24
Finished Jun 06 01:58:44 PM PDT 24
Peak memory 217000 kb
Host smart-068e6ec6-9450-4a2b-8adb-e288e02bff0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833899794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3833899794
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3939023274
Short name T763
Test name
Test status
Simulation time 41022263593 ps
CPU time 18.71 seconds
Started Jun 06 01:58:21 PM PDT 24
Finished Jun 06 01:58:41 PM PDT 24
Peak memory 217096 kb
Host smart-8f7bd3f9-e029-4e11-ac0f-3e91117a8dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939023274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3939023274
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.194748831
Short name T773
Test name
Test status
Simulation time 94860267 ps
CPU time 1.21 seconds
Started Jun 06 01:58:21 PM PDT 24
Finished Jun 06 01:58:23 PM PDT 24
Peak memory 216792 kb
Host smart-57ab19a4-b665-41dc-aa77-832062fe9ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194748831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.194748831
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3789409633
Short name T390
Test name
Test status
Simulation time 49270998 ps
CPU time 0.76 seconds
Started Jun 06 01:58:15 PM PDT 24
Finished Jun 06 01:58:17 PM PDT 24
Peak memory 206564 kb
Host smart-a828e5b5-b4d1-4d84-b14d-007b9b565c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789409633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3789409633
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.316862821
Short name T683
Test name
Test status
Simulation time 1244002756 ps
CPU time 5.07 seconds
Started Jun 06 01:58:18 PM PDT 24
Finished Jun 06 01:58:25 PM PDT 24
Peak memory 225192 kb
Host smart-00dd1d01-a6fd-420a-8ff2-88ea7145abfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316862821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.316862821
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2521833706
Short name T360
Test name
Test status
Simulation time 73559928 ps
CPU time 0.69 seconds
Started Jun 06 01:58:28 PM PDT 24
Finished Jun 06 01:58:30 PM PDT 24
Peak memory 206088 kb
Host smart-5fc572dc-925a-465b-9867-da31cefe5a3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521833706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2521833706
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3464576065
Short name T955
Test name
Test status
Simulation time 809887602 ps
CPU time 3.86 seconds
Started Jun 06 01:58:15 PM PDT 24
Finished Jun 06 01:58:20 PM PDT 24
Peak memory 233420 kb
Host smart-3e5b2f95-6336-4271-9395-543a7a707bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464576065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3464576065
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.242579132
Short name T504
Test name
Test status
Simulation time 17393242 ps
CPU time 0.78 seconds
Started Jun 06 01:58:15 PM PDT 24
Finished Jun 06 01:58:17 PM PDT 24
Peak memory 207212 kb
Host smart-1165413d-fb82-4428-9a55-644465f87937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242579132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.242579132
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.525014383
Short name T755
Test name
Test status
Simulation time 4879095911 ps
CPU time 46.45 seconds
Started Jun 06 01:58:26 PM PDT 24
Finished Jun 06 01:59:14 PM PDT 24
Peak memory 250344 kb
Host smart-44792cee-d387-4857-95f6-0b0d7af2a5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525014383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.525014383
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2063305429
Short name T603
Test name
Test status
Simulation time 90497274916 ps
CPU time 203.2 seconds
Started Jun 06 01:58:21 PM PDT 24
Finished Jun 06 02:01:45 PM PDT 24
Peak memory 251944 kb
Host smart-0fbd25e5-08ac-4ecf-8e8a-24e8b740d4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063305429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2063305429
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3640800112
Short name T458
Test name
Test status
Simulation time 897555323 ps
CPU time 5.68 seconds
Started Jun 06 01:58:19 PM PDT 24
Finished Jun 06 01:58:26 PM PDT 24
Peak memory 237772 kb
Host smart-899195fb-db43-4db0-87d0-2f317f9cd335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640800112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3640800112
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3101566049
Short name T758
Test name
Test status
Simulation time 132008477 ps
CPU time 2 seconds
Started Jun 06 01:58:21 PM PDT 24
Finished Jun 06 01:58:24 PM PDT 24
Peak memory 225160 kb
Host smart-83a62aaf-4c1e-4a0f-af98-d8e9e2f43ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101566049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3101566049
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3140509470
Short name T588
Test name
Test status
Simulation time 289472032 ps
CPU time 9.05 seconds
Started Jun 06 01:58:17 PM PDT 24
Finished Jun 06 01:58:27 PM PDT 24
Peak memory 240632 kb
Host smart-8e89d2da-2b00-4c95-a4e3-7b4caa8412aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140509470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3140509470
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.711837117
Short name T424
Test name
Test status
Simulation time 1430733411 ps
CPU time 10.44 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:49 PM PDT 24
Peak memory 233396 kb
Host smart-bd95864a-92ea-4bd8-b0eb-0837ae5c5656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711837117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.711837117
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1819312153
Short name T318
Test name
Test status
Simulation time 8584389886 ps
CPU time 14.27 seconds
Started Jun 06 01:58:21 PM PDT 24
Finished Jun 06 01:58:36 PM PDT 24
Peak memory 225220 kb
Host smart-6e110b80-2171-4579-a452-6ce2b1ecf4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819312153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1819312153
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2286581852
Short name T894
Test name
Test status
Simulation time 563849944 ps
CPU time 7.71 seconds
Started Jun 06 01:58:18 PM PDT 24
Finished Jun 06 01:58:27 PM PDT 24
Peak memory 219600 kb
Host smart-9b2debc9-0c3c-4821-a0d6-37a410202091
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2286581852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2286581852
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2345261486
Short name T422
Test name
Test status
Simulation time 2580925316 ps
CPU time 47.81 seconds
Started Jun 06 01:58:21 PM PDT 24
Finished Jun 06 01:59:10 PM PDT 24
Peak memory 251352 kb
Host smart-9a06943e-6bdf-4bbc-84a2-28b2adcf5f15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345261486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2345261486
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.273769626
Short name T492
Test name
Test status
Simulation time 41698814933 ps
CPU time 53.48 seconds
Started Jun 06 01:58:21 PM PDT 24
Finished Jun 06 01:59:16 PM PDT 24
Peak memory 217044 kb
Host smart-cd27aef6-fb2e-4a52-b3cb-e821518c0295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273769626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.273769626
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3187004266
Short name T482
Test name
Test status
Simulation time 573747738 ps
CPU time 3.97 seconds
Started Jun 06 01:58:18 PM PDT 24
Finished Jun 06 01:58:23 PM PDT 24
Peak memory 217060 kb
Host smart-c5afcacd-7cf5-4ccd-8105-5aabd4edba04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187004266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3187004266
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4133308361
Short name T735
Test name
Test status
Simulation time 221483916 ps
CPU time 6.21 seconds
Started Jun 06 01:58:19 PM PDT 24
Finished Jun 06 01:58:26 PM PDT 24
Peak memory 216944 kb
Host smart-edf93f3c-111c-4792-9e1e-13a500536e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133308361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4133308361
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1587034342
Short name T716
Test name
Test status
Simulation time 40421413 ps
CPU time 0.68 seconds
Started Jun 06 01:58:20 PM PDT 24
Finished Jun 06 01:58:22 PM PDT 24
Peak memory 206284 kb
Host smart-e3635f15-1675-4779-9a9a-16bce7946e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587034342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1587034342
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3190628573
Short name T744
Test name
Test status
Simulation time 583140679 ps
CPU time 4.4 seconds
Started Jun 06 01:58:26 PM PDT 24
Finished Jun 06 01:58:31 PM PDT 24
Peak memory 225176 kb
Host smart-9375979f-7d84-49f9-b70a-3fbbd17e0e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190628573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3190628573
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.192153886
Short name T397
Test name
Test status
Simulation time 13393570 ps
CPU time 0.74 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:58:44 PM PDT 24
Peak memory 206096 kb
Host smart-065d2797-ffc4-4100-a030-e48661a5ddc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192153886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.192153886
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2333350094
Short name T218
Test name
Test status
Simulation time 2496227034 ps
CPU time 23.12 seconds
Started Jun 06 01:58:28 PM PDT 24
Finished Jun 06 01:58:52 PM PDT 24
Peak memory 225288 kb
Host smart-8bd1f1d4-4311-4a3b-942f-ec7efe3288b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333350094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2333350094
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3427902743
Short name T673
Test name
Test status
Simulation time 59807409 ps
CPU time 0.76 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:58:38 PM PDT 24
Peak memory 207572 kb
Host smart-1954f492-562e-44d8-aebd-a5777a95fc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427902743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3427902743
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1652675385
Short name T238
Test name
Test status
Simulation time 11114406679 ps
CPU time 64.64 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:59:43 PM PDT 24
Peak memory 250080 kb
Host smart-76c84750-c350-4a50-9303-68cd9bc1b372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652675385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1652675385
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.61595679
Short name T271
Test name
Test status
Simulation time 20239221796 ps
CPU time 71.45 seconds
Started Jun 06 01:58:26 PM PDT 24
Finished Jun 06 01:59:38 PM PDT 24
Peak memory 253516 kb
Host smart-1936c0b0-9af1-457d-8ebe-65d9e9ac4a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61595679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.61595679
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2171528907
Short name T326
Test name
Test status
Simulation time 763848800 ps
CPU time 8.37 seconds
Started Jun 06 01:58:26 PM PDT 24
Finished Jun 06 01:58:35 PM PDT 24
Peak memory 241604 kb
Host smart-977ccc56-ec9f-42ef-aa84-bcf1cf3debd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171528907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2171528907
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2705141335
Short name T629
Test name
Test status
Simulation time 1348522472 ps
CPU time 4.4 seconds
Started Jun 06 01:58:29 PM PDT 24
Finished Jun 06 01:58:34 PM PDT 24
Peak memory 220300 kb
Host smart-85cd82fd-cc54-47c7-8913-0adecf274cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705141335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2705141335
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1048099560
Short name T903
Test name
Test status
Simulation time 198474967 ps
CPU time 3.66 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:43 PM PDT 24
Peak memory 225176 kb
Host smart-29ec76ab-dbf2-445b-8a45-61690ffa7b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048099560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1048099560
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3607142800
Short name T807
Test name
Test status
Simulation time 3713609941 ps
CPU time 12.05 seconds
Started Jun 06 01:58:23 PM PDT 24
Finished Jun 06 01:58:36 PM PDT 24
Peak memory 233428 kb
Host smart-e36463d7-76ff-4e5d-a1e0-378d964fd7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607142800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3607142800
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4183557377
Short name T746
Test name
Test status
Simulation time 35576856 ps
CPU time 2.36 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:47 PM PDT 24
Peak memory 227112 kb
Host smart-dcefeede-7942-4bfa-8647-8af2329d5d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183557377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4183557377
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3241519647
Short name T137
Test name
Test status
Simulation time 515788507 ps
CPU time 7.28 seconds
Started Jun 06 01:58:27 PM PDT 24
Finished Jun 06 01:58:35 PM PDT 24
Peak memory 219564 kb
Host smart-f43342cf-ecf1-4ec3-a375-64f136c5b435
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3241519647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3241519647
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1131704974
Short name T156
Test name
Test status
Simulation time 34055240255 ps
CPU time 49.16 seconds
Started Jun 06 01:58:27 PM PDT 24
Finished Jun 06 01:59:17 PM PDT 24
Peak memory 240112 kb
Host smart-0f8ab925-f86c-44fd-8b2a-4b7caf6fed68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131704974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1131704974
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2704890724
Short name T414
Test name
Test status
Simulation time 11140832853 ps
CPU time 32.7 seconds
Started Jun 06 01:58:25 PM PDT 24
Finished Jun 06 01:58:59 PM PDT 24
Peak memory 217232 kb
Host smart-b1b21417-bdef-4ab9-b402-a9f720dbf7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704890724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2704890724
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1902520173
Short name T944
Test name
Test status
Simulation time 2430789871 ps
CPU time 11.11 seconds
Started Jun 06 01:58:27 PM PDT 24
Finished Jun 06 01:58:39 PM PDT 24
Peak memory 217328 kb
Host smart-0cc26e79-d86b-4c74-ba32-65951da88068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902520173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1902520173
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3187179917
Short name T434
Test name
Test status
Simulation time 24350776 ps
CPU time 0.69 seconds
Started Jun 06 01:58:25 PM PDT 24
Finished Jun 06 01:58:27 PM PDT 24
Peak memory 206212 kb
Host smart-3e0a865b-a10c-4f1f-b1e2-d9205658672c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187179917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3187179917
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2101751774
Short name T506
Test name
Test status
Simulation time 164866608 ps
CPU time 0.87 seconds
Started Jun 06 01:58:29 PM PDT 24
Finished Jun 06 01:58:31 PM PDT 24
Peak memory 207028 kb
Host smart-55d5e38a-f45b-45e7-9dc1-34d518700a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101751774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2101751774
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.4163469705
Short name T858
Test name
Test status
Simulation time 734428521 ps
CPU time 2.92 seconds
Started Jun 06 01:58:39 PM PDT 24
Finished Jun 06 01:58:43 PM PDT 24
Peak memory 225224 kb
Host smart-654cd070-44e1-4883-bba5-8d0c7f4545ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163469705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.4163469705
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1738652374
Short name T3
Test name
Test status
Simulation time 13771325 ps
CPU time 0.71 seconds
Started Jun 06 01:57:09 PM PDT 24
Finished Jun 06 01:57:11 PM PDT 24
Peak memory 206036 kb
Host smart-f6c63f80-995d-4a14-8331-49a6d2052b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738652374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
738652374
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3358358488
Short name T185
Test name
Test status
Simulation time 238718466 ps
CPU time 2.59 seconds
Started Jun 06 01:57:13 PM PDT 24
Finished Jun 06 01:57:17 PM PDT 24
Peak memory 225160 kb
Host smart-36988530-bc57-4f7a-bd75-891c8b2d9077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358358488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3358358488
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.952668174
Short name T531
Test name
Test status
Simulation time 22964236 ps
CPU time 0.83 seconds
Started Jun 06 01:57:12 PM PDT 24
Finished Jun 06 01:57:14 PM PDT 24
Peak memory 207216 kb
Host smart-c2a64c5e-cd76-47f4-b5ba-497ab5319589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952668174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.952668174
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.635811502
Short name T33
Test name
Test status
Simulation time 22014711820 ps
CPU time 37.33 seconds
Started Jun 06 01:57:19 PM PDT 24
Finished Jun 06 01:58:03 PM PDT 24
Peak memory 238036 kb
Host smart-3515d167-a61a-4356-a4a2-3967ba0956ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635811502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.635811502
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.134256905
Short name T842
Test name
Test status
Simulation time 81937517657 ps
CPU time 79.7 seconds
Started Jun 06 01:57:21 PM PDT 24
Finished Jun 06 01:58:43 PM PDT 24
Peak memory 241736 kb
Host smart-871f5d94-5795-4bbd-9352-7fcf490044cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134256905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
134256905
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.292265904
Short name T327
Test name
Test status
Simulation time 1515169230 ps
CPU time 9.94 seconds
Started Jun 06 01:57:13 PM PDT 24
Finished Jun 06 01:57:25 PM PDT 24
Peak memory 225144 kb
Host smart-ae33401d-1b97-40f4-85a9-f325f86a2066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292265904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.292265904
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1696910318
Short name T850
Test name
Test status
Simulation time 907936158 ps
CPU time 9.84 seconds
Started Jun 06 01:57:22 PM PDT 24
Finished Jun 06 01:57:34 PM PDT 24
Peak memory 225228 kb
Host smart-1d18eed4-cc52-4775-942c-f544d645ba53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696910318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1696910318
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.97979616
Short name T921
Test name
Test status
Simulation time 49067548447 ps
CPU time 52.65 seconds
Started Jun 06 01:57:11 PM PDT 24
Finished Jun 06 01:58:05 PM PDT 24
Peak memory 249652 kb
Host smart-39cef6d1-1bfd-48b5-9c1a-700fea80f07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97979616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.97979616
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1790297065
Short name T954
Test name
Test status
Simulation time 3337673936 ps
CPU time 7.74 seconds
Started Jun 06 01:57:08 PM PDT 24
Finished Jun 06 01:57:17 PM PDT 24
Peak memory 240852 kb
Host smart-a1bd7716-d1a6-43ce-9820-7446e350972a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790297065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1790297065
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.913022164
Short name T168
Test name
Test status
Simulation time 7524405728 ps
CPU time 22.9 seconds
Started Jun 06 01:57:09 PM PDT 24
Finished Jun 06 01:57:34 PM PDT 24
Peak memory 233448 kb
Host smart-3141e105-4431-4fbf-81c0-72de36816d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913022164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.913022164
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3750537507
Short name T626
Test name
Test status
Simulation time 6890915915 ps
CPU time 9.48 seconds
Started Jun 06 01:57:13 PM PDT 24
Finished Jun 06 01:57:24 PM PDT 24
Peak memory 223876 kb
Host smart-1942f87a-0f39-44dd-a362-c6496e7f613a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3750537507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3750537507
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2269435150
Short name T67
Test name
Test status
Simulation time 553841918 ps
CPU time 1.14 seconds
Started Jun 06 01:57:16 PM PDT 24
Finished Jun 06 01:57:19 PM PDT 24
Peak memory 235800 kb
Host smart-efee1905-7c6e-4eaa-b1c0-817297be0745
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269435150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2269435150
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3656006863
Short name T608
Test name
Test status
Simulation time 2006807807 ps
CPU time 29.54 seconds
Started Jun 06 01:57:21 PM PDT 24
Finished Jun 06 01:57:53 PM PDT 24
Peak memory 225304 kb
Host smart-e92b82bb-86e5-4d95-acac-10f4e817b75a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656006863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3656006863
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.440564572
Short name T454
Test name
Test status
Simulation time 931720899 ps
CPU time 5.83 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:28 PM PDT 24
Peak memory 217056 kb
Host smart-8900b676-abe4-463e-aa5f-3a906d41a33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440564572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.440564572
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3541332883
Short name T485
Test name
Test status
Simulation time 12431228 ps
CPU time 0.73 seconds
Started Jun 06 01:57:01 PM PDT 24
Finished Jun 06 01:57:03 PM PDT 24
Peak memory 206360 kb
Host smart-6da60e3a-c891-4dd7-a131-90940e296676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541332883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3541332883
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1902483007
Short name T711
Test name
Test status
Simulation time 63606354 ps
CPU time 0.81 seconds
Started Jun 06 01:57:16 PM PDT 24
Finished Jun 06 01:57:18 PM PDT 24
Peak memory 207544 kb
Host smart-33c7a9f2-2d0b-43b9-a655-d01012bc227e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902483007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1902483007
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2308189214
Short name T832
Test name
Test status
Simulation time 10567780 ps
CPU time 0.7 seconds
Started Jun 06 01:57:02 PM PDT 24
Finished Jun 06 01:57:04 PM PDT 24
Peak memory 206220 kb
Host smart-5933b3ec-c21f-4762-b611-ab6624ed8d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308189214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2308189214
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1689291778
Short name T42
Test name
Test status
Simulation time 1658049841 ps
CPU time 9.39 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:32 PM PDT 24
Peak memory 233428 kb
Host smart-3159b140-125b-4834-8635-1f2c9c1eaa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689291778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1689291778
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1881469420
Short name T780
Test name
Test status
Simulation time 28621254 ps
CPU time 0.71 seconds
Started Jun 06 01:58:40 PM PDT 24
Finished Jun 06 01:58:42 PM PDT 24
Peak memory 205548 kb
Host smart-c9416f53-c947-4d08-be79-26e76ed55a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881469420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1881469420
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3827131653
Short name T87
Test name
Test status
Simulation time 635112353 ps
CPU time 5.93 seconds
Started Jun 06 01:58:34 PM PDT 24
Finished Jun 06 01:58:41 PM PDT 24
Peak memory 233440 kb
Host smart-c3f9812b-4817-4a96-baab-c6cf53bbd60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827131653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3827131653
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3671557957
Short name T453
Test name
Test status
Simulation time 55435287 ps
CPU time 0.8 seconds
Started Jun 06 01:58:33 PM PDT 24
Finished Jun 06 01:58:35 PM PDT 24
Peak memory 207584 kb
Host smart-e3de5721-68b1-4e75-a1f5-5db898fbc590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671557957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3671557957
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3272431050
Short name T730
Test name
Test status
Simulation time 116231698352 ps
CPU time 204.28 seconds
Started Jun 06 01:58:27 PM PDT 24
Finished Jun 06 02:01:52 PM PDT 24
Peak memory 258080 kb
Host smart-cfcb1834-5a14-4146-aedb-b5df8846e687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272431050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3272431050
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2664718697
Short name T341
Test name
Test status
Simulation time 1325333066 ps
CPU time 18.32 seconds
Started Jun 06 01:58:24 PM PDT 24
Finished Jun 06 01:58:44 PM PDT 24
Peak memory 218060 kb
Host smart-df78a00c-4280-473d-ad66-be70b2f240ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664718697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2664718697
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3421378116
Short name T226
Test name
Test status
Simulation time 91024533121 ps
CPU time 255.26 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 02:02:54 PM PDT 24
Peak memory 249944 kb
Host smart-82532875-24a9-42a7-b23b-596dbb609193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421378116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3421378116
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.363274936
Short name T293
Test name
Test status
Simulation time 737814687 ps
CPU time 6.12 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:46 PM PDT 24
Peak memory 225236 kb
Host smart-fd30c7c7-2c1e-41ef-8f2d-337dc72b3c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363274936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.363274936
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3212937081
Short name T760
Test name
Test status
Simulation time 360394400 ps
CPU time 5.01 seconds
Started Jun 06 01:58:28 PM PDT 24
Finished Jun 06 01:58:34 PM PDT 24
Peak memory 233416 kb
Host smart-00badd71-c839-4d5d-bef6-d8404d039d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212937081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3212937081
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1949539221
Short name T665
Test name
Test status
Simulation time 15206593294 ps
CPU time 42.23 seconds
Started Jun 06 01:58:26 PM PDT 24
Finished Jun 06 01:59:09 PM PDT 24
Peak memory 240888 kb
Host smart-97c1545d-39b9-4ced-a8f1-fba84f530f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949539221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1949539221
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3812202650
Short name T689
Test name
Test status
Simulation time 514420653 ps
CPU time 3.59 seconds
Started Jun 06 01:58:35 PM PDT 24
Finished Jun 06 01:58:39 PM PDT 24
Peak memory 225208 kb
Host smart-d3c4a529-2e39-43aa-834d-1d8807879295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812202650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3812202650
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1836826935
Short name T223
Test name
Test status
Simulation time 5572079498 ps
CPU time 8.71 seconds
Started Jun 06 01:58:32 PM PDT 24
Finished Jun 06 01:58:41 PM PDT 24
Peak memory 233444 kb
Host smart-a10d36bd-091f-433e-97ff-ecc7074594f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836826935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1836826935
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2850279523
Short name T551
Test name
Test status
Simulation time 385306743 ps
CPU time 4.16 seconds
Started Jun 06 01:58:31 PM PDT 24
Finished Jun 06 01:58:36 PM PDT 24
Peak memory 223624 kb
Host smart-49880de7-67e9-4617-ac16-92b3b430b580
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2850279523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2850279523
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3131690406
Short name T913
Test name
Test status
Simulation time 70561416 ps
CPU time 1.16 seconds
Started Jun 06 01:58:26 PM PDT 24
Finished Jun 06 01:58:27 PM PDT 24
Peak memory 207884 kb
Host smart-10d74064-3506-4cfd-9d5f-3b3fbdeb856a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131690406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3131690406
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4008414510
Short name T705
Test name
Test status
Simulation time 2229718928 ps
CPU time 8.83 seconds
Started Jun 06 01:58:35 PM PDT 24
Finished Jun 06 01:58:45 PM PDT 24
Peak memory 217240 kb
Host smart-58b51c7c-b88d-4aef-9c8f-d9ebf6741795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008414510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4008414510
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.507476678
Short name T398
Test name
Test status
Simulation time 16982003278 ps
CPU time 15.4 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:55 PM PDT 24
Peak memory 217044 kb
Host smart-97ce7115-6c47-4c0a-b1a7-518cc613e648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507476678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.507476678
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4147619455
Short name T459
Test name
Test status
Simulation time 59459139 ps
CPU time 1.69 seconds
Started Jun 06 01:58:26 PM PDT 24
Finished Jun 06 01:58:29 PM PDT 24
Peak memory 216976 kb
Host smart-cd53c9de-497e-4834-8a97-141d4dc38755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147619455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4147619455
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1111988483
Short name T584
Test name
Test status
Simulation time 83118261 ps
CPU time 0.7 seconds
Started Jun 06 01:58:36 PM PDT 24
Finished Jun 06 01:58:37 PM PDT 24
Peak memory 206548 kb
Host smart-4776012a-bf43-4d52-8105-46cbc520a37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111988483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1111988483
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.341711659
Short name T217
Test name
Test status
Simulation time 409987959 ps
CPU time 4.37 seconds
Started Jun 06 01:58:27 PM PDT 24
Finished Jun 06 01:58:32 PM PDT 24
Peak memory 218644 kb
Host smart-29851816-7c68-425b-a584-60923cfcbc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341711659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.341711659
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1414776304
Short name T562
Test name
Test status
Simulation time 39609903 ps
CPU time 0.69 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:40 PM PDT 24
Peak memory 205552 kb
Host smart-e4f996cd-b6aa-42c8-91e8-101658d73bad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414776304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1414776304
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3354971345
Short name T207
Test name
Test status
Simulation time 63317169 ps
CPU time 2.17 seconds
Started Jun 06 01:58:30 PM PDT 24
Finished Jun 06 01:58:33 PM PDT 24
Peak memory 225112 kb
Host smart-a5e811cc-7e25-4af7-939b-91bf4284b128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354971345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3354971345
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.4164477744
Short name T708
Test name
Test status
Simulation time 20126106 ps
CPU time 0.83 seconds
Started Jun 06 01:58:28 PM PDT 24
Finished Jun 06 01:58:30 PM PDT 24
Peak memory 207220 kb
Host smart-df7ffeeb-0c5e-4dbc-a55b-c0da517119f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164477744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.4164477744
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3576787127
Short name T170
Test name
Test status
Simulation time 24566523592 ps
CPU time 187.45 seconds
Started Jun 06 01:58:36 PM PDT 24
Finished Jun 06 02:01:45 PM PDT 24
Peak memory 249888 kb
Host smart-e025fa6f-65c8-4fad-adc4-1d8150f762e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576787127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3576787127
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1953710096
Short name T677
Test name
Test status
Simulation time 9697210899 ps
CPU time 103.53 seconds
Started Jun 06 01:58:39 PM PDT 24
Finished Jun 06 02:00:24 PM PDT 24
Peak memory 241640 kb
Host smart-9b41fd8f-6b35-4b47-bbbf-dba07f9a745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953710096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1953710096
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.437591417
Short name T729
Test name
Test status
Simulation time 1176565282 ps
CPU time 22.76 seconds
Started Jun 06 01:58:29 PM PDT 24
Finished Jun 06 01:58:52 PM PDT 24
Peak memory 241612 kb
Host smart-3de81288-73ac-459a-bfec-2caff8f63e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437591417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.437591417
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3843704834
Short name T833
Test name
Test status
Simulation time 30048104521 ps
CPU time 14.84 seconds
Started Jun 06 01:58:24 PM PDT 24
Finished Jun 06 01:58:40 PM PDT 24
Peak memory 225328 kb
Host smart-0c8c5440-443f-4082-b1fe-ada66a91fda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843704834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3843704834
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2687107227
Short name T197
Test name
Test status
Simulation time 4442169305 ps
CPU time 28.9 seconds
Started Jun 06 01:58:27 PM PDT 24
Finished Jun 06 01:58:57 PM PDT 24
Peak memory 241088 kb
Host smart-8016667f-d482-44fc-815a-7539c9a1b505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687107227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2687107227
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3214896786
Short name T933
Test name
Test status
Simulation time 3414807662 ps
CPU time 10.41 seconds
Started Jun 06 01:58:31 PM PDT 24
Finished Jun 06 01:58:42 PM PDT 24
Peak memory 233432 kb
Host smart-3728b206-c7c4-472f-869a-48d6ade804ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214896786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3214896786
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2915841533
Short name T592
Test name
Test status
Simulation time 10748776790 ps
CPU time 8.84 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:58:47 PM PDT 24
Peak memory 233408 kb
Host smart-cb7c6687-3966-4605-9d7f-16dabdcb77ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915841533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2915841533
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4148823238
Short name T736
Test name
Test status
Simulation time 323031612 ps
CPU time 5.43 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:58:44 PM PDT 24
Peak memory 223740 kb
Host smart-a5f57149-8891-448b-a38d-86b8ef2c26c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4148823238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4148823238
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1616393933
Short name T269
Test name
Test status
Simulation time 35275110371 ps
CPU time 394.29 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 02:05:14 PM PDT 24
Peak memory 271936 kb
Host smart-40897f4d-c624-4d78-b2c5-ba9046fe8764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616393933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1616393933
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.847673716
Short name T939
Test name
Test status
Simulation time 2283152147 ps
CPU time 4.24 seconds
Started Jun 06 01:58:31 PM PDT 24
Finished Jun 06 01:58:36 PM PDT 24
Peak memory 217060 kb
Host smart-8fa8ad6c-4a91-4b6c-b3cd-250da624538f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847673716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.847673716
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2229214915
Short name T436
Test name
Test status
Simulation time 313352694 ps
CPU time 1.31 seconds
Started Jun 06 01:58:23 PM PDT 24
Finished Jun 06 01:58:25 PM PDT 24
Peak memory 208372 kb
Host smart-b002ce59-2e3a-4a1c-9686-54bd3ca08888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229214915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2229214915
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3935005689
Short name T371
Test name
Test status
Simulation time 39816173 ps
CPU time 1.34 seconds
Started Jun 06 01:58:28 PM PDT 24
Finished Jun 06 01:58:31 PM PDT 24
Peak memory 216912 kb
Host smart-e61f3501-58b2-42e1-bad2-6394181e24ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935005689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3935005689
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1253809992
Short name T907
Test name
Test status
Simulation time 52359172 ps
CPU time 0.77 seconds
Started Jun 06 01:58:27 PM PDT 24
Finished Jun 06 01:58:28 PM PDT 24
Peak memory 206512 kb
Host smart-f7071276-581f-42cd-8aec-203055f4ae37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253809992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1253809992
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.217946479
Short name T508
Test name
Test status
Simulation time 145731480 ps
CPU time 2.24 seconds
Started Jun 06 01:58:28 PM PDT 24
Finished Jun 06 01:58:31 PM PDT 24
Peak memory 224992 kb
Host smart-87b847a3-a9eb-43ed-9703-32e2d3a1e55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217946479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.217946479
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2901104952
Short name T347
Test name
Test status
Simulation time 26302965 ps
CPU time 0.73 seconds
Started Jun 06 01:58:40 PM PDT 24
Finished Jun 06 01:58:42 PM PDT 24
Peak memory 206076 kb
Host smart-76c0523d-b381-428b-a5f5-840f427553f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901104952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2901104952
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1158844396
Short name T452
Test name
Test status
Simulation time 327628566 ps
CPU time 3.95 seconds
Started Jun 06 01:58:40 PM PDT 24
Finished Jun 06 01:58:45 PM PDT 24
Peak memory 225232 kb
Host smart-cbc1721a-39b9-4f42-bae1-cce0fd11ecce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158844396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1158844396
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3767856957
Short name T17
Test name
Test status
Simulation time 28764013 ps
CPU time 0.76 seconds
Started Jun 06 01:58:40 PM PDT 24
Finished Jun 06 01:58:42 PM PDT 24
Peak memory 207212 kb
Host smart-53538d00-a3d5-47a6-b64f-3a765e64e272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767856957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3767856957
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1468369363
Short name T298
Test name
Test status
Simulation time 25045661851 ps
CPU time 188.85 seconds
Started Jun 06 01:58:39 PM PDT 24
Finished Jun 06 02:01:49 PM PDT 24
Peak memory 249884 kb
Host smart-151ce569-316b-4292-9daf-ec4d8df4727e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468369363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1468369363
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.395763032
Short name T24
Test name
Test status
Simulation time 6384524468 ps
CPU time 52.41 seconds
Started Jun 06 01:58:36 PM PDT 24
Finished Jun 06 01:59:30 PM PDT 24
Peak memory 255020 kb
Host smart-53348ad4-983d-4a32-8716-f778db1cd024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395763032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.395763032
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.774496857
Short name T835
Test name
Test status
Simulation time 4191801347 ps
CPU time 64.27 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:59:42 PM PDT 24
Peak memory 251844 kb
Host smart-61368c21-5ef7-4e03-abe3-4989811c2968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774496857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.774496857
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1744770763
Short name T512
Test name
Test status
Simulation time 177353446 ps
CPU time 2.68 seconds
Started Jun 06 01:58:40 PM PDT 24
Finished Jun 06 01:58:49 PM PDT 24
Peak memory 225172 kb
Host smart-c284867c-c2fc-4946-92b6-70f41ee2cf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744770763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1744770763
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2937266056
Short name T715
Test name
Test status
Simulation time 735392330 ps
CPU time 11.02 seconds
Started Jun 06 01:58:40 PM PDT 24
Finished Jun 06 01:58:52 PM PDT 24
Peak memory 225456 kb
Host smart-b11fc862-f121-4326-8afa-850f2597fe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937266056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2937266056
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2628019954
Short name T610
Test name
Test status
Simulation time 4719441419 ps
CPU time 28.69 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:59:09 PM PDT 24
Peak memory 240288 kb
Host smart-9d9d718f-2338-4640-b7c1-db4e6a2dd5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628019954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2628019954
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1573932285
Short name T703
Test name
Test status
Simulation time 304227289 ps
CPU time 3.12 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:43 PM PDT 24
Peak memory 225152 kb
Host smart-259bf20b-ad53-43de-ab72-763de3db0bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573932285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1573932285
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2627217191
Short name T404
Test name
Test status
Simulation time 324543732 ps
CPU time 2.11 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:42 PM PDT 24
Peak memory 223588 kb
Host smart-bf8bbaf5-b65a-44db-93c6-acd4adb31dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627217191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2627217191
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2140004312
Short name T799
Test name
Test status
Simulation time 1001485358 ps
CPU time 12.02 seconds
Started Jun 06 01:58:39 PM PDT 24
Finished Jun 06 01:58:52 PM PDT 24
Peak memory 223068 kb
Host smart-5675698c-4361-414f-aaca-283d218023e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2140004312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2140004312
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.424522206
Short name T26
Test name
Test status
Simulation time 407219343 ps
CPU time 1.92 seconds
Started Jun 06 01:58:39 PM PDT 24
Finished Jun 06 01:58:42 PM PDT 24
Peak memory 217128 kb
Host smart-3ec3bc53-b0ef-4581-834b-fbce87f1b895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424522206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.424522206
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1760658400
Short name T351
Test name
Test status
Simulation time 111514053 ps
CPU time 1.42 seconds
Started Jun 06 01:58:40 PM PDT 24
Finished Jun 06 01:58:43 PM PDT 24
Peak memory 208516 kb
Host smart-3bd2ff97-872b-4f14-b20d-a2b839218abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760658400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1760658400
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.830196870
Short name T513
Test name
Test status
Simulation time 129372138 ps
CPU time 1.63 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:41 PM PDT 24
Peak memory 216964 kb
Host smart-9a5d8335-a7b7-4aee-8a34-077a90b78efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830196870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.830196870
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1559874991
Short name T687
Test name
Test status
Simulation time 239552335 ps
CPU time 0.98 seconds
Started Jun 06 01:58:40 PM PDT 24
Finished Jun 06 01:58:43 PM PDT 24
Peak memory 206624 kb
Host smart-e00e89dc-23f2-4f67-8fb9-c90b2365bbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559874991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1559874991
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3790797655
Short name T779
Test name
Test status
Simulation time 296857570 ps
CPU time 5.58 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:45 PM PDT 24
Peak memory 233376 kb
Host smart-219c2445-3a30-4554-8ac6-f6f9cd823cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790797655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3790797655
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3824243418
Short name T740
Test name
Test status
Simulation time 34030412 ps
CPU time 0.76 seconds
Started Jun 06 01:58:45 PM PDT 24
Finished Jun 06 01:58:46 PM PDT 24
Peak memory 205496 kb
Host smart-0a6f1cb0-c5e2-4042-8b8f-80d1369c2c73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824243418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3824243418
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1062041984
Short name T861
Test name
Test status
Simulation time 409194516 ps
CPU time 6.13 seconds
Started Jun 06 01:58:39 PM PDT 24
Finished Jun 06 01:58:47 PM PDT 24
Peak memory 225176 kb
Host smart-80cce136-1239-40bf-903e-bb36ba50ccf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062041984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1062041984
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3545524102
Short name T847
Test name
Test status
Simulation time 58118271 ps
CPU time 0.74 seconds
Started Jun 06 01:58:39 PM PDT 24
Finished Jun 06 01:58:42 PM PDT 24
Peak memory 207256 kb
Host smart-e31830fe-93cb-4daa-bb31-64cfa579d200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545524102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3545524102
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3720481254
Short name T263
Test name
Test status
Simulation time 56371474517 ps
CPU time 387.94 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 02:05:08 PM PDT 24
Peak memory 267192 kb
Host smart-ea30d0ec-3714-4756-8b63-e6da4a7fefa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720481254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3720481254
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3600244579
Short name T808
Test name
Test status
Simulation time 4698143855 ps
CPU time 45.55 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:59:25 PM PDT 24
Peak memory 234452 kb
Host smart-149ebfca-fbd7-4f7e-9eb2-05b25ea4138f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600244579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3600244579
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1951310639
Short name T919
Test name
Test status
Simulation time 2592849828 ps
CPU time 11.98 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:52 PM PDT 24
Peak memory 218284 kb
Host smart-81df0164-82c6-4f38-b5a3-dce3a62e2f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951310639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1951310639
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2284234585
Short name T638
Test name
Test status
Simulation time 7230890861 ps
CPU time 36.83 seconds
Started Jun 06 01:58:36 PM PDT 24
Finished Jun 06 01:59:14 PM PDT 24
Peak memory 225256 kb
Host smart-e9a8fb86-085c-4aa9-9a6e-4dae2c0f483a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284234585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2284234585
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.396437302
Short name T518
Test name
Test status
Simulation time 151028249 ps
CPU time 2.92 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:58:42 PM PDT 24
Peak memory 225160 kb
Host smart-cff4b083-7854-400e-8d54-e72b849c8821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396437302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.396437302
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.4118531201
Short name T787
Test name
Test status
Simulation time 14781471661 ps
CPU time 52.76 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:59:31 PM PDT 24
Peak memory 239952 kb
Host smart-5b8601ef-15a0-4818-a8d7-32a7cd68b3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118531201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.4118531201
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3444100069
Short name T806
Test name
Test status
Simulation time 1955542498 ps
CPU time 8.65 seconds
Started Jun 06 01:58:40 PM PDT 24
Finished Jun 06 01:58:50 PM PDT 24
Peak memory 225136 kb
Host smart-d072d981-9808-444e-9ad9-7f1638c6e879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444100069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3444100069
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1054611521
Short name T179
Test name
Test status
Simulation time 2743187932 ps
CPU time 10.31 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:58:49 PM PDT 24
Peak memory 233456 kb
Host smart-3358531d-6a90-445a-8139-2147bf75bbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054611521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1054611521
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3358087424
Short name T407
Test name
Test status
Simulation time 401661744 ps
CPU time 3.49 seconds
Started Jun 06 01:58:34 PM PDT 24
Finished Jun 06 01:58:38 PM PDT 24
Peak memory 220792 kb
Host smart-eabc8aad-8d31-4194-965b-3832cee5e91d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3358087424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3358087424
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2771634002
Short name T281
Test name
Test status
Simulation time 8111688462 ps
CPU time 22.49 seconds
Started Jun 06 01:58:40 PM PDT 24
Finished Jun 06 01:59:04 PM PDT 24
Peak memory 225332 kb
Host smart-52f4dd25-83fd-4b69-b0ad-8904590f821d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771634002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2771634002
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2222036374
Short name T597
Test name
Test status
Simulation time 4840409710 ps
CPU time 8.04 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:58:47 PM PDT 24
Peak memory 217092 kb
Host smart-2d3ccb00-adde-415c-a244-96bc6180c588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222036374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2222036374
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.733900212
Short name T767
Test name
Test status
Simulation time 7265558420 ps
CPU time 6.54 seconds
Started Jun 06 01:58:44 PM PDT 24
Finished Jun 06 01:58:52 PM PDT 24
Peak memory 217096 kb
Host smart-51b22aba-76e1-45f6-82ed-10efca2eb426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733900212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.733900212
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3620071721
Short name T356
Test name
Test status
Simulation time 465362222 ps
CPU time 2.43 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:58:41 PM PDT 24
Peak memory 216992 kb
Host smart-a745ff39-96d2-40bd-bb08-67e0cb23651d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620071721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3620071721
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.10134867
Short name T625
Test name
Test status
Simulation time 381945850 ps
CPU time 0.77 seconds
Started Jun 06 01:58:39 PM PDT 24
Finished Jun 06 01:58:41 PM PDT 24
Peak memory 206552 kb
Host smart-ab874eb8-7e63-4d11-bafb-c9e3f8ec3b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10134867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.10134867
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2704808180
Short name T617
Test name
Test status
Simulation time 2359184909 ps
CPU time 10.12 seconds
Started Jun 06 01:58:41 PM PDT 24
Finished Jun 06 01:58:53 PM PDT 24
Peak memory 233432 kb
Host smart-d6780e22-0e05-492c-b57d-b03cfc7c9823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704808180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2704808180
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1182482570
Short name T882
Test name
Test status
Simulation time 153670408 ps
CPU time 0.73 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:41 PM PDT 24
Peak memory 205532 kb
Host smart-55147f5e-f4f0-424d-9cbf-42afdfd5f267
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182482570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1182482570
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3092431097
Short name T221
Test name
Test status
Simulation time 1088273897 ps
CPU time 7.64 seconds
Started Jun 06 01:58:39 PM PDT 24
Finished Jun 06 01:58:48 PM PDT 24
Peak memory 233356 kb
Host smart-d82a71bf-67b6-4517-b9f6-ac7c89c6c344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092431097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3092431097
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2628184699
Short name T558
Test name
Test status
Simulation time 34603930 ps
CPU time 0.76 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:58:39 PM PDT 24
Peak memory 207552 kb
Host smart-410f935b-e32f-48bb-839c-c6ea7eb3cc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628184699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2628184699
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3478543020
Short name T636
Test name
Test status
Simulation time 2941230452 ps
CPU time 19.06 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:59 PM PDT 24
Peak memory 241344 kb
Host smart-62610c22-275b-45ea-b1a6-e7ba88e06d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478543020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3478543020
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.671665242
Short name T186
Test name
Test status
Simulation time 9274811135 ps
CPU time 96.53 seconds
Started Jun 06 01:58:43 PM PDT 24
Finished Jun 06 02:00:20 PM PDT 24
Peak memory 241688 kb
Host smart-22572857-2ba7-4550-9ab3-17f548d117a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671665242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.671665242
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3001885570
Short name T23
Test name
Test status
Simulation time 31133484615 ps
CPU time 167.38 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 02:01:27 PM PDT 24
Peak memory 255832 kb
Host smart-ec7f514c-2c2d-4633-94aa-e91d3e1da2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001885570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3001885570
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2598563873
Short name T332
Test name
Test status
Simulation time 1101728681 ps
CPU time 9.46 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:58:48 PM PDT 24
Peak memory 233476 kb
Host smart-0417db13-f7e9-4e25-a681-6697be0dba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598563873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2598563873
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1542399561
Short name T659
Test name
Test status
Simulation time 435676792 ps
CPU time 2.42 seconds
Started Jun 06 01:58:39 PM PDT 24
Finished Jun 06 01:58:43 PM PDT 24
Peak memory 223724 kb
Host smart-4456f08c-8c1b-47fa-a5c0-b4d9df11afc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542399561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1542399561
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3760747280
Short name T797
Test name
Test status
Simulation time 994334341 ps
CPU time 8.86 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:58:47 PM PDT 24
Peak memory 236592 kb
Host smart-61cceb3a-4779-4a63-9f4a-5b2f1fddce09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760747280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3760747280
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1225844379
Short name T681
Test name
Test status
Simulation time 299348655 ps
CPU time 3.22 seconds
Started Jun 06 01:58:44 PM PDT 24
Finished Jun 06 01:58:48 PM PDT 24
Peak memory 233432 kb
Host smart-2dddbd40-5818-471e-bfda-e02b7181857c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225844379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1225844379
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1051223614
Short name T285
Test name
Test status
Simulation time 18045202869 ps
CPU time 9.51 seconds
Started Jun 06 01:58:36 PM PDT 24
Finished Jun 06 01:58:47 PM PDT 24
Peak memory 241592 kb
Host smart-4ab0d6ef-be63-482f-9d35-8bb8eba6dbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051223614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1051223614
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.818404017
Short name T573
Test name
Test status
Simulation time 227297686 ps
CPU time 3.95 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:58:42 PM PDT 24
Peak memory 223168 kb
Host smart-aa0ea556-b0c9-4c0c-b73f-b3e5a24a49f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=818404017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.818404017
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3162042704
Short name T892
Test name
Test status
Simulation time 61034180 ps
CPU time 0.94 seconds
Started Jun 06 01:58:55 PM PDT 24
Finished Jun 06 01:58:56 PM PDT 24
Peak memory 207240 kb
Host smart-4117ad96-7ee5-4dd7-90b3-393f16b04508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162042704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3162042704
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2942169458
Short name T697
Test name
Test status
Simulation time 1656430511 ps
CPU time 9.49 seconds
Started Jun 06 01:58:40 PM PDT 24
Finished Jun 06 01:58:51 PM PDT 24
Peak memory 218644 kb
Host smart-beb523cf-74b2-419d-b1e3-b939a42d954f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942169458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2942169458
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1119056267
Short name T349
Test name
Test status
Simulation time 3757232853 ps
CPU time 6.96 seconds
Started Jun 06 01:58:39 PM PDT 24
Finished Jun 06 01:58:47 PM PDT 24
Peak memory 217112 kb
Host smart-e61cc985-0418-4f73-b187-7dbe4480df33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119056267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1119056267
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3354247092
Short name T564
Test name
Test status
Simulation time 308033657 ps
CPU time 1.56 seconds
Started Jun 06 01:58:36 PM PDT 24
Finished Jun 06 01:58:38 PM PDT 24
Peak memory 217008 kb
Host smart-5bd132cd-0847-4acf-bf3c-a13a4aab2ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354247092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3354247092
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3749754924
Short name T408
Test name
Test status
Simulation time 220927598 ps
CPU time 0.94 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:41 PM PDT 24
Peak memory 207512 kb
Host smart-66d4a614-3fdc-4e11-8bed-924d6741eb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749754924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3749754924
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.427567573
Short name T899
Test name
Test status
Simulation time 3498602926 ps
CPU time 14.14 seconds
Started Jun 06 01:58:42 PM PDT 24
Finished Jun 06 01:58:57 PM PDT 24
Peak memory 233372 kb
Host smart-5eb2dc41-86b3-404d-bebb-cd6ade30dfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427567573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.427567573
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4117486256
Short name T497
Test name
Test status
Simulation time 22630190 ps
CPU time 0.73 seconds
Started Jun 06 01:58:46 PM PDT 24
Finished Jun 06 01:58:48 PM PDT 24
Peak memory 206052 kb
Host smart-069119d0-9d00-41af-9a52-bb9989a6985b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117486256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4117486256
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1822950963
Short name T886
Test name
Test status
Simulation time 71949839 ps
CPU time 2.6 seconds
Started Jun 06 01:58:41 PM PDT 24
Finished Jun 06 01:58:45 PM PDT 24
Peak memory 233412 kb
Host smart-8cf1c934-88b0-48e1-a915-75d65a090ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822950963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1822950963
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.626695467
Short name T478
Test name
Test status
Simulation time 118583599 ps
CPU time 0.75 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:41 PM PDT 24
Peak memory 207612 kb
Host smart-55cf157d-eb48-40cd-bec1-0af1f6cb7a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626695467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.626695467
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3526096943
Short name T160
Test name
Test status
Simulation time 90855152097 ps
CPU time 173.15 seconds
Started Jun 06 01:58:55 PM PDT 24
Finished Jun 06 02:01:49 PM PDT 24
Peak memory 241240 kb
Host smart-de8fa3fd-a816-47be-9081-22972183ac27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526096943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3526096943
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.369978742
Short name T261
Test name
Test status
Simulation time 20327342255 ps
CPU time 201.13 seconds
Started Jun 06 01:58:53 PM PDT 24
Finished Jun 06 02:02:14 PM PDT 24
Peak memory 252080 kb
Host smart-f68e9524-6e5b-4776-9abb-0c549f9e3046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369978742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.369978742
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3291965355
Short name T932
Test name
Test status
Simulation time 178560003 ps
CPU time 3.09 seconds
Started Jun 06 01:58:47 PM PDT 24
Finished Jun 06 01:58:51 PM PDT 24
Peak memory 233364 kb
Host smart-34be132f-8d99-41e8-b2a4-3d8716270d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291965355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3291965355
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.239878715
Short name T187
Test name
Test status
Simulation time 1959214772 ps
CPU time 15.37 seconds
Started Jun 06 01:58:41 PM PDT 24
Finished Jun 06 01:58:58 PM PDT 24
Peak memory 233392 kb
Host smart-f62885fc-ca85-422d-9a43-3a8445f280ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239878715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.239878715
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.12666315
Short name T575
Test name
Test status
Simulation time 803736345 ps
CPU time 15.78 seconds
Started Jun 06 01:58:47 PM PDT 24
Finished Jun 06 01:59:03 PM PDT 24
Peak memory 241304 kb
Host smart-bee5fe8f-55cc-44c6-b644-009108147060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12666315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.12666315
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1378312802
Short name T208
Test name
Test status
Simulation time 1375833070 ps
CPU time 4.45 seconds
Started Jun 06 01:58:36 PM PDT 24
Finished Jun 06 01:58:41 PM PDT 24
Peak memory 225212 kb
Host smart-78f24931-af5c-4649-a33c-4d94249543ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378312802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1378312802
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.434623438
Short name T923
Test name
Test status
Simulation time 21695934536 ps
CPU time 14.03 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:58:52 PM PDT 24
Peak memory 233424 kb
Host smart-e6f79712-2429-447a-a38d-e98cd8d59a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434623438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.434623438
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3933596672
Short name T136
Test name
Test status
Simulation time 2077946068 ps
CPU time 9.26 seconds
Started Jun 06 01:58:44 PM PDT 24
Finished Jun 06 01:58:55 PM PDT 24
Peak memory 219944 kb
Host smart-432199bd-bbae-4186-b210-da994e72df54
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3933596672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3933596672
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3158549981
Short name T801
Test name
Test status
Simulation time 12556512869 ps
CPU time 126.12 seconds
Started Jun 06 01:58:54 PM PDT 24
Finished Jun 06 02:01:01 PM PDT 24
Peak memory 249928 kb
Host smart-11e63d9e-2765-4b66-8259-95eabc93ee1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158549981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3158549981
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1099662640
Short name T653
Test name
Test status
Simulation time 2412043851 ps
CPU time 8.65 seconds
Started Jun 06 01:58:39 PM PDT 24
Finished Jun 06 01:58:49 PM PDT 24
Peak memory 217204 kb
Host smart-499281f1-2985-41da-b72b-1bd2ee2de220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099662640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1099662640
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1102293373
Short name T848
Test name
Test status
Simulation time 4012008202 ps
CPU time 14.76 seconds
Started Jun 06 01:58:37 PM PDT 24
Finished Jun 06 01:58:54 PM PDT 24
Peak memory 217036 kb
Host smart-bcee66e5-54c2-4f38-ba5d-66558b42ce3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102293373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1102293373
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3661799718
Short name T634
Test name
Test status
Simulation time 54346059 ps
CPU time 1.2 seconds
Started Jun 06 01:58:39 PM PDT 24
Finished Jun 06 01:58:42 PM PDT 24
Peak memory 216984 kb
Host smart-89b9d212-e41a-4fe8-a7ad-1bb8461a9eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661799718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3661799718
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3490856051
Short name T871
Test name
Test status
Simulation time 434454157 ps
CPU time 0.82 seconds
Started Jun 06 01:58:40 PM PDT 24
Finished Jun 06 01:58:42 PM PDT 24
Peak memory 206508 kb
Host smart-bf4d41df-de15-4031-aead-c7b52096f5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490856051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3490856051
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2454689128
Short name T747
Test name
Test status
Simulation time 2959708858 ps
CPU time 8.07 seconds
Started Jun 06 01:58:38 PM PDT 24
Finished Jun 06 01:58:47 PM PDT 24
Peak memory 233424 kb
Host smart-67b6ee60-2c14-44ec-8d9d-0beea31a6a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454689128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2454689128
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1772642453
Short name T405
Test name
Test status
Simulation time 54649544 ps
CPU time 0.71 seconds
Started Jun 06 01:58:51 PM PDT 24
Finished Jun 06 01:58:52 PM PDT 24
Peak memory 206032 kb
Host smart-a9c8f2c9-2997-4477-b3fb-3a4a7ce4258c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772642453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1772642453
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1428298030
Short name T319
Test name
Test status
Simulation time 101153100 ps
CPU time 3.02 seconds
Started Jun 06 01:58:53 PM PDT 24
Finished Jun 06 01:58:57 PM PDT 24
Peak memory 233416 kb
Host smart-51fec95e-8417-4b66-8a59-0719c41e063f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428298030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1428298030
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1370498899
Short name T54
Test name
Test status
Simulation time 18701959 ps
CPU time 0.79 seconds
Started Jun 06 01:58:56 PM PDT 24
Finished Jun 06 01:58:58 PM PDT 24
Peak memory 206192 kb
Host smart-1fbcc677-b981-4715-9b1b-ea0545572cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370498899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1370498899
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3951243875
Short name T251
Test name
Test status
Simulation time 57270294162 ps
CPU time 221.84 seconds
Started Jun 06 01:58:45 PM PDT 24
Finished Jun 06 02:02:28 PM PDT 24
Peak memory 264592 kb
Host smart-43de240a-4312-4641-83fe-d02ce099ca85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951243875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3951243875
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2956585760
Short name T250
Test name
Test status
Simulation time 3122830373 ps
CPU time 64.85 seconds
Started Jun 06 01:58:52 PM PDT 24
Finished Jun 06 01:59:58 PM PDT 24
Peak memory 241692 kb
Host smart-8bebfa18-3d9c-4c28-9d40-77d88bf55567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956585760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2956585760
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2304510774
Short name T577
Test name
Test status
Simulation time 50127224190 ps
CPU time 67.97 seconds
Started Jun 06 01:58:52 PM PDT 24
Finished Jun 06 02:00:01 PM PDT 24
Peak memory 266516 kb
Host smart-3848d376-f4e0-4c6d-9336-2fb7036e65e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304510774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2304510774
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_intercept.888886384
Short name T845
Test name
Test status
Simulation time 4257294975 ps
CPU time 15.51 seconds
Started Jun 06 01:58:58 PM PDT 24
Finished Jun 06 01:59:14 PM PDT 24
Peak memory 233484 kb
Host smart-26317757-1882-4f78-ae6f-0f7159a1019a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888886384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.888886384
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.393133305
Short name T456
Test name
Test status
Simulation time 9858767741 ps
CPU time 95.01 seconds
Started Jun 06 01:58:46 PM PDT 24
Finished Jun 06 02:00:22 PM PDT 24
Peak memory 236924 kb
Host smart-03e63732-31de-4ed6-acf6-743c8ed169c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393133305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.393133305
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2119213481
Short name T732
Test name
Test status
Simulation time 6933312850 ps
CPU time 27.43 seconds
Started Jun 06 01:58:54 PM PDT 24
Finished Jun 06 01:59:22 PM PDT 24
Peak memory 241024 kb
Host smart-afcb7a12-3b85-489c-b86c-cbbeec1950a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119213481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2119213481
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3697153673
Short name T200
Test name
Test status
Simulation time 2898043405 ps
CPU time 9.33 seconds
Started Jun 06 01:58:48 PM PDT 24
Finished Jun 06 01:58:58 PM PDT 24
Peak memory 233436 kb
Host smart-8da2d97b-b18c-45ca-a857-f17e7c11a822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697153673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3697153673
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1444972602
Short name T678
Test name
Test status
Simulation time 868328545 ps
CPU time 7.16 seconds
Started Jun 06 01:58:46 PM PDT 24
Finished Jun 06 01:58:54 PM PDT 24
Peak memory 219892 kb
Host smart-0bf7187c-929a-4a68-b90f-909e2645e3a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1444972602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1444972602
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2015509877
Short name T928
Test name
Test status
Simulation time 229960539 ps
CPU time 0.91 seconds
Started Jun 06 01:58:50 PM PDT 24
Finished Jun 06 01:58:52 PM PDT 24
Peak memory 207692 kb
Host smart-57cbd4f5-f833-4895-be75-6cfb24242b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015509877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2015509877
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3491957589
Short name T601
Test name
Test status
Simulation time 27519154829 ps
CPU time 42.14 seconds
Started Jun 06 01:58:46 PM PDT 24
Finished Jun 06 01:59:29 PM PDT 24
Peak memory 217028 kb
Host smart-9711988c-5191-4358-a3d4-9f7f44ca6be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491957589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3491957589
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3047903637
Short name T412
Test name
Test status
Simulation time 15362488809 ps
CPU time 21.26 seconds
Started Jun 06 01:58:43 PM PDT 24
Finished Jun 06 01:59:05 PM PDT 24
Peak memory 217092 kb
Host smart-6ac5fa13-d7d9-4d74-bd2f-ef27dfc8948d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047903637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3047903637
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1151619358
Short name T384
Test name
Test status
Simulation time 199693812 ps
CPU time 2.76 seconds
Started Jun 06 01:59:02 PM PDT 24
Finished Jun 06 01:59:06 PM PDT 24
Peak memory 216872 kb
Host smart-e4def235-bdd3-45bc-89da-2e536b5782b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151619358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1151619358
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2270831234
Short name T80
Test name
Test status
Simulation time 263937644 ps
CPU time 0.85 seconds
Started Jun 06 01:58:45 PM PDT 24
Finished Jun 06 01:58:47 PM PDT 24
Peak memory 206488 kb
Host smart-83b1f0c1-52c3-4d08-8beb-746c1fe1aaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270831234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2270831234
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2748907467
Short name T545
Test name
Test status
Simulation time 140586384 ps
CPU time 2.46 seconds
Started Jun 06 01:58:46 PM PDT 24
Finished Jun 06 01:58:49 PM PDT 24
Peak memory 233236 kb
Host smart-a4d24c5e-291b-4ef2-9d76-82bfa4540458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748907467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2748907467
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3953916761
Short name T762
Test name
Test status
Simulation time 46692207 ps
CPU time 0.73 seconds
Started Jun 06 01:58:58 PM PDT 24
Finished Jun 06 01:58:59 PM PDT 24
Peak memory 206016 kb
Host smart-b0c78158-9d90-4ef6-b0a2-deb3fc8f72eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953916761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3953916761
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2184235625
Short name T507
Test name
Test status
Simulation time 4075451871 ps
CPU time 15.83 seconds
Started Jun 06 01:58:51 PM PDT 24
Finished Jun 06 01:59:08 PM PDT 24
Peak memory 233488 kb
Host smart-3aaa2057-4711-494e-9cba-a15207168e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184235625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2184235625
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2792930029
Short name T496
Test name
Test status
Simulation time 14818233 ps
CPU time 0.72 seconds
Started Jun 06 01:58:44 PM PDT 24
Finished Jun 06 01:58:46 PM PDT 24
Peak memory 206556 kb
Host smart-8b09972e-a966-4c52-b00c-5073bb693154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792930029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2792930029
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1840872333
Short name T489
Test name
Test status
Simulation time 30333889 ps
CPU time 0.79 seconds
Started Jun 06 01:59:06 PM PDT 24
Finished Jun 06 01:59:07 PM PDT 24
Peak memory 216496 kb
Host smart-37091b81-a78a-40d8-a5dc-b170c4c26ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840872333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1840872333
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.4169444860
Short name T178
Test name
Test status
Simulation time 3021539240 ps
CPU time 30.52 seconds
Started Jun 06 01:59:02 PM PDT 24
Finished Jun 06 01:59:33 PM PDT 24
Peak memory 225340 kb
Host smart-863172af-6e89-444a-80bb-672e43375949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169444860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.4169444860
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2637550503
Short name T827
Test name
Test status
Simulation time 9028418175 ps
CPU time 49.55 seconds
Started Jun 06 01:58:44 PM PDT 24
Finished Jun 06 01:59:35 PM PDT 24
Peak memory 249924 kb
Host smart-b3391a7f-312a-49fb-b03b-cb5f85bebb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637550503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2637550503
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3026102961
Short name T857
Test name
Test status
Simulation time 210942817 ps
CPU time 3.01 seconds
Started Jun 06 01:59:01 PM PDT 24
Finished Jun 06 01:59:05 PM PDT 24
Peak memory 233396 kb
Host smart-a447fb09-a0ac-4548-9587-ff08ab238d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026102961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3026102961
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.924161174
Short name T219
Test name
Test status
Simulation time 396453299 ps
CPU time 5.77 seconds
Started Jun 06 01:58:55 PM PDT 24
Finished Jun 06 01:59:02 PM PDT 24
Peak memory 233380 kb
Host smart-ebf06927-83da-4dfa-8042-48b86f36634b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924161174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.924161174
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2255140570
Short name T201
Test name
Test status
Simulation time 2357936936 ps
CPU time 9.91 seconds
Started Jun 06 01:58:53 PM PDT 24
Finished Jun 06 01:59:03 PM PDT 24
Peak memory 233488 kb
Host smart-7b2fa456-59ba-4a23-8636-11e6559020a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255140570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2255140570
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1700507670
Short name T432
Test name
Test status
Simulation time 1086618527 ps
CPU time 2.61 seconds
Started Jun 06 01:58:56 PM PDT 24
Finished Jun 06 01:58:59 PM PDT 24
Peak memory 225060 kb
Host smart-78e11419-ee2b-4994-9b4b-31350571a8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700507670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1700507670
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.229604545
Short name T749
Test name
Test status
Simulation time 6625644377 ps
CPU time 7.6 seconds
Started Jun 06 01:58:56 PM PDT 24
Finished Jun 06 01:59:05 PM PDT 24
Peak memory 225268 kb
Host smart-9e681a61-470a-4d39-a046-e93e46967262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229604545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.229604545
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.930933302
Short name T38
Test name
Test status
Simulation time 610957531 ps
CPU time 4.43 seconds
Started Jun 06 01:58:56 PM PDT 24
Finished Jun 06 01:59:01 PM PDT 24
Peak memory 221228 kb
Host smart-6a8f5203-e185-4751-9694-cb26d8e866f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=930933302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.930933302
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2177593824
Short name T702
Test name
Test status
Simulation time 11094082513 ps
CPU time 29.4 seconds
Started Jun 06 01:58:46 PM PDT 24
Finished Jun 06 01:59:16 PM PDT 24
Peak memory 220720 kb
Host smart-80d2c30d-7404-4abc-9873-dfee0b1c576d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177593824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2177593824
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.690816162
Short name T378
Test name
Test status
Simulation time 985283685 ps
CPU time 6.57 seconds
Started Jun 06 01:58:45 PM PDT 24
Finished Jun 06 01:58:52 PM PDT 24
Peak memory 216936 kb
Host smart-335e6f0d-ede0-4585-98d8-d8ac7a041201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690816162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.690816162
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2719127004
Short name T377
Test name
Test status
Simulation time 162705806 ps
CPU time 2.44 seconds
Started Jun 06 01:58:45 PM PDT 24
Finished Jun 06 01:58:49 PM PDT 24
Peak memory 217036 kb
Host smart-1d37ac46-91b7-4c54-9b33-a320add0109d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719127004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2719127004
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2449229764
Short name T431
Test name
Test status
Simulation time 23869695 ps
CPU time 0.74 seconds
Started Jun 06 01:58:47 PM PDT 24
Finished Jun 06 01:58:48 PM PDT 24
Peak memory 206916 kb
Host smart-df9c0a4e-2519-4212-8d92-b91ac2dfd6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449229764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2449229764
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.196193995
Short name T199
Test name
Test status
Simulation time 2232872834 ps
CPU time 12.45 seconds
Started Jun 06 01:59:00 PM PDT 24
Finished Jun 06 01:59:14 PM PDT 24
Peak memory 233468 kb
Host smart-39dd4794-f1d3-458c-9d5a-9f1433d8ecbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196193995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.196193995
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.248747736
Short name T878
Test name
Test status
Simulation time 55253349 ps
CPU time 0.72 seconds
Started Jun 06 01:58:55 PM PDT 24
Finished Jun 06 01:58:56 PM PDT 24
Peak memory 206088 kb
Host smart-79a795a2-43ae-4cbc-b11a-86290ec3aedb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248747736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.248747736
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.827814589
Short name T317
Test name
Test status
Simulation time 897184710 ps
CPU time 10.21 seconds
Started Jun 06 01:58:48 PM PDT 24
Finished Jun 06 01:58:59 PM PDT 24
Peak memory 233400 kb
Host smart-e0b5bfed-7b09-4619-b6f9-32ac0d0cc922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827814589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.827814589
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3446166397
Short name T670
Test name
Test status
Simulation time 48022499 ps
CPU time 0.82 seconds
Started Jun 06 01:59:00 PM PDT 24
Finished Jun 06 01:59:02 PM PDT 24
Peak memory 207264 kb
Host smart-ea3af692-41b0-43e4-8cd9-2861fcb1c3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446166397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3446166397
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3599336076
Short name T301
Test name
Test status
Simulation time 25805356256 ps
CPU time 78.45 seconds
Started Jun 06 01:58:46 PM PDT 24
Finished Jun 06 02:00:05 PM PDT 24
Peak memory 239560 kb
Host smart-6b493e13-5489-423d-b7ec-418a8e88a4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599336076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3599336076
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3002824720
Short name T484
Test name
Test status
Simulation time 241507311249 ps
CPU time 203.31 seconds
Started Jun 06 01:59:00 PM PDT 24
Finished Jun 06 02:02:25 PM PDT 24
Peak memory 249940 kb
Host smart-123d1731-b4b3-4ec6-b747-0ad3f82dee9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002824720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3002824720
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1659524068
Short name T385
Test name
Test status
Simulation time 3918823482 ps
CPU time 4.1 seconds
Started Jun 06 01:58:50 PM PDT 24
Finished Jun 06 01:58:54 PM PDT 24
Peak memory 225220 kb
Host smart-fc2c4154-4d05-4073-a474-aec0a00a6351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659524068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1659524068
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3099386280
Short name T788
Test name
Test status
Simulation time 8756799894 ps
CPU time 37.15 seconds
Started Jun 06 01:58:48 PM PDT 24
Finished Jun 06 01:59:26 PM PDT 24
Peak memory 233472 kb
Host smart-2771273c-2826-406e-abad-079dae313ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099386280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3099386280
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.17033895
Short name T10
Test name
Test status
Simulation time 75714714 ps
CPU time 2.83 seconds
Started Jun 06 01:58:48 PM PDT 24
Finished Jun 06 01:58:52 PM PDT 24
Peak memory 233364 kb
Host smart-0b21b096-53e7-4ebb-b997-db26b3579da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17033895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.17033895
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.4176893782
Short name T34
Test name
Test status
Simulation time 3443329737 ps
CPU time 7.1 seconds
Started Jun 06 01:58:56 PM PDT 24
Finished Jun 06 01:59:04 PM PDT 24
Peak memory 233416 kb
Host smart-c82bb8ae-2850-42b9-ac92-a0f0d2cdee27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176893782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.4176893782
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3531055475
Short name T188
Test name
Test status
Simulation time 160261177 ps
CPU time 2.08 seconds
Started Jun 06 01:58:59 PM PDT 24
Finished Jun 06 01:59:02 PM PDT 24
Peak memory 225236 kb
Host smart-e3c7edee-b735-4ec5-8fc5-74909bda0fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531055475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3531055475
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.183348654
Short name T528
Test name
Test status
Simulation time 4458319112 ps
CPU time 14.43 seconds
Started Jun 06 01:59:00 PM PDT 24
Finished Jun 06 01:59:16 PM PDT 24
Peak memory 222860 kb
Host smart-87828a43-cd9f-48c8-ac53-d17cd6ca73e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=183348654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.183348654
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3196234558
Short name T166
Test name
Test status
Simulation time 163300273 ps
CPU time 1.22 seconds
Started Jun 06 01:58:56 PM PDT 24
Finished Jun 06 01:58:58 PM PDT 24
Peak memory 207688 kb
Host smart-6bfb1837-c069-43cc-ad8d-ac1bb0b04c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196234558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3196234558
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2545160474
Short name T700
Test name
Test status
Simulation time 4704418412 ps
CPU time 25.69 seconds
Started Jun 06 01:58:45 PM PDT 24
Finished Jun 06 01:59:12 PM PDT 24
Peak memory 217028 kb
Host smart-a2063424-1eb8-4cb1-a1ff-bdf8c22dff0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545160474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2545160474
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2269794272
Short name T699
Test name
Test status
Simulation time 1615001833 ps
CPU time 6.57 seconds
Started Jun 06 01:58:43 PM PDT 24
Finished Jun 06 01:58:50 PM PDT 24
Peak memory 217044 kb
Host smart-3d3ee315-609e-4075-90af-ecf08418c473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269794272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2269794272
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4094976956
Short name T477
Test name
Test status
Simulation time 239845304 ps
CPU time 3.16 seconds
Started Jun 06 01:58:46 PM PDT 24
Finished Jun 06 01:58:50 PM PDT 24
Peak memory 216952 kb
Host smart-75b99ed8-aac0-4bfc-9e75-4afbcfb0e4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094976956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4094976956
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1732329409
Short name T537
Test name
Test status
Simulation time 73143174 ps
CPU time 0.95 seconds
Started Jun 06 01:58:53 PM PDT 24
Finished Jun 06 01:58:54 PM PDT 24
Peak memory 206572 kb
Host smart-579830e1-3ee2-480f-92ad-3e880e85842a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732329409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1732329409
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1944415776
Short name T574
Test name
Test status
Simulation time 1110599250 ps
CPU time 4.82 seconds
Started Jun 06 01:58:47 PM PDT 24
Finished Jun 06 01:58:53 PM PDT 24
Peak memory 241568 kb
Host smart-000c9091-da5a-4740-950a-576117907213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944415776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1944415776
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3591662328
Short name T725
Test name
Test status
Simulation time 21168301 ps
CPU time 0.72 seconds
Started Jun 06 01:59:00 PM PDT 24
Finished Jun 06 01:59:02 PM PDT 24
Peak memory 206152 kb
Host smart-bf855c70-3cce-4a95-a90b-66d7482e2f9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591662328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3591662328
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2131677940
Short name T721
Test name
Test status
Simulation time 153570613 ps
CPU time 3.63 seconds
Started Jun 06 01:59:04 PM PDT 24
Finished Jun 06 01:59:08 PM PDT 24
Peak memory 233440 kb
Host smart-22b1b46a-f48a-4144-aea9-82c4f9090901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131677940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2131677940
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.217485740
Short name T742
Test name
Test status
Simulation time 51243506 ps
CPU time 0.82 seconds
Started Jun 06 01:58:50 PM PDT 24
Finished Jun 06 01:58:52 PM PDT 24
Peak memory 207548 kb
Host smart-da7b87ef-44c8-4ad0-9ede-94b31142d8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217485740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.217485740
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3441984011
Short name T554
Test name
Test status
Simulation time 26732412859 ps
CPU time 46.44 seconds
Started Jun 06 01:59:05 PM PDT 24
Finished Jun 06 01:59:53 PM PDT 24
Peak memory 250516 kb
Host smart-69369065-dbd6-48b7-b487-398e420c150d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441984011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3441984011
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3236895164
Short name T47
Test name
Test status
Simulation time 128783831016 ps
CPU time 292.24 seconds
Started Jun 06 01:59:01 PM PDT 24
Finished Jun 06 02:03:54 PM PDT 24
Peak memory 255064 kb
Host smart-da7480d4-4631-49b2-85b5-c7a95d303651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236895164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3236895164
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.264304549
Short name T481
Test name
Test status
Simulation time 123790985909 ps
CPU time 41.27 seconds
Started Jun 06 01:58:57 PM PDT 24
Finished Jun 06 01:59:39 PM PDT 24
Peak memory 218340 kb
Host smart-45c72a1c-7d4c-407b-99a7-69231320853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264304549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.264304549
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2619965906
Short name T473
Test name
Test status
Simulation time 231979491 ps
CPU time 8.29 seconds
Started Jun 06 01:59:02 PM PDT 24
Finished Jun 06 01:59:11 PM PDT 24
Peak memory 236104 kb
Host smart-58d0ce52-fef0-4b37-b505-03ba1efc2a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619965906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2619965906
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3283625206
Short name T230
Test name
Test status
Simulation time 813142756 ps
CPU time 5.62 seconds
Started Jun 06 01:59:07 PM PDT 24
Finished Jun 06 01:59:14 PM PDT 24
Peak memory 220200 kb
Host smart-cf485edb-9430-47bf-bcbc-40bded9df586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283625206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3283625206
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2814278933
Short name T831
Test name
Test status
Simulation time 2272323424 ps
CPU time 30.56 seconds
Started Jun 06 01:59:07 PM PDT 24
Finished Jun 06 01:59:39 PM PDT 24
Peak memory 249884 kb
Host smart-378c62ac-9a61-41a8-b86a-84c7aa9bc398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814278933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2814278933
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3425413414
Short name T259
Test name
Test status
Simulation time 8791243876 ps
CPU time 10.7 seconds
Started Jun 06 01:58:47 PM PDT 24
Finished Jun 06 01:58:58 PM PDT 24
Peak memory 233496 kb
Host smart-ff8af922-449a-433b-8dbc-f3d834e5ab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425413414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3425413414
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3116901345
Short name T302
Test name
Test status
Simulation time 679240577 ps
CPU time 7.55 seconds
Started Jun 06 01:58:50 PM PDT 24
Finished Jun 06 01:58:59 PM PDT 24
Peak memory 225168 kb
Host smart-187723a8-fddf-4f63-ad95-01fc18156a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116901345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3116901345
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1532663122
Short name T900
Test name
Test status
Simulation time 1354693030 ps
CPU time 4.89 seconds
Started Jun 06 01:59:01 PM PDT 24
Finished Jun 06 01:59:07 PM PDT 24
Peak memory 219948 kb
Host smart-5b1a3ae7-c0a8-47a3-86c9-1e2ea209ad31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1532663122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1532663122
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.129500282
Short name T324
Test name
Test status
Simulation time 6588600468 ps
CPU time 18.02 seconds
Started Jun 06 01:59:00 PM PDT 24
Finished Jun 06 01:59:19 PM PDT 24
Peak memory 250000 kb
Host smart-3ac539ad-964c-42d1-b59e-a1bf7035a5a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129500282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.129500282
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.259842656
Short name T336
Test name
Test status
Simulation time 4161895449 ps
CPU time 26.49 seconds
Started Jun 06 01:58:55 PM PDT 24
Finished Jun 06 01:59:23 PM PDT 24
Peak memory 217000 kb
Host smart-b63171f9-0a0a-4ee4-ad7d-b902e8bfd11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259842656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.259842656
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1151766979
Short name T470
Test name
Test status
Simulation time 3707250573 ps
CPU time 5.38 seconds
Started Jun 06 01:59:02 PM PDT 24
Finished Jun 06 01:59:08 PM PDT 24
Peak memory 217084 kb
Host smart-fef6253a-35c7-4c17-9536-bbbe9c5f08e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151766979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1151766979
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1550801406
Short name T914
Test name
Test status
Simulation time 96213105 ps
CPU time 2.1 seconds
Started Jun 06 01:58:57 PM PDT 24
Finished Jun 06 01:58:59 PM PDT 24
Peak memory 217056 kb
Host smart-5ff840a9-b08d-4f62-9d48-248e18a063e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550801406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1550801406
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3437871579
Short name T499
Test name
Test status
Simulation time 55671649 ps
CPU time 0.79 seconds
Started Jun 06 01:58:47 PM PDT 24
Finished Jun 06 01:58:49 PM PDT 24
Peak memory 206564 kb
Host smart-41493884-a2bf-4299-b44e-b24b20d8327b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437871579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3437871579
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1927257371
Short name T946
Test name
Test status
Simulation time 852772562 ps
CPU time 2.65 seconds
Started Jun 06 01:59:08 PM PDT 24
Finished Jun 06 01:59:11 PM PDT 24
Peak memory 225204 kb
Host smart-31b0edff-04b9-49e6-bd1d-ef0bf6db2a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927257371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1927257371
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.137937576
Short name T57
Test name
Test status
Simulation time 13447613 ps
CPU time 0.72 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:23 PM PDT 24
Peak memory 206136 kb
Host smart-a3a3299e-26cb-4927-b9ed-c0eb67ae167e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137937576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.137937576
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.4164523204
Short name T310
Test name
Test status
Simulation time 1838951197 ps
CPU time 10.98 seconds
Started Jun 06 01:57:02 PM PDT 24
Finished Jun 06 01:57:14 PM PDT 24
Peak memory 225196 kb
Host smart-2af7d012-45f1-4f28-aa98-caec82594c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164523204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4164523204
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1939406082
Short name T790
Test name
Test status
Simulation time 52875444 ps
CPU time 0.76 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:23 PM PDT 24
Peak memory 207256 kb
Host smart-139c9513-a93c-403f-ab6d-37f0713e6658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939406082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1939406082
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3989671211
Short name T272
Test name
Test status
Simulation time 4672738931 ps
CPU time 26.94 seconds
Started Jun 06 01:57:15 PM PDT 24
Finished Jun 06 01:57:43 PM PDT 24
Peak memory 225296 kb
Host smart-b7798f32-c57d-4499-a2fe-975d8bc4088f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989671211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3989671211
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3479228620
Short name T618
Test name
Test status
Simulation time 189842122 ps
CPU time 1.99 seconds
Started Jun 06 01:57:15 PM PDT 24
Finished Jun 06 01:57:18 PM PDT 24
Peak memory 218100 kb
Host smart-9b70118c-f8dd-47cc-88fc-5a734809485a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479228620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3479228620
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.860599317
Short name T837
Test name
Test status
Simulation time 1517229719 ps
CPU time 18.65 seconds
Started Jun 06 01:57:09 PM PDT 24
Finished Jun 06 01:57:29 PM PDT 24
Peak memory 235744 kb
Host smart-7db4c9c2-8579-4cf8-9356-ac8f3397384b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860599317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.860599317
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1290101427
Short name T757
Test name
Test status
Simulation time 15774858644 ps
CPU time 28.53 seconds
Started Jun 06 01:57:13 PM PDT 24
Finished Jun 06 01:57:42 PM PDT 24
Peak memory 233484 kb
Host smart-d4cdc2f2-eabc-4b15-b53a-cabe4c48c30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290101427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1290101427
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.751514701
Short name T15
Test name
Test status
Simulation time 25329211075 ps
CPU time 43.09 seconds
Started Jun 06 01:57:15 PM PDT 24
Finished Jun 06 01:57:59 PM PDT 24
Peak memory 233364 kb
Host smart-b388bef5-3b14-4aca-976d-16256931d597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751514701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.751514701
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.4250344574
Short name T595
Test name
Test status
Simulation time 1182039906 ps
CPU time 5.93 seconds
Started Jun 06 01:57:16 PM PDT 24
Finished Jun 06 01:57:23 PM PDT 24
Peak memory 233432 kb
Host smart-989c1c3f-d636-47e9-9ec1-2d623f341ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250344574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.4250344574
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2390219922
Short name T288
Test name
Test status
Simulation time 179144439 ps
CPU time 2.81 seconds
Started Jun 06 01:57:09 PM PDT 24
Finished Jun 06 01:57:13 PM PDT 24
Peak memory 225120 kb
Host smart-06df0e70-4d7b-41d0-8cdf-fc44afbde2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390219922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2390219922
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1833099418
Short name T789
Test name
Test status
Simulation time 4986293400 ps
CPU time 12.8 seconds
Started Jun 06 01:57:15 PM PDT 24
Finished Jun 06 01:57:29 PM PDT 24
Peak memory 221520 kb
Host smart-0e821167-064e-4718-80cd-a3eadd626276
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1833099418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1833099418
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1330070380
Short name T64
Test name
Test status
Simulation time 144588133 ps
CPU time 0.95 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:24 PM PDT 24
Peak memory 235760 kb
Host smart-4d8e9607-3557-4e57-a73b-3de1a6865b90
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330070380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1330070380
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2524534962
Short name T4
Test name
Test status
Simulation time 9710299966 ps
CPU time 47.73 seconds
Started Jun 06 01:57:09 PM PDT 24
Finished Jun 06 01:57:57 PM PDT 24
Peak memory 217048 kb
Host smart-d7c6a58c-8746-45a7-a84e-20319633ea0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524534962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2524534962
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.539210489
Short name T579
Test name
Test status
Simulation time 2417983377 ps
CPU time 7.65 seconds
Started Jun 06 01:57:16 PM PDT 24
Finished Jun 06 01:57:25 PM PDT 24
Peak memory 217004 kb
Host smart-4cbc965e-6843-4bff-8ae7-6e556426e866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539210489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.539210489
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4088856723
Short name T718
Test name
Test status
Simulation time 30258778 ps
CPU time 1.31 seconds
Started Jun 06 01:57:07 PM PDT 24
Finished Jun 06 01:57:09 PM PDT 24
Peak memory 216924 kb
Host smart-5e108deb-e5a7-4d58-9d0d-d5a36a2c429c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088856723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4088856723
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.797848152
Short name T388
Test name
Test status
Simulation time 557091321 ps
CPU time 0.96 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:28 PM PDT 24
Peak memory 206540 kb
Host smart-50866d1e-1a6a-4892-8c69-f3631c1405c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797848152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.797848152
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2892510825
Short name T224
Test name
Test status
Simulation time 848446818 ps
CPU time 4.31 seconds
Started Jun 06 01:57:12 PM PDT 24
Finished Jun 06 01:57:17 PM PDT 24
Peak memory 233364 kb
Host smart-7bdc0e36-daaa-4ec8-b171-2f9e19abd645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892510825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2892510825
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3180229898
Short name T373
Test name
Test status
Simulation time 13824522 ps
CPU time 0.74 seconds
Started Jun 06 01:59:07 PM PDT 24
Finished Jun 06 01:59:09 PM PDT 24
Peak memory 206132 kb
Host smart-647c1efe-f313-4c02-af05-cc7862f451c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180229898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3180229898
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.500843563
Short name T543
Test name
Test status
Simulation time 114775803 ps
CPU time 4.17 seconds
Started Jun 06 01:59:07 PM PDT 24
Finished Jun 06 01:59:12 PM PDT 24
Peak memory 225164 kb
Host smart-ecd7726e-feef-44aa-833f-e798c9c2db19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500843563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.500843563
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.272249672
Short name T723
Test name
Test status
Simulation time 21593241 ps
CPU time 0.75 seconds
Started Jun 06 01:59:11 PM PDT 24
Finished Jun 06 01:59:13 PM PDT 24
Peak memory 207264 kb
Host smart-9306cfbb-2ae3-41a2-9f2e-d47233ff1408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272249672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.272249672
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.199849457
Short name T521
Test name
Test status
Simulation time 2675940537 ps
CPU time 30.67 seconds
Started Jun 06 01:58:54 PM PDT 24
Finished Jun 06 01:59:25 PM PDT 24
Peak memory 249812 kb
Host smart-4045d3af-edc4-4c30-b60d-dd9b8c5cd784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199849457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.199849457
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2555413811
Short name T607
Test name
Test status
Simulation time 4544856341 ps
CPU time 25.59 seconds
Started Jun 06 01:59:03 PM PDT 24
Finished Jun 06 01:59:29 PM PDT 24
Peak memory 225296 kb
Host smart-1f7472cb-7ac5-415d-9bd5-30efbffd53f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555413811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2555413811
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1919039769
Short name T917
Test name
Test status
Simulation time 4424041306 ps
CPU time 104.8 seconds
Started Jun 06 01:59:04 PM PDT 24
Finished Jun 06 02:00:50 PM PDT 24
Peak memory 266308 kb
Host smart-1b717b81-b738-4adf-bd62-3844cc00655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919039769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1919039769
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2900389633
Short name T696
Test name
Test status
Simulation time 1513659906 ps
CPU time 5.78 seconds
Started Jun 06 01:58:59 PM PDT 24
Finished Jun 06 01:59:06 PM PDT 24
Peak memory 225308 kb
Host smart-3bd795e4-4ffa-45ba-89fd-69b70c738502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900389633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2900389633
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.697933129
Short name T614
Test name
Test status
Simulation time 130710760 ps
CPU time 3.93 seconds
Started Jun 06 01:59:01 PM PDT 24
Finished Jun 06 01:59:06 PM PDT 24
Peak memory 233408 kb
Host smart-1ddc4925-c02e-4580-b100-700d54b6340b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697933129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.697933129
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.116479218
Short name T491
Test name
Test status
Simulation time 1871761964 ps
CPU time 15.56 seconds
Started Jun 06 01:59:08 PM PDT 24
Finished Jun 06 01:59:24 PM PDT 24
Peak memory 233376 kb
Host smart-48d94f6b-f300-4a6a-9877-f86057e93a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116479218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.116479218
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3906847705
Short name T600
Test name
Test status
Simulation time 672371951 ps
CPU time 5.33 seconds
Started Jun 06 01:59:03 PM PDT 24
Finished Jun 06 01:59:09 PM PDT 24
Peak memory 233392 kb
Host smart-decc1de4-a79b-4a47-bb13-dff10a2342a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906847705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3906847705
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3410213626
Short name T582
Test name
Test status
Simulation time 1813794439 ps
CPU time 4.94 seconds
Started Jun 06 01:59:02 PM PDT 24
Finished Jun 06 01:59:08 PM PDT 24
Peak memory 233356 kb
Host smart-81cbc0a2-4852-4b94-80a7-53f35b71efe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410213626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3410213626
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1900570684
Short name T138
Test name
Test status
Simulation time 274506255 ps
CPU time 3.38 seconds
Started Jun 06 01:59:01 PM PDT 24
Finished Jun 06 01:59:05 PM PDT 24
Peak memory 223600 kb
Host smart-dd900f66-1706-4825-8664-740519fbbcf6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1900570684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1900570684
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1929103239
Short name T249
Test name
Test status
Simulation time 5426454305 ps
CPU time 114 seconds
Started Jun 06 01:59:01 PM PDT 24
Finished Jun 06 02:00:56 PM PDT 24
Peak memory 253964 kb
Host smart-ff35934d-a017-49eb-b8dc-441536f88d9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929103239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1929103239
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.715693926
Short name T41
Test name
Test status
Simulation time 2624191287 ps
CPU time 15.66 seconds
Started Jun 06 01:59:03 PM PDT 24
Finished Jun 06 01:59:19 PM PDT 24
Peak memory 217028 kb
Host smart-39820471-8f35-49ef-b3d6-5078c8aff133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715693926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.715693926
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1569870821
Short name T650
Test name
Test status
Simulation time 1723421700 ps
CPU time 3.14 seconds
Started Jun 06 01:58:59 PM PDT 24
Finished Jun 06 01:59:03 PM PDT 24
Peak memory 208620 kb
Host smart-5ed9c12c-7d97-41ab-8cc9-e96653835d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569870821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1569870821
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2505392025
Short name T765
Test name
Test status
Simulation time 201874838 ps
CPU time 2.62 seconds
Started Jun 06 01:59:08 PM PDT 24
Finished Jun 06 01:59:12 PM PDT 24
Peak memory 216992 kb
Host smart-0af95aa7-5ebe-42ae-9895-5dfd218935c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505392025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2505392025
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.266633693
Short name T741
Test name
Test status
Simulation time 115281970 ps
CPU time 0.89 seconds
Started Jun 06 01:59:02 PM PDT 24
Finished Jun 06 01:59:03 PM PDT 24
Peak memory 206592 kb
Host smart-83cf79dd-121f-47ae-9bcd-75864dd29adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266633693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.266633693
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2228658530
Short name T406
Test name
Test status
Simulation time 1120934420 ps
CPU time 4.46 seconds
Started Jun 06 01:58:58 PM PDT 24
Finished Jun 06 01:59:03 PM PDT 24
Peak memory 225156 kb
Host smart-77441523-10f2-49a0-8de7-c7b8260701d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228658530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2228658530
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.248984145
Short name T627
Test name
Test status
Simulation time 20796087 ps
CPU time 0.71 seconds
Started Jun 06 01:58:55 PM PDT 24
Finished Jun 06 01:58:56 PM PDT 24
Peak memory 206184 kb
Host smart-7f614609-bcb2-41db-93a1-3990af96d1c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248984145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.248984145
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3491969944
Short name T515
Test name
Test status
Simulation time 8984048936 ps
CPU time 21.18 seconds
Started Jun 06 01:58:59 PM PDT 24
Finished Jun 06 01:59:21 PM PDT 24
Peak memory 233436 kb
Host smart-e34fbf9c-f4fb-43c3-b494-55a6210d4df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491969944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3491969944
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2477475490
Short name T394
Test name
Test status
Simulation time 15251473 ps
CPU time 0.78 seconds
Started Jun 06 01:58:59 PM PDT 24
Finished Jun 06 01:59:01 PM PDT 24
Peak memory 207200 kb
Host smart-37809e34-ce9e-46ee-8eca-e3a61649ddad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477475490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2477475490
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1757667879
Short name T39
Test name
Test status
Simulation time 3860598447 ps
CPU time 29.35 seconds
Started Jun 06 01:58:57 PM PDT 24
Finished Jun 06 01:59:27 PM PDT 24
Peak memory 236632 kb
Host smart-fd2e37f8-c0e5-4b9e-9e63-75cba19da4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757667879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1757667879
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1992131481
Short name T36
Test name
Test status
Simulation time 26357333845 ps
CPU time 207.09 seconds
Started Jun 06 01:59:06 PM PDT 24
Finished Jun 06 02:02:34 PM PDT 24
Peak memory 249936 kb
Host smart-9c3b5e2c-5640-4936-b347-c9c60bef0398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992131481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1992131481
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1717444486
Short name T176
Test name
Test status
Simulation time 3630747984 ps
CPU time 88.86 seconds
Started Jun 06 01:59:04 PM PDT 24
Finished Jun 06 02:00:34 PM PDT 24
Peak memory 249940 kb
Host smart-491c964d-9750-418b-a9de-c34606e3e590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717444486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1717444486
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3569090899
Short name T812
Test name
Test status
Simulation time 445972749 ps
CPU time 3.05 seconds
Started Jun 06 01:58:55 PM PDT 24
Finished Jun 06 01:58:59 PM PDT 24
Peak memory 225212 kb
Host smart-f5161031-017b-4741-a79e-da7c043e7e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569090899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3569090899
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.132444031
Short name T956
Test name
Test status
Simulation time 9246148453 ps
CPU time 14.36 seconds
Started Jun 06 01:59:00 PM PDT 24
Finished Jun 06 01:59:16 PM PDT 24
Peak memory 225184 kb
Host smart-b02280b1-f16e-4373-8e7a-795487ea9472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132444031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.132444031
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2589574403
Short name T527
Test name
Test status
Simulation time 258978160 ps
CPU time 6.3 seconds
Started Jun 06 01:59:06 PM PDT 24
Finished Jun 06 01:59:13 PM PDT 24
Peak memory 241480 kb
Host smart-6aafbde0-0d4a-498f-b921-139bde6137d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589574403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2589574403
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.366665297
Short name T189
Test name
Test status
Simulation time 551411182 ps
CPU time 4.84 seconds
Started Jun 06 01:59:03 PM PDT 24
Finished Jun 06 01:59:08 PM PDT 24
Peak memory 233384 kb
Host smart-422c873b-4585-48dc-9ea1-ee44c80c1416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366665297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.366665297
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3549941559
Short name T286
Test name
Test status
Simulation time 12673845567 ps
CPU time 24.56 seconds
Started Jun 06 01:59:07 PM PDT 24
Finished Jun 06 01:59:32 PM PDT 24
Peak memory 249540 kb
Host smart-d2537c6d-62c6-43d6-b575-69a741239e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549941559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3549941559
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1838243125
Short name T781
Test name
Test status
Simulation time 794093425 ps
CPU time 5.3 seconds
Started Jun 06 01:59:03 PM PDT 24
Finished Jun 06 01:59:10 PM PDT 24
Peak memory 219568 kb
Host smart-d6c9fada-85f6-475a-a4dc-9c6455107deb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1838243125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1838243125
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4055095733
Short name T896
Test name
Test status
Simulation time 66789113934 ps
CPU time 142.83 seconds
Started Jun 06 01:58:55 PM PDT 24
Finished Jun 06 02:01:19 PM PDT 24
Peak memory 258104 kb
Host smart-af3b8d5b-378e-44b4-b4b0-3962a867e187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055095733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4055095733
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3004988752
Short name T948
Test name
Test status
Simulation time 5465678533 ps
CPU time 31.98 seconds
Started Jun 06 01:59:00 PM PDT 24
Finished Jun 06 01:59:33 PM PDT 24
Peak memory 217332 kb
Host smart-8edde07e-7141-4002-886b-792b6a5e1698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004988752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3004988752
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3484394338
Short name T510
Test name
Test status
Simulation time 1281441451 ps
CPU time 2.68 seconds
Started Jun 06 01:58:59 PM PDT 24
Finished Jun 06 01:59:03 PM PDT 24
Peak memory 216960 kb
Host smart-6be10388-13e1-45a6-989b-a566b5abfcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484394338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3484394338
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.294306263
Short name T365
Test name
Test status
Simulation time 955514166 ps
CPU time 1.27 seconds
Started Jun 06 01:59:03 PM PDT 24
Finished Jun 06 01:59:06 PM PDT 24
Peak memory 217052 kb
Host smart-8abca405-c9d8-4f18-b916-3ca9e2f3e08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294306263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.294306263
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3550872083
Short name T952
Test name
Test status
Simulation time 29302076 ps
CPU time 0.77 seconds
Started Jun 06 01:58:59 PM PDT 24
Finished Jun 06 01:59:01 PM PDT 24
Peak memory 206496 kb
Host smart-649c3d38-9ea3-4acb-b71c-0c036d3f0dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550872083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3550872083
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3075972929
Short name T938
Test name
Test status
Simulation time 134701666 ps
CPU time 2.56 seconds
Started Jun 06 01:58:55 PM PDT 24
Finished Jun 06 01:58:58 PM PDT 24
Peak memory 234928 kb
Host smart-25eca988-e937-406a-b86c-852694c24774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075972929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3075972929
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1556921344
Short name T628
Test name
Test status
Simulation time 16138681 ps
CPU time 0.76 seconds
Started Jun 06 01:59:07 PM PDT 24
Finished Jun 06 01:59:09 PM PDT 24
Peak memory 206428 kb
Host smart-29fdaa54-14ba-49c1-af11-85a760a86162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556921344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1556921344
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2494295194
Short name T525
Test name
Test status
Simulation time 1962903242 ps
CPU time 7.3 seconds
Started Jun 06 01:59:57 PM PDT 24
Finished Jun 06 02:00:05 PM PDT 24
Peak memory 225188 kb
Host smart-7949ddff-9ac2-43d5-bb4d-eefaa6387ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494295194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2494295194
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1378942678
Short name T379
Test name
Test status
Simulation time 18091421 ps
CPU time 0.82 seconds
Started Jun 06 01:59:01 PM PDT 24
Finished Jun 06 01:59:03 PM PDT 24
Peak memory 207500 kb
Host smart-e6ac9fb5-9e7a-4d3f-91a5-5bfc76294bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378942678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1378942678
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3703244837
Short name T441
Test name
Test status
Simulation time 21331497682 ps
CPU time 94.08 seconds
Started Jun 06 01:58:58 PM PDT 24
Finished Jun 06 02:00:33 PM PDT 24
Peak memory 249836 kb
Host smart-b697cf34-0811-451f-83a0-7607127fef72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703244837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3703244837
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1792237253
Short name T756
Test name
Test status
Simulation time 53363318061 ps
CPU time 280.57 seconds
Started Jun 06 01:58:59 PM PDT 24
Finished Jun 06 02:03:40 PM PDT 24
Peak memory 257744 kb
Host smart-ff61dd5c-1074-4e71-aafc-7709c4793106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792237253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1792237253
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3355840124
Short name T691
Test name
Test status
Simulation time 66882579339 ps
CPU time 332.99 seconds
Started Jun 06 01:58:58 PM PDT 24
Finished Jun 06 02:04:32 PM PDT 24
Peak memory 258060 kb
Host smart-10b21c00-5fe0-45a4-ad6e-107bac5294cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355840124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3355840124
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.103880194
Short name T395
Test name
Test status
Simulation time 1002784938 ps
CPU time 6.7 seconds
Started Jun 06 01:58:57 PM PDT 24
Finished Jun 06 01:59:04 PM PDT 24
Peak memory 238708 kb
Host smart-48ccf921-8442-440f-b0a5-19586b45ad69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103880194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.103880194
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1144848202
Short name T229
Test name
Test status
Simulation time 77134500 ps
CPU time 2.78 seconds
Started Jun 06 01:59:04 PM PDT 24
Finished Jun 06 01:59:07 PM PDT 24
Peak memory 233404 kb
Host smart-6041e7ea-03ef-4ee9-8e9e-952a6bbf0ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144848202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1144848202
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.859021619
Short name T836
Test name
Test status
Simulation time 7744374646 ps
CPU time 70.96 seconds
Started Jun 06 01:59:07 PM PDT 24
Finished Jun 06 02:00:19 PM PDT 24
Peak memory 225184 kb
Host smart-20396093-787b-4cdc-82b0-5fd1d0e24076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859021619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.859021619
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2683334302
Short name T262
Test name
Test status
Simulation time 378543883 ps
CPU time 7.04 seconds
Started Jun 06 01:59:05 PM PDT 24
Finished Jun 06 01:59:13 PM PDT 24
Peak memory 241528 kb
Host smart-014f4357-3670-4d42-9f8d-695509e0d8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683334302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2683334302
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.875272944
Short name T560
Test name
Test status
Simulation time 648924248 ps
CPU time 7.44 seconds
Started Jun 06 01:58:59 PM PDT 24
Finished Jun 06 01:59:08 PM PDT 24
Peak memory 241436 kb
Host smart-846cbc44-8649-4099-b890-6dc9f69a946d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875272944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.875272944
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1040707215
Short name T142
Test name
Test status
Simulation time 116673408 ps
CPU time 3.34 seconds
Started Jun 06 01:59:04 PM PDT 24
Finished Jun 06 01:59:08 PM PDT 24
Peak memory 223168 kb
Host smart-e498261e-d512-417f-9667-74fa65ee6286
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1040707215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1040707215
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3887845704
Short name T524
Test name
Test status
Simulation time 5921710764 ps
CPU time 32.77 seconds
Started Jun 06 01:59:03 PM PDT 24
Finished Jun 06 01:59:37 PM PDT 24
Peak memory 217052 kb
Host smart-38e17a80-1fbc-46fe-a756-8c3d36dbc5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887845704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3887845704
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3833920883
Short name T693
Test name
Test status
Simulation time 1779614667 ps
CPU time 8.78 seconds
Started Jun 06 01:59:00 PM PDT 24
Finished Jun 06 01:59:09 PM PDT 24
Peak memory 217004 kb
Host smart-89d34a9f-8828-4506-b5ef-a751235688c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833920883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3833920883
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.602905230
Short name T532
Test name
Test status
Simulation time 224217297 ps
CPU time 2.32 seconds
Started Jun 06 01:59:01 PM PDT 24
Finished Jun 06 01:59:04 PM PDT 24
Peak memory 217000 kb
Host smart-bd889177-f760-49f3-9410-af6d1d9fdd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602905230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.602905230
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2333719072
Short name T869
Test name
Test status
Simulation time 153114972 ps
CPU time 0.97 seconds
Started Jun 06 01:59:00 PM PDT 24
Finished Jun 06 01:59:01 PM PDT 24
Peak memory 207584 kb
Host smart-9ec1a6c5-3bd3-4548-b7e4-c36c8829df5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333719072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2333719072
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.366592933
Short name T490
Test name
Test status
Simulation time 6837944558 ps
CPU time 23 seconds
Started Jun 06 01:58:59 PM PDT 24
Finished Jun 06 01:59:23 PM PDT 24
Peak memory 233484 kb
Host smart-5ae07abd-1676-4df7-9bbc-c8a5879a6cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366592933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.366592933
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1808985824
Short name T641
Test name
Test status
Simulation time 47467210 ps
CPU time 0.73 seconds
Started Jun 06 01:59:04 PM PDT 24
Finished Jun 06 01:59:06 PM PDT 24
Peak memory 206404 kb
Host smart-647a2d1a-779a-43ae-a0f1-abea0008b863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808985824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1808985824
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3175368809
Short name T308
Test name
Test status
Simulation time 5630429792 ps
CPU time 13.87 seconds
Started Jun 06 01:59:06 PM PDT 24
Finished Jun 06 01:59:21 PM PDT 24
Peak memory 225292 kb
Host smart-610662b6-d61b-4866-af1c-1b4578b3e3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175368809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3175368809
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1367119786
Short name T402
Test name
Test status
Simulation time 60569761 ps
CPU time 0.83 seconds
Started Jun 06 01:59:00 PM PDT 24
Finished Jun 06 01:59:01 PM PDT 24
Peak memory 207288 kb
Host smart-a32d025e-4d40-4aeb-995c-58132a59829b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367119786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1367119786
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1002253755
Short name T567
Test name
Test status
Simulation time 111840840079 ps
CPU time 195.27 seconds
Started Jun 06 01:59:13 PM PDT 24
Finished Jun 06 02:02:29 PM PDT 24
Peak memory 249872 kb
Host smart-5430aa69-784b-4ed3-8e62-27cc1433a5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002253755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1002253755
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.325138431
Short name T292
Test name
Test status
Simulation time 52166678316 ps
CPU time 193.05 seconds
Started Jun 06 01:59:04 PM PDT 24
Finished Jun 06 02:02:18 PM PDT 24
Peak memory 249928 kb
Host smart-714a8e0b-c547-4c2d-a00c-46a7fdb4df71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325138431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.325138431
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.810430754
Short name T957
Test name
Test status
Simulation time 6230505110 ps
CPU time 95.08 seconds
Started Jun 06 01:59:16 PM PDT 24
Finished Jun 06 02:00:53 PM PDT 24
Peak memory 255896 kb
Host smart-a335820c-9713-49cf-975e-632c784b420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810430754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.810430754
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1820845685
Short name T376
Test name
Test status
Simulation time 139122311 ps
CPU time 2.53 seconds
Started Jun 06 01:59:10 PM PDT 24
Finished Jun 06 01:59:13 PM PDT 24
Peak memory 225220 kb
Host smart-8ff80e04-bf95-4f88-a608-3129022b4bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820845685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1820845685
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.469046052
Short name T890
Test name
Test status
Simulation time 1090999803 ps
CPU time 12.83 seconds
Started Jun 06 01:59:13 PM PDT 24
Finished Jun 06 01:59:26 PM PDT 24
Peak memory 233392 kb
Host smart-bc91d16a-cf63-40f5-89a8-4671f237ca1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469046052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.469046052
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1365815471
Short name T853
Test name
Test status
Simulation time 4979428142 ps
CPU time 24.19 seconds
Started Jun 06 01:59:04 PM PDT 24
Finished Jun 06 01:59:30 PM PDT 24
Peak memory 233460 kb
Host smart-b12dde24-5407-494b-981a-ffcb94888177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365815471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1365815471
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1873432279
Short name T325
Test name
Test status
Simulation time 216389820 ps
CPU time 2.79 seconds
Started Jun 06 01:59:10 PM PDT 24
Finished Jun 06 01:59:14 PM PDT 24
Peak memory 233412 kb
Host smart-eca61b14-a92b-4de0-95ef-f4c6d7384e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873432279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1873432279
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1022959948
Short name T701
Test name
Test status
Simulation time 8330873657 ps
CPU time 6.33 seconds
Started Jun 06 01:59:14 PM PDT 24
Finished Jun 06 01:59:21 PM PDT 24
Peak memory 233484 kb
Host smart-79d26923-e518-4d0a-b34a-9f2a65741478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022959948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1022959948
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.735127769
Short name T924
Test name
Test status
Simulation time 2846199892 ps
CPU time 11.68 seconds
Started Jun 06 01:59:08 PM PDT 24
Finished Jun 06 01:59:20 PM PDT 24
Peak memory 223212 kb
Host smart-65474194-17f4-4b90-955f-b95507fff92e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=735127769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.735127769
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.91963986
Short name T410
Test name
Test status
Simulation time 1475437868 ps
CPU time 7.18 seconds
Started Jun 06 01:59:09 PM PDT 24
Finished Jun 06 01:59:17 PM PDT 24
Peak memory 217040 kb
Host smart-c0ceb0ff-1c01-4dd8-a84b-a29d8bf64407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91963986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.91963986
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4027644902
Short name T165
Test name
Test status
Simulation time 840512129 ps
CPU time 3.39 seconds
Started Jun 06 01:59:06 PM PDT 24
Finished Jun 06 01:59:11 PM PDT 24
Peak memory 208600 kb
Host smart-517ff31e-c465-4a68-b928-913513a1cc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027644902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4027644902
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3194519109
Short name T361
Test name
Test status
Simulation time 99891015 ps
CPU time 1.52 seconds
Started Jun 06 01:59:09 PM PDT 24
Finished Jun 06 01:59:11 PM PDT 24
Peak memory 208724 kb
Host smart-65880863-a29d-4fdc-b698-4de0aa62ee56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194519109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3194519109
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1323299756
Short name T535
Test name
Test status
Simulation time 14473603 ps
CPU time 0.74 seconds
Started Jun 06 01:59:13 PM PDT 24
Finished Jun 06 01:59:15 PM PDT 24
Peak memory 206548 kb
Host smart-22ce803a-a4c4-41d7-b58a-a4696bbb38da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323299756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1323299756
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3283788757
Short name T633
Test name
Test status
Simulation time 731384506 ps
CPU time 7.23 seconds
Started Jun 06 01:59:10 PM PDT 24
Finished Jun 06 01:59:18 PM PDT 24
Peak memory 233112 kb
Host smart-37db120b-de09-426e-a6d2-3e0758d97d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283788757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3283788757
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3212940131
Short name T941
Test name
Test status
Simulation time 14420321 ps
CPU time 0.74 seconds
Started Jun 06 01:59:12 PM PDT 24
Finished Jun 06 01:59:14 PM PDT 24
Peak memory 206144 kb
Host smart-8b8037e2-965e-438c-922c-10cd4d7cc2a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212940131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3212940131
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3594754647
Short name T196
Test name
Test status
Simulation time 377683633 ps
CPU time 2.48 seconds
Started Jun 06 01:59:18 PM PDT 24
Finished Jun 06 01:59:22 PM PDT 24
Peak memory 225244 kb
Host smart-1083affa-f4fa-4c86-86cc-68d37ae18559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594754647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3594754647
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.854895567
Short name T947
Test name
Test status
Simulation time 52621852 ps
CPU time 0.75 seconds
Started Jun 06 01:59:02 PM PDT 24
Finished Jun 06 01:59:03 PM PDT 24
Peak memory 206536 kb
Host smart-2ef233c8-cf60-4c3e-8932-386ce9e11956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854895567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.854895567
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1311294705
Short name T265
Test name
Test status
Simulation time 2961756872 ps
CPU time 75.98 seconds
Started Jun 06 01:59:06 PM PDT 24
Finished Jun 06 02:00:23 PM PDT 24
Peak memory 249900 kb
Host smart-e6e39b8c-bba8-409c-b4b6-ed829e816c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311294705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1311294705
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.190555263
Short name T203
Test name
Test status
Simulation time 25322911660 ps
CPU time 254.32 seconds
Started Jun 06 01:59:07 PM PDT 24
Finished Jun 06 02:03:23 PM PDT 24
Peak memory 256728 kb
Host smart-a92694e7-d564-456b-ab85-bdad78aa0780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190555263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.190555263
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2423851826
Short name T648
Test name
Test status
Simulation time 22322585299 ps
CPU time 206.31 seconds
Started Jun 06 01:59:07 PM PDT 24
Finished Jun 06 02:02:34 PM PDT 24
Peak memory 250268 kb
Host smart-7184b67e-27a0-4f91-8785-61136d5e36eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423851826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2423851826
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3979887835
Short name T726
Test name
Test status
Simulation time 382840935 ps
CPU time 10.05 seconds
Started Jun 06 01:59:13 PM PDT 24
Finished Jun 06 01:59:24 PM PDT 24
Peak memory 251744 kb
Host smart-85fda0a0-00c1-4906-981d-2d02543420e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979887835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3979887835
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3290462271
Short name T284
Test name
Test status
Simulation time 569245852 ps
CPU time 4.8 seconds
Started Jun 06 01:59:10 PM PDT 24
Finished Jun 06 01:59:16 PM PDT 24
Peak memory 233432 kb
Host smart-2cfc5f9d-189d-41ee-b397-3208b16b7d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290462271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3290462271
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.553411978
Short name T295
Test name
Test status
Simulation time 459283404 ps
CPU time 5.04 seconds
Started Jun 06 01:59:10 PM PDT 24
Finished Jun 06 01:59:16 PM PDT 24
Peak memory 228584 kb
Host smart-40671dd4-3dfc-4d37-8b84-7c85094e2ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553411978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.553411978
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3456257998
Short name T722
Test name
Test status
Simulation time 553543683 ps
CPU time 2.51 seconds
Started Jun 06 01:59:04 PM PDT 24
Finished Jun 06 01:59:07 PM PDT 24
Peak memory 225188 kb
Host smart-1df2e82b-ece7-4f2f-a69b-c8f6b4ee1ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456257998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3456257998
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3103486916
Short name T305
Test name
Test status
Simulation time 4974921942 ps
CPU time 9.65 seconds
Started Jun 06 01:59:09 PM PDT 24
Finished Jun 06 01:59:19 PM PDT 24
Peak memory 233468 kb
Host smart-49d39176-e19e-466a-8827-c674d58e3b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103486916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3103486916
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1273378874
Short name T472
Test name
Test status
Simulation time 12215754710 ps
CPU time 11.01 seconds
Started Jun 06 01:59:09 PM PDT 24
Finished Jun 06 01:59:21 PM PDT 24
Peak memory 223204 kb
Host smart-f2433821-02e6-46bc-ba88-c161baed0391
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1273378874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1273378874
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.131512701
Short name T750
Test name
Test status
Simulation time 9199397461 ps
CPU time 10.71 seconds
Started Jun 06 01:59:05 PM PDT 24
Finished Jun 06 01:59:17 PM PDT 24
Peak memory 217036 kb
Host smart-f1cfe3b6-0193-4abc-a089-60053d950573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131512701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.131512701
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.120099368
Short name T868
Test name
Test status
Simulation time 5162796448 ps
CPU time 6.91 seconds
Started Jun 06 01:59:07 PM PDT 24
Finished Jun 06 01:59:15 PM PDT 24
Peak memory 217120 kb
Host smart-338e4b10-998f-49dc-b3b8-6c48e108e186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120099368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.120099368
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.515494607
Short name T942
Test name
Test status
Simulation time 333296539 ps
CPU time 1.19 seconds
Started Jun 06 01:59:11 PM PDT 24
Finished Jun 06 01:59:13 PM PDT 24
Peak memory 208588 kb
Host smart-c839adf2-3b36-4135-b155-afa17390df59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515494607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.515494607
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3669035703
Short name T79
Test name
Test status
Simulation time 69298286 ps
CPU time 0.87 seconds
Started Jun 06 01:59:03 PM PDT 24
Finished Jun 06 01:59:05 PM PDT 24
Peak memory 206560 kb
Host smart-80d87520-341b-4106-b377-5b4eba026dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669035703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3669035703
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3286122931
Short name T96
Test name
Test status
Simulation time 288120103 ps
CPU time 3.87 seconds
Started Jun 06 01:59:12 PM PDT 24
Finished Jun 06 01:59:17 PM PDT 24
Peak memory 225212 kb
Host smart-e144a31f-05e6-481f-990e-04883c8e2ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286122931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3286122931
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1473611047
Short name T418
Test name
Test status
Simulation time 11458300 ps
CPU time 0.73 seconds
Started Jun 06 01:59:12 PM PDT 24
Finished Jun 06 01:59:14 PM PDT 24
Peak memory 205556 kb
Host smart-15c28d54-f561-4da6-b9bf-4fd1082c4396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473611047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1473611047
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3553674264
Short name T724
Test name
Test status
Simulation time 826087388 ps
CPU time 2.93 seconds
Started Jun 06 01:59:20 PM PDT 24
Finished Jun 06 01:59:24 PM PDT 24
Peak memory 225200 kb
Host smart-86ccf66b-f3f0-43b9-a22f-340429ca9050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553674264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3553674264
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.883507815
Short name T803
Test name
Test status
Simulation time 19320577 ps
CPU time 0.77 seconds
Started Jun 06 01:59:11 PM PDT 24
Finished Jun 06 01:59:12 PM PDT 24
Peak memory 207268 kb
Host smart-46a24656-03f1-4aad-87c9-3cd0244aaffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883507815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.883507815
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1928234969
Short name T7
Test name
Test status
Simulation time 75770296986 ps
CPU time 130.68 seconds
Started Jun 06 01:59:10 PM PDT 24
Finished Jun 06 02:01:21 PM PDT 24
Peak memory 239948 kb
Host smart-aa24db9f-3e8c-466f-b6a4-e9e51831ca58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928234969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1928234969
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1695889781
Short name T542
Test name
Test status
Simulation time 22949368270 ps
CPU time 80.15 seconds
Started Jun 06 01:59:11 PM PDT 24
Finished Jun 06 02:00:32 PM PDT 24
Peak memory 251908 kb
Host smart-1209c81f-cb33-44b5-8e59-a5afa4983d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695889781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1695889781
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3311490459
Short name T287
Test name
Test status
Simulation time 6315115453 ps
CPU time 91.13 seconds
Started Jun 06 01:59:06 PM PDT 24
Finished Jun 06 02:00:38 PM PDT 24
Peak memory 256088 kb
Host smart-5518468e-5b5d-4701-a96f-81861c6b82f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311490459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3311490459
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1454530968
Short name T635
Test name
Test status
Simulation time 6912530115 ps
CPU time 23.31 seconds
Started Jun 06 01:59:04 PM PDT 24
Finished Jun 06 01:59:28 PM PDT 24
Peak memory 253528 kb
Host smart-e783d074-7548-45aa-b999-04068b2985b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454530968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1454530968
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1186090821
Short name T865
Test name
Test status
Simulation time 2218192107 ps
CPU time 14.93 seconds
Started Jun 06 01:59:04 PM PDT 24
Finished Jun 06 01:59:20 PM PDT 24
Peak memory 233476 kb
Host smart-dba8a9aa-6789-45a4-a94c-69cca049f908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186090821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1186090821
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1756097971
Short name T895
Test name
Test status
Simulation time 2910229133 ps
CPU time 30.18 seconds
Started Jun 06 01:59:06 PM PDT 24
Finished Jun 06 01:59:37 PM PDT 24
Peak memory 241548 kb
Host smart-86f92cd6-ccfe-4ba2-8788-c0b022cfab49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756097971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1756097971
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.4129224945
Short name T572
Test name
Test status
Simulation time 36566890 ps
CPU time 2.59 seconds
Started Jun 06 01:59:10 PM PDT 24
Finished Jun 06 01:59:13 PM PDT 24
Peak memory 233424 kb
Host smart-e35eb670-5371-4647-9ee5-6df6842cf60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129224945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.4129224945
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2465230714
Short name T462
Test name
Test status
Simulation time 6383433033 ps
CPU time 18.98 seconds
Started Jun 06 01:59:10 PM PDT 24
Finished Jun 06 01:59:30 PM PDT 24
Peak memory 233508 kb
Host smart-f5809224-c773-45d5-928d-b452150ba42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465230714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2465230714
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.465241463
Short name T589
Test name
Test status
Simulation time 495597571 ps
CPU time 3.84 seconds
Started Jun 06 01:59:13 PM PDT 24
Finished Jun 06 01:59:18 PM PDT 24
Peak memory 219932 kb
Host smart-fd014829-08fc-43f7-b9c5-ab5369e861e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=465241463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.465241463
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1989066973
Short name T611
Test name
Test status
Simulation time 48901287 ps
CPU time 1.08 seconds
Started Jun 06 01:59:06 PM PDT 24
Finished Jun 06 01:59:08 PM PDT 24
Peak memory 208520 kb
Host smart-ba4cbab6-d298-4d52-9a1e-37416f04495a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989066973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1989066973
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.634363296
Short name T704
Test name
Test status
Simulation time 5728946979 ps
CPU time 30.66 seconds
Started Jun 06 01:59:06 PM PDT 24
Finished Jun 06 01:59:38 PM PDT 24
Peak memory 220920 kb
Host smart-4bbc0227-77bd-4f50-9726-eee8a1c4501c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634363296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.634363296
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1950831547
Short name T362
Test name
Test status
Simulation time 623861364 ps
CPU time 2.36 seconds
Started Jun 06 01:59:09 PM PDT 24
Finished Jun 06 01:59:12 PM PDT 24
Peak memory 208552 kb
Host smart-474e0e26-8256-454a-b708-5e64e1c3ac03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950831547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1950831547
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3240678441
Short name T856
Test name
Test status
Simulation time 134882839 ps
CPU time 1.1 seconds
Started Jun 06 01:59:05 PM PDT 24
Finished Jun 06 01:59:07 PM PDT 24
Peak memory 208028 kb
Host smart-6d53e489-4061-4c2b-9ff0-e11852816580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240678441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3240678441
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1020365833
Short name T433
Test name
Test status
Simulation time 33449374 ps
CPU time 0.7 seconds
Started Jun 06 01:59:12 PM PDT 24
Finished Jun 06 01:59:14 PM PDT 24
Peak memory 206220 kb
Host smart-f69ff70e-b5da-4b59-a278-f13a8dd3bd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020365833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1020365833
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1567796852
Short name T792
Test name
Test status
Simulation time 424585301 ps
CPU time 6.33 seconds
Started Jun 06 01:59:12 PM PDT 24
Finished Jun 06 01:59:19 PM PDT 24
Peak memory 233440 kb
Host smart-98cdfb92-c4db-4855-b973-5eae0f5d35d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567796852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1567796852
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.4085683134
Short name T876
Test name
Test status
Simulation time 24917087 ps
CPU time 0.75 seconds
Started Jun 06 01:59:14 PM PDT 24
Finished Jun 06 01:59:16 PM PDT 24
Peak memory 205464 kb
Host smart-496f56a6-f7ef-440a-8069-9277bff56474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085683134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
4085683134
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1257683788
Short name T959
Test name
Test status
Simulation time 164333821 ps
CPU time 3.54 seconds
Started Jun 06 01:59:16 PM PDT 24
Finished Jun 06 01:59:21 PM PDT 24
Peak memory 225164 kb
Host smart-98a1a0d4-d3b9-4e60-876e-ec88f436514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257683788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1257683788
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1295623311
Short name T695
Test name
Test status
Simulation time 99340968 ps
CPU time 0.79 seconds
Started Jun 06 01:59:09 PM PDT 24
Finished Jun 06 01:59:11 PM PDT 24
Peak memory 207220 kb
Host smart-0c298e4c-7c1e-4503-96bd-fa7180d73122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295623311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1295623311
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3688532666
Short name T674
Test name
Test status
Simulation time 1422662573 ps
CPU time 3.58 seconds
Started Jun 06 01:59:21 PM PDT 24
Finished Jun 06 01:59:26 PM PDT 24
Peak memory 225212 kb
Host smart-d2f1cfcd-61e6-4b86-a590-d0e07ca3571a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688532666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3688532666
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.4042189501
Short name T710
Test name
Test status
Simulation time 64600643866 ps
CPU time 343.45 seconds
Started Jun 06 01:59:15 PM PDT 24
Finished Jun 06 02:05:00 PM PDT 24
Peak memory 249728 kb
Host smart-9ae5bf94-867b-4646-9b7e-953ff3248b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042189501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.4042189501
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1140470512
Short name T44
Test name
Test status
Simulation time 16791777929 ps
CPU time 179.4 seconds
Started Jun 06 01:59:29 PM PDT 24
Finished Jun 06 02:02:29 PM PDT 24
Peak memory 249924 kb
Host smart-f0e143fa-912a-4276-82eb-57c06720a136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140470512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1140470512
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3161990570
Short name T346
Test name
Test status
Simulation time 513648533 ps
CPU time 5.35 seconds
Started Jun 06 01:59:23 PM PDT 24
Finished Jun 06 01:59:29 PM PDT 24
Peak memory 239548 kb
Host smart-5faf758d-0518-46dc-8e8b-88b8d1ce8585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161990570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3161990570
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1829755126
Short name T863
Test name
Test status
Simulation time 3156222618 ps
CPU time 9.29 seconds
Started Jun 06 01:59:15 PM PDT 24
Finished Jun 06 01:59:26 PM PDT 24
Peak memory 233512 kb
Host smart-2879df4e-f06b-42b2-ba99-f433b0adbc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829755126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1829755126
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.68196197
Short name T640
Test name
Test status
Simulation time 530785403 ps
CPU time 8.37 seconds
Started Jun 06 01:59:18 PM PDT 24
Finished Jun 06 01:59:28 PM PDT 24
Peak memory 233428 kb
Host smart-6549ac91-9a8e-4b74-818e-ad179911426b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68196197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.68196197
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1797296127
Short name T167
Test name
Test status
Simulation time 22937603291 ps
CPU time 10.95 seconds
Started Jun 06 01:59:14 PM PDT 24
Finished Jun 06 01:59:26 PM PDT 24
Peak memory 225284 kb
Host smart-3987e566-a014-4972-b3f9-4fe0fd26698a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797296127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1797296127
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2296026260
Short name T838
Test name
Test status
Simulation time 4881443753 ps
CPU time 13.76 seconds
Started Jun 06 01:59:04 PM PDT 24
Finished Jun 06 01:59:19 PM PDT 24
Peak memory 240940 kb
Host smart-45f2d4ae-82e1-45b3-b345-c650debde2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296026260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2296026260
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2059282372
Short name T609
Test name
Test status
Simulation time 5697810677 ps
CPU time 9.39 seconds
Started Jun 06 01:59:14 PM PDT 24
Finished Jun 06 01:59:25 PM PDT 24
Peak memory 220032 kb
Host smart-9b6d044c-4d30-474f-984e-ba72215bb404
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2059282372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2059282372
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.317335274
Short name T782
Test name
Test status
Simulation time 4439876286 ps
CPU time 29.51 seconds
Started Jun 06 01:59:07 PM PDT 24
Finished Jun 06 01:59:37 PM PDT 24
Peak memory 216996 kb
Host smart-6aec5a3e-667e-47a7-8dfe-e693825c307c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317335274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.317335274
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4226242869
Short name T881
Test name
Test status
Simulation time 213471090 ps
CPU time 4.28 seconds
Started Jun 06 01:59:05 PM PDT 24
Finished Jun 06 01:59:11 PM PDT 24
Peak memory 217028 kb
Host smart-f2010d77-6171-4f05-a8dd-a190366e073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226242869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4226242869
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1584648490
Short name T555
Test name
Test status
Simulation time 127353440 ps
CPU time 0.84 seconds
Started Jun 06 01:59:10 PM PDT 24
Finished Jun 06 01:59:11 PM PDT 24
Peak memory 206568 kb
Host smart-bb3ba93d-e493-45b6-921b-634e0229fab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584648490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1584648490
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3208034108
Short name T950
Test name
Test status
Simulation time 145290122 ps
CPU time 2.14 seconds
Started Jun 06 01:59:14 PM PDT 24
Finished Jun 06 01:59:17 PM PDT 24
Peak memory 225188 kb
Host smart-c1e8df0e-95d5-459a-ba3b-31c8cf04a120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208034108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3208034108
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1686466348
Short name T593
Test name
Test status
Simulation time 24001345 ps
CPU time 0.74 seconds
Started Jun 06 01:59:14 PM PDT 24
Finished Jun 06 01:59:16 PM PDT 24
Peak memory 206064 kb
Host smart-22dfa227-aaf1-4b34-9553-1d0775e8723e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686466348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1686466348
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3780791008
Short name T86
Test name
Test status
Simulation time 1245203759 ps
CPU time 4.4 seconds
Started Jun 06 01:59:14 PM PDT 24
Finished Jun 06 01:59:19 PM PDT 24
Peak memory 225160 kb
Host smart-942378c4-013a-42c1-ba48-417096f8dd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780791008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3780791008
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1660391120
Short name T663
Test name
Test status
Simulation time 33761984 ps
CPU time 0.73 seconds
Started Jun 06 01:59:14 PM PDT 24
Finished Jun 06 01:59:16 PM PDT 24
Peak memory 207268 kb
Host smart-da14b800-ed47-40c9-be12-96b08e41b037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660391120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1660391120
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2964779839
Short name T243
Test name
Test status
Simulation time 14111078716 ps
CPU time 125.92 seconds
Started Jun 06 01:59:16 PM PDT 24
Finished Jun 06 02:01:23 PM PDT 24
Peak memory 250084 kb
Host smart-cd76d0b7-a44a-4c7c-a585-83ec7bc17879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964779839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2964779839
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1905505860
Short name T546
Test name
Test status
Simulation time 1738349776 ps
CPU time 24.38 seconds
Started Jun 06 01:59:14 PM PDT 24
Finished Jun 06 01:59:40 PM PDT 24
Peak memory 239108 kb
Host smart-a4e0fbfc-49ce-4be0-a130-2cb5adaba915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905505860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1905505860
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.915816483
Short name T690
Test name
Test status
Simulation time 198961173 ps
CPU time 5.07 seconds
Started Jun 06 01:59:18 PM PDT 24
Finished Jun 06 01:59:25 PM PDT 24
Peak memory 225128 kb
Host smart-b5ed21b6-2caa-4160-bfe2-61fe433eb613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915816483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.915816483
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1191130015
Short name T83
Test name
Test status
Simulation time 318083851 ps
CPU time 5.08 seconds
Started Jun 06 01:59:15 PM PDT 24
Finished Jun 06 01:59:21 PM PDT 24
Peak memory 233264 kb
Host smart-fa53b663-63bb-4a57-9239-88939e67a0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191130015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1191130015
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.137765023
Short name T304
Test name
Test status
Simulation time 765921337 ps
CPU time 17 seconds
Started Jun 06 01:59:15 PM PDT 24
Finished Jun 06 01:59:34 PM PDT 24
Peak memory 239820 kb
Host smart-0deb47db-438c-4904-8d86-8f749532ce47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137765023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.137765023
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.937730540
Short name T737
Test name
Test status
Simulation time 1843791328 ps
CPU time 5.6 seconds
Started Jun 06 01:59:15 PM PDT 24
Finished Jun 06 01:59:22 PM PDT 24
Peak memory 233640 kb
Host smart-7a9a3956-8889-4422-93e8-3b851dd7b4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937730540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.937730540
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3691601005
Short name T210
Test name
Test status
Simulation time 1839481401 ps
CPU time 6.14 seconds
Started Jun 06 01:59:15 PM PDT 24
Finished Jun 06 01:59:23 PM PDT 24
Peak memory 225184 kb
Host smart-3ab9bf56-5dbe-420d-a5cc-494aa0f26b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691601005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3691601005
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3505227279
Short name T413
Test name
Test status
Simulation time 266206029 ps
CPU time 4.99 seconds
Started Jun 06 01:59:25 PM PDT 24
Finished Jun 06 01:59:31 PM PDT 24
Peak memory 219372 kb
Host smart-9ef15f43-59f2-4445-b932-4646c2f42a99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3505227279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3505227279
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4024343914
Short name T342
Test name
Test status
Simulation time 26713627875 ps
CPU time 30.33 seconds
Started Jun 06 01:59:15 PM PDT 24
Finished Jun 06 01:59:47 PM PDT 24
Peak memory 217048 kb
Host smart-34e4693a-723b-494e-a090-ab8c692de43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024343914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4024343914
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.843009022
Short name T358
Test name
Test status
Simulation time 17571231938 ps
CPU time 14.26 seconds
Started Jun 06 01:59:14 PM PDT 24
Finished Jun 06 01:59:29 PM PDT 24
Peak memory 216984 kb
Host smart-a897334e-66ef-459f-950c-64d79d280e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843009022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.843009022
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.901508439
Short name T533
Test name
Test status
Simulation time 342334690 ps
CPU time 10.46 seconds
Started Jun 06 01:59:14 PM PDT 24
Finished Jun 06 01:59:26 PM PDT 24
Peak memory 216996 kb
Host smart-37046f31-079f-4743-878f-b94960c80b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901508439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.901508439
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.407595654
Short name T447
Test name
Test status
Simulation time 37461737 ps
CPU time 0.8 seconds
Started Jun 06 01:59:24 PM PDT 24
Finished Jun 06 01:59:26 PM PDT 24
Peak memory 206552 kb
Host smart-c1ec90ff-30bd-4433-9173-99f9fa515bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407595654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.407595654
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1857467982
Short name T631
Test name
Test status
Simulation time 110923858 ps
CPU time 2.35 seconds
Started Jun 06 01:59:16 PM PDT 24
Finished Jun 06 01:59:20 PM PDT 24
Peak memory 224580 kb
Host smart-03427321-6e46-42d8-b835-9025e231e603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857467982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1857467982
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3307547460
Short name T713
Test name
Test status
Simulation time 12849555 ps
CPU time 0.74 seconds
Started Jun 06 01:59:31 PM PDT 24
Finished Jun 06 01:59:32 PM PDT 24
Peak memory 205564 kb
Host smart-d15cae7c-65c0-42ee-8ee2-ce6c18a9dd73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307547460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3307547460
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.177229845
Short name T754
Test name
Test status
Simulation time 70507517 ps
CPU time 2.4 seconds
Started Jun 06 01:59:15 PM PDT 24
Finished Jun 06 01:59:19 PM PDT 24
Peak memory 225236 kb
Host smart-843daf73-36f8-4615-a0df-923c1d14ead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177229845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.177229845
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.382298041
Short name T547
Test name
Test status
Simulation time 35370006 ps
CPU time 0.79 seconds
Started Jun 06 01:59:14 PM PDT 24
Finished Jun 06 01:59:16 PM PDT 24
Peak memory 207176 kb
Host smart-c9a00699-c22e-4b44-be45-a2434beb2649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382298041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.382298041
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1191565080
Short name T778
Test name
Test status
Simulation time 6051735157 ps
CPU time 54.03 seconds
Started Jun 06 01:59:32 PM PDT 24
Finished Jun 06 02:00:27 PM PDT 24
Peak memory 239980 kb
Host smart-6f617cce-b6c9-47ba-a5f1-81a4d2f03704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191565080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1191565080
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.946193580
Short name T270
Test name
Test status
Simulation time 75125074208 ps
CPU time 195.24 seconds
Started Jun 06 01:59:27 PM PDT 24
Finished Jun 06 02:02:43 PM PDT 24
Peak memory 249904 kb
Host smart-6d085db7-174a-48b6-8c54-b1f85d602e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946193580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.946193580
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2005960502
Short name T739
Test name
Test status
Simulation time 18183028554 ps
CPU time 103.04 seconds
Started Jun 06 01:59:32 PM PDT 24
Finished Jun 06 02:01:16 PM PDT 24
Peak memory 249940 kb
Host smart-0529817e-3ea7-4062-b7f6-e7e36e3303ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005960502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2005960502
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.529434903
Short name T370
Test name
Test status
Simulation time 16840844192 ps
CPU time 31.24 seconds
Started Jun 06 01:59:32 PM PDT 24
Finished Jun 06 02:00:03 PM PDT 24
Peak memory 240816 kb
Host smart-e9eb04de-0a5e-451e-8976-d7fcb64b480e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529434903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.529434903
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3443786268
Short name T906
Test name
Test status
Simulation time 666757526 ps
CPU time 4.62 seconds
Started Jun 06 01:59:19 PM PDT 24
Finished Jun 06 01:59:25 PM PDT 24
Peak memory 225184 kb
Host smart-a7f32fb0-a622-47ab-aab6-d10349f4ea0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443786268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3443786268
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2040279171
Short name T191
Test name
Test status
Simulation time 296150627 ps
CPU time 2.28 seconds
Started Jun 06 01:59:20 PM PDT 24
Finished Jun 06 01:59:23 PM PDT 24
Peak memory 219332 kb
Host smart-a84f6e7d-02db-458b-9ee1-1766ac504dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040279171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2040279171
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.954156625
Short name T296
Test name
Test status
Simulation time 4326243535 ps
CPU time 8.19 seconds
Started Jun 06 01:59:16 PM PDT 24
Finished Jun 06 01:59:26 PM PDT 24
Peak memory 225284 kb
Host smart-6a353455-b4c4-4b50-8e96-c021f8720601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954156625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.954156625
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1758961908
Short name T368
Test name
Test status
Simulation time 113492317 ps
CPU time 2.55 seconds
Started Jun 06 01:59:17 PM PDT 24
Finished Jun 06 01:59:20 PM PDT 24
Peak memory 227280 kb
Host smart-fe8039bf-d00a-47f8-a1a5-3374e803b7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758961908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1758961908
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2443038948
Short name T599
Test name
Test status
Simulation time 348519394 ps
CPU time 4.84 seconds
Started Jun 06 01:59:29 PM PDT 24
Finished Jun 06 01:59:35 PM PDT 24
Peak memory 219952 kb
Host smart-ee70c3ce-33f7-484e-869c-4ce3145313e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2443038948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2443038948
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2918716547
Short name T132
Test name
Test status
Simulation time 11670347408 ps
CPU time 164.69 seconds
Started Jun 06 01:59:30 PM PDT 24
Finished Jun 06 02:02:16 PM PDT 24
Peak memory 257308 kb
Host smart-71d98526-9e44-4383-8b61-dac5f316715e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918716547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2918716547
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.525199262
Short name T465
Test name
Test status
Simulation time 1551759493 ps
CPU time 24.12 seconds
Started Jun 06 01:59:16 PM PDT 24
Finished Jun 06 01:59:42 PM PDT 24
Peak memory 220620 kb
Host smart-fe422189-ec45-401d-99f8-67bb1cfde089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525199262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.525199262
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1621600551
Short name T795
Test name
Test status
Simulation time 7196776550 ps
CPU time 21.99 seconds
Started Jun 06 01:59:14 PM PDT 24
Finished Jun 06 01:59:38 PM PDT 24
Peak memory 217096 kb
Host smart-0747e5db-6c1b-4d86-b7d8-f9010777d19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621600551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1621600551
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.107456053
Short name T587
Test name
Test status
Simulation time 664554487 ps
CPU time 3.96 seconds
Started Jun 06 01:59:20 PM PDT 24
Finished Jun 06 01:59:25 PM PDT 24
Peak memory 217048 kb
Host smart-b8564830-35fc-48e8-9d09-17aa94b36bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107456053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.107456053
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.4141980460
Short name T766
Test name
Test status
Simulation time 44053223 ps
CPU time 0.84 seconds
Started Jun 06 01:59:18 PM PDT 24
Finished Jun 06 01:59:21 PM PDT 24
Peak memory 206540 kb
Host smart-f92c87dd-3b51-40de-9cda-20597bb6271a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141980460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.4141980460
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2126495659
Short name T401
Test name
Test status
Simulation time 299068002 ps
CPU time 2.23 seconds
Started Jun 06 01:59:16 PM PDT 24
Finished Jun 06 01:59:20 PM PDT 24
Peak memory 224792 kb
Host smart-cdd2c916-a87d-4ec0-8b18-79eb2c993a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126495659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2126495659
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2291902845
Short name T889
Test name
Test status
Simulation time 22246801 ps
CPU time 0.71 seconds
Started Jun 06 01:59:27 PM PDT 24
Finished Jun 06 01:59:28 PM PDT 24
Peak memory 205520 kb
Host smart-88e35914-4cca-4be4-9ae7-443a2fd9dd4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291902845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2291902845
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3520202663
Short name T877
Test name
Test status
Simulation time 85079161 ps
CPU time 2.86 seconds
Started Jun 06 01:59:30 PM PDT 24
Finished Jun 06 01:59:33 PM PDT 24
Peak memory 233364 kb
Host smart-02ac3e71-7963-4c0b-853c-135809b9292c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520202663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3520202663
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1659889029
Short name T463
Test name
Test status
Simulation time 17361373 ps
CPU time 0.79 seconds
Started Jun 06 01:59:26 PM PDT 24
Finished Jun 06 01:59:28 PM PDT 24
Peak memory 207508 kb
Host smart-4d77b2b5-bb5a-46c5-a5f3-188f13757f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659889029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1659889029
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3677351197
Short name T258
Test name
Test status
Simulation time 3850766933 ps
CPU time 30.76 seconds
Started Jun 06 01:59:30 PM PDT 24
Finished Jun 06 02:00:01 PM PDT 24
Peak memory 249848 kb
Host smart-d54288ce-00c0-4394-9d64-613b7ea039a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677351197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3677351197
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1880877667
Short name T240
Test name
Test status
Simulation time 4734289688 ps
CPU time 85.31 seconds
Started Jun 06 01:59:27 PM PDT 24
Finished Jun 06 02:00:53 PM PDT 24
Peak memory 256616 kb
Host smart-c903cb4e-2a69-409a-9088-de2b5cbfd78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880877667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1880877667
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1844953256
Short name T129
Test name
Test status
Simulation time 68237589413 ps
CPU time 157.17 seconds
Started Jun 06 01:59:32 PM PDT 24
Finished Jun 06 02:02:10 PM PDT 24
Peak memory 270332 kb
Host smart-cb3221a4-fbde-4a14-a18c-9b3859c31d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844953256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1844953256
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.457433363
Short name T330
Test name
Test status
Simulation time 42819924761 ps
CPU time 45.81 seconds
Started Jun 06 01:59:27 PM PDT 24
Finished Jun 06 02:00:13 PM PDT 24
Peak memory 233476 kb
Host smart-78adb895-1777-4efd-94b1-5b84b02a1969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457433363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.457433363
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.518667051
Short name T852
Test name
Test status
Simulation time 167459729 ps
CPU time 3.2 seconds
Started Jun 06 01:59:31 PM PDT 24
Finished Jun 06 01:59:35 PM PDT 24
Peak memory 225096 kb
Host smart-5bc4ba1d-ff15-4793-90c2-ee11bfef0384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518667051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.518667051
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3708169500
Short name T818
Test name
Test status
Simulation time 147424302 ps
CPU time 3.9 seconds
Started Jun 06 01:59:26 PM PDT 24
Finished Jun 06 01:59:31 PM PDT 24
Peak memory 233652 kb
Host smart-4a29e006-e0c7-4555-bc11-846885a92b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708169500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3708169500
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1107442588
Short name T945
Test name
Test status
Simulation time 834472343 ps
CPU time 7.45 seconds
Started Jun 06 01:59:29 PM PDT 24
Finished Jun 06 01:59:38 PM PDT 24
Peak memory 225216 kb
Host smart-693d2771-9d11-4059-a05b-b57f487900bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107442588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1107442588
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2262104947
Short name T860
Test name
Test status
Simulation time 8184988800 ps
CPU time 15.36 seconds
Started Jun 06 01:59:25 PM PDT 24
Finished Jun 06 01:59:42 PM PDT 24
Peak memory 249704 kb
Host smart-5d268329-7753-4f72-8d63-7b0136ca8e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262104947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2262104947
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2064901564
Short name T731
Test name
Test status
Simulation time 5475975025 ps
CPU time 12.39 seconds
Started Jun 06 01:59:30 PM PDT 24
Finished Jun 06 01:59:43 PM PDT 24
Peak memory 221024 kb
Host smart-0ffe4dc4-2af1-475b-b61f-8a3c50be93ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2064901564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2064901564
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1299355045
Short name T149
Test name
Test status
Simulation time 22647504152 ps
CPU time 61.93 seconds
Started Jun 06 01:59:30 PM PDT 24
Finished Jun 06 02:00:32 PM PDT 24
Peak memory 240712 kb
Host smart-c78378bd-f9be-4eb7-8b63-eb644d20b976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299355045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1299355045
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.4003657908
Short name T604
Test name
Test status
Simulation time 595218253 ps
CPU time 6.21 seconds
Started Jun 06 01:59:30 PM PDT 24
Finished Jun 06 01:59:37 PM PDT 24
Peak memory 216932 kb
Host smart-4dd1f21f-69b4-4a26-8120-d53b6af5a19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003657908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4003657908
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.129994851
Short name T828
Test name
Test status
Simulation time 9546652081 ps
CPU time 12.79 seconds
Started Jun 06 01:59:28 PM PDT 24
Finished Jun 06 01:59:41 PM PDT 24
Peak memory 217056 kb
Host smart-0fc737a1-806c-4fe8-8ed4-72d1ecc81e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129994851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.129994851
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1349811911
Short name T864
Test name
Test status
Simulation time 213072742 ps
CPU time 1.09 seconds
Started Jun 06 01:59:27 PM PDT 24
Finished Jun 06 01:59:29 PM PDT 24
Peak memory 216928 kb
Host smart-d261c058-362c-42c6-9076-92604baca199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349811911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1349811911
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.4229486012
Short name T841
Test name
Test status
Simulation time 40623105 ps
CPU time 0.68 seconds
Started Jun 06 01:59:26 PM PDT 24
Finished Jun 06 01:59:27 PM PDT 24
Peak memory 206280 kb
Host smart-1514c8cf-3f44-48f1-b03f-3a7180a13950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229486012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.4229486012
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2474594193
Short name T960
Test name
Test status
Simulation time 600693708 ps
CPU time 4.13 seconds
Started Jun 06 01:59:30 PM PDT 24
Finished Jun 06 01:59:35 PM PDT 24
Peak memory 225200 kb
Host smart-d6c74a30-0675-4153-9675-12ef77ab7795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474594193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2474594193
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1660736793
Short name T56
Test name
Test status
Simulation time 20137319 ps
CPU time 0.73 seconds
Started Jun 06 01:57:22 PM PDT 24
Finished Jun 06 01:57:25 PM PDT 24
Peak memory 206108 kb
Host smart-953b8d86-8a10-4b85-81a6-466a1394f49e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660736793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
660736793
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3543326730
Short name T449
Test name
Test status
Simulation time 10920298051 ps
CPU time 23.31 seconds
Started Jun 06 01:57:18 PM PDT 24
Finished Jun 06 01:57:43 PM PDT 24
Peak memory 225192 kb
Host smart-28aad52b-623b-41d0-84ad-ff6ddfbbc20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543326730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3543326730
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3998837391
Short name T843
Test name
Test status
Simulation time 54560455 ps
CPU time 0.84 seconds
Started Jun 06 01:57:10 PM PDT 24
Finished Jun 06 01:57:12 PM PDT 24
Peak memory 207268 kb
Host smart-dd6e0f0d-57e3-4a28-840b-293a202c02fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998837391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3998837391
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2349915356
Short name T679
Test name
Test status
Simulation time 3064843067 ps
CPU time 39.66 seconds
Started Jun 06 01:57:13 PM PDT 24
Finished Jun 06 01:57:54 PM PDT 24
Peak memory 249832 kb
Host smart-906ed552-c811-4a35-b96a-f83a53792b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349915356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2349915356
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1285985184
Short name T131
Test name
Test status
Simulation time 11399506058 ps
CPU time 70.8 seconds
Started Jun 06 01:57:18 PM PDT 24
Finished Jun 06 01:58:31 PM PDT 24
Peak memory 253656 kb
Host smart-f63e698e-6804-4c9b-96f7-8d69e8063172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285985184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1285985184
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1994381608
Short name T672
Test name
Test status
Simulation time 21406386586 ps
CPU time 157.3 seconds
Started Jun 06 01:57:18 PM PDT 24
Finished Jun 06 01:59:56 PM PDT 24
Peak memory 249944 kb
Host smart-bea9e4be-111e-4d01-be9a-4fc7fbded420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994381608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1994381608
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2386539799
Short name T514
Test name
Test status
Simulation time 466071326 ps
CPU time 10.11 seconds
Started Jun 06 01:57:21 PM PDT 24
Finished Jun 06 01:57:37 PM PDT 24
Peak memory 225228 kb
Host smart-62140537-7f48-4f11-9418-e30806e70a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386539799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2386539799
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.691564219
Short name T474
Test name
Test status
Simulation time 159863355 ps
CPU time 2.63 seconds
Started Jun 06 01:57:19 PM PDT 24
Finished Jun 06 01:57:28 PM PDT 24
Peak memory 233484 kb
Host smart-686e9d4c-3b2a-4707-b46e-aa1663913f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691564219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.691564219
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.4094121165
Short name T918
Test name
Test status
Simulation time 1098706411 ps
CPU time 9.03 seconds
Started Jun 06 01:57:14 PM PDT 24
Finished Jun 06 01:57:24 PM PDT 24
Peak memory 225156 kb
Host smart-a38d65e6-1946-41aa-93f1-21c55a5219d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094121165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4094121165
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.904890330
Short name T29
Test name
Test status
Simulation time 5450703486 ps
CPU time 17.44 seconds
Started Jun 06 01:57:13 PM PDT 24
Finished Jun 06 01:57:32 PM PDT 24
Peak memory 241616 kb
Host smart-c01d4485-71d8-42e5-98ff-46ce8cd6aa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904890330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
904890330
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1407168047
Short name T209
Test name
Test status
Simulation time 8212866320 ps
CPU time 15.7 seconds
Started Jun 06 01:57:13 PM PDT 24
Finished Jun 06 01:57:30 PM PDT 24
Peak memory 241124 kb
Host smart-f378478a-ae1b-4737-a6f3-9a3ffcd52901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407168047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1407168047
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.953952164
Short name T569
Test name
Test status
Simulation time 2290209058 ps
CPU time 11.74 seconds
Started Jun 06 01:57:17 PM PDT 24
Finished Jun 06 01:57:30 PM PDT 24
Peak memory 223260 kb
Host smart-35e79169-48ba-4272-aa9e-4b794a84a75a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=953952164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.953952164
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2741882795
Short name T253
Test name
Test status
Simulation time 234932723742 ps
CPU time 346.73 seconds
Started Jun 06 01:57:26 PM PDT 24
Finished Jun 06 02:03:14 PM PDT 24
Peak memory 266332 kb
Host smart-95c438c3-5359-4f44-81c0-ef16dbb713c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741882795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2741882795
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2018331044
Short name T839
Test name
Test status
Simulation time 10900375008 ps
CPU time 43.61 seconds
Started Jun 06 01:57:14 PM PDT 24
Finished Jun 06 01:57:59 PM PDT 24
Peak memory 217016 kb
Host smart-2996c3c2-cad8-43f4-9ff2-d6292e96f915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018331044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2018331044
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2611291907
Short name T383
Test name
Test status
Simulation time 655539280 ps
CPU time 1.83 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:24 PM PDT 24
Peak memory 208572 kb
Host smart-5b07c790-2f65-49b5-89f6-a68fcebd908f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611291907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2611291907
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3055026300
Short name T161
Test name
Test status
Simulation time 48418787 ps
CPU time 0.76 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:23 PM PDT 24
Peak memory 206512 kb
Host smart-2eb15e66-f94e-4400-b0ad-894b81a6a3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055026300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3055026300
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2658572385
Short name T389
Test name
Test status
Simulation time 65392937 ps
CPU time 0.82 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:22 PM PDT 24
Peak memory 207536 kb
Host smart-3af9062e-dc45-40f3-935e-f27d4f99449b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658572385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2658572385
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.4093725282
Short name T866
Test name
Test status
Simulation time 456037854 ps
CPU time 5.26 seconds
Started Jun 06 01:57:15 PM PDT 24
Finished Jun 06 01:57:22 PM PDT 24
Peak memory 233332 kb
Host smart-2cb20308-8d31-4653-b01f-991898bc0a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093725282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4093725282
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3177003504
Short name T425
Test name
Test status
Simulation time 14956904 ps
CPU time 0.73 seconds
Started Jun 06 01:57:19 PM PDT 24
Finished Jun 06 01:57:21 PM PDT 24
Peak memory 205484 kb
Host smart-4e5e49d3-05fa-446f-b2b2-0ae9032fed37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177003504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
177003504
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3254547079
Short name T624
Test name
Test status
Simulation time 679616903 ps
CPU time 4.31 seconds
Started Jun 06 01:57:17 PM PDT 24
Finished Jun 06 01:57:23 PM PDT 24
Peak memory 225168 kb
Host smart-8b33d12c-42fa-4ab2-bc06-92bbf3c3d6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254547079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3254547079
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.734168677
Short name T720
Test name
Test status
Simulation time 28681840 ps
CPU time 0.75 seconds
Started Jun 06 01:57:19 PM PDT 24
Finished Jun 06 01:57:21 PM PDT 24
Peak memory 207200 kb
Host smart-3e8531fb-96c1-48cb-b646-cef5add3ddb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734168677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.734168677
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1322506693
Short name T235
Test name
Test status
Simulation time 5672705122 ps
CPU time 51.7 seconds
Started Jun 06 01:57:17 PM PDT 24
Finished Jun 06 01:58:10 PM PDT 24
Peak memory 250012 kb
Host smart-c04a2f71-da68-4c3a-ad39-85480213f6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322506693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1322506693
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.395919422
Short name T951
Test name
Test status
Simulation time 3139530226 ps
CPU time 14.07 seconds
Started Jun 06 01:57:11 PM PDT 24
Finished Jun 06 01:57:26 PM PDT 24
Peak memory 233496 kb
Host smart-af285cf3-55ea-4b99-a937-d1bcd06f031b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395919422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.395919422
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.979316132
Short name T290
Test name
Test status
Simulation time 5957800437 ps
CPU time 26.75 seconds
Started Jun 06 01:57:17 PM PDT 24
Finished Jun 06 01:57:45 PM PDT 24
Peak memory 225236 kb
Host smart-dfd57bd2-5abf-4726-b3c2-e5df410fcc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979316132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.979316132
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1006601115
Short name T785
Test name
Test status
Simulation time 16438545269 ps
CPU time 40.54 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:58:03 PM PDT 24
Peak memory 225224 kb
Host smart-d9f33fe9-08a9-4988-acd6-95aaa4139ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006601115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1006601115
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2611599824
Short name T195
Test name
Test status
Simulation time 315613772 ps
CPU time 2.27 seconds
Started Jun 06 01:57:16 PM PDT 24
Finished Jun 06 01:57:20 PM PDT 24
Peak memory 225032 kb
Host smart-ad07ae97-fbe3-4d18-9269-95ea6a42dd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611599824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2611599824
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1954694002
Short name T748
Test name
Test status
Simulation time 117301243 ps
CPU time 3.46 seconds
Started Jun 06 01:57:14 PM PDT 24
Finished Jun 06 01:57:19 PM PDT 24
Peak memory 233380 kb
Host smart-e01595f5-2225-497c-8a78-ef43d3daaa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954694002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1954694002
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.532553934
Short name T834
Test name
Test status
Simulation time 5314892688 ps
CPU time 16.2 seconds
Started Jun 06 01:57:18 PM PDT 24
Finished Jun 06 01:57:36 PM PDT 24
Peak memory 220056 kb
Host smart-b082f1be-a2ed-426d-a417-f05584a9edca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=532553934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.532553934
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3590923948
Short name T155
Test name
Test status
Simulation time 19656409327 ps
CPU time 42.64 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:58:04 PM PDT 24
Peak memory 249936 kb
Host smart-ff6a9af0-cbd8-42c3-9bc3-e22239b78845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590923948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3590923948
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1239295836
Short name T902
Test name
Test status
Simulation time 4145368984 ps
CPU time 19.99 seconds
Started Jun 06 01:57:38 PM PDT 24
Finished Jun 06 01:58:00 PM PDT 24
Peak memory 217132 kb
Host smart-ef29e0a8-f574-48f1-93ba-4a8737a1af6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239295836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1239295836
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3085918916
Short name T488
Test name
Test status
Simulation time 2774780049 ps
CPU time 9.55 seconds
Started Jun 06 01:57:17 PM PDT 24
Finished Jun 06 01:57:27 PM PDT 24
Peak memory 217032 kb
Host smart-2ec8116b-b027-47d4-8193-95cd193a9d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085918916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3085918916
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3959406605
Short name T632
Test name
Test status
Simulation time 192165158 ps
CPU time 1.31 seconds
Started Jun 06 01:57:16 PM PDT 24
Finished Jun 06 01:57:19 PM PDT 24
Peak memory 217268 kb
Host smart-e4e0a50b-2314-43f9-ac7d-69921f5bc932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959406605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3959406605
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1584262327
Short name T157
Test name
Test status
Simulation time 109629251 ps
CPU time 0.96 seconds
Started Jun 06 01:57:26 PM PDT 24
Finished Jun 06 01:57:28 PM PDT 24
Peak memory 206588 kb
Host smart-a4220113-beb8-4eff-bd21-7fb4bda99e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584262327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1584262327
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2353718158
Short name T580
Test name
Test status
Simulation time 15532102078 ps
CPU time 26.26 seconds
Started Jun 06 01:57:14 PM PDT 24
Finished Jun 06 01:57:41 PM PDT 24
Peak memory 225296 kb
Host smart-f284184b-8cbf-44a0-b588-2cd2658b2bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353718158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2353718158
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3157809498
Short name T776
Test name
Test status
Simulation time 15289401 ps
CPU time 0.75 seconds
Started Jun 06 01:57:19 PM PDT 24
Finished Jun 06 01:57:22 PM PDT 24
Peak memory 205548 kb
Host smart-6a02ed87-e705-4053-a8f1-4f27966e45cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157809498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
157809498
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4215442980
Short name T426
Test name
Test status
Simulation time 45280168 ps
CPU time 2.35 seconds
Started Jun 06 01:57:22 PM PDT 24
Finished Jun 06 01:57:26 PM PDT 24
Peak memory 233368 kb
Host smart-e9cfb588-9e26-4aa5-a91d-c06328f644af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215442980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4215442980
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1631640850
Short name T612
Test name
Test status
Simulation time 59360640 ps
CPU time 0.74 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:24 PM PDT 24
Peak memory 207132 kb
Host smart-843cc4bc-fb1e-43dc-b285-830c1d3db514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631640850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1631640850
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.322055166
Short name T177
Test name
Test status
Simulation time 3592149638 ps
CPU time 52.06 seconds
Started Jun 06 01:57:16 PM PDT 24
Finished Jun 06 01:58:09 PM PDT 24
Peak memory 255480 kb
Host smart-b695e311-d92f-4f4e-a239-a49c5d3c89d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322055166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.322055166
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.4068528636
Short name T343
Test name
Test status
Simulation time 689792867 ps
CPU time 9.56 seconds
Started Jun 06 01:57:14 PM PDT 24
Finished Jun 06 01:57:25 PM PDT 24
Peak memory 223804 kb
Host smart-ba6c6e2f-e168-429b-aa83-a0e9454bdb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068528636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.4068528636
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2375468466
Short name T111
Test name
Test status
Simulation time 1555853008 ps
CPU time 8.85 seconds
Started Jun 06 01:57:21 PM PDT 24
Finished Jun 06 01:57:32 PM PDT 24
Peak memory 233372 kb
Host smart-91c80e06-3717-44ef-a5ab-0a1d3ca13ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375468466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2375468466
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1579096795
Short name T920
Test name
Test status
Simulation time 1849704880 ps
CPU time 10.9 seconds
Started Jun 06 01:57:11 PM PDT 24
Finished Jun 06 01:57:23 PM PDT 24
Peak memory 225128 kb
Host smart-36843a00-244a-4427-b1b4-c0ad8eaa4b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579096795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1579096795
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2891130774
Short name T655
Test name
Test status
Simulation time 155470311 ps
CPU time 2.58 seconds
Started Jun 06 01:57:16 PM PDT 24
Finished Jun 06 01:57:20 PM PDT 24
Peak memory 225108 kb
Host smart-a7438153-69e8-4bcb-b87f-d94f6a9d53ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891130774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2891130774
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.498417983
Short name T430
Test name
Test status
Simulation time 297884600 ps
CPU time 5.69 seconds
Started Jun 06 01:57:18 PM PDT 24
Finished Jun 06 01:57:25 PM PDT 24
Peak memory 233364 kb
Host smart-d7f36877-c466-4937-b706-b09576d39e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498417983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
498417983
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2070134050
Short name T953
Test name
Test status
Simulation time 39431883135 ps
CPU time 12.59 seconds
Started Jun 06 01:57:15 PM PDT 24
Finished Jun 06 01:57:28 PM PDT 24
Peak memory 241476 kb
Host smart-84ec2742-5b0d-4c67-88b4-a86fcff7092d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070134050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2070134050
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1093095237
Short name T822
Test name
Test status
Simulation time 8363047108 ps
CPU time 23.2 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:45 PM PDT 24
Peak memory 221116 kb
Host smart-98f39695-acac-4d4e-8294-03f222015716
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1093095237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1093095237
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.4038505633
Short name T151
Test name
Test status
Simulation time 72850244814 ps
CPU time 52.47 seconds
Started Jun 06 01:57:18 PM PDT 24
Finished Jun 06 01:58:11 PM PDT 24
Peak memory 239732 kb
Host smart-56d79a0c-3f2c-40c6-9c4a-0b0d46f30593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038505633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.4038505633
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1463008840
Short name T568
Test name
Test status
Simulation time 97844517 ps
CPU time 0.7 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:23 PM PDT 24
Peak memory 206292 kb
Host smart-e6da5779-6acd-4aa0-9e56-d7e257ac6239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463008840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1463008840
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2441713280
Short name T457
Test name
Test status
Simulation time 10886124625 ps
CPU time 7.12 seconds
Started Jun 06 01:57:16 PM PDT 24
Finished Jun 06 01:57:24 PM PDT 24
Peak memory 217056 kb
Host smart-88d78300-08a8-4122-b3d8-3f218ca65618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441713280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2441713280
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1993741559
Short name T586
Test name
Test status
Simulation time 160805749 ps
CPU time 1.32 seconds
Started Jun 06 01:57:19 PM PDT 24
Finished Jun 06 01:57:22 PM PDT 24
Peak memory 217052 kb
Host smart-e10a4a60-4026-4297-8b07-8f884adb4f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993741559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1993741559
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.931087117
Short name T18
Test name
Test status
Simulation time 37075493 ps
CPU time 0.87 seconds
Started Jun 06 01:57:18 PM PDT 24
Finished Jun 06 01:57:21 PM PDT 24
Peak memory 207564 kb
Host smart-50b7bb35-f81f-43d9-9da4-84397de7385f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931087117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.931087117
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2331467
Short name T682
Test name
Test status
Simulation time 22812242373 ps
CPU time 18.68 seconds
Started Jun 06 01:57:19 PM PDT 24
Finished Jun 06 01:57:39 PM PDT 24
Peak memory 233512 kb
Host smart-72db8a80-853e-4a25-8082-ff22efa1bf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2331467
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.889792698
Short name T694
Test name
Test status
Simulation time 11568956 ps
CPU time 0.73 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:23 PM PDT 24
Peak memory 206416 kb
Host smart-edf9db73-14da-4e87-8879-66d2d8608fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889792698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.889792698
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3613483985
Short name T320
Test name
Test status
Simulation time 1300889466 ps
CPU time 6.2 seconds
Started Jun 06 01:57:50 PM PDT 24
Finished Jun 06 01:57:58 PM PDT 24
Peak memory 233348 kb
Host smart-096a4f40-6858-4821-aa24-2aab7014f328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613483985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3613483985
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.461476041
Short name T19
Test name
Test status
Simulation time 18224634 ps
CPU time 0.79 seconds
Started Jun 06 01:57:22 PM PDT 24
Finished Jun 06 01:57:24 PM PDT 24
Peak memory 207556 kb
Host smart-1b765329-2b98-4b8b-ad2a-54bb0d53e0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461476041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.461476041
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.297489418
Short name T623
Test name
Test status
Simulation time 15424630737 ps
CPU time 51.92 seconds
Started Jun 06 01:57:49 PM PDT 24
Finished Jun 06 01:58:42 PM PDT 24
Peak memory 249912 kb
Host smart-04cdbf46-e9d1-4dcb-91b7-2186c3c6e7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297489418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.297489418
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2071650811
Short name T247
Test name
Test status
Simulation time 14745253847 ps
CPU time 163.15 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 02:00:05 PM PDT 24
Peak memory 252232 kb
Host smart-01c0cc07-38b9-4c38-8ef3-3b1ea028824b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071650811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2071650811
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3012681059
Short name T429
Test name
Test status
Simulation time 560093184 ps
CPU time 4.01 seconds
Started Jun 06 01:57:21 PM PDT 24
Finished Jun 06 01:57:27 PM PDT 24
Peak memory 225240 kb
Host smart-601cb020-a82d-48df-9273-1026660acb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012681059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3012681059
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.495806055
Short name T84
Test name
Test status
Simulation time 3273868953 ps
CPU time 26.82 seconds
Started Jun 06 01:57:10 PM PDT 24
Finished Jun 06 01:57:38 PM PDT 24
Peak memory 225232 kb
Host smart-3ebb2bfd-fa41-4b3f-91c9-4656619bf0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495806055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.495806055
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.808511982
Short name T566
Test name
Test status
Simulation time 4036976363 ps
CPU time 19.23 seconds
Started Jun 06 01:57:26 PM PDT 24
Finished Jun 06 01:57:46 PM PDT 24
Peak memory 233448 kb
Host smart-33c86123-49bc-4c8b-923c-d6e7a25d7d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808511982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.808511982
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2919077486
Short name T260
Test name
Test status
Simulation time 7837106929 ps
CPU time 20.93 seconds
Started Jun 06 01:57:19 PM PDT 24
Finished Jun 06 01:57:42 PM PDT 24
Peak memory 225196 kb
Host smart-4524973f-c3a6-4cf3-906e-91de543902cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919077486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2919077486
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2576426862
Short name T734
Test name
Test status
Simulation time 1929444070 ps
CPU time 8.39 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:31 PM PDT 24
Peak memory 233376 kb
Host smart-b115d931-fbeb-4348-82a9-b70acc425bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576426862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2576426862
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1955004854
Short name T666
Test name
Test status
Simulation time 1342891110 ps
CPU time 4.93 seconds
Started Jun 06 01:57:19 PM PDT 24
Finished Jun 06 01:57:26 PM PDT 24
Peak memory 223672 kb
Host smart-249ed515-73d5-4e45-9d77-8b656d7adb14
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1955004854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1955004854
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.667507461
Short name T380
Test name
Test status
Simulation time 202530297 ps
CPU time 1.12 seconds
Started Jun 06 01:57:19 PM PDT 24
Finished Jun 06 01:57:21 PM PDT 24
Peak memory 207908 kb
Host smart-e9eedca3-4d08-4a45-bd45-02787c525de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667507461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.667507461
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2093214876
Short name T344
Test name
Test status
Simulation time 1655161016 ps
CPU time 16.25 seconds
Started Jun 06 01:57:25 PM PDT 24
Finished Jun 06 01:57:42 PM PDT 24
Peak memory 217016 kb
Host smart-833b0328-e93a-4fc5-9d30-b1907567654f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093214876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2093214876
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.4051997047
Short name T493
Test name
Test status
Simulation time 8280582722 ps
CPU time 6.02 seconds
Started Jun 06 01:57:26 PM PDT 24
Finished Jun 06 01:57:33 PM PDT 24
Peak memory 217080 kb
Host smart-0999ca6f-eee4-4fba-be38-4dcb8e3a3470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051997047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.4051997047
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2136983250
Short name T717
Test name
Test status
Simulation time 34371328 ps
CPU time 1.03 seconds
Started Jun 06 01:57:24 PM PDT 24
Finished Jun 06 01:57:26 PM PDT 24
Peak memory 207868 kb
Host smart-6bd70fb0-89a1-4b67-81cf-a1dc0a5f15f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136983250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2136983250
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2124080907
Short name T893
Test name
Test status
Simulation time 33373888 ps
CPU time 0.71 seconds
Started Jun 06 01:57:28 PM PDT 24
Finished Jun 06 01:57:29 PM PDT 24
Peak memory 206244 kb
Host smart-a086c203-47d4-44f3-ad80-4491bb396d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124080907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2124080907
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.676601313
Short name T598
Test name
Test status
Simulation time 1258766006 ps
CPU time 3.04 seconds
Started Jun 06 01:57:17 PM PDT 24
Finished Jun 06 01:57:21 PM PDT 24
Peak memory 233444 kb
Host smart-d6d28266-404d-4cb1-bbee-a380323848e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676601313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.676601313
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3460536803
Short name T733
Test name
Test status
Simulation time 146391464 ps
CPU time 0.72 seconds
Started Jun 06 01:57:21 PM PDT 24
Finished Jun 06 01:57:24 PM PDT 24
Peak memory 205500 kb
Host smart-b4fae5e4-4cd6-4ed6-8d88-54d8dace7393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460536803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
460536803
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3407170122
Short name T158
Test name
Test status
Simulation time 491141576 ps
CPU time 2.43 seconds
Started Jun 06 01:57:18 PM PDT 24
Finished Jun 06 01:57:22 PM PDT 24
Peak memory 225224 kb
Host smart-bfb8d65c-71be-411f-a6a1-24ddc545763e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407170122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3407170122
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2395127160
Short name T651
Test name
Test status
Simulation time 29945819 ps
CPU time 0.74 seconds
Started Jun 06 01:57:18 PM PDT 24
Finished Jun 06 01:57:21 PM PDT 24
Peak memory 206508 kb
Host smart-202d5ff1-166b-4c84-b674-7afad632f398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395127160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2395127160
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3797716525
Short name T743
Test name
Test status
Simulation time 3994118744 ps
CPU time 23.14 seconds
Started Jun 06 01:57:21 PM PDT 24
Finished Jun 06 01:57:47 PM PDT 24
Peak memory 249888 kb
Host smart-7d8d2ae5-0633-4bf7-aa10-c41ef8856d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797716525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3797716525
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3533277638
Short name T680
Test name
Test status
Simulation time 2937867365 ps
CPU time 27.96 seconds
Started Jun 06 01:57:21 PM PDT 24
Finished Jun 06 01:57:51 PM PDT 24
Peak memory 225280 kb
Host smart-d57c3a05-73c4-44b8-b6d2-ef14963aefbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533277638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3533277638
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3520511121
Short name T162
Test name
Test status
Simulation time 18627393070 ps
CPU time 175.23 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 02:00:18 PM PDT 24
Peak memory 255676 kb
Host smart-51fcfe6f-33c5-44af-b1b2-f6647fe94941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520511121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3520511121
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2631011451
Short name T738
Test name
Test status
Simulation time 1840297388 ps
CPU time 26.01 seconds
Started Jun 06 01:57:26 PM PDT 24
Finished Jun 06 01:57:53 PM PDT 24
Peak memory 225276 kb
Host smart-4e34a487-8a39-40e4-bc31-553546592132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631011451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2631011451
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2170364565
Short name T214
Test name
Test status
Simulation time 2178539747 ps
CPU time 7.48 seconds
Started Jun 06 01:57:29 PM PDT 24
Finished Jun 06 01:57:37 PM PDT 24
Peak memory 233516 kb
Host smart-be072c3b-0c16-4823-b4d2-39b2f178da69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170364565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2170364565
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1328011606
Short name T498
Test name
Test status
Simulation time 30123365 ps
CPU time 2.19 seconds
Started Jun 06 01:57:39 PM PDT 24
Finished Jun 06 01:57:43 PM PDT 24
Peak memory 223608 kb
Host smart-cacf68f1-bb96-4ed0-95f4-6dc1ba00bfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328011606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1328011606
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3565982137
Short name T89
Test name
Test status
Simulation time 1226414653 ps
CPU time 5.92 seconds
Started Jun 06 01:57:21 PM PDT 24
Finished Jun 06 01:57:29 PM PDT 24
Peak memory 233404 kb
Host smart-bee901c9-dfb1-43c7-94c9-9ec1366be592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565982137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3565982137
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.324942764
Short name T205
Test name
Test status
Simulation time 27351301984 ps
CPU time 21.5 seconds
Started Jun 06 01:57:45 PM PDT 24
Finished Jun 06 01:58:08 PM PDT 24
Peak memory 233516 kb
Host smart-020215e9-86b9-49dc-91b8-a11b7654421a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324942764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.324942764
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.537245905
Short name T387
Test name
Test status
Simulation time 5957408269 ps
CPU time 10.36 seconds
Started Jun 06 01:57:38 PM PDT 24
Finished Jun 06 01:57:50 PM PDT 24
Peak memory 223724 kb
Host smart-6e6d5f27-d79a-4fbe-b96d-98b73aeee96c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=537245905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.537245905
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1947006961
Short name T134
Test name
Test status
Simulation time 56857799303 ps
CPU time 240.78 seconds
Started Jun 06 01:57:22 PM PDT 24
Finished Jun 06 02:01:24 PM PDT 24
Peak memory 274432 kb
Host smart-0285b729-02c3-4712-bad0-a32450fba9a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947006961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1947006961
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1875237843
Short name T719
Test name
Test status
Simulation time 40465026 ps
CPU time 0.71 seconds
Started Jun 06 01:57:23 PM PDT 24
Finished Jun 06 01:57:25 PM PDT 24
Peak memory 206280 kb
Host smart-c453b642-3605-48be-a4ab-dc838fa65563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875237843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1875237843
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1026466848
Short name T444
Test name
Test status
Simulation time 5409038628 ps
CPU time 8.54 seconds
Started Jun 06 01:57:19 PM PDT 24
Finished Jun 06 01:57:29 PM PDT 24
Peak memory 217064 kb
Host smart-0eee631c-d55c-4f73-b9bc-3925ae5a9ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026466848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1026466848
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2191575030
Short name T428
Test name
Test status
Simulation time 103756934 ps
CPU time 1.88 seconds
Started Jun 06 01:57:24 PM PDT 24
Finished Jun 06 01:57:27 PM PDT 24
Peak memory 217004 kb
Host smart-f75b4506-2f18-4431-97e3-53bda905add5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191575030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2191575030
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1688365441
Short name T916
Test name
Test status
Simulation time 35548322 ps
CPU time 0.71 seconds
Started Jun 06 01:57:20 PM PDT 24
Finished Jun 06 01:57:23 PM PDT 24
Peak memory 206248 kb
Host smart-83ad8728-a56d-4421-ae66-2f1a93cee923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688365441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1688365441
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2947731934
Short name T311
Test name
Test status
Simulation time 941381897 ps
CPU time 5.88 seconds
Started Jun 06 01:57:33 PM PDT 24
Finished Jun 06 01:57:39 PM PDT 24
Peak memory 233428 kb
Host smart-619d1fd7-5833-4521-897c-2981a7a7368b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947731934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2947731934
Directory /workspace/9.spi_device_upload/latest
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