Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3787424	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4102151

1

T1

8671

T2

1

T3

5233

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4482913	1			T1	3700		T2	1		T3	1767
values[0x0]	1702717	1			T1	4218		T2	5		T3	2163
values[0x1]	1703945	1			T1	4143		T2	7		T3	2234

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2682304	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5207271

1

T1

9514

T2

2

T3

5431

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27558	1			T1	1		T3	20		T4	1
valid_sources[0x01]	29185	1			T1	39		T3	19		T6	5
valid_sources[0x02]	33868	1			T1	2		T3	43		T6	5
valid_sources[0x03]	28648	1			T1	453		T3	14		T6	9
valid_sources[0x04]	28891	1			T1	3		T3	19		T6	1
valid_sources[0x05]	29113	1			T1	1		T3	31		T6	7
valid_sources[0x06]	29769	1			T3	25		T6	4		T7	10
valid_sources[0x07]	29237	1			T1	1		T3	24		T6	8
valid_sources[0x08]	28566	1			T1	13		T3	33		T6	12
valid_sources[0x09]	30138	1			T1	1		T3	31		T6	10
valid_sources[0x0a]	26659	1			T1	313		T3	33		T6	9
valid_sources[0x0b]	31928	1			T1	3		T3	22		T6	11
valid_sources[0x0c]	27281	1			T1	2		T3	19		T6	13
valid_sources[0x0d]	29094	1			T1	33		T3	25		T6	5
valid_sources[0x0e]	28041	1			T1	58		T3	9		T6	8
valid_sources[0x0f]	29257	1			T1	4		T3	12		T6	5
valid_sources[0x10]	30387	1			T1	417		T3	32		T6	8
valid_sources[0x11]	31919	1			T3	55		T6	10		T7	8
valid_sources[0x12]	29608	1			T1	57		T3	23		T6	6
valid_sources[0x13]	28711	1			T1	2		T3	36		T6	19
valid_sources[0x14]	29667	1			T1	1		T3	13		T6	15
valid_sources[0x15]	30413	1			T1	94		T3	30		T6	9
valid_sources[0x16]	29003	1			T1	51		T3	42		T6	7
valid_sources[0x17]	31063	1			T3	18		T6	3		T7	9
valid_sources[0x18]	30655	1			T3	39		T6	11		T7	9
valid_sources[0x19]	33842	1			T3	11		T6	5		T7	8
valid_sources[0x1a]	28179	1			T3	8		T6	9		T7	5
valid_sources[0x1b]	31509	1			T1	76		T3	31		T6	6
valid_sources[0x1c]	29364	1			T3	13		T6	10		T7	7
valid_sources[0x1d]	28125	1			T1	1		T3	16		T6	9
valid_sources[0x1e]	28854	1			T1	40		T3	20		T6	17
valid_sources[0x1f]	26341	1			T3	49		T6	5		T7	8
valid_sources[0x20]	30888	1			T1	1		T3	13		T6	7
valid_sources[0x21]	30941	1			T1	2		T3	13		T6	3
valid_sources[0x22]	29178	1			T1	106		T3	30		T6	3
valid_sources[0x23]	34018	1			T1	105		T3	21		T6	2
valid_sources[0x24]	28733	1			T3	19		T6	9		T7	9
valid_sources[0x25]	28180	1			T1	255		T3	22		T6	7
valid_sources[0x26]	28901	1			T1	45		T3	20		T6	6
valid_sources[0x27]	27578	1			T3	23		T4	2		T6	3
valid_sources[0x28]	30295	1			T3	30		T6	5		T7	4
valid_sources[0x29]	28108	1			T1	1		T3	38		T6	1
valid_sources[0x2a]	32798	1			T1	13		T3	4		T6	7
valid_sources[0x2b]	26081	1			T1	100		T3	16		T6	15
valid_sources[0x2c]	29090	1			T1	3		T3	27		T6	10
valid_sources[0x2d]	29588	1			T3	9		T6	20		T7	10
valid_sources[0x2e]	30743	1			T1	68		T3	25		T6	8
valid_sources[0x2f]	35846	1			T1	17		T3	49		T6	12
valid_sources[0x30]	28568	1			T1	20		T3	35		T6	5
valid_sources[0x31]	28994	1			T3	15		T6	4		T7	11
valid_sources[0x32]	36490	1			T1	3		T3	22		T6	12
valid_sources[0x33]	27817	1			T1	1		T3	30		T6	9
valid_sources[0x34]	27343	1			T1	18		T3	24		T6	12
valid_sources[0x35]	45504	1			T3	36		T6	12		T7	8
valid_sources[0x36]	33826	1			T1	1		T3	35		T6	18
valid_sources[0x37]	28969	1			T1	1		T3	16		T6	10
valid_sources[0x38]	28911	1			T1	27		T3	17		T6	8
valid_sources[0x39]	31373	1			T3	24		T6	7		T7	4
valid_sources[0x3a]	28542	1			T1	6		T3	29		T6	29
valid_sources[0x3b]	29926	1			T1	6		T3	23		T6	10
valid_sources[0x3c]	31168	1			T1	2		T3	30		T6	9
valid_sources[0x3d]	27737	1			T3	15		T4	3		T6	3
valid_sources[0x3e]	28670	1			T1	2		T3	38		T6	1
valid_sources[0x3f]	31080	1			T3	19		T6	7		T7	6
valid_sources[0x40]	93658	1			T1	3		T3	12		T6	17
valid_sources[0x41]	33396	1			T3	21		T6	11		T7	8
valid_sources[0x42]	29509	1			T1	172		T3	14		T6	10
valid_sources[0x43]	29487	1			T1	115		T3	7		T6	13
valid_sources[0x44]	28374	1			T1	1		T3	20		T6	3
valid_sources[0x45]	27260	1			T3	25		T6	7		T7	5
valid_sources[0x46]	29228	1			T1	2		T3	40		T6	16
valid_sources[0x47]	29091	1			T3	19		T6	6		T7	9
valid_sources[0x48]	28673	1			T1	12		T3	19		T4	1
valid_sources[0x49]	30914	1			T1	1		T3	58		T6	18
valid_sources[0x4a]	30926	1			T1	9		T3	34		T6	3
valid_sources[0x4b]	32464	1			T3	12		T6	6		T7	6
valid_sources[0x4c]	27506	1			T1	6		T3	16		T6	4
valid_sources[0x4d]	27847	1			T1	70		T3	44		T6	12
valid_sources[0x4e]	30324	1			T1	2		T3	20		T6	4
valid_sources[0x4f]	30372	1			T1	2		T3	21		T6	7
valid_sources[0x50]	27202	1			T1	388		T3	20		T6	7
valid_sources[0x51]	29998	1			T1	14		T3	16		T6	12
valid_sources[0x52]	28472	1			T1	38		T3	32		T6	17
valid_sources[0x53]	39194	1			T1	163		T3	26		T6	17
valid_sources[0x54]	29054	1			T3	9		T6	11		T7	7
valid_sources[0x55]	27898	1			T1	21		T3	39		T6	5
valid_sources[0x56]	29940	1			T1	1		T3	10		T6	5
valid_sources[0x57]	27769	1			T1	207		T3	12		T6	8
valid_sources[0x58]	32178	1			T3	30		T6	4		T7	5
valid_sources[0x59]	30105	1			T1	96		T3	12		T6	10
valid_sources[0x5a]	35371	1			T1	16		T3	17		T6	12
valid_sources[0x5b]	28455	1			T1	322		T3	22		T6	7
valid_sources[0x5c]	30013	1			T1	1		T3	34		T6	12
valid_sources[0x5d]	29728	1			T3	28		T6	6		T7	7
valid_sources[0x5e]	28290	1			T3	11		T6	10		T7	5
valid_sources[0x5f]	32022	1			T3	16		T6	5		T7	3
valid_sources[0x60]	28108	1			T3	21		T6	5		T7	4
valid_sources[0x61]	28166	1			T1	16		T3	16		T4	1
valid_sources[0x62]	31448	1			T1	25		T3	26		T4	1
valid_sources[0x63]	32221	1			T3	48		T6	15		T7	5
valid_sources[0x64]	28000	1			T1	3		T3	40		T6	5
valid_sources[0x65]	30092	1			T1	1		T3	25		T6	4
valid_sources[0x66]	29306	1			T1	1		T3	11		T6	17
valid_sources[0x67]	34514	1			T3	25		T6	7		T7	4
valid_sources[0x68]	29234	1			T1	3		T3	25		T6	14
valid_sources[0x69]	26472	1			T3	15		T6	8		T7	6
valid_sources[0x6a]	27406	1			T1	68		T3	27		T6	9
valid_sources[0x6b]	75891	1			T1	53		T3	35		T6	16
valid_sources[0x6c]	28595	1			T1	4		T3	47		T6	6
valid_sources[0x6d]	28646	1			T1	2		T3	17		T6	10
valid_sources[0x6e]	31010	1			T1	6		T3	23		T6	2
valid_sources[0x6f]	28002	1			T1	2		T3	13		T6	1
valid_sources[0x70]	35005	1			T3	26		T6	5		T7	6
valid_sources[0x71]	29985	1			T3	20		T6	13		T7	8
valid_sources[0x72]	29812	1			T1	87		T3	33		T6	9
valid_sources[0x73]	29636	1			T3	23		T6	22		T7	8
valid_sources[0x74]	28999	1			T1	55		T3	43		T6	7
valid_sources[0x75]	28412	1			T1	7		T3	16		T6	5
valid_sources[0x76]	29093	1			T1	24		T3	49		T6	5
valid_sources[0x77]	26740	1			T3	32		T6	7		T7	9
valid_sources[0x78]	27647	1			T1	1		T3	26		T6	6
valid_sources[0x79]	28538	1			T1	53		T3	9		T6	1
valid_sources[0x7a]	28598	1			T1	5		T3	30		T6	9
valid_sources[0x7b]	30520	1			T3	44		T6	10		T7	6
valid_sources[0x7c]	30858	1			T1	5		T3	7		T6	6
valid_sources[0x7d]	27851	1			T3	48		T6	6		T7	9
valid_sources[0x7e]	28929	1			T1	5		T3	25		T6	5
valid_sources[0x7f]	29310	1			T3	34		T6	9		T7	6
valid_sources[0x80]	27539	1			T1	327		T3	11		T6	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1043887

1

T1

1459

T2

1

T3

859

values[0x0]

all_enables

biggest_size

1540430

1

T1

3721

T3

2157

T4

13

values[0x1]

all_enables

biggest_size

1517834

1

T1

3491

T3

2217

T4

9