Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3809552

1

T1

3390

T2

12

T3

931

full_word

4103414

1

T1

8671

T2

1

T3

5233

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7912556	1			T1	12061		T2	13		T3	6164
auto[TlIntgErrCmd]	137	1			T66	3		T99	10		T100	9
auto[TlIntgErrData]	137	1			T66	3		T99	10		T100	4
auto[TlIntgErrBoth]	136	1			T66	4		T99	10		T100	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4486286

1

T1

3700

T2

1

T3

1767

auto[1]

3426680

1

T1

8361

T2

12

T3

4397

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3441962	1			T1	2241		T3	908		T5	1
auto[TlIntgErrNone]	partial	auto[1]	367214	1			T1	1149		T2	12		T3	23
auto[TlIntgErrNone]	full_word	auto[0]	1044145	1			T1	1459		T2	1		T3	859
auto[TlIntgErrNone]	full_word	auto[1]	3059235	1			T1	7212		T3	4374		T4	22
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T99	6		T100	1		T108	5
auto[TlIntgErrCmd]	partial	auto[1]	72	1			T66	3		T99	4		T100	8
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T173	1		T176	1		T177	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T108	1		T178	1		-	-
auto[TlIntgErrData]	partial	auto[0]	59	1			T66	2		T99	2		T100	1
auto[TlIntgErrData]	partial	auto[1]	67	1			T66	1		T99	6		T100	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T99	1		T173	1		T176	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T99	1		T175	1		T173	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T66	3		T99	2		T100	4
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T66	1		T99	7		T100	2
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T100	1		T110	1		T175	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T99	1		T110	2		T174	1