Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	558361495	2830316	0	0
gen_wmask[1].MaskCheckPortA_A	558361495	2830316	0	0
gen_wmask[2].MaskCheckPortA_A	558361495	2830316	0	0
gen_wmask[3].MaskCheckPortA_A	558361495	2830316	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558361495	2830316	0	0
T1	782066	10604	0	0
T2	1446	0	0	0
T3	322744	4163	0	0
T4	3857	0	0	0
T5	9362	832	0	0
T6	42419	832	0	0
T7	41516	832	0	0
T8	1030316	14688	0	0
T9	7185	149	0	0
T10	39554	832	0	0
T11	208354	832	0	0
T12	0	186	0	0
T14	0	2642	0	0
T17	0	2999	0	0
T18	0	3630	0	0
T21	0	5996	0	0
T26	0	6762	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558361495	2830316	0	0
T1	782066	10604	0	0
T2	1446	0	0	0
T3	322744	4163	0	0
T4	3857	0	0	0
T5	9362	832	0	0
T6	42419	832	0	0
T7	41516	832	0	0
T8	1030316	14688	0	0
T9	7185	149	0	0
T10	39554	832	0	0
T11	208354	832	0	0
T12	0	186	0	0
T14	0	2642	0	0
T17	0	2999	0	0
T18	0	3630	0	0
T21	0	5996	0	0
T26	0	6762	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558361495	2830316	0	0
T1	782066	10604	0	0
T2	1446	0	0	0
T3	322744	4163	0	0
T4	3857	0	0	0
T5	9362	832	0	0
T6	42419	832	0	0
T7	41516	832	0	0
T8	1030316	14688	0	0
T9	7185	149	0	0
T10	39554	832	0	0
T11	208354	832	0	0
T12	0	186	0	0
T14	0	2642	0	0
T17	0	2999	0	0
T18	0	3630	0	0
T21	0	5996	0	0
T26	0	6762	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558361495	2830316	0	0
T1	782066	10604	0	0
T2	1446	0	0	0
T3	322744	4163	0	0
T4	3857	0	0	0
T5	9362	832	0	0
T6	42419	832	0	0
T7	41516	832	0	0
T8	1030316	14688	0	0
T9	7185	149	0	0
T10	39554	832	0	0
T11	208354	832	0	0
T12	0	186	0	0
T14	0	2642	0	0
T17	0	2999	0	0
T18	0	3630	0	0
T21	0	5996	0	0
T26	0	6762	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	421146246	1884264	0	0
gen_wmask[1].MaskCheckPortA_A	421146246	1884264	0	0
gen_wmask[2].MaskCheckPortA_A	421146246	1884264	0	0
gen_wmask[3].MaskCheckPortA_A	421146246	1884264	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	1884264	0	0
T1	179030	6027	0	0
T2	1446	0	0	0
T3	122276	4160	0	0
T4	3209	0	0	0
T5	5250	832	0	0
T6	32703	832	0	0
T7	30876	832	0	0
T8	305137	5948	0	0
T9	4719	21	0	0
T10	32394	832	0	0
T11	0	832	0	0
T12	0	19	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	1884264	0	0
T1	179030	6027	0	0
T2	1446	0	0	0
T3	122276	4160	0	0
T4	3209	0	0	0
T5	5250	832	0	0
T6	32703	832	0	0
T7	30876	832	0	0
T8	305137	5948	0	0
T9	4719	21	0	0
T10	32394	832	0	0
T11	0	832	0	0
T12	0	19	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	1884264	0	0
T1	179030	6027	0	0
T2	1446	0	0	0
T3	122276	4160	0	0
T4	3209	0	0	0
T5	5250	832	0	0
T6	32703	832	0	0
T7	30876	832	0	0
T8	305137	5948	0	0
T9	4719	21	0	0
T10	32394	832	0	0
T11	0	832	0	0
T12	0	19	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	1884264	0	0
T1	179030	6027	0	0
T2	1446	0	0	0
T3	122276	4160	0	0
T4	3209	0	0	0
T5	5250	832	0	0
T6	32703	832	0	0
T7	30876	832	0	0
T8	305137	5948	0	0
T9	4719	21	0	0
T10	32394	832	0	0
T11	0	832	0	0
T12	0	19	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	137215249	946052	0	0
gen_wmask[1].MaskCheckPortA_A	137215249	946052	0	0
gen_wmask[2].MaskCheckPortA_A	137215249	946052	0	0
gen_wmask[3].MaskCheckPortA_A	137215249	946052	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	946052	0	0
T1	603036	4577	0	0
T3	200468	3	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	8740	0	0
T9	2466	128	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T12	0	167	0	0
T14	0	2642	0	0
T17	0	2999	0	0
T18	0	3630	0	0
T21	0	5996	0	0
T26	0	6762	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	946052	0	0
T1	603036	4577	0	0
T3	200468	3	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	8740	0	0
T9	2466	128	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T12	0	167	0	0
T14	0	2642	0	0
T17	0	2999	0	0
T18	0	3630	0	0
T21	0	5996	0	0
T26	0	6762	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	946052	0	0
T1	603036	4577	0	0
T3	200468	3	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	8740	0	0
T9	2466	128	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T12	0	167	0	0
T14	0	2642	0	0
T17	0	2999	0	0
T18	0	3630	0	0
T21	0	5996	0	0
T26	0	6762	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	946052	0	0
T1	603036	4577	0	0
T3	200468	3	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	8740	0	0
T9	2466	128	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T12	0	167	0	0
T14	0	2642	0	0
T17	0	2999	0	0
T18	0	3630	0	0
T21	0	5996	0	0
T26	0	6762	0	0