Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	423465160	2567034	0	0
DepthKnown_A	423465160	423334403	0	0
RvalidKnown_A	423465160	423334403	0	0
WreadyKnown_A	423465160	423334403	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	2567034	0	0
T1	179030	6654	0	0
T2	1446	0	0	0
T3	122276	4991	0	0
T4	3209	0	0	0
T5	5250	1663	0	0
T6	32703	1663	0	0
T7	30876	832	0	0
T8	305137	9978	0	0
T9	4719	0	0	0
T10	32394	1663	0	0
T11	0	832	0	0
T15	0	832	0	0
T19	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	423465160	2847867	0	0
DepthKnown_A	423465160	423334403	0	0
RvalidKnown_A	423465160	423334403	0	0
WreadyKnown_A	423465160	423334403	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	2847867	0	0
T1	179030	4992	0	0
T2	1446	0	0	0
T3	122276	4160	0	0
T4	3209	0	0	0
T5	5250	832	0	0
T6	32703	832	0	0
T7	30876	2636	0	0
T8	305137	4992	0	0
T9	4719	0	0	0
T10	32394	832	0	0
T11	0	832	0	0
T15	0	832	0	0
T19	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	423465160	163505	0	0
DepthKnown_A	423465160	423334403	0	0
RvalidKnown_A	423465160	423334403	0	0
WreadyKnown_A	423465160	423334403	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	163505	0	0
T1	179030	1168	0	0
T2	1446	0	0	0
T3	122276	0	0	0
T4	3209	0	0	0
T5	5250	0	0	0
T6	32703	0	0	0
T7	30876	0	0	0
T8	305137	959	0	0
T9	4719	35	0	0
T10	32394	0	0	0
T12	0	43	0	0
T14	0	680	0	0
T17	0	768	0	0
T18	0	940	0	0
T21	0	494	0	0
T26	0	1159	0	0
T27	0	303	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	423465160	397990	0	0
DepthKnown_A	423465160	423334403	0	0
RvalidKnown_A	423465160	423334403	0	0
WreadyKnown_A	423465160	423334403	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	397990	0	0
T1	179030	1168	0	0
T2	1446	0	0	0
T3	122276	0	0	0
T4	3209	0	0	0
T5	5250	0	0	0
T6	32703	0	0	0
T7	30876	0	0	0
T8	305137	4157	0	0
T9	4719	35	0	0
T10	32394	0	0	0
T12	0	43	0	0
T14	0	680	0	0
T17	0	768	0	0
T18	0	940	0	0
T21	0	2190	0	0
T26	0	1159	0	0
T27	0	303	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	423465160	6562541	0	0
DepthKnown_A	423465160	423334403	0	0
RvalidKnown_A	423465160	423334403	0	0
WreadyKnown_A	423465160	423334403	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	6562541	0	0
T1	179030	5973	0	0
T2	1446	13	0	0
T3	122276	2005	0	0
T4	3209	29	0	0
T5	5250	46	0	0
T6	32703	1315	0	0
T7	30876	928	0	0
T8	305137	8757	0	0
T9	4719	822	0	0
T10	32394	1458	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	423465160	14693031	0	0
DepthKnown_A	423465160	423334403	0	0
RvalidKnown_A	423465160	423334403	0	0
WreadyKnown_A	423465160	423334403	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	14693031	0	0
T1	179030	5901	0	0
T2	1446	13	0	0
T3	122276	2004	0	0
T4	3209	29	0	0
T5	5250	46	0	0
T6	32703	1315	0	0
T7	30876	2745	0	0
T8	305137	33604	0	0
T9	4719	822	0	0
T10	32394	1458	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423465160	423334403	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0