Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Unreachable
1	1	Covered	T1,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	695576744	557030485	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	695576744	3202828	0	0
GntImpliesValid_A	695576744	3202828	0	0
GrantKnown_A	695576744	557030485	0	0
IdxKnown_A	695576744	557030485	0	0
IndexIsCorrect_A	695576744	3202828	0	0
LockArbDecision_A	695576744	0	0	0
NoReadyValidNoGrant_A	695576744	0	0	0
ReadyAndValidImplyGrant_A	695576744	3202828	0	0
ReqAndReadyImplyGrant_A	695576744	3202828	0	0
ReqImpliesValid_A	695576744	3202828	0	0
ReqStaysHighUntilGranted0_M	695576744	0	0	0
RoundRobin_A	695576744	2	0	906
ValidKnown_A	695576744	557030485	0	0
gen_data_port_assertion.DataFlow_A	695576744	3202828	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695576744	557030485	0	0
T1	1385102	777363	0	0
T2	1446	1380	0	0
T3	523212	322339	0	0
T4	4505	3779	0	0
T5	13474	9273	0	0
T6	52135	42195	0	0
T7	52156	41440	0	0
T8	1755495	1024824	0	0
T9	9651	6911	0	0
T10	46714	39500	0	0
T11	416708	207936	0	0
T12	0	3152	0	0
T13	0	15872	0	0
T14	0	101840	0	0
T15	0	28288	0	0
T17	0	99688	0	0
T18	0	397904	0	0
T19	0	53524	0	0
T21	0	4	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695576744	3202828	0	0
T1	1385102	12918	0	0
T2	1446	0	0	0
T3	523212	4166	0	0
T4	4505	0	0	0
T5	13474	832	0	0
T6	52135	832	0	0
T7	52156	832	0	0
T8	1755495	16712	0	0
T9	9651	210	0	0
T10	46714	832	0	0
T11	416708	832	0	0
T12	0	250	0	0
T14	0	3832	0	0
T17	0	4227	0	0
T18	0	5172	0	0
T21	0	5996	0	0
T25	0	12	0	0
T26	0	8958	0	0
T27	0	1793	0	0
T30	0	7747	0	0
T47	0	203	0	0
T48	0	5	0	0
T49	0	3856	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695576744	3202828	0	0
T1	1385102	12918	0	0
T2	1446	0	0	0
T3	523212	4166	0	0
T4	4505	0	0	0
T5	13474	832	0	0
T6	52135	832	0	0
T7	52156	832	0	0
T8	1755495	16712	0	0
T9	9651	210	0	0
T10	46714	832	0	0
T11	416708	832	0	0
T12	0	250	0	0
T14	0	3832	0	0
T17	0	4227	0	0
T18	0	5172	0	0
T21	0	5996	0	0
T25	0	12	0	0
T26	0	8958	0	0
T27	0	1793	0	0
T30	0	7747	0	0
T47	0	203	0	0
T48	0	5	0	0
T49	0	3856	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695576744	557030485	0	0
T1	1385102	777363	0	0
T2	1446	1380	0	0
T3	523212	322339	0	0
T4	4505	3779	0	0
T5	13474	9273	0	0
T6	52135	42195	0	0
T7	52156	41440	0	0
T8	1755495	1024824	0	0
T9	9651	6911	0	0
T10	46714	39500	0	0
T11	416708	207936	0	0
T12	0	3152	0	0
T13	0	15872	0	0
T14	0	101840	0	0
T15	0	28288	0	0
T17	0	99688	0	0
T18	0	397904	0	0
T19	0	53524	0	0
T21	0	4	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695576744	557030485	0	0
T1	1385102	777363	0	0
T2	1446	1380	0	0
T3	523212	322339	0	0
T4	4505	3779	0	0
T5	13474	9273	0	0
T6	52135	42195	0	0
T7	52156	41440	0	0
T8	1755495	1024824	0	0
T9	9651	6911	0	0
T10	46714	39500	0	0
T11	416708	207936	0	0
T12	0	3152	0	0
T13	0	15872	0	0
T14	0	101840	0	0
T15	0	28288	0	0
T17	0	99688	0	0
T18	0	397904	0	0
T19	0	53524	0	0
T21	0	4	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695576744	3202828	0	0
T1	1385102	12918	0	0
T2	1446	0	0	0
T3	523212	4166	0	0
T4	4505	0	0	0
T5	13474	832	0	0
T6	52135	832	0	0
T7	52156	832	0	0
T8	1755495	16712	0	0
T9	9651	210	0	0
T10	46714	832	0	0
T11	416708	832	0	0
T12	0	250	0	0
T14	0	3832	0	0
T17	0	4227	0	0
T18	0	5172	0	0
T21	0	5996	0	0
T25	0	12	0	0
T26	0	8958	0	0
T27	0	1793	0	0
T30	0	7747	0	0
T47	0	203	0	0
T48	0	5	0	0
T49	0	3856	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695576744	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695576744	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695576744	3202828	0	0
T1	1385102	12918	0	0
T2	1446	0	0	0
T3	523212	4166	0	0
T4	4505	0	0	0
T5	13474	832	0	0
T6	52135	832	0	0
T7	52156	832	0	0
T8	1755495	16712	0	0
T9	9651	210	0	0
T10	46714	832	0	0
T11	416708	832	0	0
T12	0	250	0	0
T14	0	3832	0	0
T17	0	4227	0	0
T18	0	5172	0	0
T21	0	5996	0	0
T25	0	12	0	0
T26	0	8958	0	0
T27	0	1793	0	0
T30	0	7747	0	0
T47	0	203	0	0
T48	0	5	0	0
T49	0	3856	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695576744	3202828	0	0
T1	1385102	12918	0	0
T2	1446	0	0	0
T3	523212	4166	0	0
T4	4505	0	0	0
T5	13474	832	0	0
T6	52135	832	0	0
T7	52156	832	0	0
T8	1755495	16712	0	0
T9	9651	210	0	0
T10	46714	832	0	0
T11	416708	832	0	0
T12	0	250	0	0
T14	0	3832	0	0
T17	0	4227	0	0
T18	0	5172	0	0
T21	0	5996	0	0
T25	0	12	0	0
T26	0	8958	0	0
T27	0	1793	0	0
T30	0	7747	0	0
T47	0	203	0	0
T48	0	5	0	0
T49	0	3856	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695576744	3202828	0	0
T1	1385102	12918	0	0
T2	1446	0	0	0
T3	523212	4166	0	0
T4	4505	0	0	0
T5	13474	832	0	0
T6	52135	832	0	0
T7	52156	832	0	0
T8	1755495	16712	0	0
T9	9651	210	0	0
T10	46714	832	0	0
T11	416708	832	0	0
T12	0	250	0	0
T14	0	3832	0	0
T17	0	4227	0	0
T18	0	5172	0	0
T21	0	5996	0	0
T25	0	12	0	0
T26	0	8958	0	0
T27	0	1793	0	0
T30	0	7747	0	0
T47	0	203	0	0
T48	0	5	0	0
T49	0	3856	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	695576744	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695576744	2	0	906
T50	336090	1	0	1
T51	0	1	0	0
T52	78129	0	0	1
T53	1105	0	0	1
T54	166611	0	0	1
T55	46621	0	0	1
T56	3223	0	0	1
T57	242950	0	0	1
T58	13705	0	0	1
T59	13991	0	0	1
T60	448613	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695576744	557030485	0	0
T1	1385102	777363	0	0
T2	1446	1380	0	0
T3	523212	322339	0	0
T4	4505	3779	0	0
T5	13474	9273	0	0
T6	52135	42195	0	0
T7	52156	41440	0	0
T8	1755495	1024824	0	0
T9	9651	6911	0	0
T10	46714	39500	0	0
T11	416708	207936	0	0
T12	0	3152	0	0
T13	0	15872	0	0
T14	0	101840	0	0
T15	0	28288	0	0
T17	0	99688	0	0
T18	0	397904	0	0
T19	0	53524	0	0
T21	0	4	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695576744	3202828	0	0
T1	1385102	12918	0	0
T2	1446	0	0	0
T3	523212	4166	0	0
T4	4505	0	0	0
T5	13474	832	0	0
T6	52135	832	0	0
T7	52156	832	0	0
T8	1755495	16712	0	0
T9	9651	210	0	0
T10	46714	832	0	0
T11	416708	832	0	0
T12	0	250	0	0
T14	0	3832	0	0
T17	0	4227	0	0
T18	0	5172	0	0
T21	0	5996	0	0
T25	0	12	0	0
T26	0	8958	0	0
T27	0	1793	0	0
T30	0	7747	0	0
T47	0	203	0	0
T48	0	5	0	0
T49	0	3856	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Unreachable
1	1	Covered	T1,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T8,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	137215249	28662416	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	137215249	652022	0	0
GntImpliesValid_A	137215249	652022	0	0
GrantKnown_A	137215249	28662416	0	0
IdxKnown_A	137215249	28662416	0	0
IndexIsCorrect_A	137215249	652022	0	0
LockArbDecision_A	137215249	0	0	0
NoReadyValidNoGrant_A	137215249	0	0	0
ReadyAndValidImplyGrant_A	137215249	652022	0	0
ReqAndReadyImplyGrant_A	137215249	652022	0	0
ReqImpliesValid_A	137215249	652022	0	0
ReqStaysHighUntilGranted0_M	137215249	0	0	0
RoundRobin_A	137215249	0	0	0
ValidKnown_A	137215249	28662416	0	0
gen_data_port_assertion.DataFlow_A	137215249	652022	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	28662416	0	0
T1	603036	389232	0	0
T3	200468	0	0	0
T4	648	648	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	320224	0	0
T9	2466	2256	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T12	0	3152	0	0
T13	0	15872	0	0
T14	0	101840	0	0
T17	0	99688	0	0
T18	0	397904	0	0
T21	0	4	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	652022	0	0
T1	603036	5059	0	0
T3	200468	0	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	3993	0	0
T9	2466	154	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T12	0	188	0	0
T14	0	3832	0	0
T17	0	4227	0	0
T18	0	5172	0	0
T26	0	5425	0	0
T27	0	1526	0	0
T47	0	203	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	652022	0	0
T1	603036	5059	0	0
T3	200468	0	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	3993	0	0
T9	2466	154	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T12	0	188	0	0
T14	0	3832	0	0
T17	0	4227	0	0
T18	0	5172	0	0
T26	0	5425	0	0
T27	0	1526	0	0
T47	0	203	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	28662416	0	0
T1	603036	389232	0	0
T3	200468	0	0	0
T4	648	648	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	320224	0	0
T9	2466	2256	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T12	0	3152	0	0
T13	0	15872	0	0
T14	0	101840	0	0
T17	0	99688	0	0
T18	0	397904	0	0
T21	0	4	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	28662416	0	0
T1	603036	389232	0	0
T3	200468	0	0	0
T4	648	648	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	320224	0	0
T9	2466	2256	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T12	0	3152	0	0
T13	0	15872	0	0
T14	0	101840	0	0
T17	0	99688	0	0
T18	0	397904	0	0
T21	0	4	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	652022	0	0
T1	603036	5059	0	0
T3	200468	0	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	3993	0	0
T9	2466	154	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T12	0	188	0	0
T14	0	3832	0	0
T17	0	4227	0	0
T18	0	5172	0	0
T26	0	5425	0	0
T27	0	1526	0	0
T47	0	203	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	652022	0	0
T1	603036	5059	0	0
T3	200468	0	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	3993	0	0
T9	2466	154	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T12	0	188	0	0
T14	0	3832	0	0
T17	0	4227	0	0
T18	0	5172	0	0
T26	0	5425	0	0
T27	0	1526	0	0
T47	0	203	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	652022	0	0
T1	603036	5059	0	0
T3	200468	0	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	3993	0	0
T9	2466	154	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T12	0	188	0	0
T14	0	3832	0	0
T17	0	4227	0	0
T18	0	5172	0	0
T26	0	5425	0	0
T27	0	1526	0	0
T47	0	203	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	652022	0	0
T1	603036	5059	0	0
T3	200468	0	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	3993	0	0
T9	2466	154	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T12	0	188	0	0
T14	0	3832	0	0
T17	0	4227	0	0
T18	0	5172	0	0
T26	0	5425	0	0
T27	0	1526	0	0
T47	0	203	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	28662416	0	0
T1	603036	389232	0	0
T3	200468	0	0	0
T4	648	648	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	320224	0	0
T9	2466	2256	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T12	0	3152	0	0
T13	0	15872	0	0
T14	0	101840	0	0
T17	0	99688	0	0
T18	0	397904	0	0
T21	0	4	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	652022	0	0
T1	603036	5059	0	0
T3	200468	0	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	3993	0	0
T9	2466	154	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T12	0	188	0	0
T14	0	3832	0	0
T17	0	4227	0	0
T18	0	5172	0	0
T26	0	5425	0	0
T27	0	1526	0	0
T47	0	203	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	137215249	107307232	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	137215249	511337	0	0
GntImpliesValid_A	137215249	511337	0	0
GrantKnown_A	137215249	107307232	0	0
IdxKnown_A	137215249	107307232	0	0
IndexIsCorrect_A	137215249	511337	0	0
LockArbDecision_A	137215249	0	0	0
NoReadyValidNoGrant_A	137215249	0	0	0
ReadyAndValidImplyGrant_A	137215249	511337	0	0
ReqAndReadyImplyGrant_A	137215249	511337	0	0
ReqImpliesValid_A	137215249	511337	0	0
ReqStaysHighUntilGranted0_M	137215249	0	0	0
RoundRobin_A	137215249	0	0	0
ValidKnown_A	137215249	107307232	0	0
gen_data_port_assertion.DataFlow_A	137215249	511337	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	107307232	0	0
T1	603036	209166	0	0
T3	200468	200068	0	0
T4	648	0	0	0
T5	4112	4112	0	0
T6	9716	9552	0	0
T7	10640	10640	0	0
T8	725179	399547	0	0
T9	2466	0	0	0
T10	7160	7160	0	0
T11	208354	207936	0	0
T15	0	28288	0	0
T19	0	53524	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	511337	0	0
T1	603036	654	0	0
T3	200468	3	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	5801	0	0
T9	2466	0	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T21	0	5996	0	0
T25	0	12	0	0
T26	0	3533	0	0
T27	0	267	0	0
T30	0	7747	0	0
T48	0	5	0	0
T49	0	3856	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	511337	0	0
T1	603036	654	0	0
T3	200468	3	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	5801	0	0
T9	2466	0	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T21	0	5996	0	0
T25	0	12	0	0
T26	0	3533	0	0
T27	0	267	0	0
T30	0	7747	0	0
T48	0	5	0	0
T49	0	3856	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	107307232	0	0
T1	603036	209166	0	0
T3	200468	200068	0	0
T4	648	0	0	0
T5	4112	4112	0	0
T6	9716	9552	0	0
T7	10640	10640	0	0
T8	725179	399547	0	0
T9	2466	0	0	0
T10	7160	7160	0	0
T11	208354	207936	0	0
T15	0	28288	0	0
T19	0	53524	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	107307232	0	0
T1	603036	209166	0	0
T3	200468	200068	0	0
T4	648	0	0	0
T5	4112	4112	0	0
T6	9716	9552	0	0
T7	10640	10640	0	0
T8	725179	399547	0	0
T9	2466	0	0	0
T10	7160	7160	0	0
T11	208354	207936	0	0
T15	0	28288	0	0
T19	0	53524	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	511337	0	0
T1	603036	654	0	0
T3	200468	3	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	5801	0	0
T9	2466	0	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T21	0	5996	0	0
T25	0	12	0	0
T26	0	3533	0	0
T27	0	267	0	0
T30	0	7747	0	0
T48	0	5	0	0
T49	0	3856	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	511337	0	0
T1	603036	654	0	0
T3	200468	3	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	5801	0	0
T9	2466	0	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T21	0	5996	0	0
T25	0	12	0	0
T26	0	3533	0	0
T27	0	267	0	0
T30	0	7747	0	0
T48	0	5	0	0
T49	0	3856	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	511337	0	0
T1	603036	654	0	0
T3	200468	3	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	5801	0	0
T9	2466	0	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T21	0	5996	0	0
T25	0	12	0	0
T26	0	3533	0	0
T27	0	267	0	0
T30	0	7747	0	0
T48	0	5	0	0
T49	0	3856	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	511337	0	0
T1	603036	654	0	0
T3	200468	3	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	5801	0	0
T9	2466	0	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T21	0	5996	0	0
T25	0	12	0	0
T26	0	3533	0	0
T27	0	267	0	0
T30	0	7747	0	0
T48	0	5	0	0
T49	0	3856	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	107307232	0	0
T1	603036	209166	0	0
T3	200468	200068	0	0
T4	648	0	0	0
T5	4112	4112	0	0
T6	9716	9552	0	0
T7	10640	10640	0	0
T8	725179	399547	0	0
T9	2466	0	0	0
T10	7160	7160	0	0
T11	208354	207936	0	0
T15	0	28288	0	0
T19	0	53524	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	137215249	511337	0	0
T1	603036	654	0	0
T3	200468	3	0	0
T4	648	0	0	0
T5	4112	0	0	0
T6	9716	0	0	0
T7	10640	0	0	0
T8	725179	5801	0	0
T9	2466	0	0	0
T10	7160	0	0	0
T11	208354	0	0	0
T21	0	5996	0	0
T25	0	12	0	0
T26	0	3533	0	0
T27	0	267	0	0
T30	0	7747	0	0
T48	0	5	0	0
T49	0	3856	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	421146246	421060837	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	421146246	2039469	0	0
GntImpliesValid_A	421146246	2039469	0	0
GrantKnown_A	421146246	421060837	0	0
IdxKnown_A	421146246	421060837	0	0
IndexIsCorrect_A	421146246	2039469	0	0
LockArbDecision_A	421146246	0	0	0
NoReadyValidNoGrant_A	421146246	0	0	0
ReadyAndValidImplyGrant_A	421146246	2039469	0	0
ReqAndReadyImplyGrant_A	421146246	2039469	0	0
ReqImpliesValid_A	421146246	2039469	0	0
ReqStaysHighUntilGranted0_M	421146246	0	0	0
RoundRobin_A	421146246	2	0	906
ValidKnown_A	421146246	421060837	0	0
gen_data_port_assertion.DataFlow_A	421146246	2039469	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	421060837	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	2039469	0	0
T1	179030	7205	0	0
T2	1446	0	0	0
T3	122276	4163	0	0
T4	3209	0	0	0
T5	5250	832	0	0
T6	32703	832	0	0
T7	30876	832	0	0
T8	305137	6918	0	0
T9	4719	56	0	0
T10	32394	832	0	0
T11	0	832	0	0
T12	0	62	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	2039469	0	0
T1	179030	7205	0	0
T2	1446	0	0	0
T3	122276	4163	0	0
T4	3209	0	0	0
T5	5250	832	0	0
T6	32703	832	0	0
T7	30876	832	0	0
T8	305137	6918	0	0
T9	4719	56	0	0
T10	32394	832	0	0
T11	0	832	0	0
T12	0	62	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	421060837	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	421060837	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	2039469	0	0
T1	179030	7205	0	0
T2	1446	0	0	0
T3	122276	4163	0	0
T4	3209	0	0	0
T5	5250	832	0	0
T6	32703	832	0	0
T7	30876	832	0	0
T8	305137	6918	0	0
T9	4719	56	0	0
T10	32394	832	0	0
T11	0	832	0	0
T12	0	62	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	2039469	0	0
T1	179030	7205	0	0
T2	1446	0	0	0
T3	122276	4163	0	0
T4	3209	0	0	0
T5	5250	832	0	0
T6	32703	832	0	0
T7	30876	832	0	0
T8	305137	6918	0	0
T9	4719	56	0	0
T10	32394	832	0	0
T11	0	832	0	0
T12	0	62	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	2039469	0	0
T1	179030	7205	0	0
T2	1446	0	0	0
T3	122276	4163	0	0
T4	3209	0	0	0
T5	5250	832	0	0
T6	32703	832	0	0
T7	30876	832	0	0
T8	305137	6918	0	0
T9	4719	56	0	0
T10	32394	832	0	0
T11	0	832	0	0
T12	0	62	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	2039469	0	0
T1	179030	7205	0	0
T2	1446	0	0	0
T3	122276	4163	0	0
T4	3209	0	0	0
T5	5250	832	0	0
T6	32703	832	0	0
T7	30876	832	0	0
T8	305137	6918	0	0
T9	4719	56	0	0
T10	32394	832	0	0
T11	0	832	0	0
T12	0	62	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	2	0	906
T50	336090	1	0	1
T51	0	1	0	0
T52	78129	0	0	1
T53	1105	0	0	1
T54	166611	0	0	1
T55	46621	0	0	1
T56	3223	0	0	1
T57	242950	0	0	1
T58	13705	0	0	1
T59	13991	0	0	1
T60	448613	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	421060837	0	0
T1	179030	178965	0	0
T2	1446	1380	0	0
T3	122276	122271	0	0
T4	3209	3131	0	0
T5	5250	5161	0	0
T6	32703	32643	0	0
T7	30876	30800	0	0
T8	305137	305053	0	0
T9	4719	4655	0	0
T10	32394	32340	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421146246	2039469	0	0
T1	179030	7205	0	0
T2	1446	0	0	0
T3	122276	4163	0	0
T4	3209	0	0	0
T5	5250	832	0	0
T6	32703	832	0	0
T7	30876	832	0	0
T8	305137	6918	0	0
T9	4719	56	0	0
T10	32394	832	0	0
T11	0	832	0	0
T12	0	62	0	0