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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.09 98.30 94.11 98.61 89.36 97.16 95.84 99.25


Total test records in report: 1081
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1010 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3427708273 Jun 07 07:44:16 PM PDT 24 Jun 07 07:44:20 PM PDT 24 42117651 ps
T1011 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1888930257 Jun 07 07:44:33 PM PDT 24 Jun 07 07:44:44 PM PDT 24 415382692 ps
T1012 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3490025125 Jun 07 07:44:25 PM PDT 24 Jun 07 07:44:31 PM PDT 24 152101973 ps
T1013 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4138643643 Jun 07 07:44:10 PM PDT 24 Jun 07 07:44:14 PM PDT 24 205762439 ps
T126 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2235627254 Jun 07 07:44:32 PM PDT 24 Jun 07 07:44:36 PM PDT 24 21446263 ps
T1014 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1131338181 Jun 07 07:44:17 PM PDT 24 Jun 07 07:44:20 PM PDT 24 206812083 ps
T1015 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1640546746 Jun 07 07:44:26 PM PDT 24 Jun 07 07:44:31 PM PDT 24 496822554 ps
T1016 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1503092204 Jun 07 07:43:54 PM PDT 24 Jun 07 07:43:59 PM PDT 24 42038226 ps
T1017 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3599833045 Jun 07 07:44:06 PM PDT 24 Jun 07 07:44:09 PM PDT 24 17615940 ps
T1018 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3452464851 Jun 07 07:44:33 PM PDT 24 Jun 07 07:44:37 PM PDT 24 49555660 ps
T1019 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3310045577 Jun 07 07:44:34 PM PDT 24 Jun 07 07:44:38 PM PDT 24 19872159 ps
T127 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.799188259 Jun 07 07:44:06 PM PDT 24 Jun 07 07:44:10 PM PDT 24 99174154 ps
T178 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2386968427 Jun 07 07:44:09 PM PDT 24 Jun 07 07:44:35 PM PDT 24 4224675975 ps
T1020 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1404218734 Jun 07 07:44:06 PM PDT 24 Jun 07 07:44:09 PM PDT 24 14348227 ps
T1021 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1280001281 Jun 07 07:44:23 PM PDT 24 Jun 07 07:44:26 PM PDT 24 78884188 ps
T1022 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1379830652 Jun 07 07:44:33 PM PDT 24 Jun 07 07:44:37 PM PDT 24 48229532 ps
T1023 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2425213849 Jun 07 07:44:33 PM PDT 24 Jun 07 07:44:37 PM PDT 24 225788151 ps
T1024 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1486686974 Jun 07 07:44:06 PM PDT 24 Jun 07 07:44:20 PM PDT 24 395446234 ps
T1025 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4066980722 Jun 07 07:43:44 PM PDT 24 Jun 07 07:43:59 PM PDT 24 2526797718 ps
T1026 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.833821107 Jun 07 07:44:26 PM PDT 24 Jun 07 07:44:29 PM PDT 24 23237295 ps
T1027 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4149379241 Jun 07 07:44:04 PM PDT 24 Jun 07 07:44:09 PM PDT 24 67429692 ps
T1028 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.610166247 Jun 07 07:44:11 PM PDT 24 Jun 07 07:44:14 PM PDT 24 53138043 ps
T1029 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2367677934 Jun 07 07:44:14 PM PDT 24 Jun 07 07:44:17 PM PDT 24 40452920 ps
T1030 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.924642809 Jun 07 07:44:16 PM PDT 24 Jun 07 07:44:22 PM PDT 24 207281787 ps
T1031 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4243515890 Jun 07 07:44:02 PM PDT 24 Jun 07 07:44:29 PM PDT 24 9374489192 ps
T87 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3248485561 Jun 07 07:43:53 PM PDT 24 Jun 07 07:43:55 PM PDT 24 59581519 ps
T1032 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1614759226 Jun 07 07:44:43 PM PDT 24 Jun 07 07:44:46 PM PDT 24 17089971 ps
T1033 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2970151837 Jun 07 07:44:25 PM PDT 24 Jun 07 07:44:28 PM PDT 24 53034070 ps
T1034 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2934391573 Jun 07 07:44:18 PM PDT 24 Jun 07 07:44:23 PM PDT 24 74227630 ps
T1035 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.658938719 Jun 07 07:44:40 PM PDT 24 Jun 07 07:44:42 PM PDT 24 70565003 ps
T1036 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3490574404 Jun 07 07:44:14 PM PDT 24 Jun 07 07:44:19 PM PDT 24 53489065 ps
T1037 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1966228069 Jun 07 07:44:32 PM PDT 24 Jun 07 07:44:38 PM PDT 24 99598903 ps
T1038 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.763548163 Jun 07 07:44:16 PM PDT 24 Jun 07 07:44:19 PM PDT 24 95661950 ps
T1039 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1242844089 Jun 07 07:44:24 PM PDT 24 Jun 07 07:44:42 PM PDT 24 1635836357 ps
T1040 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3625320882 Jun 07 07:44:02 PM PDT 24 Jun 07 07:44:07 PM PDT 24 36654427 ps
T1041 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.290267595 Jun 07 07:44:31 PM PDT 24 Jun 07 07:44:38 PM PDT 24 1943854081 ps
T1042 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.344943476 Jun 07 07:44:01 PM PDT 24 Jun 07 07:44:07 PM PDT 24 1218254307 ps
T1043 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3685706629 Jun 07 07:44:34 PM PDT 24 Jun 07 07:44:38 PM PDT 24 159509329 ps
T1044 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1254186734 Jun 07 07:44:35 PM PDT 24 Jun 07 07:44:38 PM PDT 24 15688362 ps
T1045 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2628783894 Jun 07 07:44:03 PM PDT 24 Jun 07 07:44:17 PM PDT 24 191926778 ps
T1046 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2203199888 Jun 07 07:43:54 PM PDT 24 Jun 07 07:44:21 PM PDT 24 5299284758 ps
T1047 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2752074570 Jun 07 07:43:50 PM PDT 24 Jun 07 07:43:54 PM PDT 24 72947728 ps
T1048 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1467328549 Jun 07 07:44:04 PM PDT 24 Jun 07 07:44:07 PM PDT 24 13578343 ps
T1049 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.398085971 Jun 07 07:44:34 PM PDT 24 Jun 07 07:44:37 PM PDT 24 47525796 ps
T177 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1269317266 Jun 07 07:44:12 PM PDT 24 Jun 07 07:44:19 PM PDT 24 1041261620 ps
T1050 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1361512449 Jun 07 07:44:25 PM PDT 24 Jun 07 07:44:29 PM PDT 24 149304101 ps
T88 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1943023626 Jun 07 07:44:05 PM PDT 24 Jun 07 07:44:09 PM PDT 24 51256825 ps
T1051 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.690005453 Jun 07 07:44:41 PM PDT 24 Jun 07 07:44:43 PM PDT 24 74498251 ps
T1052 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3134640364 Jun 07 07:44:35 PM PDT 24 Jun 07 07:44:38 PM PDT 24 44766864 ps
T1053 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.620995057 Jun 07 07:44:30 PM PDT 24 Jun 07 07:44:33 PM PDT 24 52639302 ps
T1054 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2317726373 Jun 07 07:43:55 PM PDT 24 Jun 07 07:44:10 PM PDT 24 806202050 ps
T1055 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1564166927 Jun 07 07:44:33 PM PDT 24 Jun 07 07:44:36 PM PDT 24 17379549 ps
T1056 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.741094119 Jun 07 07:43:54 PM PDT 24 Jun 07 07:43:57 PM PDT 24 27830723 ps
T1057 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1334774980 Jun 07 07:44:32 PM PDT 24 Jun 07 07:44:35 PM PDT 24 17909207 ps
T1058 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2004401679 Jun 07 07:44:31 PM PDT 24 Jun 07 07:44:33 PM PDT 24 14412316 ps
T1059 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2370540289 Jun 07 07:44:13 PM PDT 24 Jun 07 07:44:18 PM PDT 24 60153717 ps
T1060 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2801770542 Jun 07 07:44:34 PM PDT 24 Jun 07 07:44:37 PM PDT 24 42989731 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2088430140 Jun 07 07:43:55 PM PDT 24 Jun 07 07:44:02 PM PDT 24 154668307 ps
T1062 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4158983420 Jun 07 07:43:42 PM PDT 24 Jun 07 07:43:46 PM PDT 24 269597095 ps
T1063 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1525071025 Jun 07 07:44:10 PM PDT 24 Jun 07 07:44:21 PM PDT 24 1486108029 ps
T1064 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.522792748 Jun 07 07:44:16 PM PDT 24 Jun 07 07:44:20 PM PDT 24 102446531 ps
T89 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2091311732 Jun 07 07:43:44 PM PDT 24 Jun 07 07:43:46 PM PDT 24 42899279 ps
T1065 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1055128811 Jun 07 07:44:38 PM PDT 24 Jun 07 07:44:40 PM PDT 24 34490687 ps
T1066 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.693434156 Jun 07 07:44:26 PM PDT 24 Jun 07 07:44:31 PM PDT 24 48876552 ps
T1067 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1451848352 Jun 07 07:44:16 PM PDT 24 Jun 07 07:44:19 PM PDT 24 128668329 ps
T1068 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1264890974 Jun 07 07:44:02 PM PDT 24 Jun 07 07:44:05 PM PDT 24 19477192 ps
T1069 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3647883085 Jun 07 07:44:02 PM PDT 24 Jun 07 07:44:29 PM PDT 24 1030346219 ps
T1070 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.761788310 Jun 07 07:44:05 PM PDT 24 Jun 07 07:44:09 PM PDT 24 94228307 ps
T1071 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2098157283 Jun 07 07:44:27 PM PDT 24 Jun 07 07:44:32 PM PDT 24 173211491 ps
T1072 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.756258296 Jun 07 07:44:17 PM PDT 24 Jun 07 07:44:22 PM PDT 24 276638023 ps
T1073 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1945674734 Jun 07 07:44:31 PM PDT 24 Jun 07 07:44:34 PM PDT 24 56432187 ps
T1074 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1929188216 Jun 07 07:44:09 PM PDT 24 Jun 07 07:44:12 PM PDT 24 74896564 ps
T1075 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.950112817 Jun 07 07:44:31 PM PDT 24 Jun 07 07:44:34 PM PDT 24 32096267 ps
T1076 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2815066868 Jun 07 07:44:01 PM PDT 24 Jun 07 07:44:05 PM PDT 24 68805051 ps
T1077 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2587359351 Jun 07 07:43:54 PM PDT 24 Jun 07 07:43:58 PM PDT 24 26963318 ps
T172 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3428003152 Jun 07 07:44:18 PM PDT 24 Jun 07 07:44:24 PM PDT 24 688474584 ps
T1078 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1806532270 Jun 07 07:44:16 PM PDT 24 Jun 07 07:44:19 PM PDT 24 57274728 ps
T1079 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4285015331 Jun 07 07:44:28 PM PDT 24 Jun 07 07:44:43 PM PDT 24 3176457262 ps
T1080 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1829129480 Jun 07 07:43:54 PM PDT 24 Jun 07 07:44:13 PM PDT 24 2685603105 ps
T1081 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1875722510 Jun 07 07:44:17 PM PDT 24 Jun 07 07:44:39 PM PDT 24 8972838661 ps
T90 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2021617911 Jun 07 07:44:06 PM PDT 24 Jun 07 07:44:09 PM PDT 24 93709146 ps

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3573863663
Short name T8
Test name
Test status
Simulation time 3082208270 ps
CPU time 74.46 seconds
Started Jun 07 07:53:09 PM PDT 24
Finished Jun 07 07:54:24 PM PDT 24
Peak memory 256544 kb
Host smart-743e283b-1731-4064-99eb-728acbea453f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573863663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3573863663
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2746911456
Short name T26
Test name
Test status
Simulation time 15808038932 ps
CPU time 127.18 seconds
Started Jun 07 07:55:34 PM PDT 24
Finished Jun 07 07:57:43 PM PDT 24
Peak memory 254796 kb
Host smart-f336b9d8-f0c4-495d-8e2f-3feaf06621bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746911456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2746911456
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4156520352
Short name T18
Test name
Test status
Simulation time 1858186389 ps
CPU time 25.79 seconds
Started Jun 07 07:53:31 PM PDT 24
Finished Jun 07 07:54:00 PM PDT 24
Peak memory 217204 kb
Host smart-656d631d-e290-4104-89a3-ca7142500cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156520352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4156520352
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3393923378
Short name T100
Test name
Test status
Simulation time 2853810466 ps
CPU time 16.16 seconds
Started Jun 07 07:44:27 PM PDT 24
Finished Jun 07 07:44:46 PM PDT 24
Peak memory 216920 kb
Host smart-0ba44742-3c0f-4145-a709-a74adbef80d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393923378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3393923378
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2715830212
Short name T37
Test name
Test status
Simulation time 45038176357 ps
CPU time 466.32 seconds
Started Jun 07 07:52:43 PM PDT 24
Finished Jun 07 08:00:31 PM PDT 24
Peak memory 274512 kb
Host smart-123f6e59-1347-4fbd-86ae-0d23a1fb23ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715830212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2715830212
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.432470456
Short name T70
Test name
Test status
Simulation time 80523109323 ps
CPU time 704 seconds
Started Jun 07 07:51:37 PM PDT 24
Finished Jun 07 08:03:23 PM PDT 24
Peak memory 282812 kb
Host smart-1f948647-f8bd-49eb-9828-12afa1f67944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432470456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.432470456
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3332153386
Short name T22
Test name
Test status
Simulation time 199881883143 ps
CPU time 1842.81 seconds
Started Jun 07 07:53:10 PM PDT 24
Finished Jun 07 08:23:55 PM PDT 24
Peak memory 290944 kb
Host smart-dd3c2e66-fdc1-4298-9d0c-803fb00f09bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332153386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3332153386
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3512694543
Short name T71
Test name
Test status
Simulation time 15651886 ps
CPU time 0.79 seconds
Started Jun 07 07:49:36 PM PDT 24
Finished Jun 07 07:49:37 PM PDT 24
Peak memory 216976 kb
Host smart-5a7309d2-6cb4-4dfd-b400-82c869d2da99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512694543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3512694543
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2232958665
Short name T34
Test name
Test status
Simulation time 96746619116 ps
CPU time 973.85 seconds
Started Jun 07 07:54:20 PM PDT 24
Finished Jun 07 08:10:35 PM PDT 24
Peak memory 253360 kb
Host smart-3694539d-31ae-4436-8170-520621892730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232958665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2232958665
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3787929399
Short name T68
Test name
Test status
Simulation time 173139748 ps
CPU time 4.22 seconds
Started Jun 07 07:44:11 PM PDT 24
Finished Jun 07 07:44:17 PM PDT 24
Peak memory 215520 kb
Host smart-68572c1f-f36b-4748-8735-a885118e46a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787929399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3787929399
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.324959795
Short name T216
Test name
Test status
Simulation time 159670470038 ps
CPU time 620.36 seconds
Started Jun 07 07:54:48 PM PDT 24
Finished Jun 07 08:05:09 PM PDT 24
Peak memory 269340 kb
Host smart-0e2f37a2-ac81-4dee-ad87-730988257212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324959795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.324959795
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.794203826
Short name T43
Test name
Test status
Simulation time 3071655110 ps
CPU time 13.52 seconds
Started Jun 07 07:52:42 PM PDT 24
Finished Jun 07 07:52:57 PM PDT 24
Peak memory 225500 kb
Host smart-5b6cfbc3-a90d-4fce-91e5-b95c785066e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794203826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.794203826
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1502230144
Short name T345
Test name
Test status
Simulation time 19840915 ps
CPU time 0.72 seconds
Started Jun 07 07:52:09 PM PDT 24
Finished Jun 07 07:52:12 PM PDT 24
Peak memory 206320 kb
Host smart-51bbb37f-2515-4b14-98ec-640ee253b612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502230144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1502230144
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3190463868
Short name T39
Test name
Test status
Simulation time 12700326722 ps
CPU time 180.02 seconds
Started Jun 07 07:54:28 PM PDT 24
Finished Jun 07 07:57:29 PM PDT 24
Peak memory 266512 kb
Host smart-e976a05c-2b5d-455c-88a8-095c8476ddf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190463868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3190463868
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2614327475
Short name T189
Test name
Test status
Simulation time 270377322303 ps
CPU time 649.14 seconds
Started Jun 07 07:52:46 PM PDT 24
Finished Jun 07 08:03:35 PM PDT 24
Peak memory 253104 kb
Host smart-72a5bca1-4796-464e-889d-9d7db93a078f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614327475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2614327475
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3946071561
Short name T1
Test name
Test status
Simulation time 3729748852 ps
CPU time 53.36 seconds
Started Jun 07 07:55:00 PM PDT 24
Finished Jun 07 07:55:56 PM PDT 24
Peak memory 250228 kb
Host smart-7c23f97f-e410-4fe4-9fc2-8843134791ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946071561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3946071561
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1000129726
Short name T118
Test name
Test status
Simulation time 289058511 ps
CPU time 2.68 seconds
Started Jun 07 07:43:54 PM PDT 24
Finished Jun 07 07:43:58 PM PDT 24
Peak memory 215340 kb
Host smart-ba70fd12-1765-4591-be8c-6663627af6dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000129726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
000129726
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3774000378
Short name T219
Test name
Test status
Simulation time 832935949112 ps
CPU time 1103.31 seconds
Started Jun 07 07:53:40 PM PDT 24
Finished Jun 07 08:12:07 PM PDT 24
Peak memory 274672 kb
Host smart-afe2b9cf-ca45-41ef-8595-3b925011184b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774000378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3774000378
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2953283054
Short name T185
Test name
Test status
Simulation time 22746591100 ps
CPU time 353.93 seconds
Started Jun 07 07:50:20 PM PDT 24
Finished Jun 07 07:56:18 PM PDT 24
Peak memory 274528 kb
Host smart-fdda3a92-6413-4acc-b8a8-e2044d963007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953283054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2953283054
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3508477097
Short name T32
Test name
Test status
Simulation time 73590593278 ps
CPU time 386.92 seconds
Started Jun 07 07:54:01 PM PDT 24
Finished Jun 07 08:00:30 PM PDT 24
Peak memory 255472 kb
Host smart-93262785-7679-4f6e-b71d-8ef3ecb70551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508477097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3508477097
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3079896240
Short name T74
Test name
Test status
Simulation time 106863260 ps
CPU time 1.07 seconds
Started Jun 07 07:49:45 PM PDT 24
Finished Jun 07 07:49:47 PM PDT 24
Peak memory 236184 kb
Host smart-832eebec-5bd4-48bd-b417-31e1eb0eef1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079896240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3079896240
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1322047087
Short name T188
Test name
Test status
Simulation time 89500919382 ps
CPU time 265.61 seconds
Started Jun 07 07:54:08 PM PDT 24
Finished Jun 07 07:58:35 PM PDT 24
Peak memory 254220 kb
Host smart-e28ec797-6dcd-4c2a-af8f-17560865ce36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322047087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1322047087
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2328135218
Short name T221
Test name
Test status
Simulation time 27630414869 ps
CPU time 109.15 seconds
Started Jun 07 07:49:44 PM PDT 24
Finished Jun 07 07:51:34 PM PDT 24
Peak memory 257376 kb
Host smart-011faad1-c100-4c2d-b926-d3258c565db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328135218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2328135218
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2910942433
Short name T38
Test name
Test status
Simulation time 163375869063 ps
CPU time 294.93 seconds
Started Jun 07 07:51:23 PM PDT 24
Finished Jun 07 07:56:20 PM PDT 24
Peak memory 252576 kb
Host smart-5d4f6870-2b26-4dd3-a94f-8db0856b8181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910942433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2910942433
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3158732133
Short name T224
Test name
Test status
Simulation time 272837632124 ps
CPU time 642.31 seconds
Started Jun 07 07:52:01 PM PDT 24
Finished Jun 07 08:02:45 PM PDT 24
Peak memory 255900 kb
Host smart-dd00479f-94c0-456b-9f58-52af613fa5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158732133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3158732133
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1448918674
Short name T20
Test name
Test status
Simulation time 44861221376 ps
CPU time 56.19 seconds
Started Jun 07 07:54:47 PM PDT 24
Finished Jun 07 07:55:45 PM PDT 24
Peak memory 233624 kb
Host smart-04e3d6bc-70c0-40da-8fcd-3eeb8999933a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448918674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1448918674
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.291978369
Short name T173
Test name
Test status
Simulation time 2013014859 ps
CPU time 14.77 seconds
Started Jun 07 07:44:23 PM PDT 24
Finished Jun 07 07:44:39 PM PDT 24
Peak memory 215420 kb
Host smart-0a0ab48d-495d-4e53-8e87-a06923e875da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291978369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.291978369
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.4278405929
Short name T281
Test name
Test status
Simulation time 139084142237 ps
CPU time 336.56 seconds
Started Jun 07 07:54:52 PM PDT 24
Finished Jun 07 08:00:30 PM PDT 24
Peak memory 266488 kb
Host smart-f0fa6990-f93f-42ff-a802-9eebdd610660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278405929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.4278405929
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.4028449265
Short name T50
Test name
Test status
Simulation time 48012858136 ps
CPU time 84.53 seconds
Started Jun 07 07:51:16 PM PDT 24
Finished Jun 07 07:52:42 PM PDT 24
Peak memory 257880 kb
Host smart-2841cf8b-bcee-4edc-a494-3a010631279e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028449265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.4028449265
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.329471440
Short name T833
Test name
Test status
Simulation time 13870442160 ps
CPU time 83.31 seconds
Started Jun 07 07:52:12 PM PDT 24
Finished Jun 07 07:53:38 PM PDT 24
Peak memory 261392 kb
Host smart-fcc6d7da-9392-4f4e-9551-f1ce2a30c923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329471440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.329471440
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3530190773
Short name T265
Test name
Test status
Simulation time 10915265531 ps
CPU time 61.33 seconds
Started Jun 07 07:54:59 PM PDT 24
Finished Jun 07 07:56:02 PM PDT 24
Peak memory 256936 kb
Host smart-9f298e31-e8ca-4a9b-88b9-ec20eee6c116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530190773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3530190773
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3982956834
Short name T182
Test name
Test status
Simulation time 224590985 ps
CPU time 2.63 seconds
Started Jun 07 07:50:18 PM PDT 24
Finished Jun 07 07:50:23 PM PDT 24
Peak memory 225300 kb
Host smart-9b990185-cc93-4a34-885b-0c5ba2b9df67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982956834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3982956834
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1061124733
Short name T105
Test name
Test status
Simulation time 711687409 ps
CPU time 4.16 seconds
Started Jun 07 07:44:09 PM PDT 24
Finished Jun 07 07:44:15 PM PDT 24
Peak memory 215528 kb
Host smart-af98702f-0ca5-46c0-8889-83ec5c968932
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061124733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
061124733
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1993228713
Short name T997
Test name
Test status
Simulation time 357198557 ps
CPU time 12.01 seconds
Started Jun 07 07:44:14 PM PDT 24
Finished Jun 07 07:44:27 PM PDT 24
Peak memory 215348 kb
Host smart-90899585-ba27-401b-b22d-a70b5ea6b0af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993228713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1993228713
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3920243953
Short name T304
Test name
Test status
Simulation time 1824444026 ps
CPU time 11.28 seconds
Started Jun 07 07:49:52 PM PDT 24
Finished Jun 07 07:50:05 PM PDT 24
Peak memory 225376 kb
Host smart-9d34b44d-f01c-4f92-b8b7-ef7f3c5524de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920243953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3920243953
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3909045669
Short name T378
Test name
Test status
Simulation time 36160007667 ps
CPU time 246.98 seconds
Started Jun 07 07:52:00 PM PDT 24
Finished Jun 07 07:56:08 PM PDT 24
Peak memory 255908 kb
Host smart-a05bd69d-ad66-4531-a4af-9549b220cdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909045669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3909045669
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.895604904
Short name T282
Test name
Test status
Simulation time 19844505927 ps
CPU time 113.01 seconds
Started Jun 07 07:53:20 PM PDT 24
Finished Jun 07 07:55:15 PM PDT 24
Peak memory 258072 kb
Host smart-7381d94a-e4a0-47fd-b16d-bd88108f8938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895604904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.895604904
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.4199355305
Short name T285
Test name
Test status
Simulation time 10695305866 ps
CPU time 226.11 seconds
Started Jun 07 07:54:50 PM PDT 24
Finished Jun 07 07:58:37 PM PDT 24
Peak memory 272784 kb
Host smart-04008763-be42-4da5-b688-5115c8d58fa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199355305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.4199355305
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3151591433
Short name T197
Test name
Test status
Simulation time 6653854919 ps
CPU time 72.89 seconds
Started Jun 07 07:55:44 PM PDT 24
Finished Jun 07 07:56:59 PM PDT 24
Peak memory 253828 kb
Host smart-d8cc1a92-6d94-4b6b-9ade-1cddd4004a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151591433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3151591433
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1259589924
Short name T108
Test name
Test status
Simulation time 2023298142 ps
CPU time 22.84 seconds
Started Jun 07 07:43:46 PM PDT 24
Finished Jun 07 07:44:11 PM PDT 24
Peak memory 215416 kb
Host smart-ba15cd79-aa0f-4bed-b1f2-922f40b41f87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259589924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1259589924
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3428003152
Short name T172
Test name
Test status
Simulation time 688474584 ps
CPU time 4.29 seconds
Started Jun 07 07:44:18 PM PDT 24
Finished Jun 07 07:44:24 PM PDT 24
Peak memory 215436 kb
Host smart-21e6f987-64ec-434e-a263-8b9c09ec453d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428003152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3428003152
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3218163960
Short name T292
Test name
Test status
Simulation time 12338565854 ps
CPU time 194.08 seconds
Started Jun 07 07:51:18 PM PDT 24
Finished Jun 07 07:54:34 PM PDT 24
Peak memory 258328 kb
Host smart-3904c138-d347-43c3-89df-53d2bdd26c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218163960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3218163960
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1487254284
Short name T131
Test name
Test status
Simulation time 122350290525 ps
CPU time 363 seconds
Started Jun 07 07:51:20 PM PDT 24
Finished Jun 07 07:57:25 PM PDT 24
Peak memory 267520 kb
Host smart-3f46897d-2279-4186-b9ff-c6fce6964167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487254284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1487254284
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.654724055
Short name T421
Test name
Test status
Simulation time 6531040200 ps
CPU time 82.65 seconds
Started Jun 07 07:51:21 PM PDT 24
Finished Jun 07 07:52:46 PM PDT 24
Peak memory 256676 kb
Host smart-8931bc74-884d-4133-8d00-9c78dd164fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654724055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.654724055
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3542558667
Short name T237
Test name
Test status
Simulation time 8659392670 ps
CPU time 64.82 seconds
Started Jun 07 07:51:37 PM PDT 24
Finished Jun 07 07:52:43 PM PDT 24
Peak memory 258240 kb
Host smart-234fb1ce-d098-42cf-8542-87193ebca7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542558667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3542558667
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1691466744
Short name T137
Test name
Test status
Simulation time 2104878853 ps
CPU time 21.71 seconds
Started Jun 07 07:51:46 PM PDT 24
Finished Jun 07 07:52:09 PM PDT 24
Peak memory 250844 kb
Host smart-eff0dfff-21b0-4ce4-874e-261823476d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691466744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1691466744
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1982032300
Short name T132
Test name
Test status
Simulation time 27958936427 ps
CPU time 353 seconds
Started Jun 07 07:52:10 PM PDT 24
Finished Jun 07 07:58:05 PM PDT 24
Peak memory 267396 kb
Host smart-95edb0c8-7f52-44fb-aa05-c2ecb55b50e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982032300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1982032300
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3608446325
Short name T927
Test name
Test status
Simulation time 102475722 ps
CPU time 2.47 seconds
Started Jun 07 07:53:20 PM PDT 24
Finished Jun 07 07:53:24 PM PDT 24
Peak memory 225344 kb
Host smart-9854fef0-32f4-4b4d-bca3-1d3a6e36a924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608446325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3608446325
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2925507516
Short name T279
Test name
Test status
Simulation time 76997619730 ps
CPU time 591.19 seconds
Started Jun 07 07:53:31 PM PDT 24
Finished Jun 07 08:03:26 PM PDT 24
Peak memory 265908 kb
Host smart-1ef0341c-6d7e-4a25-a8f3-67b4b3a77c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925507516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2925507516
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.881403670
Short name T321
Test name
Test status
Simulation time 7856295265 ps
CPU time 90.53 seconds
Started Jun 07 07:53:32 PM PDT 24
Finished Jun 07 07:55:07 PM PDT 24
Peak memory 250256 kb
Host smart-04daddb9-2e1a-4340-b79d-74daf4895e48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881403670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.881403670
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2986739655
Short name T268
Test name
Test status
Simulation time 852238851 ps
CPU time 11.08 seconds
Started Jun 07 07:51:45 PM PDT 24
Finished Jun 07 07:51:57 PM PDT 24
Peak memory 225336 kb
Host smart-a570d53b-59a7-491e-9a5f-1a6d2fb5ed16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986739655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2986739655
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2091311732
Short name T89
Test name
Test status
Simulation time 42899279 ps
CPU time 1.42 seconds
Started Jun 07 07:43:44 PM PDT 24
Finished Jun 07 07:43:46 PM PDT 24
Peak memory 207064 kb
Host smart-5af7a818-2d90-41a9-ac4e-a3e612e98729
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091311732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2091311732
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2511844091
Short name T30
Test name
Test status
Simulation time 43776552166 ps
CPU time 423.81 seconds
Started Jun 07 07:51:12 PM PDT 24
Finished Jun 07 07:58:19 PM PDT 24
Peak memory 266484 kb
Host smart-a4e2e8b0-4d53-4309-8ce8-baa456c0162c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511844091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2511844091
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_upload.249952106
Short name T97
Test name
Test status
Simulation time 27733690156 ps
CPU time 9.67 seconds
Started Jun 07 07:51:19 PM PDT 24
Finished Jun 07 07:51:31 PM PDT 24
Peak memory 233676 kb
Host smart-04c9a560-3113-4319-ace5-3c8241400992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249952106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.249952106
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1829129480
Short name T1080
Test name
Test status
Simulation time 2685603105 ps
CPU time 17.16 seconds
Started Jun 07 07:43:54 PM PDT 24
Finished Jun 07 07:44:13 PM PDT 24
Peak memory 215356 kb
Host smart-2ab51a3a-0587-42df-9616-55462303fa9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829129480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1829129480
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4066980722
Short name T1025
Test name
Test status
Simulation time 2526797718 ps
CPU time 13.48 seconds
Started Jun 07 07:43:44 PM PDT 24
Finished Jun 07 07:43:59 PM PDT 24
Peak memory 207156 kb
Host smart-eb2344a7-8886-4404-8087-ea3b301200f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066980722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4066980722
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1503092204
Short name T1016
Test name
Test status
Simulation time 42038226 ps
CPU time 2.67 seconds
Started Jun 07 07:43:54 PM PDT 24
Finished Jun 07 07:43:59 PM PDT 24
Peak memory 217032 kb
Host smart-e522560c-5bd0-4aca-ad18-da6a55ec1521
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503092204 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1503092204
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4158983420
Short name T1062
Test name
Test status
Simulation time 269597095 ps
CPU time 2.22 seconds
Started Jun 07 07:43:42 PM PDT 24
Finished Jun 07 07:43:46 PM PDT 24
Peak memory 215228 kb
Host smart-d282fcd2-79c9-4891-896f-5a3f29a927fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158983420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
158983420
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2756732257
Short name T970
Test name
Test status
Simulation time 12294987 ps
CPU time 0.76 seconds
Started Jun 07 07:43:46 PM PDT 24
Finished Jun 07 07:43:49 PM PDT 24
Peak memory 203868 kb
Host smart-284b746d-fb14-4677-9b28-66ae352980fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756732257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
756732257
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1150514880
Short name T125
Test name
Test status
Simulation time 103717903 ps
CPU time 1.75 seconds
Started Jun 07 07:43:45 PM PDT 24
Finished Jun 07 07:43:49 PM PDT 24
Peak memory 215372 kb
Host smart-2a514aa1-fc9c-4922-8d8a-1f0aee8097ed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150514880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1150514880
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1066910986
Short name T973
Test name
Test status
Simulation time 30533386 ps
CPU time 0.71 seconds
Started Jun 07 07:43:47 PM PDT 24
Finished Jun 07 07:43:49 PM PDT 24
Peak memory 203756 kb
Host smart-6c436b6d-d63a-43b8-87af-e5c281f81b39
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066910986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1066910986
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.741094119
Short name T1056
Test name
Test status
Simulation time 27830723 ps
CPU time 1.7 seconds
Started Jun 07 07:43:54 PM PDT 24
Finished Jun 07 07:43:57 PM PDT 24
Peak memory 207176 kb
Host smart-88e265ea-8e27-4be0-aea3-519d4066e1fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741094119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.741094119
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2752074570
Short name T1047
Test name
Test status
Simulation time 72947728 ps
CPU time 2.25 seconds
Started Jun 07 07:43:50 PM PDT 24
Finished Jun 07 07:43:54 PM PDT 24
Peak memory 215592 kb
Host smart-ff5a6807-e6f7-46a0-b369-6214ac696cd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752074570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
752074570
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2203199888
Short name T1046
Test name
Test status
Simulation time 5299284758 ps
CPU time 23.84 seconds
Started Jun 07 07:43:54 PM PDT 24
Finished Jun 07 07:44:21 PM PDT 24
Peak memory 207140 kb
Host smart-123e8023-4309-41df-b0b4-372d97002285
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203199888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2203199888
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2612260136
Short name T115
Test name
Test status
Simulation time 2172708685 ps
CPU time 31.72 seconds
Started Jun 07 07:43:54 PM PDT 24
Finished Jun 07 07:44:28 PM PDT 24
Peak memory 207228 kb
Host smart-20b97db0-5859-4754-b081-8b097b848a7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612260136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2612260136
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3248485561
Short name T87
Test name
Test status
Simulation time 59581519 ps
CPU time 1.23 seconds
Started Jun 07 07:43:53 PM PDT 24
Finished Jun 07 07:43:55 PM PDT 24
Peak memory 207088 kb
Host smart-e9743f73-57e2-495f-9a6f-e2496f13451c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248485561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3248485561
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1341013164
Short name T112
Test name
Test status
Simulation time 243362559 ps
CPU time 4.48 seconds
Started Jun 07 07:43:52 PM PDT 24
Finished Jun 07 07:43:58 PM PDT 24
Peak memory 217568 kb
Host smart-beaae54d-f2a3-45cc-bab6-35987db136a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341013164 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1341013164
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2590126814
Short name T994
Test name
Test status
Simulation time 64096674 ps
CPU time 0.79 seconds
Started Jun 07 07:43:55 PM PDT 24
Finished Jun 07 07:43:58 PM PDT 24
Peak memory 203872 kb
Host smart-74e9bf01-b0a6-4ab0-a76b-afbe9fcbd2a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590126814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
590126814
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2587359351
Short name T1077
Test name
Test status
Simulation time 26963318 ps
CPU time 1.73 seconds
Started Jun 07 07:43:54 PM PDT 24
Finished Jun 07 07:43:58 PM PDT 24
Peak memory 215396 kb
Host smart-400936a9-6f54-43af-af91-df3f0bea9cf7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587359351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2587359351
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.175650888
Short name T980
Test name
Test status
Simulation time 15629518 ps
CPU time 0.67 seconds
Started Jun 07 07:43:54 PM PDT 24
Finished Jun 07 07:43:56 PM PDT 24
Peak memory 203788 kb
Host smart-54f5de36-d4f7-4fa2-b286-0d3aa7d7d236
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175650888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.175650888
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2088430140
Short name T1061
Test name
Test status
Simulation time 154668307 ps
CPU time 4.16 seconds
Started Jun 07 07:43:55 PM PDT 24
Finished Jun 07 07:44:02 PM PDT 24
Peak memory 215380 kb
Host smart-6bc90329-1a2d-486d-8136-5f8715c7fdb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088430140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2088430140
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2493374536
Short name T987
Test name
Test status
Simulation time 425561467 ps
CPU time 4.75 seconds
Started Jun 07 07:43:55 PM PDT 24
Finished Jun 07 07:44:02 PM PDT 24
Peak memory 215548 kb
Host smart-b33279ba-5c1e-4d31-8471-5f71a5a19d77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493374536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
493374536
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2317726373
Short name T1054
Test name
Test status
Simulation time 806202050 ps
CPU time 13.57 seconds
Started Jun 07 07:43:55 PM PDT 24
Finished Jun 07 07:44:10 PM PDT 24
Peak memory 215860 kb
Host smart-3d0d47ca-d20a-42b6-9f9c-2ce28d2a821e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317726373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2317726373
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.143413950
Short name T150
Test name
Test status
Simulation time 250753915 ps
CPU time 2.74 seconds
Started Jun 07 07:44:13 PM PDT 24
Finished Jun 07 07:44:17 PM PDT 24
Peak memory 216448 kb
Host smart-b2840ebf-a055-47a5-adbf-fa2deb041025
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143413950 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.143413950
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2367677934
Short name T1029
Test name
Test status
Simulation time 40452920 ps
CPU time 1.35 seconds
Started Jun 07 07:44:14 PM PDT 24
Finished Jun 07 07:44:17 PM PDT 24
Peak memory 215340 kb
Host smart-8424729a-6904-4321-bd66-41ed75c8212e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367677934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2367677934
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3191316161
Short name T990
Test name
Test status
Simulation time 28944854 ps
CPU time 0.72 seconds
Started Jun 07 07:44:10 PM PDT 24
Finished Jun 07 07:44:13 PM PDT 24
Peak memory 203564 kb
Host smart-6d8fca2b-f35f-4e99-8038-bad4834141c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191316161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3191316161
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.227897033
Short name T1004
Test name
Test status
Simulation time 63597652 ps
CPU time 4.21 seconds
Started Jun 07 07:44:12 PM PDT 24
Finished Jun 07 07:44:17 PM PDT 24
Peak memory 215328 kb
Host smart-848ee8c2-54aa-49db-a9d3-2c1fa7c20f84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227897033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.227897033
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3483752522
Short name T151
Test name
Test status
Simulation time 102179973 ps
CPU time 2.66 seconds
Started Jun 07 07:44:18 PM PDT 24
Finished Jun 07 07:44:23 PM PDT 24
Peak memory 217876 kb
Host smart-777b0e95-3cc9-4ce5-89b2-8d6761a1b49a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483752522 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3483752522
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1806532270
Short name T1078
Test name
Test status
Simulation time 57274728 ps
CPU time 2.01 seconds
Started Jun 07 07:44:16 PM PDT 24
Finished Jun 07 07:44:19 PM PDT 24
Peak memory 207056 kb
Host smart-7e285376-edc8-40b1-ad00-19bb03308d6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806532270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1806532270
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2436473033
Short name T962
Test name
Test status
Simulation time 99357850 ps
CPU time 0.72 seconds
Started Jun 07 07:44:12 PM PDT 24
Finished Jun 07 07:44:14 PM PDT 24
Peak memory 204164 kb
Host smart-22702e7d-31f5-4f94-b8ab-4190aa12fbcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436473033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2436473033
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1131338181
Short name T1014
Test name
Test status
Simulation time 206812083 ps
CPU time 1.65 seconds
Started Jun 07 07:44:17 PM PDT 24
Finished Jun 07 07:44:20 PM PDT 24
Peak memory 215372 kb
Host smart-17a4382d-b8fc-4e2d-b8a0-f2239a47ad78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131338181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1131338181
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.457970763
Short name T1005
Test name
Test status
Simulation time 35516083 ps
CPU time 2.15 seconds
Started Jun 07 07:44:12 PM PDT 24
Finished Jun 07 07:44:15 PM PDT 24
Peak memory 215428 kb
Host smart-b5a08209-fd23-42c7-8395-087c82ec2c04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457970763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.457970763
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1269317266
Short name T177
Test name
Test status
Simulation time 1041261620 ps
CPU time 6.35 seconds
Started Jun 07 07:44:12 PM PDT 24
Finished Jun 07 07:44:19 PM PDT 24
Peak memory 217124 kb
Host smart-70d5f61f-c6de-4e4f-9bc7-2abb54f91541
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269317266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1269317266
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2934391573
Short name T1034
Test name
Test status
Simulation time 74227630 ps
CPU time 2.52 seconds
Started Jun 07 07:44:18 PM PDT 24
Finished Jun 07 07:44:23 PM PDT 24
Peak memory 215560 kb
Host smart-f455653d-6dfb-46e8-968c-ae52b087c607
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934391573 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2934391573
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3471517773
Short name T117
Test name
Test status
Simulation time 195883056 ps
CPU time 2.85 seconds
Started Jun 07 07:44:20 PM PDT 24
Finished Jun 07 07:44:24 PM PDT 24
Peak memory 215348 kb
Host smart-a330d880-bdeb-4f8d-8471-eff90ca1040a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471517773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3471517773
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.652371126
Short name T964
Test name
Test status
Simulation time 16624043 ps
CPU time 0.75 seconds
Started Jun 07 07:44:19 PM PDT 24
Finished Jun 07 07:44:22 PM PDT 24
Peak memory 204176 kb
Host smart-3cedfe38-e56d-44b0-a772-a2de05fa17b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652371126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.652371126
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.756258296
Short name T1072
Test name
Test status
Simulation time 276638023 ps
CPU time 3.33 seconds
Started Jun 07 07:44:17 PM PDT 24
Finished Jun 07 07:44:22 PM PDT 24
Peak memory 215408 kb
Host smart-063a7561-a758-46ae-bb2d-24a34be7d72f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756258296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.756258296
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3743157440
Short name T101
Test name
Test status
Simulation time 109876213 ps
CPU time 4.02 seconds
Started Jun 07 07:44:18 PM PDT 24
Finished Jun 07 07:44:24 PM PDT 24
Peak memory 218968 kb
Host smart-da1dc629-25ea-4604-9b1b-4542dc739542
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743157440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3743157440
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2484859591
Short name T110
Test name
Test status
Simulation time 1011168145 ps
CPU time 19.99 seconds
Started Jun 07 07:44:18 PM PDT 24
Finished Jun 07 07:44:40 PM PDT 24
Peak memory 217028 kb
Host smart-72654e2f-e586-41a2-a9cf-b57261b03510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484859591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2484859591
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3427708273
Short name T1010
Test name
Test status
Simulation time 42117651 ps
CPU time 2.73 seconds
Started Jun 07 07:44:16 PM PDT 24
Finished Jun 07 07:44:20 PM PDT 24
Peak memory 217188 kb
Host smart-43e68552-b0e1-4a1d-9b86-f1929914b2ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427708273 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3427708273
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1451848352
Short name T1067
Test name
Test status
Simulation time 128668329 ps
CPU time 1.22 seconds
Started Jun 07 07:44:16 PM PDT 24
Finished Jun 07 07:44:19 PM PDT 24
Peak memory 215368 kb
Host smart-569e7904-be99-4fa1-886d-25da9788acb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451848352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1451848352
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.763548163
Short name T1038
Test name
Test status
Simulation time 95661950 ps
CPU time 0.69 seconds
Started Jun 07 07:44:16 PM PDT 24
Finished Jun 07 07:44:19 PM PDT 24
Peak memory 204120 kb
Host smart-b934426d-cce5-447f-9af6-24b88a7b17ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763548163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.763548163
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3995173576
Short name T993
Test name
Test status
Simulation time 276842534 ps
CPU time 3 seconds
Started Jun 07 07:44:16 PM PDT 24
Finished Jun 07 07:44:21 PM PDT 24
Peak memory 215452 kb
Host smart-b1fcc41a-db9e-4245-9632-805f1e5274fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995173576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3995173576
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1213849506
Short name T1003
Test name
Test status
Simulation time 111188814 ps
CPU time 1.76 seconds
Started Jun 07 07:44:17 PM PDT 24
Finished Jun 07 07:44:20 PM PDT 24
Peak memory 215460 kb
Host smart-9f8cf320-651a-4394-aa39-1bb5d81f233c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213849506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1213849506
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1283042275
Short name T66
Test name
Test status
Simulation time 215682390 ps
CPU time 6.86 seconds
Started Jun 07 07:44:16 PM PDT 24
Finished Jun 07 07:44:25 PM PDT 24
Peak memory 215328 kb
Host smart-2a3fa24d-998e-4917-88c4-9911d096c602
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283042275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1283042275
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1687018881
Short name T984
Test name
Test status
Simulation time 456537161 ps
CPU time 3.53 seconds
Started Jun 07 07:44:23 PM PDT 24
Finished Jun 07 07:44:28 PM PDT 24
Peak memory 217424 kb
Host smart-a8515412-e0a2-4db1-be44-7250acffa968
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687018881 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1687018881
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.522792748
Short name T1064
Test name
Test status
Simulation time 102446531 ps
CPU time 2.52 seconds
Started Jun 07 07:44:16 PM PDT 24
Finished Jun 07 07:44:20 PM PDT 24
Peak memory 215260 kb
Host smart-e9671a36-bfcf-4610-982d-1be6bb7d1d16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522792748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.522792748
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.833821107
Short name T1026
Test name
Test status
Simulation time 23237295 ps
CPU time 0.77 seconds
Started Jun 07 07:44:26 PM PDT 24
Finished Jun 07 07:44:29 PM PDT 24
Peak memory 203944 kb
Host smart-4e742661-e214-4b91-b6a5-a793a3602888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833821107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.833821107
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.924642809
Short name T1030
Test name
Test status
Simulation time 207281787 ps
CPU time 4.29 seconds
Started Jun 07 07:44:16 PM PDT 24
Finished Jun 07 07:44:22 PM PDT 24
Peak memory 215324 kb
Host smart-7a89d57a-47f9-4cdb-9366-ef5d4c5417d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924642809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.924642809
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1875722510
Short name T1081
Test name
Test status
Simulation time 8972838661 ps
CPU time 20.43 seconds
Started Jun 07 07:44:17 PM PDT 24
Finished Jun 07 07:44:39 PM PDT 24
Peak memory 215420 kb
Host smart-0643adae-2769-466e-905d-71f6af8e3076
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875722510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1875722510
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2098157283
Short name T1071
Test name
Test status
Simulation time 173211491 ps
CPU time 1.65 seconds
Started Jun 07 07:44:27 PM PDT 24
Finished Jun 07 07:44:32 PM PDT 24
Peak memory 215516 kb
Host smart-fe73f3a1-10f7-493b-b5d9-18115a5aa0a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098157283 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2098157283
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1849298941
Short name T123
Test name
Test status
Simulation time 77877445 ps
CPU time 1.37 seconds
Started Jun 07 07:44:25 PM PDT 24
Finished Jun 07 07:44:28 PM PDT 24
Peak memory 207084 kb
Host smart-4df09f47-e14f-4913-96c3-50896e6a5e1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849298941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1849298941
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3282053486
Short name T967
Test name
Test status
Simulation time 91035570 ps
CPU time 0.71 seconds
Started Jun 07 07:44:26 PM PDT 24
Finished Jun 07 07:44:28 PM PDT 24
Peak memory 204176 kb
Host smart-576c7591-35f5-414e-81d5-894bb0d9443b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282053486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3282053486
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.976259336
Short name T983
Test name
Test status
Simulation time 432229145 ps
CPU time 3.73 seconds
Started Jun 07 07:44:24 PM PDT 24
Finished Jun 07 07:44:29 PM PDT 24
Peak memory 215404 kb
Host smart-dd774fcd-f73a-48db-9ded-6b3fc6b29421
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976259336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.976259336
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.693434156
Short name T1066
Test name
Test status
Simulation time 48876552 ps
CPU time 3.04 seconds
Started Jun 07 07:44:26 PM PDT 24
Finished Jun 07 07:44:31 PM PDT 24
Peak memory 215616 kb
Host smart-68d1ead6-9b70-4918-80f7-f9ef873ab287
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693434156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.693434156
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2610288713
Short name T998
Test name
Test status
Simulation time 254388673 ps
CPU time 3.87 seconds
Started Jun 07 07:44:28 PM PDT 24
Finished Jun 07 07:44:34 PM PDT 24
Peak memory 218112 kb
Host smart-299639ec-17d8-454b-a3a0-c7476ece35b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610288713 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2610288713
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2206649074
Short name T979
Test name
Test status
Simulation time 21835155 ps
CPU time 1.3 seconds
Started Jun 07 07:44:25 PM PDT 24
Finished Jun 07 07:44:29 PM PDT 24
Peak memory 207152 kb
Host smart-f18937bf-3c25-4c9c-b578-c8bda2cddc9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206649074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2206649074
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1043396473
Short name T966
Test name
Test status
Simulation time 15415593 ps
CPU time 0.77 seconds
Started Jun 07 07:44:24 PM PDT 24
Finished Jun 07 07:44:27 PM PDT 24
Peak memory 204164 kb
Host smart-7e98ea54-53b6-47d4-8f6b-ff89f8d819dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043396473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1043396473
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.687357296
Short name T971
Test name
Test status
Simulation time 425460954 ps
CPU time 1.91 seconds
Started Jun 07 07:44:25 PM PDT 24
Finished Jun 07 07:44:29 PM PDT 24
Peak memory 215444 kb
Host smart-56c167f7-0bfb-4249-ab93-11b8e6e8e77a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687357296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.687357296
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.860591099
Short name T977
Test name
Test status
Simulation time 238161147 ps
CPU time 2.11 seconds
Started Jun 07 07:44:24 PM PDT 24
Finished Jun 07 07:44:28 PM PDT 24
Peak memory 215596 kb
Host smart-db20a195-a515-4a04-86fb-c5cf8afa8861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860591099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.860591099
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1361512449
Short name T1050
Test name
Test status
Simulation time 149304101 ps
CPU time 2.45 seconds
Started Jun 07 07:44:25 PM PDT 24
Finished Jun 07 07:44:29 PM PDT 24
Peak memory 216988 kb
Host smart-4b23100b-c6c8-4bb7-a1d3-450109603d3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361512449 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1361512449
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1280001281
Short name T1021
Test name
Test status
Simulation time 78884188 ps
CPU time 1.41 seconds
Started Jun 07 07:44:23 PM PDT 24
Finished Jun 07 07:44:26 PM PDT 24
Peak memory 207020 kb
Host smart-bd5f109b-cc3b-46f5-9c1a-b9967c89edba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280001281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1280001281
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2970151837
Short name T1033
Test name
Test status
Simulation time 53034070 ps
CPU time 0.76 seconds
Started Jun 07 07:44:25 PM PDT 24
Finished Jun 07 07:44:28 PM PDT 24
Peak memory 204168 kb
Host smart-b45a27d4-bc0e-4516-8cdd-c6f267729bd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970151837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2970151837
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1640546746
Short name T1015
Test name
Test status
Simulation time 496822554 ps
CPU time 3.07 seconds
Started Jun 07 07:44:26 PM PDT 24
Finished Jun 07 07:44:31 PM PDT 24
Peak memory 215444 kb
Host smart-a3536b31-d15c-4830-9a54-b0cb59102597
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640546746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1640546746
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3490025125
Short name T1012
Test name
Test status
Simulation time 152101973 ps
CPU time 4.29 seconds
Started Jun 07 07:44:25 PM PDT 24
Finished Jun 07 07:44:31 PM PDT 24
Peak memory 216508 kb
Host smart-440d3e25-24c4-4459-9c5f-5f91ad5f8a8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490025125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3490025125
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1242844089
Short name T1039
Test name
Test status
Simulation time 1635836357 ps
CPU time 16.31 seconds
Started Jun 07 07:44:24 PM PDT 24
Finished Jun 07 07:44:42 PM PDT 24
Peak memory 215516 kb
Host smart-b3690dd4-63c9-42f9-a608-ea4da70c9852
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242844089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1242844089
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1966228069
Short name T1037
Test name
Test status
Simulation time 99598903 ps
CPU time 3.44 seconds
Started Jun 07 07:44:32 PM PDT 24
Finished Jun 07 07:44:38 PM PDT 24
Peak memory 217360 kb
Host smart-650ddd4c-1405-4184-b575-d7ed23d16f18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966228069 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1966228069
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.345360383
Short name T114
Test name
Test status
Simulation time 95127773 ps
CPU time 2.54 seconds
Started Jun 07 07:44:33 PM PDT 24
Finished Jun 07 07:44:38 PM PDT 24
Peak memory 215360 kb
Host smart-0a503396-c152-498a-8d1a-211834ea11cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345360383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.345360383
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1379830652
Short name T1022
Test name
Test status
Simulation time 48229532 ps
CPU time 0.72 seconds
Started Jun 07 07:44:33 PM PDT 24
Finished Jun 07 07:44:37 PM PDT 24
Peak memory 203820 kb
Host smart-bdae1a22-73ab-4a82-bc5d-68e339e5ef6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379830652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1379830652
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3309059184
Short name T958
Test name
Test status
Simulation time 208106404 ps
CPU time 2.95 seconds
Started Jun 07 07:44:32 PM PDT 24
Finished Jun 07 07:44:38 PM PDT 24
Peak memory 215412 kb
Host smart-0298670a-e7d3-4ab9-b22a-99e36cd9246b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309059184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3309059184
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1711223998
Short name T67
Test name
Test status
Simulation time 172719084 ps
CPU time 4.37 seconds
Started Jun 07 07:44:25 PM PDT 24
Finished Jun 07 07:44:31 PM PDT 24
Peak memory 216528 kb
Host smart-9fa43295-d608-432b-876e-aaddc17a7ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711223998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1711223998
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4285015331
Short name T1079
Test name
Test status
Simulation time 3176457262 ps
CPU time 12.95 seconds
Started Jun 07 07:44:28 PM PDT 24
Finished Jun 07 07:44:43 PM PDT 24
Peak memory 215352 kb
Host smart-f2c5a72b-0f92-44ac-9d0b-8b2f96c7d947
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285015331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4285015331
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.324769757
Short name T972
Test name
Test status
Simulation time 87721599 ps
CPU time 1.81 seconds
Started Jun 07 07:44:33 PM PDT 24
Finished Jun 07 07:44:37 PM PDT 24
Peak memory 215416 kb
Host smart-b11964cd-8084-45c4-89bc-139f29336c3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324769757 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.324769757
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2235627254
Short name T126
Test name
Test status
Simulation time 21446263 ps
CPU time 1.18 seconds
Started Jun 07 07:44:32 PM PDT 24
Finished Jun 07 07:44:36 PM PDT 24
Peak memory 207156 kb
Host smart-8d2a762f-9a7e-4bd2-817d-7dbe74b9b399
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235627254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2235627254
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1970008229
Short name T959
Test name
Test status
Simulation time 124512952 ps
CPU time 0.74 seconds
Started Jun 07 07:44:31 PM PDT 24
Finished Jun 07 07:44:34 PM PDT 24
Peak memory 204144 kb
Host smart-f9b327db-6e9c-4cd8-b6c3-c53e864c751e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970008229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1970008229
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2425213849
Short name T1023
Test name
Test status
Simulation time 225788151 ps
CPU time 1.85 seconds
Started Jun 07 07:44:33 PM PDT 24
Finished Jun 07 07:44:37 PM PDT 24
Peak memory 215372 kb
Host smart-0ba069eb-5196-412b-b3c5-dc931d1d0931
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425213849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2425213849
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.290267595
Short name T1041
Test name
Test status
Simulation time 1943854081 ps
CPU time 4.38 seconds
Started Jun 07 07:44:31 PM PDT 24
Finished Jun 07 07:44:38 PM PDT 24
Peak memory 216552 kb
Host smart-d1c12a97-74f9-40df-888c-718ddb89ac48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290267595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.290267595
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1888930257
Short name T1011
Test name
Test status
Simulation time 415382692 ps
CPU time 8.48 seconds
Started Jun 07 07:44:33 PM PDT 24
Finished Jun 07 07:44:44 PM PDT 24
Peak memory 216276 kb
Host smart-dc7cc380-6f76-49d2-906f-7e7a4dc90353
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888930257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1888930257
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4243515890
Short name T1031
Test name
Test status
Simulation time 9374489192 ps
CPU time 24.84 seconds
Started Jun 07 07:44:02 PM PDT 24
Finished Jun 07 07:44:29 PM PDT 24
Peak memory 207184 kb
Host smart-8225ce45-8815-46d8-84b9-0c4a29a62556
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243515890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.4243515890
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2628783894
Short name T1045
Test name
Test status
Simulation time 191926778 ps
CPU time 12.6 seconds
Started Jun 07 07:44:03 PM PDT 24
Finished Jun 07 07:44:17 PM PDT 24
Peak memory 207052 kb
Host smart-928517e7-aed5-4fde-af39-04328e887174
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628783894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2628783894
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1943023626
Short name T88
Test name
Test status
Simulation time 51256825 ps
CPU time 1.33 seconds
Started Jun 07 07:44:05 PM PDT 24
Finished Jun 07 07:44:09 PM PDT 24
Peak memory 207100 kb
Host smart-dbeba499-1ede-4c9c-9c62-6924443f4f0f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943023626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1943023626
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1953067336
Short name T111
Test name
Test status
Simulation time 173339602 ps
CPU time 2.55 seconds
Started Jun 07 07:44:06 PM PDT 24
Finished Jun 07 07:44:10 PM PDT 24
Peak memory 216480 kb
Host smart-0b5080fd-daf3-4294-8f01-39d8667695fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953067336 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1953067336
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.799188259
Short name T127
Test name
Test status
Simulation time 99174154 ps
CPU time 2.43 seconds
Started Jun 07 07:44:06 PM PDT 24
Finished Jun 07 07:44:10 PM PDT 24
Peak memory 215352 kb
Host smart-826cd1f0-77de-46ad-ae92-163c31426ea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799188259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.799188259
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1404218734
Short name T1020
Test name
Test status
Simulation time 14348227 ps
CPU time 0.8 seconds
Started Jun 07 07:44:06 PM PDT 24
Finished Jun 07 07:44:09 PM PDT 24
Peak memory 203828 kb
Host smart-c27062ac-61fb-47df-9faf-b75636a065cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404218734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
404218734
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3968038650
Short name T119
Test name
Test status
Simulation time 174779940 ps
CPU time 1.92 seconds
Started Jun 07 07:44:02 PM PDT 24
Finished Jun 07 07:44:06 PM PDT 24
Peak memory 215388 kb
Host smart-e775c9b3-4823-4b1f-85ce-65e3ae3f80ae
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968038650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3968038650
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1467328549
Short name T1048
Test name
Test status
Simulation time 13578343 ps
CPU time 0.69 seconds
Started Jun 07 07:44:04 PM PDT 24
Finished Jun 07 07:44:07 PM PDT 24
Peak memory 203792 kb
Host smart-1280dc62-31b4-4369-8113-5326818b9404
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467328549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1467328549
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2910649317
Short name T985
Test name
Test status
Simulation time 411501675 ps
CPU time 2.2 seconds
Started Jun 07 07:44:01 PM PDT 24
Finished Jun 07 07:44:05 PM PDT 24
Peak memory 215380 kb
Host smart-8315c0b4-de07-4741-9e18-2a4d8b4a82cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910649317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2910649317
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.344943476
Short name T1042
Test name
Test status
Simulation time 1218254307 ps
CPU time 4.45 seconds
Started Jun 07 07:44:01 PM PDT 24
Finished Jun 07 07:44:07 PM PDT 24
Peak memory 215504 kb
Host smart-676fbb02-dec4-4b26-be20-8fa8a285f7df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344943476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.344943476
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4241608731
Short name T992
Test name
Test status
Simulation time 2041280908 ps
CPU time 18.8 seconds
Started Jun 07 07:44:07 PM PDT 24
Finished Jun 07 07:44:27 PM PDT 24
Peak memory 215416 kb
Host smart-a69576b3-6b01-4223-9b6b-d28e6554f5b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241608731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.4241608731
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3124711526
Short name T968
Test name
Test status
Simulation time 14291760 ps
CPU time 0.76 seconds
Started Jun 07 07:44:31 PM PDT 24
Finished Jun 07 07:44:35 PM PDT 24
Peak memory 203844 kb
Host smart-0b9c8c6f-a6da-4152-9c7d-0234aadc3146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124711526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3124711526
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3093141941
Short name T965
Test name
Test status
Simulation time 30424341 ps
CPU time 0.77 seconds
Started Jun 07 07:44:33 PM PDT 24
Finished Jun 07 07:44:37 PM PDT 24
Peak memory 204176 kb
Host smart-996a7bce-5c9a-42fa-8f39-10c3bad8316e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093141941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3093141941
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.620995057
Short name T1053
Test name
Test status
Simulation time 52639302 ps
CPU time 0.72 seconds
Started Jun 07 07:44:30 PM PDT 24
Finished Jun 07 07:44:33 PM PDT 24
Peak memory 203864 kb
Host smart-1f449cc3-64d3-46f8-8374-0366293a5abd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620995057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.620995057
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2721951564
Short name T982
Test name
Test status
Simulation time 15652280 ps
CPU time 0.76 seconds
Started Jun 07 07:44:33 PM PDT 24
Finished Jun 07 07:44:36 PM PDT 24
Peak memory 204168 kb
Host smart-84eb660b-ba6e-4281-a903-d35060098ecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721951564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2721951564
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.950112817
Short name T1075
Test name
Test status
Simulation time 32096267 ps
CPU time 0.74 seconds
Started Jun 07 07:44:31 PM PDT 24
Finished Jun 07 07:44:34 PM PDT 24
Peak memory 204184 kb
Host smart-458771e3-8a01-4f9d-8479-a8598efa7d79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950112817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.950112817
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2801770542
Short name T1060
Test name
Test status
Simulation time 42989731 ps
CPU time 0.76 seconds
Started Jun 07 07:44:34 PM PDT 24
Finished Jun 07 07:44:37 PM PDT 24
Peak memory 204112 kb
Host smart-4de24b0b-15e8-4cbd-879d-c602b4554093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801770542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2801770542
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3310045577
Short name T1019
Test name
Test status
Simulation time 19872159 ps
CPU time 0.71 seconds
Started Jun 07 07:44:34 PM PDT 24
Finished Jun 07 07:44:38 PM PDT 24
Peak memory 204136 kb
Host smart-0350f0da-a78d-40e6-8cd8-e93e7001b222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310045577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3310045577
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3685706629
Short name T1043
Test name
Test status
Simulation time 159509329 ps
CPU time 0.76 seconds
Started Jun 07 07:44:34 PM PDT 24
Finished Jun 07 07:44:38 PM PDT 24
Peak memory 204112 kb
Host smart-af650445-2b39-49b5-86e7-a39bb08af8cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685706629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3685706629
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.948842987
Short name T955
Test name
Test status
Simulation time 34574568 ps
CPU time 0.68 seconds
Started Jun 07 07:44:30 PM PDT 24
Finished Jun 07 07:44:32 PM PDT 24
Peak memory 203740 kb
Host smart-1c7cf98f-c1d5-42eb-9d9a-7a53d07f3fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948842987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.948842987
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2004401679
Short name T1058
Test name
Test status
Simulation time 14412316 ps
CPU time 0.72 seconds
Started Jun 07 07:44:31 PM PDT 24
Finished Jun 07 07:44:33 PM PDT 24
Peak memory 204172 kb
Host smart-014f22e5-13d7-4d99-83d9-642739f0325a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004401679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2004401679
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4063552587
Short name T121
Test name
Test status
Simulation time 3380185999 ps
CPU time 24.35 seconds
Started Jun 07 07:44:02 PM PDT 24
Finished Jun 07 07:44:29 PM PDT 24
Peak memory 215412 kb
Host smart-5ca61430-3d3d-4f39-8e97-c86f81868afa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063552587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.4063552587
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1486686974
Short name T1024
Test name
Test status
Simulation time 395446234 ps
CPU time 11.82 seconds
Started Jun 07 07:44:06 PM PDT 24
Finished Jun 07 07:44:20 PM PDT 24
Peak memory 207168 kb
Host smart-08d18bf5-a465-49a5-a001-8a9a6679f0d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486686974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1486686974
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1185906169
Short name T1001
Test name
Test status
Simulation time 62976126 ps
CPU time 1.24 seconds
Started Jun 07 07:44:03 PM PDT 24
Finished Jun 07 07:44:07 PM PDT 24
Peak memory 216372 kb
Host smart-58c1370d-6d42-4874-b1a4-4e1aa5902067
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185906169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1185906169
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.230055215
Short name T98
Test name
Test status
Simulation time 29165361 ps
CPU time 2.04 seconds
Started Jun 07 07:44:04 PM PDT 24
Finished Jun 07 07:44:08 PM PDT 24
Peak memory 216496 kb
Host smart-d522c4ed-2d81-4609-81db-b1f4f3da9835
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230055215 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.230055215
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2815066868
Short name T1076
Test name
Test status
Simulation time 68805051 ps
CPU time 2.34 seconds
Started Jun 07 07:44:01 PM PDT 24
Finished Jun 07 07:44:05 PM PDT 24
Peak memory 207072 kb
Host smart-ebf39c73-2e22-4f3e-a66a-f3e4442660ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815066868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
815066868
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4213249374
Short name T1007
Test name
Test status
Simulation time 35273005 ps
CPU time 0.81 seconds
Started Jun 07 07:44:01 PM PDT 24
Finished Jun 07 07:44:04 PM PDT 24
Peak memory 203848 kb
Host smart-da70c419-8e0e-4fbb-90ca-efdf8063c647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213249374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4
213249374
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1776058383
Short name T116
Test name
Test status
Simulation time 112667289 ps
CPU time 1.36 seconds
Started Jun 07 07:44:04 PM PDT 24
Finished Jun 07 07:44:08 PM PDT 24
Peak memory 215284 kb
Host smart-0b532e23-f1da-47fd-9f06-b99f79e7f732
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776058383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1776058383
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.489411414
Short name T1000
Test name
Test status
Simulation time 33641253 ps
CPU time 0.68 seconds
Started Jun 07 07:44:02 PM PDT 24
Finished Jun 07 07:44:05 PM PDT 24
Peak memory 203624 kb
Host smart-039f7019-4d0f-4d31-a46c-64e77a67f11d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489411414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.489411414
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1280448633
Short name T135
Test name
Test status
Simulation time 159698536 ps
CPU time 2.05 seconds
Started Jun 07 07:44:04 PM PDT 24
Finished Jun 07 07:44:09 PM PDT 24
Peak memory 215372 kb
Host smart-9099901a-ef56-4862-80b0-8c26d14a2a39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280448633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1280448633
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2316912363
Short name T104
Test name
Test status
Simulation time 92659415 ps
CPU time 3.28 seconds
Started Jun 07 07:44:04 PM PDT 24
Finished Jun 07 07:44:10 PM PDT 24
Peak memory 215628 kb
Host smart-66b754a1-8079-430a-ac43-598fc02a5df5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316912363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
316912363
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1427886634
Short name T175
Test name
Test status
Simulation time 808246571 ps
CPU time 14.21 seconds
Started Jun 07 07:44:01 PM PDT 24
Finished Jun 07 07:44:16 PM PDT 24
Peak memory 215352 kb
Host smart-628bb49a-82ac-4cf4-8f8f-a060d66ab532
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427886634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1427886634
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1564166927
Short name T1055
Test name
Test status
Simulation time 17379549 ps
CPU time 0.79 seconds
Started Jun 07 07:44:33 PM PDT 24
Finished Jun 07 07:44:36 PM PDT 24
Peak memory 204176 kb
Host smart-92aba349-3e50-4b4d-8a23-2f4c1fa45431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564166927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1564166927
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.615320185
Short name T1009
Test name
Test status
Simulation time 22010885 ps
CPU time 0.71 seconds
Started Jun 07 07:44:31 PM PDT 24
Finished Jun 07 07:44:34 PM PDT 24
Peak memory 203828 kb
Host smart-5e342ec5-698c-4c64-957a-04632537cb69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615320185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.615320185
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3134640364
Short name T1052
Test name
Test status
Simulation time 44766864 ps
CPU time 0.71 seconds
Started Jun 07 07:44:35 PM PDT 24
Finished Jun 07 07:44:38 PM PDT 24
Peak memory 203832 kb
Host smart-872f6096-ca4c-4645-b549-18f241f25409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134640364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3134640364
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.398085971
Short name T1049
Test name
Test status
Simulation time 47525796 ps
CPU time 0.69 seconds
Started Jun 07 07:44:34 PM PDT 24
Finished Jun 07 07:44:37 PM PDT 24
Peak memory 204136 kb
Host smart-46d6005b-c105-4a07-a4bb-23682bbbf8d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398085971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.398085971
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1953024846
Short name T976
Test name
Test status
Simulation time 14425708 ps
CPU time 0.83 seconds
Started Jun 07 07:44:33 PM PDT 24
Finished Jun 07 07:44:37 PM PDT 24
Peak memory 203840 kb
Host smart-75b985c4-8cb6-4b43-9dd8-2d9ca829e42f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953024846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1953024846
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3136022879
Short name T981
Test name
Test status
Simulation time 12142593 ps
CPU time 0.75 seconds
Started Jun 07 07:44:31 PM PDT 24
Finished Jun 07 07:44:34 PM PDT 24
Peak memory 203864 kb
Host smart-f18a0381-3b74-459d-8133-2db8a4c58f0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136022879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3136022879
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1334774980
Short name T1057
Test name
Test status
Simulation time 17909207 ps
CPU time 0.78 seconds
Started Jun 07 07:44:32 PM PDT 24
Finished Jun 07 07:44:35 PM PDT 24
Peak memory 204128 kb
Host smart-f90b6782-9d24-4ea2-a7bd-b0a08fbb2549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334774980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1334774980
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.925464293
Short name T1006
Test name
Test status
Simulation time 35380418 ps
CPU time 0.77 seconds
Started Jun 07 07:44:32 PM PDT 24
Finished Jun 07 07:44:35 PM PDT 24
Peak memory 204136 kb
Host smart-6f2daa4d-1a3f-4342-bebb-225bf28d151d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925464293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.925464293
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3452464851
Short name T1018
Test name
Test status
Simulation time 49555660 ps
CPU time 0.83 seconds
Started Jun 07 07:44:33 PM PDT 24
Finished Jun 07 07:44:37 PM PDT 24
Peak memory 203864 kb
Host smart-91c2bf53-a2ee-4e20-87ba-b7d0c6f07a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452464851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3452464851
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1945674734
Short name T1073
Test name
Test status
Simulation time 56432187 ps
CPU time 0.74 seconds
Started Jun 07 07:44:31 PM PDT 24
Finished Jun 07 07:44:34 PM PDT 24
Peak memory 203816 kb
Host smart-fb2df324-a9c7-447e-a7a3-67cd80281100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945674734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1945674734
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2381039309
Short name T113
Test name
Test status
Simulation time 621416900 ps
CPU time 15.16 seconds
Started Jun 07 07:44:04 PM PDT 24
Finished Jun 07 07:44:21 PM PDT 24
Peak memory 215296 kb
Host smart-9fc6f277-28d6-4be7-980e-f80d6dd8d96d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381039309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2381039309
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.862007493
Short name T124
Test name
Test status
Simulation time 546730207 ps
CPU time 35.35 seconds
Started Jun 07 07:44:04 PM PDT 24
Finished Jun 07 07:44:41 PM PDT 24
Peak memory 207172 kb
Host smart-30093a4c-fd51-4229-8edb-07a2e9e29d2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862007493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.862007493
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2021617911
Short name T90
Test name
Test status
Simulation time 93709146 ps
CPU time 1.36 seconds
Started Jun 07 07:44:06 PM PDT 24
Finished Jun 07 07:44:09 PM PDT 24
Peak memory 207084 kb
Host smart-a37119e2-aa62-4dd5-9583-439b48e6b313
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021617911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2021617911
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1917957133
Short name T1002
Test name
Test status
Simulation time 54186594 ps
CPU time 4.02 seconds
Started Jun 07 07:44:03 PM PDT 24
Finished Jun 07 07:44:09 PM PDT 24
Peak memory 218336 kb
Host smart-15942d1e-cda4-4322-8826-014546cf44b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917957133 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1917957133
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1264890974
Short name T1068
Test name
Test status
Simulation time 19477192 ps
CPU time 1.25 seconds
Started Jun 07 07:44:02 PM PDT 24
Finished Jun 07 07:44:05 PM PDT 24
Peak memory 207160 kb
Host smart-5f4a0437-4471-41b5-b832-cafa10e83e8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264890974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
264890974
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1341188648
Short name T989
Test name
Test status
Simulation time 46355702 ps
CPU time 0.71 seconds
Started Jun 07 07:44:06 PM PDT 24
Finished Jun 07 07:44:09 PM PDT 24
Peak memory 203816 kb
Host smart-9b016d32-778b-43bf-a32d-cc896f891fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341188648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
341188648
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4149379241
Short name T1027
Test name
Test status
Simulation time 67429692 ps
CPU time 2.34 seconds
Started Jun 07 07:44:04 PM PDT 24
Finished Jun 07 07:44:09 PM PDT 24
Peak memory 215364 kb
Host smart-32d81d21-199c-458c-8efc-b5e0884ed570
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149379241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4149379241
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.193564400
Short name T956
Test name
Test status
Simulation time 26732421 ps
CPU time 0.66 seconds
Started Jun 07 07:44:07 PM PDT 24
Finished Jun 07 07:44:09 PM PDT 24
Peak memory 203808 kb
Host smart-762ef6c3-ba86-4d6b-90d1-7fbfcd4df67d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193564400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.193564400
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2714214978
Short name T986
Test name
Test status
Simulation time 64803574 ps
CPU time 4.04 seconds
Started Jun 07 07:44:04 PM PDT 24
Finished Jun 07 07:44:10 PM PDT 24
Peak memory 215388 kb
Host smart-f004f7cc-773d-4ab4-8b2b-e087cf369611
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714214978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2714214978
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.761788310
Short name T1070
Test name
Test status
Simulation time 94228307 ps
CPU time 1.53 seconds
Started Jun 07 07:44:05 PM PDT 24
Finished Jun 07 07:44:09 PM PDT 24
Peak memory 215536 kb
Host smart-ac57d8cb-6284-4180-be45-454fa84cb257
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761788310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.761788310
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1160991707
Short name T174
Test name
Test status
Simulation time 565065267 ps
CPU time 7.43 seconds
Started Jun 07 07:44:05 PM PDT 24
Finished Jun 07 07:44:15 PM PDT 24
Peak memory 215416 kb
Host smart-b7bc9598-1373-4b2a-ade3-8c0992741784
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160991707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1160991707
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2318213124
Short name T978
Test name
Test status
Simulation time 11983713 ps
CPU time 0.76 seconds
Started Jun 07 07:44:31 PM PDT 24
Finished Jun 07 07:44:34 PM PDT 24
Peak memory 203856 kb
Host smart-e2546344-8768-4edb-9fcd-821aca291073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318213124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2318213124
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4004118193
Short name T991
Test name
Test status
Simulation time 15005080 ps
CPU time 0.78 seconds
Started Jun 07 07:44:33 PM PDT 24
Finished Jun 07 07:44:36 PM PDT 24
Peak memory 203860 kb
Host smart-c3c1674d-f466-4237-aa65-ed445d784c8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004118193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
4004118193
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1254186734
Short name T1044
Test name
Test status
Simulation time 15688362 ps
CPU time 0.77 seconds
Started Jun 07 07:44:35 PM PDT 24
Finished Jun 07 07:44:38 PM PDT 24
Peak memory 203812 kb
Host smart-ed674963-7a64-4502-8c98-1fecbe38780d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254186734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1254186734
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1055128811
Short name T1065
Test name
Test status
Simulation time 34490687 ps
CPU time 0.71 seconds
Started Jun 07 07:44:38 PM PDT 24
Finished Jun 07 07:44:40 PM PDT 24
Peak memory 203824 kb
Host smart-068ea42f-85ea-431b-926c-b00c8d82d226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055128811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1055128811
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1614759226
Short name T1032
Test name
Test status
Simulation time 17089971 ps
CPU time 0.76 seconds
Started Jun 07 07:44:43 PM PDT 24
Finished Jun 07 07:44:46 PM PDT 24
Peak memory 203880 kb
Host smart-3c16d1fb-c2dc-4fee-9ec9-aaff987c0f51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614759226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1614759226
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.658938719
Short name T1035
Test name
Test status
Simulation time 70565003 ps
CPU time 0.77 seconds
Started Jun 07 07:44:40 PM PDT 24
Finished Jun 07 07:44:42 PM PDT 24
Peak memory 204156 kb
Host smart-89017843-dbcd-45e2-b5d8-9fd042e15606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658938719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.658938719
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4045302630
Short name T974
Test name
Test status
Simulation time 91575860 ps
CPU time 0.73 seconds
Started Jun 07 07:44:42 PM PDT 24
Finished Jun 07 07:44:44 PM PDT 24
Peak memory 203864 kb
Host smart-5e8185c2-d016-417b-9e81-c34c65f19d29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045302630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4045302630
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.193817882
Short name T975
Test name
Test status
Simulation time 61464373 ps
CPU time 0.75 seconds
Started Jun 07 07:44:39 PM PDT 24
Finished Jun 07 07:44:41 PM PDT 24
Peak memory 203832 kb
Host smart-2eb5f9b8-0bb6-4065-9337-2a92379213b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193817882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.193817882
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2842194521
Short name T961
Test name
Test status
Simulation time 40228451 ps
CPU time 0.67 seconds
Started Jun 07 07:44:39 PM PDT 24
Finished Jun 07 07:44:41 PM PDT 24
Peak memory 203876 kb
Host smart-0a375d75-39ad-41b9-872d-5dd2f014850b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842194521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2842194521
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.690005453
Short name T1051
Test name
Test status
Simulation time 74498251 ps
CPU time 0.69 seconds
Started Jun 07 07:44:41 PM PDT 24
Finished Jun 07 07:44:43 PM PDT 24
Peak memory 204168 kb
Host smart-077f2091-7ec3-4c65-9d9d-2ab6dac00b8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690005453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.690005453
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3490574404
Short name T1036
Test name
Test status
Simulation time 53489065 ps
CPU time 3.65 seconds
Started Jun 07 07:44:14 PM PDT 24
Finished Jun 07 07:44:19 PM PDT 24
Peak memory 215504 kb
Host smart-c50ad403-5c20-47be-87df-cc092be32811
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490574404 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3490574404
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3625320882
Short name T1040
Test name
Test status
Simulation time 36654427 ps
CPU time 2.48 seconds
Started Jun 07 07:44:02 PM PDT 24
Finished Jun 07 07:44:07 PM PDT 24
Peak memory 215280 kb
Host smart-20d1b73c-60af-4747-a2e3-5ad071de559c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625320882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
625320882
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3599833045
Short name T1017
Test name
Test status
Simulation time 17615940 ps
CPU time 0.71 seconds
Started Jun 07 07:44:06 PM PDT 24
Finished Jun 07 07:44:09 PM PDT 24
Peak memory 203860 kb
Host smart-60927076-4cde-4c5f-9f7d-7cb123438f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599833045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
599833045
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3293825279
Short name T963
Test name
Test status
Simulation time 120730049 ps
CPU time 3.76 seconds
Started Jun 07 07:44:14 PM PDT 24
Finished Jun 07 07:44:19 PM PDT 24
Peak memory 215360 kb
Host smart-a0e5032d-cabb-4fcf-a8b8-04ff05773e9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293825279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3293825279
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.346851074
Short name T999
Test name
Test status
Simulation time 338015522 ps
CPU time 2.28 seconds
Started Jun 07 07:44:02 PM PDT 24
Finished Jun 07 07:44:06 PM PDT 24
Peak memory 215440 kb
Host smart-f3cd1362-9742-43d4-be12-d00fd808cf25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346851074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.346851074
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3647883085
Short name T1069
Test name
Test status
Simulation time 1030346219 ps
CPU time 24.59 seconds
Started Jun 07 07:44:02 PM PDT 24
Finished Jun 07 07:44:29 PM PDT 24
Peak memory 215896 kb
Host smart-0ff4e57a-2278-422a-9ae4-7609653c57c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647883085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3647883085
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4251440286
Short name T1008
Test name
Test status
Simulation time 166689726 ps
CPU time 2.53 seconds
Started Jun 07 07:44:13 PM PDT 24
Finished Jun 07 07:44:17 PM PDT 24
Peak memory 217116 kb
Host smart-abcd40b9-e1c3-4ad0-b751-819b451ca7d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251440286 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4251440286
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1267364944
Short name T120
Test name
Test status
Simulation time 24173333 ps
CPU time 1.52 seconds
Started Jun 07 07:44:10 PM PDT 24
Finished Jun 07 07:44:13 PM PDT 24
Peak memory 215340 kb
Host smart-299a084d-4a73-46ba-b273-cb0f47a8047b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267364944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
267364944
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3881705599
Short name T996
Test name
Test status
Simulation time 47934659 ps
CPU time 0.76 seconds
Started Jun 07 07:44:10 PM PDT 24
Finished Jun 07 07:44:12 PM PDT 24
Peak memory 203832 kb
Host smart-f984192f-f175-4837-8c60-994b64a009e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881705599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
881705599
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2633603031
Short name T969
Test name
Test status
Simulation time 62025420 ps
CPU time 1.89 seconds
Started Jun 07 07:44:09 PM PDT 24
Finished Jun 07 07:44:13 PM PDT 24
Peak memory 215332 kb
Host smart-f8961ac5-b972-4507-8a68-63ace5f31ab0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633603031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2633603031
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2386968427
Short name T178
Test name
Test status
Simulation time 4224675975 ps
CPU time 24.27 seconds
Started Jun 07 07:44:09 PM PDT 24
Finished Jun 07 07:44:35 PM PDT 24
Peak memory 216116 kb
Host smart-4f15e80e-bdcb-434e-8baf-b6d7e9ddd34e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386968427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2386968427
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2370540289
Short name T1059
Test name
Test status
Simulation time 60153717 ps
CPU time 3.74 seconds
Started Jun 07 07:44:13 PM PDT 24
Finished Jun 07 07:44:18 PM PDT 24
Peak memory 218092 kb
Host smart-742f4f7c-8876-4add-a0e5-6907a55b7ea2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370540289 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2370540289
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4138643643
Short name T1013
Test name
Test status
Simulation time 205762439 ps
CPU time 1.37 seconds
Started Jun 07 07:44:10 PM PDT 24
Finished Jun 07 07:44:14 PM PDT 24
Peak memory 215372 kb
Host smart-f822db88-340e-4082-b9c7-75c8faa61f11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138643643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4
138643643
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1269127482
Short name T957
Test name
Test status
Simulation time 14263697 ps
CPU time 0.78 seconds
Started Jun 07 07:44:08 PM PDT 24
Finished Jun 07 07:44:11 PM PDT 24
Peak memory 203864 kb
Host smart-68dedd6f-879c-4148-a0af-349ee9c3aceb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269127482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
269127482
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.830248637
Short name T149
Test name
Test status
Simulation time 241497579 ps
CPU time 1.82 seconds
Started Jun 07 07:44:12 PM PDT 24
Finished Jun 07 07:44:15 PM PDT 24
Peak memory 215316 kb
Host smart-19839bf4-a79b-4fc3-8a7c-42bb9b87c977
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830248637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.830248637
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.107246929
Short name T988
Test name
Test status
Simulation time 69639996 ps
CPU time 4.18 seconds
Started Jun 07 07:44:10 PM PDT 24
Finished Jun 07 07:44:16 PM PDT 24
Peak memory 215536 kb
Host smart-aaeb2181-d5cc-447f-a41c-60dc8a4c3e43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107246929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.107246929
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1525071025
Short name T1063
Test name
Test status
Simulation time 1486108029 ps
CPU time 8.85 seconds
Started Jun 07 07:44:10 PM PDT 24
Finished Jun 07 07:44:21 PM PDT 24
Peak memory 215336 kb
Host smart-e0aea333-f49d-4086-8c90-9772ee30b183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525071025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1525071025
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.610166247
Short name T1028
Test name
Test status
Simulation time 53138043 ps
CPU time 1.7 seconds
Started Jun 07 07:44:11 PM PDT 24
Finished Jun 07 07:44:14 PM PDT 24
Peak memory 216192 kb
Host smart-08d7bcdb-030f-4092-8af4-76e88ed33485
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610166247 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.610166247
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.914803832
Short name T122
Test name
Test status
Simulation time 282435031 ps
CPU time 2.4 seconds
Started Jun 07 07:44:11 PM PDT 24
Finished Jun 07 07:44:15 PM PDT 24
Peak memory 215284 kb
Host smart-e9430a37-8607-4ec4-9eba-1d24050ce133
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914803832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.914803832
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1458424353
Short name T995
Test name
Test status
Simulation time 80195413 ps
CPU time 0.72 seconds
Started Jun 07 07:44:09 PM PDT 24
Finished Jun 07 07:44:12 PM PDT 24
Peak memory 203860 kb
Host smart-a36f6a76-653d-4dc4-bd1f-e941f5ef4a58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458424353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
458424353
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1020604740
Short name T136
Test name
Test status
Simulation time 163956970 ps
CPU time 4.02 seconds
Started Jun 07 07:44:11 PM PDT 24
Finished Jun 07 07:44:17 PM PDT 24
Peak memory 215416 kb
Host smart-cbb37505-ffd2-4efd-90a9-9b8c6e2fcc95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020604740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1020604740
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2753522719
Short name T106
Test name
Test status
Simulation time 751335436 ps
CPU time 4.94 seconds
Started Jun 07 07:44:14 PM PDT 24
Finished Jun 07 07:44:21 PM PDT 24
Peak memory 215556 kb
Host smart-8c585e1d-87ab-4b42-a9bb-85c3db07c58e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753522719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
753522719
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.352756779
Short name T176
Test name
Test status
Simulation time 421653727 ps
CPU time 6.58 seconds
Started Jun 07 07:44:15 PM PDT 24
Finished Jun 07 07:44:23 PM PDT 24
Peak memory 215716 kb
Host smart-e3fca04f-341c-4f7a-86c9-ebddce455037
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352756779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.352756779
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2581111689
Short name T109
Test name
Test status
Simulation time 91631034 ps
CPU time 1.87 seconds
Started Jun 07 07:44:11 PM PDT 24
Finished Jun 07 07:44:14 PM PDT 24
Peak memory 216376 kb
Host smart-47955d0a-4b14-4f34-b77f-dad843af95f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581111689 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2581111689
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1929188216
Short name T1074
Test name
Test status
Simulation time 74896564 ps
CPU time 1.65 seconds
Started Jun 07 07:44:09 PM PDT 24
Finished Jun 07 07:44:12 PM PDT 24
Peak memory 215232 kb
Host smart-227718fc-2a84-4b70-944a-eb29d45dcc0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929188216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
929188216
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2981405170
Short name T960
Test name
Test status
Simulation time 56086004 ps
CPU time 0.73 seconds
Started Jun 07 07:44:11 PM PDT 24
Finished Jun 07 07:44:13 PM PDT 24
Peak memory 203864 kb
Host smart-2983ecfb-9bf8-4bfd-ac21-7b48ceecb878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981405170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
981405170
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2996876109
Short name T134
Test name
Test status
Simulation time 744106450 ps
CPU time 4.33 seconds
Started Jun 07 07:44:14 PM PDT 24
Finished Jun 07 07:44:20 PM PDT 24
Peak memory 215348 kb
Host smart-2b051633-ef82-457c-a15c-7ec904e76a7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996876109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2996876109
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3888631748
Short name T107
Test name
Test status
Simulation time 247375586 ps
CPU time 2.93 seconds
Started Jun 07 07:44:15 PM PDT 24
Finished Jun 07 07:44:19 PM PDT 24
Peak memory 215540 kb
Host smart-c5f7d9ce-60e4-48d9-8005-9cdc3f088f13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888631748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
888631748
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.298178958
Short name T99
Test name
Test status
Simulation time 1024749277 ps
CPU time 20.33 seconds
Started Jun 07 07:44:14 PM PDT 24
Finished Jun 07 07:44:36 PM PDT 24
Peak memory 215732 kb
Host smart-272fc989-cf15-466d-9517-166531161f52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298178958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.298178958
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1601832757
Short name T954
Test name
Test status
Simulation time 47069421 ps
CPU time 0.72 seconds
Started Jun 07 07:49:52 PM PDT 24
Finished Jun 07 07:49:53 PM PDT 24
Peak memory 206268 kb
Host smart-3b241b72-e53b-488b-8f18-cf10dbf43c3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601832757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
601832757
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2134487664
Short name T358
Test name
Test status
Simulation time 125078463 ps
CPU time 3.36 seconds
Started Jun 07 07:49:45 PM PDT 24
Finished Jun 07 07:49:49 PM PDT 24
Peak memory 233516 kb
Host smart-c72447a1-e01f-482e-9605-4014b00c798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134487664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2134487664
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2085978241
Short name T374
Test name
Test status
Simulation time 75610891 ps
CPU time 0.75 seconds
Started Jun 07 07:49:39 PM PDT 24
Finished Jun 07 07:49:41 PM PDT 24
Peak memory 207380 kb
Host smart-a3506885-d58d-4c96-ab1e-dc8ce6d18d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085978241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2085978241
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1886949011
Short name T848
Test name
Test status
Simulation time 28383379148 ps
CPU time 264.03 seconds
Started Jun 07 07:49:46 PM PDT 24
Finished Jun 07 07:54:11 PM PDT 24
Peak memory 250532 kb
Host smart-431cc9bb-194d-45af-8276-ff366c6c8c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886949011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1886949011
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.220994215
Short name T595
Test name
Test status
Simulation time 212570711706 ps
CPU time 543.68 seconds
Started Jun 07 07:49:44 PM PDT 24
Finished Jun 07 07:58:49 PM PDT 24
Peak memory 250204 kb
Host smart-ecc6c78b-b7bd-4a6f-9ddb-392b5987ad2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220994215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
220994215
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2254508113
Short name T40
Test name
Test status
Simulation time 37511875 ps
CPU time 2.8 seconds
Started Jun 07 07:49:43 PM PDT 24
Finished Jun 07 07:49:46 PM PDT 24
Peak memory 225312 kb
Host smart-d4d919fd-dd06-4218-8d3f-01fd57337a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254508113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2254508113
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2477622075
Short name T793
Test name
Test status
Simulation time 867365316 ps
CPU time 9.22 seconds
Started Jun 07 07:49:36 PM PDT 24
Finished Jun 07 07:49:46 PM PDT 24
Peak memory 233572 kb
Host smart-9f012fb2-724b-4bbd-ad42-4c44ecd44200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477622075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2477622075
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.4252710750
Short name T744
Test name
Test status
Simulation time 598923444 ps
CPU time 8.23 seconds
Started Jun 07 07:49:37 PM PDT 24
Finished Jun 07 07:49:46 PM PDT 24
Peak memory 237024 kb
Host smart-e39b271f-3576-461c-91b3-ecbfa19fcffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252710750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4252710750
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3566556117
Short name T693
Test name
Test status
Simulation time 14461836047 ps
CPU time 11.25 seconds
Started Jun 07 07:49:37 PM PDT 24
Finished Jun 07 07:49:49 PM PDT 24
Peak memory 233672 kb
Host smart-bf6d5f9f-a219-44a0-ab25-884ba7ac256e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566556117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3566556117
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2571936387
Short name T571
Test name
Test status
Simulation time 64459090 ps
CPU time 2.34 seconds
Started Jun 07 07:49:39 PM PDT 24
Finished Jun 07 07:49:42 PM PDT 24
Peak memory 225016 kb
Host smart-e1da96e4-3885-4b7c-bcab-7f7673497088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571936387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2571936387
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.111648265
Short name T879
Test name
Test status
Simulation time 3463758823 ps
CPU time 7.61 seconds
Started Jun 07 07:49:45 PM PDT 24
Finished Jun 07 07:49:53 PM PDT 24
Peak memory 224008 kb
Host smart-b55e58b7-2b7a-4c64-a0c4-6796ffbf7732
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=111648265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.111648265
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3424461135
Short name T799
Test name
Test status
Simulation time 8612999903 ps
CPU time 49.79 seconds
Started Jun 07 07:49:44 PM PDT 24
Finished Jun 07 07:50:35 PM PDT 24
Peak memory 257016 kb
Host smart-4a627066-8d95-4be2-8326-7380d1e67cc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424461135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3424461135
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3724462499
Short name T917
Test name
Test status
Simulation time 8838920521 ps
CPU time 46.44 seconds
Started Jun 07 07:49:38 PM PDT 24
Finished Jun 07 07:50:26 PM PDT 24
Peak memory 217272 kb
Host smart-e54067c6-aa00-47ef-beb5-11bb66ad5811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724462499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3724462499
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.771341614
Short name T470
Test name
Test status
Simulation time 8364945285 ps
CPU time 6.46 seconds
Started Jun 07 07:49:38 PM PDT 24
Finished Jun 07 07:49:45 PM PDT 24
Peak memory 217300 kb
Host smart-4f0b0673-a9e4-476e-8338-986b7ccf81c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771341614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.771341614
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3379143716
Short name T310
Test name
Test status
Simulation time 86931110 ps
CPU time 0.8 seconds
Started Jun 07 07:49:36 PM PDT 24
Finished Jun 07 07:49:38 PM PDT 24
Peak memory 207244 kb
Host smart-6a922263-cd22-4b8e-aace-daf3b2e04fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379143716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3379143716
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2501108523
Short name T633
Test name
Test status
Simulation time 72358434 ps
CPU time 0.7 seconds
Started Jun 07 07:49:39 PM PDT 24
Finished Jun 07 07:49:40 PM PDT 24
Peak memory 206368 kb
Host smart-57c9aa04-d4f7-42ea-9869-c2e0db31054e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501108523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2501108523
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2053141630
Short name T494
Test name
Test status
Simulation time 150321220 ps
CPU time 2.38 seconds
Started Jun 07 07:49:37 PM PDT 24
Finished Jun 07 07:49:40 PM PDT 24
Peak memory 225148 kb
Host smart-90dd5094-36c3-474e-8900-0d21a872fa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053141630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2053141630
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1624455997
Short name T676
Test name
Test status
Simulation time 40963847 ps
CPU time 0.77 seconds
Started Jun 07 07:50:02 PM PDT 24
Finished Jun 07 07:50:05 PM PDT 24
Peak memory 206264 kb
Host smart-dc8b84ee-66ff-4c26-9a49-3bfe2d08bf04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624455997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
624455997
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1024529300
Short name T506
Test name
Test status
Simulation time 36272700 ps
CPU time 3.05 seconds
Started Jun 07 07:49:56 PM PDT 24
Finished Jun 07 07:50:00 PM PDT 24
Peak memory 233336 kb
Host smart-ec12af61-8a07-4d89-8ca3-4385f00abc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024529300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1024529300
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2150717257
Short name T729
Test name
Test status
Simulation time 53888020 ps
CPU time 0.8 seconds
Started Jun 07 07:49:53 PM PDT 24
Finished Jun 07 07:49:55 PM PDT 24
Peak memory 207420 kb
Host smart-c4464f55-8122-4165-b061-46a3358ef644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150717257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2150717257
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2322858799
Short name T880
Test name
Test status
Simulation time 8588864652 ps
CPU time 89.13 seconds
Started Jun 07 07:50:00 PM PDT 24
Finished Jun 07 07:51:32 PM PDT 24
Peak memory 250080 kb
Host smart-a52f51a6-fe79-40ba-b472-cad03f3081f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322858799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2322858799
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.923570030
Short name T785
Test name
Test status
Simulation time 28833125715 ps
CPU time 62.04 seconds
Started Jun 07 07:50:01 PM PDT 24
Finished Jun 07 07:51:06 PM PDT 24
Peak memory 225496 kb
Host smart-ca64099b-5f15-4361-8b1c-6db16f0249a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923570030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.923570030
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3604547488
Short name T309
Test name
Test status
Simulation time 25120787903 ps
CPU time 152.8 seconds
Started Jun 07 07:50:01 PM PDT 24
Finished Jun 07 07:52:37 PM PDT 24
Peak memory 266240 kb
Host smart-c2a9db72-51e3-4d65-ba61-44b69e30e2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604547488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3604547488
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_intercept.720586695
Short name T227
Test name
Test status
Simulation time 2093343109 ps
CPU time 13.31 seconds
Started Jun 07 07:49:52 PM PDT 24
Finished Jun 07 07:50:06 PM PDT 24
Peak memory 225268 kb
Host smart-60fff4f1-f667-4b05-b6c6-53db5cc7c930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720586695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.720586695
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3449733928
Short name T407
Test name
Test status
Simulation time 39963429574 ps
CPU time 68.47 seconds
Started Jun 07 07:49:56 PM PDT 24
Finished Jun 07 07:51:05 PM PDT 24
Peak memory 241516 kb
Host smart-1a9426ce-9a84-40db-8afa-6e6ac70e3e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449733928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3449733928
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2500919376
Short name T582
Test name
Test status
Simulation time 31394104 ps
CPU time 2.47 seconds
Started Jun 07 07:49:53 PM PDT 24
Finished Jun 07 07:49:57 PM PDT 24
Peak memory 233492 kb
Host smart-e1d0342a-0a93-4c96-aa79-cd79408015b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500919376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2500919376
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3874655561
Short name T607
Test name
Test status
Simulation time 5247961109 ps
CPU time 8.15 seconds
Started Jun 07 07:49:54 PM PDT 24
Finished Jun 07 07:50:03 PM PDT 24
Peak memory 225504 kb
Host smart-1e8f9978-361f-46f0-8dbd-aa52caf07908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874655561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3874655561
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1273945902
Short name T454
Test name
Test status
Simulation time 290334426 ps
CPU time 5.55 seconds
Started Jun 07 07:49:53 PM PDT 24
Finished Jun 07 07:49:59 PM PDT 24
Peak memory 221016 kb
Host smart-dae50888-bc9a-448b-8998-1c7e03f44a27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1273945902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1273945902
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2067781364
Short name T72
Test name
Test status
Simulation time 78979973 ps
CPU time 1.14 seconds
Started Jun 07 07:50:00 PM PDT 24
Finished Jun 07 07:50:04 PM PDT 24
Peak memory 235876 kb
Host smart-c9a53e35-d7d8-49aa-a8e9-152953312faa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067781364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2067781364
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.999261625
Short name T64
Test name
Test status
Simulation time 1308326556 ps
CPU time 28.54 seconds
Started Jun 07 07:50:01 PM PDT 24
Finished Jun 07 07:50:32 PM PDT 24
Peak memory 254812 kb
Host smart-0178dfdd-93a4-4300-beb6-f4a3b1cffd65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999261625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.999261625
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4107376856
Short name T790
Test name
Test status
Simulation time 11372129550 ps
CPU time 15.77 seconds
Started Jun 07 07:49:52 PM PDT 24
Finished Jun 07 07:50:08 PM PDT 24
Peak memory 217260 kb
Host smart-12f0ff33-da80-401f-b776-1acf439014a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107376856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4107376856
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.347889357
Short name T628
Test name
Test status
Simulation time 1944415573 ps
CPU time 10.99 seconds
Started Jun 07 07:49:52 PM PDT 24
Finished Jun 07 07:50:03 PM PDT 24
Peak memory 217192 kb
Host smart-d972384e-d261-439b-b034-7c000be5e74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347889357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.347889357
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3247208641
Short name T890
Test name
Test status
Simulation time 188285023 ps
CPU time 1.79 seconds
Started Jun 07 07:49:51 PM PDT 24
Finished Jun 07 07:49:54 PM PDT 24
Peak memory 217188 kb
Host smart-d36f2f6e-ab48-4cec-bd90-acac811639ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247208641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3247208641
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3233396491
Short name T942
Test name
Test status
Simulation time 136636078 ps
CPU time 0.94 seconds
Started Jun 07 07:49:52 PM PDT 24
Finished Jun 07 07:49:54 PM PDT 24
Peak memory 206676 kb
Host smart-5956bb44-cfc8-411b-b52d-df5fb82ee2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233396491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3233396491
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.304186268
Short name T267
Test name
Test status
Simulation time 5555148504 ps
CPU time 24.59 seconds
Started Jun 07 07:49:53 PM PDT 24
Finished Jun 07 07:50:19 PM PDT 24
Peak memory 233676 kb
Host smart-2abb71cc-03ed-4415-a15f-753d9ae6bc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304186268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.304186268
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.313674758
Short name T756
Test name
Test status
Simulation time 11427467 ps
CPU time 0.7 seconds
Started Jun 07 07:51:15 PM PDT 24
Finished Jun 07 07:51:18 PM PDT 24
Peak memory 205664 kb
Host smart-ad3e44ea-d71e-4434-a544-73063e56fa99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313674758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.313674758
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.707858688
Short name T397
Test name
Test status
Simulation time 853870689 ps
CPU time 3.46 seconds
Started Jun 07 07:51:18 PM PDT 24
Finished Jun 07 07:51:23 PM PDT 24
Peak memory 225252 kb
Host smart-96eeb457-a338-4ab2-b8b1-82166259162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707858688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.707858688
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1263462432
Short name T774
Test name
Test status
Simulation time 64844676 ps
CPU time 0.77 seconds
Started Jun 07 07:51:14 PM PDT 24
Finished Jun 07 07:51:17 PM PDT 24
Peak memory 206316 kb
Host smart-d53e549c-6567-45aa-97ac-b6645b016087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263462432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1263462432
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1102786222
Short name T885
Test name
Test status
Simulation time 16758614 ps
CPU time 0.78 seconds
Started Jun 07 07:51:19 PM PDT 24
Finished Jun 07 07:51:21 PM PDT 24
Peak memory 216664 kb
Host smart-a5939603-7f19-4a31-aa96-4a374851e623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102786222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1102786222
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.535112906
Short name T305
Test name
Test status
Simulation time 1716653687 ps
CPU time 13.91 seconds
Started Jun 07 07:51:15 PM PDT 24
Finished Jun 07 07:51:31 PM PDT 24
Peak memory 225348 kb
Host smart-605bdc11-de40-4f2d-8267-e06ef9d5b19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535112906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.535112906
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3198735530
Short name T211
Test name
Test status
Simulation time 4395674999 ps
CPU time 14.36 seconds
Started Jun 07 07:51:22 PM PDT 24
Finished Jun 07 07:51:38 PM PDT 24
Peak memory 225444 kb
Host smart-3bfcda8b-f1f8-432f-8bd9-96d2e3d65e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198735530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3198735530
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4077438146
Short name T247
Test name
Test status
Simulation time 20594919416 ps
CPU time 65.19 seconds
Started Jun 07 07:51:17 PM PDT 24
Finished Jun 07 07:52:24 PM PDT 24
Peak memory 234848 kb
Host smart-8bf38b27-461c-4847-9430-c68e3efed7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077438146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4077438146
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2582873531
Short name T703
Test name
Test status
Simulation time 759033394 ps
CPU time 3.93 seconds
Started Jun 07 07:51:16 PM PDT 24
Finished Jun 07 07:51:22 PM PDT 24
Peak memory 233536 kb
Host smart-0ff84a43-a74e-4915-9e01-31c4d65abae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582873531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2582873531
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3451541718
Short name T725
Test name
Test status
Simulation time 361235073 ps
CPU time 6.16 seconds
Started Jun 07 07:51:18 PM PDT 24
Finished Jun 07 07:51:26 PM PDT 24
Peak memory 241256 kb
Host smart-7c7710c4-f4ab-4ab7-9dbf-eea9c173ef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451541718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3451541718
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3846866487
Short name T862
Test name
Test status
Simulation time 773874659 ps
CPU time 6.99 seconds
Started Jun 07 07:51:19 PM PDT 24
Finished Jun 07 07:51:28 PM PDT 24
Peak memory 223340 kb
Host smart-840d38a5-22c9-44ab-bbd7-b856ee829e81
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3846866487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3846866487
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.4091788865
Short name T710
Test name
Test status
Simulation time 53596946111 ps
CPU time 112.41 seconds
Started Jun 07 07:51:22 PM PDT 24
Finished Jun 07 07:53:16 PM PDT 24
Peak memory 250168 kb
Host smart-141c11e8-8034-4b20-a839-b537f4e61e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091788865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.4091788865
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.510073907
Short name T562
Test name
Test status
Simulation time 3094100211 ps
CPU time 6.51 seconds
Started Jun 07 07:51:17 PM PDT 24
Finished Jun 07 07:51:25 PM PDT 24
Peak memory 219352 kb
Host smart-278d514d-db2c-4e9f-97d0-74676a34a358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510073907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.510073907
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2268348357
Short name T362
Test name
Test status
Simulation time 1471083175 ps
CPU time 6.87 seconds
Started Jun 07 07:51:21 PM PDT 24
Finished Jun 07 07:51:30 PM PDT 24
Peak memory 217196 kb
Host smart-1a3ecd0f-9f24-4650-a95b-2dc1bf6b4357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268348357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2268348357
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1573660167
Short name T807
Test name
Test status
Simulation time 95505401 ps
CPU time 1.14 seconds
Started Jun 07 07:51:16 PM PDT 24
Finished Jun 07 07:51:19 PM PDT 24
Peak memory 208588 kb
Host smart-b11a7276-2e09-49a6-8bd6-6b213c9f361a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573660167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1573660167
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.227879930
Short name T409
Test name
Test status
Simulation time 59494741 ps
CPU time 0.92 seconds
Started Jun 07 07:51:17 PM PDT 24
Finished Jun 07 07:51:20 PM PDT 24
Peak memory 207200 kb
Host smart-526b922e-c187-4846-9921-5f4c64983fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227879930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.227879930
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.236440786
Short name T375
Test name
Test status
Simulation time 18249836 ps
CPU time 0.75 seconds
Started Jun 07 07:51:20 PM PDT 24
Finished Jun 07 07:51:23 PM PDT 24
Peak memory 206268 kb
Host smart-ca4e28fc-dd67-490f-a756-17577361ce61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236440786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.236440786
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.226132157
Short name T621
Test name
Test status
Simulation time 8650624546 ps
CPU time 21.79 seconds
Started Jun 07 07:51:20 PM PDT 24
Finished Jun 07 07:51:44 PM PDT 24
Peak memory 233628 kb
Host smart-f6b4cdbb-b298-41ea-822d-61053b41341b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226132157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.226132157
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1768187737
Short name T385
Test name
Test status
Simulation time 20539724 ps
CPU time 0.85 seconds
Started Jun 07 07:51:19 PM PDT 24
Finished Jun 07 07:51:21 PM PDT 24
Peak memory 207652 kb
Host smart-efba5d27-79f3-43d3-b2e8-1a252e763d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768187737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1768187737
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2784074893
Short name T698
Test name
Test status
Simulation time 931750521 ps
CPU time 5.05 seconds
Started Jun 07 07:51:19 PM PDT 24
Finished Jun 07 07:51:26 PM PDT 24
Peak memory 225384 kb
Host smart-f4ac26a1-1891-4dc6-a81f-6c6e0c896366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784074893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2784074893
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1656709768
Short name T916
Test name
Test status
Simulation time 104478527 ps
CPU time 2.76 seconds
Started Jun 07 07:51:21 PM PDT 24
Finished Jun 07 07:51:26 PM PDT 24
Peak memory 225220 kb
Host smart-83b9874f-86af-4015-8d20-85ed3eec8b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656709768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1656709768
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1075213468
Short name T795
Test name
Test status
Simulation time 4714184340 ps
CPU time 46.25 seconds
Started Jun 07 07:51:23 PM PDT 24
Finished Jun 07 07:52:11 PM PDT 24
Peak memory 241900 kb
Host smart-08792b6b-fe0d-407f-a862-f69e1086cad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075213468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1075213468
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3505353288
Short name T424
Test name
Test status
Simulation time 2324982272 ps
CPU time 5.28 seconds
Started Jun 07 07:51:20 PM PDT 24
Finished Jun 07 07:51:27 PM PDT 24
Peak memory 241604 kb
Host smart-b4ee40b0-71be-4f54-9ee1-d01c49f18aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505353288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3505353288
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2693021677
Short name T606
Test name
Test status
Simulation time 60741198 ps
CPU time 2.49 seconds
Started Jun 07 07:51:18 PM PDT 24
Finished Jun 07 07:51:22 PM PDT 24
Peak memory 225352 kb
Host smart-02734576-7dbf-47e6-8e25-71f2a4275b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693021677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2693021677
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2660821915
Short name T141
Test name
Test status
Simulation time 120566232 ps
CPU time 4.31 seconds
Started Jun 07 07:51:20 PM PDT 24
Finished Jun 07 07:51:26 PM PDT 24
Peak memory 223980 kb
Host smart-c9fadb9e-28ce-4c2d-823b-caf4d7158b98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2660821915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2660821915
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1055800219
Short name T836
Test name
Test status
Simulation time 13964057158 ps
CPU time 54.95 seconds
Started Jun 07 07:51:23 PM PDT 24
Finished Jun 07 07:52:19 PM PDT 24
Peak memory 238488 kb
Host smart-4603aa89-f650-45a0-a894-da801b17f2a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055800219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1055800219
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1575757884
Short name T331
Test name
Test status
Simulation time 233960166 ps
CPU time 0.76 seconds
Started Jun 07 07:51:18 PM PDT 24
Finished Jun 07 07:51:20 PM PDT 24
Peak memory 206828 kb
Host smart-e8f51e99-9c3f-41c6-8fa1-161946214290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575757884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1575757884
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3857445582
Short name T647
Test name
Test status
Simulation time 6559238164 ps
CPU time 6.41 seconds
Started Jun 07 07:51:20 PM PDT 24
Finished Jun 07 07:51:28 PM PDT 24
Peak memory 217224 kb
Host smart-1b62c476-40e3-4de9-98fc-1427826911c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857445582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3857445582
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1328540338
Short name T903
Test name
Test status
Simulation time 14929442 ps
CPU time 0.77 seconds
Started Jun 07 07:51:19 PM PDT 24
Finished Jun 07 07:51:21 PM PDT 24
Peak memory 206688 kb
Host smart-e148ad48-e2e3-46ac-bebe-c8c10857dbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328540338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1328540338
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1408566589
Short name T511
Test name
Test status
Simulation time 175178485 ps
CPU time 0.89 seconds
Started Jun 07 07:51:19 PM PDT 24
Finished Jun 07 07:51:21 PM PDT 24
Peak memory 206676 kb
Host smart-0ed9d29d-883a-4433-ac2e-8d006c254f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408566589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1408566589
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.413229830
Short name T889
Test name
Test status
Simulation time 22082552796 ps
CPU time 17.57 seconds
Started Jun 07 07:51:20 PM PDT 24
Finished Jun 07 07:51:39 PM PDT 24
Peak memory 233648 kb
Host smart-84a18b52-c0b6-47f7-9eb6-32ac95377e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413229830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.413229830
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3803378924
Short name T632
Test name
Test status
Simulation time 40156057 ps
CPU time 0.7 seconds
Started Jun 07 07:51:35 PM PDT 24
Finished Jun 07 07:51:37 PM PDT 24
Peak memory 206308 kb
Host smart-0fe4cd86-013c-46db-927e-66af7ee0f52a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803378924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3803378924
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1427606653
Short name T592
Test name
Test status
Simulation time 374542048 ps
CPU time 5.5 seconds
Started Jun 07 07:51:29 PM PDT 24
Finished Jun 07 07:51:35 PM PDT 24
Peak memory 225372 kb
Host smart-4ba51751-9fb9-492e-9a30-d322d632ec6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427606653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1427606653
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2210425233
Short name T864
Test name
Test status
Simulation time 14494379 ps
CPU time 0.78 seconds
Started Jun 07 07:51:21 PM PDT 24
Finished Jun 07 07:51:24 PM PDT 24
Peak memory 207732 kb
Host smart-3212737f-25c8-4cbe-9e12-28a739bfb765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210425233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2210425233
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.99572707
Short name T691
Test name
Test status
Simulation time 10284898987 ps
CPU time 57.78 seconds
Started Jun 07 07:51:37 PM PDT 24
Finished Jun 07 07:52:37 PM PDT 24
Peak memory 251888 kb
Host smart-f107abb3-3505-44c5-b5d0-22f7f623c011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99572707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.99572707
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2396927996
Short name T256
Test name
Test status
Simulation time 1951420678 ps
CPU time 37.36 seconds
Started Jun 07 07:51:38 PM PDT 24
Finished Jun 07 07:52:17 PM PDT 24
Peak memory 225376 kb
Host smart-fca535b7-6702-4f10-9b75-ad7baee73671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396927996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2396927996
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1958729625
Short name T85
Test name
Test status
Simulation time 260882667 ps
CPU time 7.5 seconds
Started Jun 07 07:51:28 PM PDT 24
Finished Jun 07 07:51:37 PM PDT 24
Peak memory 225332 kb
Host smart-9d671192-2dea-4239-b0c8-5712104398e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958729625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1958729625
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1688346697
Short name T242
Test name
Test status
Simulation time 2687040083 ps
CPU time 27.81 seconds
Started Jun 07 07:51:31 PM PDT 24
Finished Jun 07 07:52:00 PM PDT 24
Peak memory 233680 kb
Host smart-7479f496-3e11-4815-8209-4c84a313a5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688346697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1688346697
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2765468758
Short name T213
Test name
Test status
Simulation time 3400176756 ps
CPU time 33.99 seconds
Started Jun 07 07:51:27 PM PDT 24
Finished Jun 07 07:52:02 PM PDT 24
Peak memory 227880 kb
Host smart-08ebb535-06cd-4dd8-92b3-1eb1a71a6fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765468758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2765468758
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1457573610
Short name T939
Test name
Test status
Simulation time 2398946460 ps
CPU time 9.29 seconds
Started Jun 07 07:51:28 PM PDT 24
Finished Jun 07 07:51:39 PM PDT 24
Peak memory 233704 kb
Host smart-84a17a56-e202-43db-a8ea-8ee6f567e08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457573610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1457573610
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1834850128
Short name T741
Test name
Test status
Simulation time 32573327611 ps
CPU time 24.3 seconds
Started Jun 07 07:51:30 PM PDT 24
Finished Jun 07 07:51:55 PM PDT 24
Peak memory 233760 kb
Host smart-5b7d41b0-3916-4a52-9b53-77e71ea9c4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834850128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1834850128
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3500469380
Short name T686
Test name
Test status
Simulation time 1242904769 ps
CPU time 13.38 seconds
Started Jun 07 07:51:30 PM PDT 24
Finished Jun 07 07:51:45 PM PDT 24
Peak memory 219932 kb
Host smart-8a316a76-8b67-4c26-a5b6-6e0e532a1953
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3500469380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3500469380
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2428158592
Short name T460
Test name
Test status
Simulation time 10246455608 ps
CPU time 15.42 seconds
Started Jun 07 07:51:28 PM PDT 24
Finished Jun 07 07:51:44 PM PDT 24
Peak memory 217176 kb
Host smart-82929cb6-2eba-4e59-8151-781f58f37bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428158592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2428158592
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3327132099
Short name T443
Test name
Test status
Simulation time 6677448458 ps
CPU time 5.19 seconds
Started Jun 07 07:51:30 PM PDT 24
Finished Jun 07 07:51:36 PM PDT 24
Peak memory 217368 kb
Host smart-6b93d6f7-619f-4447-ace1-92a94ff9a028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327132099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3327132099
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1277225040
Short name T361
Test name
Test status
Simulation time 178111223 ps
CPU time 1.43 seconds
Started Jun 07 07:51:29 PM PDT 24
Finished Jun 07 07:51:31 PM PDT 24
Peak memory 217040 kb
Host smart-5e7a3ada-60f7-45e1-9dfb-f8af45b9c133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277225040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1277225040
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2589055021
Short name T837
Test name
Test status
Simulation time 40384257 ps
CPU time 0.85 seconds
Started Jun 07 07:51:27 PM PDT 24
Finished Jun 07 07:51:28 PM PDT 24
Peak memory 206688 kb
Host smart-244ecd5c-3960-4aa9-847c-b8ca6825dc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589055021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2589055021
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2031945789
Short name T913
Test name
Test status
Simulation time 11167405569 ps
CPU time 44.62 seconds
Started Jun 07 07:51:27 PM PDT 24
Finished Jun 07 07:52:13 PM PDT 24
Peak memory 241840 kb
Host smart-9eb9a4cb-8f91-44f8-8b13-05f49f6fa0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031945789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2031945789
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3148957946
Short name T731
Test name
Test status
Simulation time 34299154 ps
CPU time 0.72 seconds
Started Jun 07 07:51:52 PM PDT 24
Finished Jun 07 07:51:54 PM PDT 24
Peak memory 206616 kb
Host smart-a93a8045-b952-40f7-afd3-20addc109be8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148957946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3148957946
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1218491391
Short name T248
Test name
Test status
Simulation time 2257499678 ps
CPU time 4.98 seconds
Started Jun 07 07:51:44 PM PDT 24
Finished Jun 07 07:51:50 PM PDT 24
Peak memory 233708 kb
Host smart-a5501c2b-6ee0-452a-97c3-9adab06de7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218491391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1218491391
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1309926267
Short name T732
Test name
Test status
Simulation time 24452425 ps
CPU time 0.79 seconds
Started Jun 07 07:51:37 PM PDT 24
Finished Jun 07 07:51:39 PM PDT 24
Peak memory 207420 kb
Host smart-dc1f91d0-b1a5-4cc2-91ba-5bc108293d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309926267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1309926267
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3176040638
Short name T3
Test name
Test status
Simulation time 33047708215 ps
CPU time 95.96 seconds
Started Jun 07 07:51:46 PM PDT 24
Finished Jun 07 07:53:23 PM PDT 24
Peak memory 241844 kb
Host smart-9a93d2cb-baf1-4302-83db-1f37e2455c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176040638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3176040638
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1649841820
Short name T733
Test name
Test status
Simulation time 15545256343 ps
CPU time 89.7 seconds
Started Jun 07 07:51:45 PM PDT 24
Finished Jun 07 07:53:16 PM PDT 24
Peak memory 250104 kb
Host smart-8103c460-ca27-4634-a544-1d7266472dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649841820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1649841820
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1281589152
Short name T351
Test name
Test status
Simulation time 2585799064 ps
CPU time 10.99 seconds
Started Jun 07 07:51:53 PM PDT 24
Finished Jun 07 07:52:06 PM PDT 24
Peak memory 231676 kb
Host smart-6d199372-b5ab-4615-91ad-f4601245c45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281589152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1281589152
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2055775554
Short name T780
Test name
Test status
Simulation time 1105034292 ps
CPU time 11.98 seconds
Started Jun 07 07:51:47 PM PDT 24
Finished Jun 07 07:52:00 PM PDT 24
Peak memory 238536 kb
Host smart-a84af83d-e1fd-499d-913a-3c76275b6834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055775554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2055775554
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3369480190
Short name T641
Test name
Test status
Simulation time 7637900089 ps
CPU time 7.54 seconds
Started Jun 07 07:51:52 PM PDT 24
Finished Jun 07 07:52:02 PM PDT 24
Peak memory 225312 kb
Host smart-f92e5a4b-c9ce-4fcd-9465-f4a68df579a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369480190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3369480190
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4030568290
Short name T615
Test name
Test status
Simulation time 17543371864 ps
CPU time 20.83 seconds
Started Jun 07 07:51:43 PM PDT 24
Finished Jun 07 07:52:05 PM PDT 24
Peak memory 225492 kb
Host smart-60fac1f0-9ed7-42fb-a116-47b3bf8d05a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030568290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4030568290
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2526525390
Short name T877
Test name
Test status
Simulation time 852790184 ps
CPU time 6.26 seconds
Started Jun 07 07:51:44 PM PDT 24
Finished Jun 07 07:51:52 PM PDT 24
Peak memory 223368 kb
Host smart-0fe48866-b1fe-407a-b69b-151a18cafdb2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2526525390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2526525390
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3893989618
Short name T156
Test name
Test status
Simulation time 39113529 ps
CPU time 0.95 seconds
Started Jun 07 07:51:52 PM PDT 24
Finished Jun 07 07:51:55 PM PDT 24
Peak memory 207740 kb
Host smart-560cc76e-9898-4121-ba0b-c2eefd31c11f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893989618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3893989618
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3887155771
Short name T813
Test name
Test status
Simulation time 9323388743 ps
CPU time 36.33 seconds
Started Jun 07 07:51:37 PM PDT 24
Finished Jun 07 07:52:14 PM PDT 24
Peak memory 217472 kb
Host smart-ea1db9a0-08d9-4805-be17-c263ef965374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887155771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3887155771
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.4046511425
Short name T335
Test name
Test status
Simulation time 4433035849 ps
CPU time 7.13 seconds
Started Jun 07 07:51:37 PM PDT 24
Finished Jun 07 07:51:45 PM PDT 24
Peak memory 217344 kb
Host smart-01c1aaf7-718f-4c06-8ea1-96498e854c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046511425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.4046511425
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1994156043
Short name T412
Test name
Test status
Simulation time 22453162 ps
CPU time 1.35 seconds
Started Jun 07 07:51:36 PM PDT 24
Finished Jun 07 07:51:38 PM PDT 24
Peak memory 208924 kb
Host smart-c7d7c602-7150-4de8-a205-a6ae31c850df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994156043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1994156043
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.750249678
Short name T435
Test name
Test status
Simulation time 310728531 ps
CPU time 0.98 seconds
Started Jun 07 07:51:37 PM PDT 24
Finished Jun 07 07:51:39 PM PDT 24
Peak memory 206676 kb
Host smart-ec0b2120-763a-433c-994d-0c55d9225bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750249678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.750249678
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1367517841
Short name T57
Test name
Test status
Simulation time 2454059948 ps
CPU time 11.64 seconds
Started Jun 07 07:51:45 PM PDT 24
Finished Jun 07 07:51:57 PM PDT 24
Peak memory 241696 kb
Host smart-1c6326de-a13d-4885-8390-83e176cdcf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367517841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1367517841
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2451352994
Short name T391
Test name
Test status
Simulation time 20125730 ps
CPU time 0.72 seconds
Started Jun 07 07:52:01 PM PDT 24
Finished Jun 07 07:52:04 PM PDT 24
Peak memory 206252 kb
Host smart-51959e2b-a422-446a-b53a-15681068b00c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451352994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2451352994
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.658466743
Short name T909
Test name
Test status
Simulation time 37690540 ps
CPU time 2.76 seconds
Started Jun 07 07:51:53 PM PDT 24
Finished Jun 07 07:51:58 PM PDT 24
Peak memory 233532 kb
Host smart-fb7f4627-4a20-43fc-87f6-f27404b8edba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658466743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.658466743
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.6113848
Short name T327
Test name
Test status
Simulation time 12760276 ps
CPU time 0.78 seconds
Started Jun 07 07:51:53 PM PDT 24
Finished Jun 07 07:51:56 PM PDT 24
Peak memory 206412 kb
Host smart-54db8db4-86c5-4b92-a799-328a17e73cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6113848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.6113848
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.841698638
Short name T617
Test name
Test status
Simulation time 11597730485 ps
CPU time 29.12 seconds
Started Jun 07 07:51:52 PM PDT 24
Finished Jun 07 07:52:23 PM PDT 24
Peak memory 238304 kb
Host smart-8974f697-8825-47b8-89a3-a169c4db4ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841698638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.841698638
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.4200943199
Short name T167
Test name
Test status
Simulation time 376581194494 ps
CPU time 850.87 seconds
Started Jun 07 07:51:53 PM PDT 24
Finished Jun 07 08:06:06 PM PDT 24
Peak memory 257236 kb
Host smart-a11c57da-7043-4cf2-956b-ea8dca77e8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200943199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4200943199
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2030403604
Short name T166
Test name
Test status
Simulation time 35556478160 ps
CPU time 346.95 seconds
Started Jun 07 07:52:01 PM PDT 24
Finished Jun 07 07:57:50 PM PDT 24
Peak memory 258012 kb
Host smart-43b03299-f9c4-4b54-ac3c-160f61394b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030403604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2030403604
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2711677232
Short name T644
Test name
Test status
Simulation time 390019417 ps
CPU time 3.89 seconds
Started Jun 07 07:51:51 PM PDT 24
Finished Jun 07 07:51:56 PM PDT 24
Peak memory 233588 kb
Host smart-82576140-0f9f-4a08-b894-f5b547ed0d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711677232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2711677232
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.653177177
Short name T416
Test name
Test status
Simulation time 3675423503 ps
CPU time 17.08 seconds
Started Jun 07 07:51:52 PM PDT 24
Finished Jun 07 07:52:11 PM PDT 24
Peak memory 233696 kb
Host smart-3543163e-7d33-4ff7-be6d-4addfc9f6346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653177177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.653177177
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2266871938
Short name T411
Test name
Test status
Simulation time 32238996 ps
CPU time 2.77 seconds
Started Jun 07 07:51:51 PM PDT 24
Finished Jun 07 07:51:56 PM PDT 24
Peak memory 233372 kb
Host smart-e8944338-1fbf-41be-9593-04e8ad8b9577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266871938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2266871938
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3722883834
Short name T926
Test name
Test status
Simulation time 3807541514 ps
CPU time 10.46 seconds
Started Jun 07 07:51:52 PM PDT 24
Finished Jun 07 07:52:04 PM PDT 24
Peak memory 241732 kb
Host smart-67aebd87-fe6d-4a8d-9f88-a754e76b56f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722883834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3722883834
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1115804587
Short name T611
Test name
Test status
Simulation time 14601437142 ps
CPU time 12.85 seconds
Started Jun 07 07:51:53 PM PDT 24
Finished Jun 07 07:52:08 PM PDT 24
Peak memory 233684 kb
Host smart-edd04f67-18b6-4566-88f6-12392f02e152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115804587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1115804587
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1322440075
Short name T59
Test name
Test status
Simulation time 145779182 ps
CPU time 3.95 seconds
Started Jun 07 07:51:52 PM PDT 24
Finished Jun 07 07:51:58 PM PDT 24
Peak memory 223928 kb
Host smart-e893bbb6-8b05-418c-9474-f7701019a50e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1322440075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1322440075
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.4116701254
Short name T260
Test name
Test status
Simulation time 43212603047 ps
CPU time 458.67 seconds
Started Jun 07 07:52:01 PM PDT 24
Finished Jun 07 07:59:41 PM PDT 24
Peak memory 257828 kb
Host smart-831d705b-feab-4a5a-9be2-fa3a18fefc57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116701254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.4116701254
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3769273048
Short name T584
Test name
Test status
Simulation time 2576623816 ps
CPU time 20.36 seconds
Started Jun 07 07:51:51 PM PDT 24
Finished Jun 07 07:52:13 PM PDT 24
Peak memory 220944 kb
Host smart-50e77d25-ed99-4765-bc4b-80a6bc9c257f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769273048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3769273048
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.4187187268
Short name T863
Test name
Test status
Simulation time 207495143 ps
CPU time 1.18 seconds
Started Jun 07 07:51:53 PM PDT 24
Finished Jun 07 07:51:56 PM PDT 24
Peak memory 208544 kb
Host smart-06ac163c-e706-4236-8466-bb6d06924fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187187268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.4187187268
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.393225744
Short name T650
Test name
Test status
Simulation time 19124254 ps
CPU time 0.9 seconds
Started Jun 07 07:51:51 PM PDT 24
Finished Jun 07 07:51:54 PM PDT 24
Peak memory 207724 kb
Host smart-adde9890-c14b-438f-99e1-2fb5de67e091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393225744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.393225744
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.995170372
Short name T517
Test name
Test status
Simulation time 81891791 ps
CPU time 1 seconds
Started Jun 07 07:51:52 PM PDT 24
Finished Jun 07 07:51:55 PM PDT 24
Peak memory 207708 kb
Host smart-0bcde536-216a-4345-ad5b-5964cb6dd2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995170372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.995170372
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.719426688
Short name T168
Test name
Test status
Simulation time 11683431230 ps
CPU time 16.57 seconds
Started Jun 07 07:51:52 PM PDT 24
Finished Jun 07 07:52:10 PM PDT 24
Peak memory 233608 kb
Host smart-ab58518f-8229-4754-8141-ffc838d2d921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719426688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.719426688
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2634578631
Short name T452
Test name
Test status
Simulation time 13795017 ps
CPU time 0.74 seconds
Started Jun 07 07:52:01 PM PDT 24
Finished Jun 07 07:52:04 PM PDT 24
Peak memory 205624 kb
Host smart-32c3ea36-a32d-44d0-9e51-d8bbbaea1c64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634578631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2634578631
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1094750005
Short name T145
Test name
Test status
Simulation time 51595913 ps
CPU time 2.43 seconds
Started Jun 07 07:52:01 PM PDT 24
Finished Jun 07 07:52:05 PM PDT 24
Peak memory 233508 kb
Host smart-40c59277-5d43-4e69-9b4e-e206c4956ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094750005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1094750005
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1566858837
Short name T662
Test name
Test status
Simulation time 14564991 ps
CPU time 0.81 seconds
Started Jun 07 07:52:01 PM PDT 24
Finished Jun 07 07:52:04 PM PDT 24
Peak memory 207384 kb
Host smart-9bc8da27-f477-4d79-8ee1-0b14967b261f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566858837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1566858837
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.65451742
Short name T49
Test name
Test status
Simulation time 42244823445 ps
CPU time 99.09 seconds
Started Jun 07 07:52:02 PM PDT 24
Finished Jun 07 07:53:43 PM PDT 24
Peak memory 254148 kb
Host smart-7ae41e8e-90b1-45c9-a35d-f3721dd02048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65451742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.65451742
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.322996014
Short name T775
Test name
Test status
Simulation time 31781977857 ps
CPU time 44.21 seconds
Started Jun 07 07:52:05 PM PDT 24
Finished Jun 07 07:52:51 PM PDT 24
Peak memory 238224 kb
Host smart-7b71bb37-f953-44f0-b1bb-6d8c99d182a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322996014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.322996014
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2579860440
Short name T918
Test name
Test status
Simulation time 5131495082 ps
CPU time 8.67 seconds
Started Jun 07 07:52:03 PM PDT 24
Finished Jun 07 07:52:14 PM PDT 24
Peak memory 237008 kb
Host smart-2f829c65-1831-4e06-9fef-1bfbcb7ad0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579860440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2579860440
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.664391625
Short name T208
Test name
Test status
Simulation time 4063229284 ps
CPU time 8.18 seconds
Started Jun 07 07:52:02 PM PDT 24
Finished Jun 07 07:52:13 PM PDT 24
Peak memory 225348 kb
Host smart-5b608b20-bd17-4e52-b08b-349b96e7d345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664391625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.664391625
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1341882372
Short name T148
Test name
Test status
Simulation time 3609946415 ps
CPU time 31.23 seconds
Started Jun 07 07:52:00 PM PDT 24
Finished Jun 07 07:52:33 PM PDT 24
Peak memory 233564 kb
Host smart-c5a8411c-6c49-401d-b73a-684c4518db5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341882372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1341882372
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1843695666
Short name T529
Test name
Test status
Simulation time 837185471 ps
CPU time 5.36 seconds
Started Jun 07 07:51:58 PM PDT 24
Finished Jun 07 07:52:05 PM PDT 24
Peak memory 233588 kb
Host smart-36c9cf6e-1888-4178-aeeb-bd58bcb082a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843695666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1843695666
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.661890228
Short name T832
Test name
Test status
Simulation time 251517698 ps
CPU time 2.72 seconds
Started Jun 07 07:52:02 PM PDT 24
Finished Jun 07 07:52:08 PM PDT 24
Peak memory 225380 kb
Host smart-8af50ab8-847a-40c5-b146-dd4c59e5f3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661890228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.661890228
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1137486171
Short name T778
Test name
Test status
Simulation time 7300172236 ps
CPU time 21.57 seconds
Started Jun 07 07:52:04 PM PDT 24
Finished Jun 07 07:52:28 PM PDT 24
Peak memory 220088 kb
Host smart-982bdd65-7ba7-4314-93b9-a7babc8b64ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1137486171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1137486171
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1207165290
Short name T154
Test name
Test status
Simulation time 57739938108 ps
CPU time 352.47 seconds
Started Jun 07 07:52:03 PM PDT 24
Finished Jun 07 07:57:58 PM PDT 24
Peak memory 258304 kb
Host smart-688f6f75-56b4-44e1-9fe4-727b9548ca26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207165290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1207165290
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1811614830
Short name T566
Test name
Test status
Simulation time 15742828633 ps
CPU time 26.66 seconds
Started Jun 07 07:52:01 PM PDT 24
Finished Jun 07 07:52:30 PM PDT 24
Peak memory 217228 kb
Host smart-db6435a7-74c5-420d-abad-2fe0e22d610b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811614830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1811614830
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1485184063
Short name T766
Test name
Test status
Simulation time 2565348732 ps
CPU time 10.93 seconds
Started Jun 07 07:52:02 PM PDT 24
Finished Jun 07 07:52:16 PM PDT 24
Peak memory 217236 kb
Host smart-313b1221-86ab-4712-8135-8dd3aded0805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485184063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1485184063
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1539395476
Short name T803
Test name
Test status
Simulation time 499404230 ps
CPU time 4.8 seconds
Started Jun 07 07:52:01 PM PDT 24
Finished Jun 07 07:52:09 PM PDT 24
Peak memory 217096 kb
Host smart-02ea4932-fe17-4c19-ae3d-9ef2eb8116e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539395476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1539395476
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.328928424
Short name T815
Test name
Test status
Simulation time 78749687 ps
CPU time 0.75 seconds
Started Jun 07 07:52:01 PM PDT 24
Finished Jun 07 07:52:05 PM PDT 24
Peak memory 206660 kb
Host smart-0dbbc663-a39a-4ae6-9560-42e787bf86c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328928424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.328928424
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3968698130
Short name T525
Test name
Test status
Simulation time 82175889709 ps
CPU time 30.5 seconds
Started Jun 07 07:52:00 PM PDT 24
Finished Jun 07 07:52:33 PM PDT 24
Peak memory 233560 kb
Host smart-cfb48672-f480-4e86-a12b-82ab97ecb424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968698130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3968698130
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2236997458
Short name T949
Test name
Test status
Simulation time 22383135 ps
CPU time 0.76 seconds
Started Jun 07 07:52:10 PM PDT 24
Finished Jun 07 07:52:13 PM PDT 24
Peak memory 206624 kb
Host smart-bba969c6-ba63-4e54-810c-59a40206dcc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236997458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2236997458
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3516508476
Short name T839
Test name
Test status
Simulation time 117098835 ps
CPU time 3.79 seconds
Started Jun 07 07:52:02 PM PDT 24
Finished Jun 07 07:52:08 PM PDT 24
Peak memory 233592 kb
Host smart-40b74652-f93b-422e-a24a-9b1f818a9860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516508476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3516508476
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.397014556
Short name T61
Test name
Test status
Simulation time 12828266 ps
CPU time 0.78 seconds
Started Jun 07 07:52:01 PM PDT 24
Finished Jun 07 07:52:05 PM PDT 24
Peak memory 207700 kb
Host smart-37b2ccb5-49b9-41ca-a4a6-4a488d20f22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397014556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.397014556
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1167836452
Short name T51
Test name
Test status
Simulation time 43329032165 ps
CPU time 180.17 seconds
Started Jun 07 07:52:04 PM PDT 24
Finished Jun 07 07:55:06 PM PDT 24
Peak memory 258236 kb
Host smart-4fed854e-84c3-4d5b-95ab-07c2d668f71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167836452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1167836452
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1772871446
Short name T642
Test name
Test status
Simulation time 36532559613 ps
CPU time 348.83 seconds
Started Jun 07 07:52:11 PM PDT 24
Finished Jun 07 07:58:02 PM PDT 24
Peak memory 257204 kb
Host smart-5b1b00f2-dc1a-4423-9a3b-b9e69f464477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772871446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1772871446
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.972546449
Short name T858
Test name
Test status
Simulation time 9645087990 ps
CPU time 18.71 seconds
Started Jun 07 07:52:00 PM PDT 24
Finished Jun 07 07:52:20 PM PDT 24
Peak memory 239848 kb
Host smart-c395871f-484c-43e6-afab-a8ed7b9f5136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972546449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.972546449
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1706479725
Short name T28
Test name
Test status
Simulation time 1020451019 ps
CPU time 10.99 seconds
Started Jun 07 07:52:00 PM PDT 24
Finished Jun 07 07:52:13 PM PDT 24
Peak memory 225352 kb
Host smart-eeafd126-7320-470a-bd19-c11ba2f3dfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706479725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1706479725
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4273126195
Short name T888
Test name
Test status
Simulation time 6331860224 ps
CPU time 20.57 seconds
Started Jun 07 07:52:03 PM PDT 24
Finished Jun 07 07:52:26 PM PDT 24
Peak memory 240332 kb
Host smart-806b4619-bd32-4dde-a4d4-1ab4d3e06dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273126195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4273126195
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1496268692
Short name T648
Test name
Test status
Simulation time 115176525 ps
CPU time 2.22 seconds
Started Jun 07 07:52:01 PM PDT 24
Finished Jun 07 07:52:06 PM PDT 24
Peak memory 224008 kb
Host smart-a8f3f866-e462-44c5-ad05-2bab10f9ed67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496268692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1496268692
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.876525353
Short name T203
Test name
Test status
Simulation time 1723021789 ps
CPU time 7.29 seconds
Started Jun 07 07:52:04 PM PDT 24
Finished Jun 07 07:52:14 PM PDT 24
Peak memory 233348 kb
Host smart-f3f06405-7ae7-48ce-8be3-144bbc7c2d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876525353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.876525353
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3228179734
Short name T859
Test name
Test status
Simulation time 3084352637 ps
CPU time 7.82 seconds
Started Jun 07 07:52:01 PM PDT 24
Finished Jun 07 07:52:11 PM PDT 24
Peak memory 223248 kb
Host smart-bac73e00-a21b-4c17-801b-defa6ee82107
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3228179734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3228179734
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4151328596
Short name T523
Test name
Test status
Simulation time 123322563 ps
CPU time 0.92 seconds
Started Jun 07 07:52:09 PM PDT 24
Finished Jun 07 07:52:11 PM PDT 24
Peak memory 207776 kb
Host smart-c67f7bb3-a8a7-4780-8f3d-82f396df06d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151328596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4151328596
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.22116690
Short name T313
Test name
Test status
Simulation time 930445441 ps
CPU time 14.59 seconds
Started Jun 07 07:52:04 PM PDT 24
Finished Jun 07 07:52:21 PM PDT 24
Peak memory 217120 kb
Host smart-597579ab-4a9f-404e-b237-d65f6aeada8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22116690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.22116690
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3566025746
Short name T384
Test name
Test status
Simulation time 8013615594 ps
CPU time 7.1 seconds
Started Jun 07 07:52:01 PM PDT 24
Finished Jun 07 07:52:11 PM PDT 24
Peak memory 217292 kb
Host smart-8af08fdb-c35b-44e1-9af2-d94591c4695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566025746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3566025746
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2514089581
Short name T757
Test name
Test status
Simulation time 228098354 ps
CPU time 4.99 seconds
Started Jun 07 07:52:03 PM PDT 24
Finished Jun 07 07:52:10 PM PDT 24
Peak memory 217120 kb
Host smart-9f512e85-b7cf-4d50-b3ca-6b360f0f95a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514089581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2514089581
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2229154317
Short name T635
Test name
Test status
Simulation time 70616494 ps
CPU time 0.91 seconds
Started Jun 07 07:52:02 PM PDT 24
Finished Jun 07 07:52:06 PM PDT 24
Peak memory 206656 kb
Host smart-ce42b3e2-3d0f-4bc1-938d-b4972de8e2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229154317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2229154317
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3556605510
Short name T671
Test name
Test status
Simulation time 268954538 ps
CPU time 5.53 seconds
Started Jun 07 07:52:02 PM PDT 24
Finished Jun 07 07:52:11 PM PDT 24
Peak memory 241260 kb
Host smart-a04c4422-a4b4-44d2-8b28-e349e6ab42b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556605510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3556605510
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1122622555
Short name T883
Test name
Test status
Simulation time 30456280 ps
CPU time 2.42 seconds
Started Jun 07 07:52:10 PM PDT 24
Finished Jun 07 07:52:15 PM PDT 24
Peak memory 233360 kb
Host smart-1cd5d8c3-1eea-4b34-90ea-b42619222610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122622555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1122622555
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.656764964
Short name T559
Test name
Test status
Simulation time 18830271 ps
CPU time 0.77 seconds
Started Jun 07 07:52:10 PM PDT 24
Finished Jun 07 07:52:13 PM PDT 24
Peak memory 206704 kb
Host smart-e41c9f60-2aa1-44bb-94bf-fdfda31b169d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656764964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.656764964
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1819872247
Short name T133
Test name
Test status
Simulation time 3630099892 ps
CPU time 85.91 seconds
Started Jun 07 07:52:11 PM PDT 24
Finished Jun 07 07:53:39 PM PDT 24
Peak memory 258248 kb
Host smart-d05c0dd0-1cdb-4486-8696-2a8788e4d557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819872247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1819872247
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1884968714
Short name T298
Test name
Test status
Simulation time 1863800527 ps
CPU time 22.94 seconds
Started Jun 07 07:52:12 PM PDT 24
Finished Jun 07 07:52:37 PM PDT 24
Peak memory 254000 kb
Host smart-5b6dcf9d-13c3-4f70-aefa-36f431dd0e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884968714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1884968714
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1128445360
Short name T770
Test name
Test status
Simulation time 208921698 ps
CPU time 3.86 seconds
Started Jun 07 07:52:10 PM PDT 24
Finished Jun 07 07:52:17 PM PDT 24
Peak memory 233512 kb
Host smart-6ce9a5d9-c044-49f9-a4ac-187de15788cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128445360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1128445360
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1047788572
Short name T244
Test name
Test status
Simulation time 333465212 ps
CPU time 5.38 seconds
Started Jun 07 07:52:10 PM PDT 24
Finished Jun 07 07:52:18 PM PDT 24
Peak memory 233544 kb
Host smart-5d6d63c0-8b6b-41f2-b4d1-d25aa63c2d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047788572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1047788572
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.557657002
Short name T612
Test name
Test status
Simulation time 8750443797 ps
CPU time 31.28 seconds
Started Jun 07 07:52:09 PM PDT 24
Finished Jun 07 07:52:43 PM PDT 24
Peak memory 240408 kb
Host smart-ba67a3ca-94c4-446a-806e-c9242bd75040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557657002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.557657002
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1759328831
Short name T822
Test name
Test status
Simulation time 1234531834 ps
CPU time 4.69 seconds
Started Jun 07 07:52:12 PM PDT 24
Finished Jun 07 07:52:19 PM PDT 24
Peak memory 225324 kb
Host smart-8f25f735-b0f7-4c0f-adf9-33e2f73dccc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759328831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1759328831
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2101029806
Short name T274
Test name
Test status
Simulation time 8451897359 ps
CPU time 7.79 seconds
Started Jun 07 07:52:14 PM PDT 24
Finished Jun 07 07:52:23 PM PDT 24
Peak memory 233672 kb
Host smart-bff38a3d-0a70-4e63-bdca-a396e530c5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101029806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2101029806
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1599014224
Short name T893
Test name
Test status
Simulation time 219878289 ps
CPU time 4.12 seconds
Started Jun 07 07:52:10 PM PDT 24
Finished Jun 07 07:52:16 PM PDT 24
Peak memory 221024 kb
Host smart-b01f041d-6bd4-4554-9fd8-191897b6eba8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1599014224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1599014224
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2416439646
Short name T467
Test name
Test status
Simulation time 9025920693 ps
CPU time 52.79 seconds
Started Jun 07 07:52:10 PM PDT 24
Finished Jun 07 07:53:06 PM PDT 24
Peak memory 218912 kb
Host smart-f528bb58-f659-466c-98ee-8c2c445d063a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416439646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2416439646
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3543761123
Short name T427
Test name
Test status
Simulation time 32038800 ps
CPU time 0.7 seconds
Started Jun 07 07:52:10 PM PDT 24
Finished Jun 07 07:52:13 PM PDT 24
Peak memory 206520 kb
Host smart-1ac9f598-8b7b-47bb-b386-2cd17cbc01cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543761123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3543761123
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2884950086
Short name T47
Test name
Test status
Simulation time 343254229 ps
CPU time 8.86 seconds
Started Jun 07 07:52:09 PM PDT 24
Finished Jun 07 07:52:19 PM PDT 24
Peak memory 217152 kb
Host smart-b990e5ef-911f-4f1e-9ee1-576c5b098f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884950086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2884950086
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.744208500
Short name T363
Test name
Test status
Simulation time 28567628 ps
CPU time 0.71 seconds
Started Jun 07 07:52:10 PM PDT 24
Finished Jun 07 07:52:13 PM PDT 24
Peak memory 206700 kb
Host smart-d85c5639-68b6-4cc0-92db-e34f0f363a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744208500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.744208500
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3582916358
Short name T912
Test name
Test status
Simulation time 7735863143 ps
CPU time 14.53 seconds
Started Jun 07 07:52:11 PM PDT 24
Finished Jun 07 07:52:28 PM PDT 24
Peak memory 249572 kb
Host smart-58759b13-6757-43f6-ad8d-4e20c15b03bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582916358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3582916358
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.273429441
Short name T475
Test name
Test status
Simulation time 37724722 ps
CPU time 0.73 seconds
Started Jun 07 07:52:22 PM PDT 24
Finished Jun 07 07:52:25 PM PDT 24
Peak memory 205684 kb
Host smart-16781811-64de-4fbf-ad90-78b81e631016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273429441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.273429441
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3188551753
Short name T787
Test name
Test status
Simulation time 106477618 ps
CPU time 2.86 seconds
Started Jun 07 07:52:22 PM PDT 24
Finished Jun 07 07:52:27 PM PDT 24
Peak memory 233372 kb
Host smart-4a8dab80-4752-42ef-bc57-4b905d04f6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188551753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3188551753
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.193909754
Short name T872
Test name
Test status
Simulation time 28182118 ps
CPU time 0.81 seconds
Started Jun 07 07:52:13 PM PDT 24
Finished Jun 07 07:52:16 PM PDT 24
Peak memory 207416 kb
Host smart-646743fa-cb9e-476b-8a1b-7eb76c1557d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193909754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.193909754
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.730155646
Short name T925
Test name
Test status
Simulation time 82763766601 ps
CPU time 163.91 seconds
Started Jun 07 07:52:21 PM PDT 24
Finished Jun 07 07:55:06 PM PDT 24
Peak memory 257648 kb
Host smart-bb6715b6-4a55-42b6-8675-d52c20bc8137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730155646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.730155646
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.606491300
Short name T924
Test name
Test status
Simulation time 76769220498 ps
CPU time 183.33 seconds
Started Jun 07 07:52:25 PM PDT 24
Finished Jun 07 07:55:30 PM PDT 24
Peak memory 250392 kb
Host smart-b75c4d60-d46a-484d-a419-c6ae63dc6395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606491300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.606491300
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1906672170
Short name T231
Test name
Test status
Simulation time 179051227663 ps
CPU time 145.5 seconds
Started Jun 07 07:52:22 PM PDT 24
Finished Jun 07 07:54:50 PM PDT 24
Peak memory 254120 kb
Host smart-5662d18f-3bab-4ab5-bbb7-3d5ae48b16a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906672170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1906672170
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1889923406
Short name T395
Test name
Test status
Simulation time 109216196 ps
CPU time 2.95 seconds
Started Jun 07 07:52:22 PM PDT 24
Finished Jun 07 07:52:26 PM PDT 24
Peak memory 233580 kb
Host smart-6816f432-699a-4d6a-9c44-0e72d16e710f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889923406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1889923406
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2812069281
Short name T654
Test name
Test status
Simulation time 749121624 ps
CPU time 8.73 seconds
Started Jun 07 07:52:26 PM PDT 24
Finished Jun 07 07:52:36 PM PDT 24
Peak memory 225380 kb
Host smart-ca1fcc5a-f8c0-4219-a854-068a698b2cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812069281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2812069281
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.177417800
Short name T531
Test name
Test status
Simulation time 3276635335 ps
CPU time 10.83 seconds
Started Jun 07 07:52:23 PM PDT 24
Finished Jun 07 07:52:36 PM PDT 24
Peak memory 225412 kb
Host smart-f434c8c2-4b63-423f-86e8-9a66d3966a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177417800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.177417800
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1409518632
Short name T800
Test name
Test status
Simulation time 3850351002 ps
CPU time 8.62 seconds
Started Jun 07 07:52:09 PM PDT 24
Finished Jun 07 07:52:19 PM PDT 24
Peak memory 241012 kb
Host smart-272f577e-24c1-4130-8b0e-9f1a235ef25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409518632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1409518632
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1528049079
Short name T801
Test name
Test status
Simulation time 423164925 ps
CPU time 2.93 seconds
Started Jun 07 07:52:11 PM PDT 24
Finished Jun 07 07:52:16 PM PDT 24
Peak memory 225276 kb
Host smart-469938f0-3c67-4788-920b-a40ed689f1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528049079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1528049079
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3668263853
Short name T444
Test name
Test status
Simulation time 443968148 ps
CPU time 3.97 seconds
Started Jun 07 07:52:25 PM PDT 24
Finished Jun 07 07:52:30 PM PDT 24
Peak memory 223428 kb
Host smart-10099944-3ca6-439e-8293-8b86ea0df010
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3668263853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3668263853
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.4180405888
Short name T183
Test name
Test status
Simulation time 60316770735 ps
CPU time 137.53 seconds
Started Jun 07 07:52:23 PM PDT 24
Finished Jun 07 07:54:43 PM PDT 24
Peak memory 225512 kb
Host smart-7d018278-8e21-48e4-ba6d-301a08309833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180405888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.4180405888
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.4043921136
Short name T14
Test name
Test status
Simulation time 6927081521 ps
CPU time 26.71 seconds
Started Jun 07 07:52:11 PM PDT 24
Finished Jun 07 07:52:41 PM PDT 24
Peak memory 217324 kb
Host smart-e3611aeb-8743-4d46-9aca-22f60f9e072b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043921136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.4043921136
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2712088996
Short name T81
Test name
Test status
Simulation time 78966168241 ps
CPU time 13.68 seconds
Started Jun 07 07:52:10 PM PDT 24
Finished Jun 07 07:52:26 PM PDT 24
Peak memory 217276 kb
Host smart-d773f554-0a8f-4587-9a57-79981d02edad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712088996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2712088996
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.552610244
Short name T783
Test name
Test status
Simulation time 74710746 ps
CPU time 1.24 seconds
Started Jun 07 07:52:10 PM PDT 24
Finished Jun 07 07:52:13 PM PDT 24
Peak memory 208748 kb
Host smart-46b8c842-1bcd-4429-9397-07dd4bd20f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552610244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.552610244
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2004861238
Short name T86
Test name
Test status
Simulation time 46452045 ps
CPU time 0.85 seconds
Started Jun 07 07:52:12 PM PDT 24
Finished Jun 07 07:52:15 PM PDT 24
Peak memory 206712 kb
Host smart-4d9846a5-a3b0-48a0-9db3-bbbe24ab92b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004861238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2004861238
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3172921546
Short name T486
Test name
Test status
Simulation time 112378728 ps
CPU time 2.38 seconds
Started Jun 07 07:52:21 PM PDT 24
Finished Jun 07 07:52:25 PM PDT 24
Peak memory 225304 kb
Host smart-2abaa810-bd74-41ab-9e2f-7d6b22c7853d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172921546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3172921546
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1862701996
Short name T623
Test name
Test status
Simulation time 92684887 ps
CPU time 0.74 seconds
Started Jun 07 07:52:33 PM PDT 24
Finished Jun 07 07:52:35 PM PDT 24
Peak memory 206232 kb
Host smart-4245b3d4-ef0c-4458-b5d1-9eaa8b409244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862701996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1862701996
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3926480520
Short name T252
Test name
Test status
Simulation time 713651496 ps
CPU time 3.32 seconds
Started Jun 07 07:52:34 PM PDT 24
Finished Jun 07 07:52:39 PM PDT 24
Peak memory 225440 kb
Host smart-1e50b559-aabf-4330-a2bc-e421182e1ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926480520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3926480520
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2195249736
Short name T399
Test name
Test status
Simulation time 55090125 ps
CPU time 0.73 seconds
Started Jun 07 07:52:21 PM PDT 24
Finished Jun 07 07:52:23 PM PDT 24
Peak memory 206344 kb
Host smart-9f5d105a-60a3-419b-9677-cbfa9511f4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195249736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2195249736
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.676420513
Short name T524
Test name
Test status
Simulation time 3502764978 ps
CPU time 61.26 seconds
Started Jun 07 07:52:31 PM PDT 24
Finished Jun 07 07:53:33 PM PDT 24
Peak memory 251140 kb
Host smart-a527a1fe-e16f-4611-9c72-c6996f8f6108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676420513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.676420513
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3341049229
Short name T234
Test name
Test status
Simulation time 7617297673 ps
CPU time 60.68 seconds
Started Jun 07 07:52:34 PM PDT 24
Finished Jun 07 07:53:36 PM PDT 24
Peak memory 225616 kb
Host smart-0ad06157-68d4-4482-8ed5-8a45d02fe6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341049229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3341049229
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.714562446
Short name T190
Test name
Test status
Simulation time 66911782867 ps
CPU time 375.05 seconds
Started Jun 07 07:52:31 PM PDT 24
Finished Jun 07 07:58:47 PM PDT 24
Peak memory 254288 kb
Host smart-d07f4aed-f103-42c2-90e3-39d9f9981c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714562446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.714562446
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1190241437
Short name T602
Test name
Test status
Simulation time 5974175537 ps
CPU time 6.78 seconds
Started Jun 07 07:52:33 PM PDT 24
Finished Jun 07 07:52:41 PM PDT 24
Peak memory 233764 kb
Host smart-86041c73-51ec-4bbf-bb4e-d47c74fe5f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190241437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1190241437
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4245886861
Short name T243
Test name
Test status
Simulation time 1955328984 ps
CPU time 18.52 seconds
Started Jun 07 07:52:23 PM PDT 24
Finished Jun 07 07:52:43 PM PDT 24
Peak memory 225260 kb
Host smart-c5722c06-cb13-4021-85dc-ec9692652b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245886861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4245886861
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1869882038
Short name T102
Test name
Test status
Simulation time 17929595299 ps
CPU time 167.14 seconds
Started Jun 07 07:52:23 PM PDT 24
Finished Jun 07 07:55:12 PM PDT 24
Peak memory 241056 kb
Host smart-e2de15b6-6524-4bd8-bcc4-28228e2bca5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869882038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1869882038
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1335940889
Short name T718
Test name
Test status
Simulation time 455756251 ps
CPU time 3.17 seconds
Started Jun 07 07:52:23 PM PDT 24
Finished Jun 07 07:52:28 PM PDT 24
Peak memory 233544 kb
Host smart-551d0a90-e65d-4c6a-9150-c8ec23ca5c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335940889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1335940889
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2792030600
Short name T567
Test name
Test status
Simulation time 5427980645 ps
CPU time 11.35 seconds
Started Jun 07 07:52:26 PM PDT 24
Finished Jun 07 07:52:38 PM PDT 24
Peak memory 233684 kb
Host smart-031a5f0d-c68e-4209-8f17-83ab3598296d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792030600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2792030600
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3521036780
Short name T735
Test name
Test status
Simulation time 1506093173 ps
CPU time 10.62 seconds
Started Jun 07 07:52:34 PM PDT 24
Finished Jun 07 07:52:46 PM PDT 24
Peak memory 220836 kb
Host smart-8215a5e2-4778-470b-9405-bfb987f7b1d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3521036780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3521036780
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.592018562
Short name T232
Test name
Test status
Simulation time 6568910802 ps
CPU time 112.89 seconds
Started Jun 07 07:52:31 PM PDT 24
Finished Jun 07 07:54:24 PM PDT 24
Peak memory 250036 kb
Host smart-99c8f0e6-ef57-4ae9-8c1b-de0cbb7632d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592018562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.592018562
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.864391264
Short name T619
Test name
Test status
Simulation time 2522172221 ps
CPU time 6.3 seconds
Started Jun 07 07:52:23 PM PDT 24
Finished Jun 07 07:52:31 PM PDT 24
Peak memory 219904 kb
Host smart-c44ead8a-b84c-400d-90a9-44387fc92486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864391264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.864391264
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2176282358
Short name T543
Test name
Test status
Simulation time 75681578453 ps
CPU time 13.52 seconds
Started Jun 07 07:52:26 PM PDT 24
Finished Jun 07 07:52:40 PM PDT 24
Peak memory 217324 kb
Host smart-8b312ded-0b99-40a8-869c-fed301f41227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176282358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2176282358
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1501127779
Short name T670
Test name
Test status
Simulation time 150745436 ps
CPU time 1.28 seconds
Started Jun 07 07:52:24 PM PDT 24
Finished Jun 07 07:52:27 PM PDT 24
Peak memory 208924 kb
Host smart-56e58f21-bdfc-4eb7-9d07-1ad6a616a7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501127779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1501127779
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1986631385
Short name T396
Test name
Test status
Simulation time 185580567 ps
CPU time 1.01 seconds
Started Jun 07 07:52:21 PM PDT 24
Finished Jun 07 07:52:24 PM PDT 24
Peak memory 207744 kb
Host smart-ca89f6e2-8918-44a2-a917-d5d8f016593e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986631385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1986631385
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3173337035
Short name T518
Test name
Test status
Simulation time 3883103533 ps
CPU time 8.44 seconds
Started Jun 07 07:52:24 PM PDT 24
Finished Jun 07 07:52:34 PM PDT 24
Peak memory 241888 kb
Host smart-1aa21490-d780-4a55-840d-de4f4d4681fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173337035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3173337035
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2649810635
Short name T755
Test name
Test status
Simulation time 13651345 ps
CPU time 0.74 seconds
Started Jun 07 07:50:12 PM PDT 24
Finished Jun 07 07:50:15 PM PDT 24
Peak memory 205704 kb
Host smart-4cb5c853-8970-4b9e-8f4b-2a25ecf6fb7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649810635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
649810635
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2601493444
Short name T94
Test name
Test status
Simulation time 415494993 ps
CPU time 6.82 seconds
Started Jun 07 07:50:03 PM PDT 24
Finished Jun 07 07:50:13 PM PDT 24
Peak memory 225252 kb
Host smart-27c58e33-aced-452d-b2d3-d8d2775f2c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601493444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2601493444
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.442400482
Short name T704
Test name
Test status
Simulation time 58443636 ps
CPU time 0.82 seconds
Started Jun 07 07:49:59 PM PDT 24
Finished Jun 07 07:50:03 PM PDT 24
Peak memory 206720 kb
Host smart-c47ea021-5533-4ef0-a222-13345dbfa4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442400482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.442400482
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3436639409
Short name T545
Test name
Test status
Simulation time 9636925738 ps
CPU time 56.92 seconds
Started Jun 07 07:50:11 PM PDT 24
Finished Jun 07 07:51:11 PM PDT 24
Peak memory 239220 kb
Host smart-7fb1cae5-e67f-4958-a90f-b6b6c4de8b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436639409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3436639409
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.239553859
Short name T722
Test name
Test status
Simulation time 16913353350 ps
CPU time 106.76 seconds
Started Jun 07 07:50:09 PM PDT 24
Finished Jun 07 07:51:58 PM PDT 24
Peak memory 266808 kb
Host smart-1389dd9a-c9ba-43e4-ac51-997e8911d536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239553859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.239553859
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.994665231
Short name T410
Test name
Test status
Simulation time 32469041680 ps
CPU time 91.01 seconds
Started Jun 07 07:50:11 PM PDT 24
Finished Jun 07 07:51:44 PM PDT 24
Peak memory 250136 kb
Host smart-572a7930-b441-4924-a603-9e5ce337525e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994665231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
994665231
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2332551499
Short name T842
Test name
Test status
Simulation time 5700950759 ps
CPU time 21.85 seconds
Started Jun 07 07:50:12 PM PDT 24
Finished Jun 07 07:50:36 PM PDT 24
Peak memory 249332 kb
Host smart-4be19eee-0bd0-4304-8515-e395c6e2231b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332551499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2332551499
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2671010304
Short name T661
Test name
Test status
Simulation time 981756123 ps
CPU time 7.61 seconds
Started Jun 07 07:50:00 PM PDT 24
Finished Jun 07 07:50:10 PM PDT 24
Peak memory 233532 kb
Host smart-85018058-8540-4833-b4c2-aaacd3ae173f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671010304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2671010304
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1383362032
Short name T712
Test name
Test status
Simulation time 19758692611 ps
CPU time 35.02 seconds
Started Jun 07 07:50:02 PM PDT 24
Finished Jun 07 07:50:40 PM PDT 24
Peak memory 233704 kb
Host smart-7688a85b-33b9-4797-8dcd-d76de6190642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383362032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1383362032
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2322101497
Short name T277
Test name
Test status
Simulation time 8022089840 ps
CPU time 7.48 seconds
Started Jun 07 07:50:00 PM PDT 24
Finished Jun 07 07:50:10 PM PDT 24
Peak memory 233708 kb
Host smart-d1a1340e-6d5b-48ea-bd48-be2eab8e8d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322101497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2322101497
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2357470194
Short name T31
Test name
Test status
Simulation time 211122760 ps
CPU time 4.97 seconds
Started Jun 07 07:50:01 PM PDT 24
Finished Jun 07 07:50:09 PM PDT 24
Peak memory 235664 kb
Host smart-6ee209ab-8317-4d1e-a088-93a2160b0669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357470194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2357470194
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.4161135728
Short name T369
Test name
Test status
Simulation time 859675921 ps
CPU time 8.33 seconds
Started Jun 07 07:50:10 PM PDT 24
Finished Jun 07 07:50:21 PM PDT 24
Peak memory 223692 kb
Host smart-167b3587-a799-455d-9431-c90a5b138284
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4161135728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.4161135728
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2661869511
Short name T73
Test name
Test status
Simulation time 136103375 ps
CPU time 1.25 seconds
Started Jun 07 07:50:09 PM PDT 24
Finished Jun 07 07:50:13 PM PDT 24
Peak memory 235796 kb
Host smart-b1b5338e-d245-4a21-b88f-2f9cd229e619
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661869511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2661869511
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1568841426
Short name T627
Test name
Test status
Simulation time 191843166 ps
CPU time 0.97 seconds
Started Jun 07 07:50:12 PM PDT 24
Finished Jun 07 07:50:16 PM PDT 24
Peak memory 207716 kb
Host smart-68860f35-0816-452d-a774-1608cfefd7c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568841426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1568841426
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3258088477
Short name T441
Test name
Test status
Simulation time 4771196498 ps
CPU time 19.09 seconds
Started Jun 07 07:50:01 PM PDT 24
Finished Jun 07 07:50:23 PM PDT 24
Peak memory 220676 kb
Host smart-8cc3f2f4-7c59-45a1-90b8-8cd9509aa982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258088477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3258088477
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3353673943
Short name T665
Test name
Test status
Simulation time 28458887 ps
CPU time 0.73 seconds
Started Jun 07 07:50:00 PM PDT 24
Finished Jun 07 07:50:04 PM PDT 24
Peak memory 206608 kb
Host smart-7a8b4ffb-37c9-4363-a7ee-76ca790e7253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353673943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3353673943
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.592359598
Short name T394
Test name
Test status
Simulation time 201784731 ps
CPU time 1.17 seconds
Started Jun 07 07:50:00 PM PDT 24
Finished Jun 07 07:50:04 PM PDT 24
Peak memory 216912 kb
Host smart-4c948243-1cce-4e44-8f84-1b78a7d81266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592359598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.592359598
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4082080854
Short name T683
Test name
Test status
Simulation time 55093078 ps
CPU time 0.81 seconds
Started Jun 07 07:50:00 PM PDT 24
Finished Jun 07 07:50:04 PM PDT 24
Peak memory 206716 kb
Host smart-78795233-33b9-428a-8a42-af36c572f695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082080854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4082080854
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2016935508
Short name T915
Test name
Test status
Simulation time 39361619215 ps
CPU time 40.52 seconds
Started Jun 07 07:50:00 PM PDT 24
Finished Jun 07 07:50:44 PM PDT 24
Peak memory 249936 kb
Host smart-bff49c6c-09bd-4703-b663-f64ab8fadb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016935508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2016935508
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.861695477
Short name T499
Test name
Test status
Simulation time 41180364 ps
CPU time 0.72 seconds
Started Jun 07 07:52:43 PM PDT 24
Finished Jun 07 07:52:45 PM PDT 24
Peak memory 206296 kb
Host smart-92b84d4c-9b48-4dc5-9be8-951f3ba05852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861695477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.861695477
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2593974047
Short name T480
Test name
Test status
Simulation time 201461576 ps
CPU time 5.08 seconds
Started Jun 07 07:52:42 PM PDT 24
Finished Jun 07 07:52:49 PM PDT 24
Peak memory 233492 kb
Host smart-110afd5d-cff1-4c70-98c5-3786eda61e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593974047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2593974047
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2768272826
Short name T496
Test name
Test status
Simulation time 71121517 ps
CPU time 0.82 seconds
Started Jun 07 07:52:34 PM PDT 24
Finished Jun 07 07:52:35 PM PDT 24
Peak memory 207424 kb
Host smart-5fee76ca-b6d1-4600-983c-5836b029921d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768272826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2768272826
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2168964209
Short name T763
Test name
Test status
Simulation time 114907387750 ps
CPU time 181.45 seconds
Started Jun 07 07:52:44 PM PDT 24
Finished Jun 07 07:55:46 PM PDT 24
Peak memory 255328 kb
Host smart-8f547be6-b3c9-44e0-bd51-4a9d5ba17d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168964209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2168964209
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.4033440885
Short name T814
Test name
Test status
Simulation time 21271494548 ps
CPU time 170.37 seconds
Started Jun 07 07:52:41 PM PDT 24
Finished Jun 07 07:55:33 PM PDT 24
Peak memory 250180 kb
Host smart-34a74721-2a56-42cd-837b-e3b265e48812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033440885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.4033440885
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2848195293
Short name T288
Test name
Test status
Simulation time 67041155184 ps
CPU time 446.66 seconds
Started Jun 07 07:52:42 PM PDT 24
Finished Jun 07 08:00:10 PM PDT 24
Peak memory 257200 kb
Host smart-151c08ec-78b8-40f4-a352-7a8e3d8f2aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848195293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2848195293
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_intercept.619683721
Short name T52
Test name
Test status
Simulation time 4340679060 ps
CPU time 8.76 seconds
Started Jun 07 07:52:32 PM PDT 24
Finished Jun 07 07:52:42 PM PDT 24
Peak memory 233776 kb
Host smart-a89de9ae-bb73-4b83-932c-e8511c442b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619683721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.619683721
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2042118112
Short name T348
Test name
Test status
Simulation time 65420550 ps
CPU time 2.68 seconds
Started Jun 07 07:52:41 PM PDT 24
Finished Jun 07 07:52:45 PM PDT 24
Peak memory 233392 kb
Host smart-f529b2ac-b55b-40b1-b4f1-966d27ee9b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042118112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2042118112
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1983726998
Short name T229
Test name
Test status
Simulation time 6898230308 ps
CPU time 8.68 seconds
Started Jun 07 07:52:32 PM PDT 24
Finished Jun 07 07:52:41 PM PDT 24
Peak memory 241444 kb
Host smart-b65d4aa7-c572-4417-8e93-be2cd1231286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983726998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1983726998
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3469026139
Short name T692
Test name
Test status
Simulation time 479697191 ps
CPU time 7.66 seconds
Started Jun 07 07:52:30 PM PDT 24
Finished Jun 07 07:52:39 PM PDT 24
Peak memory 225352 kb
Host smart-d2d90e32-005b-4add-bb9a-b6c17ec62a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469026139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3469026139
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.369490784
Short name T951
Test name
Test status
Simulation time 1066613246 ps
CPU time 8.17 seconds
Started Jun 07 07:52:40 PM PDT 24
Finished Jun 07 07:52:50 PM PDT 24
Peak memory 222704 kb
Host smart-6f68a06a-774a-4dc8-b624-ac23d6f1347a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=369490784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.369490784
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3390207166
Short name T311
Test name
Test status
Simulation time 18283613619 ps
CPU time 26.23 seconds
Started Jun 07 07:52:32 PM PDT 24
Finished Jun 07 07:52:59 PM PDT 24
Peak memory 217212 kb
Host smart-82e20155-b966-4bbe-a00d-73e601694898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390207166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3390207166
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2802894115
Short name T341
Test name
Test status
Simulation time 11504662999 ps
CPU time 16.94 seconds
Started Jun 07 07:52:32 PM PDT 24
Finished Jun 07 07:52:50 PM PDT 24
Peak memory 217168 kb
Host smart-d473f8d8-26ed-4541-8067-eaf8ad9bdd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802894115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2802894115
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3475902121
Short name T82
Test name
Test status
Simulation time 48444031 ps
CPU time 1.22 seconds
Started Jun 07 07:52:34 PM PDT 24
Finished Jun 07 07:52:36 PM PDT 24
Peak memory 217180 kb
Host smart-aea6845c-a179-480a-a2a0-07328f0c1fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475902121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3475902121
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1852413478
Short name T851
Test name
Test status
Simulation time 86998711 ps
CPU time 0.8 seconds
Started Jun 07 07:52:34 PM PDT 24
Finished Jun 07 07:52:36 PM PDT 24
Peak memory 206680 kb
Host smart-380d4fdb-3496-4931-8d1f-0dfebc442401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852413478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1852413478
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1445327174
Short name T753
Test name
Test status
Simulation time 11658297086 ps
CPU time 21.3 seconds
Started Jun 07 07:52:40 PM PDT 24
Finished Jun 07 07:53:03 PM PDT 24
Peak memory 233676 kb
Host smart-f507beca-992d-46be-9776-452a961a1ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445327174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1445327174
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3671008486
Short name T794
Test name
Test status
Simulation time 14764800 ps
CPU time 0.74 seconds
Started Jun 07 07:52:52 PM PDT 24
Finished Jun 07 07:52:53 PM PDT 24
Peak memory 205712 kb
Host smart-0b87e6f7-dc7d-4785-ad1c-3daaf9360c89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671008486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3671008486
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1078330324
Short name T514
Test name
Test status
Simulation time 3121717602 ps
CPU time 8.45 seconds
Started Jun 07 07:52:41 PM PDT 24
Finished Jun 07 07:52:51 PM PDT 24
Peak memory 233704 kb
Host smart-a87d977f-02f2-4218-b624-2f3970db76ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078330324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1078330324
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2542047487
Short name T325
Test name
Test status
Simulation time 27893529 ps
CPU time 0.81 seconds
Started Jun 07 07:52:42 PM PDT 24
Finished Jun 07 07:52:44 PM PDT 24
Peak memory 207404 kb
Host smart-c50e28c6-90ce-4164-a3f0-2a5c82dbf995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542047487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2542047487
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2968883087
Short name T222
Test name
Test status
Simulation time 16906258077 ps
CPU time 57.21 seconds
Started Jun 07 07:52:50 PM PDT 24
Finished Jun 07 07:53:48 PM PDT 24
Peak memory 250380 kb
Host smart-b9ae2a9e-14ea-4353-8bda-d485f12108b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968883087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2968883087
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1317141641
Short name T207
Test name
Test status
Simulation time 2538863005 ps
CPU time 54.07 seconds
Started Jun 07 07:52:49 PM PDT 24
Finished Jun 07 07:53:44 PM PDT 24
Peak memory 254928 kb
Host smart-b2341e9c-d986-42d2-8bfe-5a871fdcf8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317141641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1317141641
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.4001069400
Short name T491
Test name
Test status
Simulation time 145101692 ps
CPU time 4.22 seconds
Started Jun 07 07:52:49 PM PDT 24
Finished Jun 07 07:52:53 PM PDT 24
Peak memory 225292 kb
Host smart-57a82fe7-bcee-4f4b-a401-c012c5f49f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001069400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.4001069400
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1523093951
Short name T191
Test name
Test status
Simulation time 8512929169 ps
CPU time 19.34 seconds
Started Jun 07 07:52:43 PM PDT 24
Finished Jun 07 07:53:03 PM PDT 24
Peak memory 225500 kb
Host smart-d69b4639-e08e-4930-80b2-adcf2099d02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523093951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1523093951
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3746874404
Short name T557
Test name
Test status
Simulation time 3122113121 ps
CPU time 28.87 seconds
Started Jun 07 07:52:40 PM PDT 24
Finished Jun 07 07:53:10 PM PDT 24
Peak memory 225412 kb
Host smart-3b386dea-e637-4306-aeb3-94f88081b4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746874404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3746874404
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1105994786
Short name T334
Test name
Test status
Simulation time 18022931971 ps
CPU time 16.49 seconds
Started Jun 07 07:52:41 PM PDT 24
Finished Jun 07 07:52:59 PM PDT 24
Peak memory 241396 kb
Host smart-a980bb20-19fb-48c4-b7a3-04c399fb8c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105994786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1105994786
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1289295880
Short name T948
Test name
Test status
Simulation time 1490105774 ps
CPU time 9.64 seconds
Started Jun 07 07:52:41 PM PDT 24
Finished Jun 07 07:52:52 PM PDT 24
Peak memory 225388 kb
Host smart-8cce6e68-a257-487e-b4e3-68f5f1fa6fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289295880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1289295880
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2647452690
Short name T797
Test name
Test status
Simulation time 165156562 ps
CPU time 4.07 seconds
Started Jun 07 07:52:49 PM PDT 24
Finished Jun 07 07:52:54 PM PDT 24
Peak memory 221376 kb
Host smart-ce1137e4-869a-440d-89bf-0e90ac14edce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2647452690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2647452690
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3682611834
Short name T643
Test name
Test status
Simulation time 12598398584 ps
CPU time 99.04 seconds
Started Jun 07 07:52:49 PM PDT 24
Finished Jun 07 07:54:30 PM PDT 24
Peak memory 239984 kb
Host smart-415bd897-dcc3-44eb-bf2e-6750efd4685f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682611834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3682611834
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3310733586
Short name T437
Test name
Test status
Simulation time 4749224830 ps
CPU time 25.56 seconds
Started Jun 07 07:52:42 PM PDT 24
Finished Jun 07 07:53:09 PM PDT 24
Peak memory 217380 kb
Host smart-4020c9b0-ab0c-4c7c-b135-dbe8f406a0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310733586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3310733586
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1726396554
Short name T159
Test name
Test status
Simulation time 4218850361 ps
CPU time 13.7 seconds
Started Jun 07 07:52:42 PM PDT 24
Finished Jun 07 07:52:58 PM PDT 24
Peak memory 217304 kb
Host smart-e960c38a-4fa2-45d0-b4e8-7633c329b4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726396554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1726396554
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2242350129
Short name T616
Test name
Test status
Simulation time 167866118 ps
CPU time 1.32 seconds
Started Jun 07 07:52:43 PM PDT 24
Finished Jun 07 07:52:46 PM PDT 24
Peak memory 209016 kb
Host smart-bdb9ee16-e593-4621-8a20-853922f9d088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242350129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2242350129
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1206735249
Short name T618
Test name
Test status
Simulation time 42813089 ps
CPU time 0.78 seconds
Started Jun 07 07:52:41 PM PDT 24
Finished Jun 07 07:52:44 PM PDT 24
Peak memory 206700 kb
Host smart-8589fc4c-7a77-49bb-8a43-cca06f2d163e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206735249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1206735249
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2854673721
Short name T667
Test name
Test status
Simulation time 4878791862 ps
CPU time 11.31 seconds
Started Jun 07 07:52:42 PM PDT 24
Finished Jun 07 07:52:55 PM PDT 24
Peak memory 241812 kb
Host smart-41224e5c-a60c-47ab-86aa-2735f4fe9a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854673721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2854673721
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.928191227
Short name T847
Test name
Test status
Simulation time 14373678 ps
CPU time 0.76 seconds
Started Jun 07 07:52:54 PM PDT 24
Finished Jun 07 07:52:55 PM PDT 24
Peak memory 206212 kb
Host smart-59442dc9-bc6b-41c6-b0af-3c8a28a7ea20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928191227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.928191227
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2821044400
Short name T808
Test name
Test status
Simulation time 416580832 ps
CPU time 2.48 seconds
Started Jun 07 07:52:53 PM PDT 24
Finished Jun 07 07:52:57 PM PDT 24
Peak memory 225332 kb
Host smart-126f538e-771f-404a-8d79-78768401d7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821044400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2821044400
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.175387273
Short name T417
Test name
Test status
Simulation time 43025026 ps
CPU time 0.71 seconds
Started Jun 07 07:52:49 PM PDT 24
Finished Jun 07 07:52:51 PM PDT 24
Peak memory 206696 kb
Host smart-f071debb-e37b-4fa9-9646-3804127a6ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175387273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.175387273
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.491504515
Short name T54
Test name
Test status
Simulation time 16829455582 ps
CPU time 174.42 seconds
Started Jun 07 07:52:54 PM PDT 24
Finished Jun 07 07:55:50 PM PDT 24
Peak memory 253328 kb
Host smart-9e436da3-b68f-4a91-8394-b1d13671336d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491504515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.491504515
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1961109569
Short name T293
Test name
Test status
Simulation time 9092109367 ps
CPU time 158.76 seconds
Started Jun 07 07:52:50 PM PDT 24
Finished Jun 07 07:55:30 PM PDT 24
Peak memory 256216 kb
Host smart-abbc096c-1449-4686-88de-333edd5008db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961109569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1961109569
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1569942463
Short name T687
Test name
Test status
Simulation time 104600985429 ps
CPU time 234.13 seconds
Started Jun 07 07:52:49 PM PDT 24
Finished Jun 07 07:56:45 PM PDT 24
Peak memory 250116 kb
Host smart-9ee5657b-4be0-496f-826e-44ecc96c722e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569942463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1569942463
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2780214201
Short name T512
Test name
Test status
Simulation time 875868641 ps
CPU time 18.06 seconds
Started Jun 07 07:52:49 PM PDT 24
Finished Jun 07 07:53:08 PM PDT 24
Peak memory 236372 kb
Host smart-6c88fae3-68a2-4745-a015-7e904185000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780214201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2780214201
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1137094485
Short name T186
Test name
Test status
Simulation time 8393028314 ps
CPU time 19.1 seconds
Started Jun 07 07:52:50 PM PDT 24
Finished Jun 07 07:53:11 PM PDT 24
Peak memory 225388 kb
Host smart-5a7489ad-4ce0-4e38-9b02-0012589f1610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137094485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1137094485
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3714909040
Short name T944
Test name
Test status
Simulation time 649448957 ps
CPU time 7.82 seconds
Started Jun 07 07:52:53 PM PDT 24
Finished Jun 07 07:53:02 PM PDT 24
Peak memory 233568 kb
Host smart-2d180532-aa7f-4325-8b66-095ce6a43500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714909040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3714909040
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4265082781
Short name T906
Test name
Test status
Simulation time 1338737208 ps
CPU time 5.71 seconds
Started Jun 07 07:52:49 PM PDT 24
Finished Jun 07 07:52:56 PM PDT 24
Peak memory 233580 kb
Host smart-5f3ed156-036b-4fab-82e5-74979da24d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265082781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4265082781
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2418497437
Short name T685
Test name
Test status
Simulation time 1602557869 ps
CPU time 8.52 seconds
Started Jun 07 07:52:51 PM PDT 24
Finished Jun 07 07:53:00 PM PDT 24
Peak memory 225292 kb
Host smart-4186a3aa-ea54-4802-88b7-52d85e06a78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418497437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2418497437
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1632546280
Short name T905
Test name
Test status
Simulation time 422204712 ps
CPU time 5.03 seconds
Started Jun 07 07:52:54 PM PDT 24
Finished Jun 07 07:53:00 PM PDT 24
Peak memory 223972 kb
Host smart-9f80b5a9-9050-4034-823d-0036e2f06453
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1632546280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1632546280
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.202873469
Short name T287
Test name
Test status
Simulation time 94789911112 ps
CPU time 297.83 seconds
Started Jun 07 07:52:48 PM PDT 24
Finished Jun 07 07:57:46 PM PDT 24
Peak memory 266500 kb
Host smart-429e1ffd-d611-4fd7-849b-d1961ecb22c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202873469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.202873469
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1260494285
Short name T911
Test name
Test status
Simulation time 2155559527 ps
CPU time 5.91 seconds
Started Jun 07 07:52:49 PM PDT 24
Finished Jun 07 07:52:56 PM PDT 24
Peak memory 217440 kb
Host smart-c148ff69-e017-4d9c-9ff2-488dcac8a64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260494285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1260494285
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3688190545
Short name T535
Test name
Test status
Simulation time 411658754 ps
CPU time 2.25 seconds
Started Jun 07 07:52:53 PM PDT 24
Finished Jun 07 07:52:56 PM PDT 24
Peak memory 216796 kb
Host smart-bbbc45b6-6589-4921-907b-06593d23ea88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688190545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3688190545
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.4127147985
Short name T952
Test name
Test status
Simulation time 11026474 ps
CPU time 0.71 seconds
Started Jun 07 07:52:50 PM PDT 24
Finished Jun 07 07:52:52 PM PDT 24
Peak memory 206356 kb
Host smart-507d29c7-1a71-4820-b7e3-2bc226227fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127147985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.4127147985
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.440647796
Short name T715
Test name
Test status
Simulation time 17008948 ps
CPU time 0.72 seconds
Started Jun 07 07:52:54 PM PDT 24
Finished Jun 07 07:52:55 PM PDT 24
Peak memory 206584 kb
Host smart-34823c17-d91e-4347-bb86-46d0ac96e52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440647796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.440647796
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3334600148
Short name T209
Test name
Test status
Simulation time 9357652448 ps
CPU time 30.24 seconds
Started Jun 07 07:52:52 PM PDT 24
Finished Jun 07 07:53:23 PM PDT 24
Peak memory 250048 kb
Host smart-977d7b2d-903d-4358-838f-bc9514d65f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334600148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3334600148
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2344600575
Short name T333
Test name
Test status
Simulation time 29168055 ps
CPU time 0.68 seconds
Started Jun 07 07:52:59 PM PDT 24
Finished Jun 07 07:53:00 PM PDT 24
Peak memory 205644 kb
Host smart-43f0f78e-018f-46ee-8944-1abdde3ce25c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344600575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2344600575
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2059399303
Short name T891
Test name
Test status
Simulation time 2310530348 ps
CPU time 14.23 seconds
Started Jun 07 07:53:00 PM PDT 24
Finished Jun 07 07:53:16 PM PDT 24
Peak memory 225312 kb
Host smart-b9db669c-9188-46ac-ada3-b61de8721b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059399303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2059399303
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1636588128
Short name T810
Test name
Test status
Simulation time 22457376 ps
CPU time 0.79 seconds
Started Jun 07 07:52:48 PM PDT 24
Finished Jun 07 07:52:50 PM PDT 24
Peak memory 207376 kb
Host smart-79af6a0d-b796-4599-91af-cced752819b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636588128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1636588128
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3239349208
Short name T936
Test name
Test status
Simulation time 23653155340 ps
CPU time 82.9 seconds
Started Jun 07 07:52:59 PM PDT 24
Finished Jun 07 07:54:24 PM PDT 24
Peak memory 241780 kb
Host smart-635c59d9-16a5-4df4-a76c-c03d9273b60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239349208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3239349208
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2800965016
Short name T210
Test name
Test status
Simulation time 25620751945 ps
CPU time 162.99 seconds
Started Jun 07 07:53:01 PM PDT 24
Finished Jun 07 07:55:45 PM PDT 24
Peak memory 250140 kb
Host smart-e4f3955a-4d32-4937-85da-abbfea6571da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800965016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2800965016
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3734182839
Short name T198
Test name
Test status
Simulation time 47297285712 ps
CPU time 430.72 seconds
Started Jun 07 07:53:02 PM PDT 24
Finished Jun 07 08:00:14 PM PDT 24
Peak memory 266536 kb
Host smart-3cd0d3e1-d5a9-4fd5-8d93-3fc0ef30ee68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734182839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3734182839
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3983991269
Short name T425
Test name
Test status
Simulation time 448654864 ps
CPU time 8.56 seconds
Started Jun 07 07:52:59 PM PDT 24
Finished Jun 07 07:53:08 PM PDT 24
Peak memory 225380 kb
Host smart-838ae2d2-2ba8-44b0-b2b5-ab6182775a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983991269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3983991269
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3010219971
Short name T474
Test name
Test status
Simulation time 134473926 ps
CPU time 4.92 seconds
Started Jun 07 07:52:59 PM PDT 24
Finished Jun 07 07:53:06 PM PDT 24
Peak memory 233572 kb
Host smart-7a52f4f3-fee3-4895-be01-399e06cc8949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010219971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3010219971
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2848459375
Short name T214
Test name
Test status
Simulation time 512235119 ps
CPU time 8.81 seconds
Started Jun 07 07:53:00 PM PDT 24
Finished Jun 07 07:53:10 PM PDT 24
Peak memory 225348 kb
Host smart-e0be990b-aedf-41c1-8372-88cffce55f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848459375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2848459375
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1865536395
Short name T513
Test name
Test status
Simulation time 16848999289 ps
CPU time 6.56 seconds
Started Jun 07 07:52:59 PM PDT 24
Finished Jun 07 07:53:06 PM PDT 24
Peak memory 228924 kb
Host smart-b9782af4-7256-479a-8ba3-e2366f32184d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865536395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1865536395
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1931723903
Short name T609
Test name
Test status
Simulation time 7520569398 ps
CPU time 21.03 seconds
Started Jun 07 07:52:59 PM PDT 24
Finished Jun 07 07:53:21 PM PDT 24
Peak memory 233652 kb
Host smart-17dee2e9-40f6-4176-ae5e-7ae5329cf6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931723903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1931723903
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2344933283
Short name T468
Test name
Test status
Simulation time 476271090 ps
CPU time 4.06 seconds
Started Jun 07 07:53:01 PM PDT 24
Finished Jun 07 07:53:06 PM PDT 24
Peak memory 223380 kb
Host smart-d09c7611-66c8-4f14-a738-d05b3f16cc16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2344933283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2344933283
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2245132017
Short name T283
Test name
Test status
Simulation time 38552426564 ps
CPU time 78.81 seconds
Started Jun 07 07:53:00 PM PDT 24
Finished Jun 07 07:54:20 PM PDT 24
Peak memory 254984 kb
Host smart-dd04d425-8386-44ac-9806-5a141f2230c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245132017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2245132017
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3005839210
Short name T772
Test name
Test status
Simulation time 32488132992 ps
CPU time 46.78 seconds
Started Jun 07 07:52:57 PM PDT 24
Finished Jun 07 07:53:45 PM PDT 24
Peak memory 217368 kb
Host smart-35bc4d88-449f-42b8-bd19-87b3febc9717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005839210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3005839210
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4205369859
Short name T921
Test name
Test status
Simulation time 661334942 ps
CPU time 1.54 seconds
Started Jun 07 07:53:00 PM PDT 24
Finished Jun 07 07:53:03 PM PDT 24
Peak memory 208656 kb
Host smart-ad8acaa4-beb5-46b7-8a3d-3fee7d0fcf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205369859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4205369859
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.418069107
Short name T161
Test name
Test status
Simulation time 1564847432 ps
CPU time 4.37 seconds
Started Jun 07 07:52:59 PM PDT 24
Finished Jun 07 07:53:05 PM PDT 24
Peak memory 217168 kb
Host smart-42ac5078-ad10-4b32-84e1-409a92507282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418069107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.418069107
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.807203373
Short name T749
Test name
Test status
Simulation time 342668883 ps
CPU time 0.88 seconds
Started Jun 07 07:53:03 PM PDT 24
Finished Jun 07 07:53:05 PM PDT 24
Peak memory 206648 kb
Host smart-7ccf051e-cecc-40a2-8b13-178650d9dc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807203373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.807203373
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1353917355
Short name T682
Test name
Test status
Simulation time 488550278 ps
CPU time 5.71 seconds
Started Jun 07 07:52:59 PM PDT 24
Finished Jun 07 07:53:06 PM PDT 24
Peak memory 225312 kb
Host smart-711708a7-8b8a-4872-bd9e-20c8d4d988d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353917355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1353917355
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3558833536
Short name T53
Test name
Test status
Simulation time 11410633 ps
CPU time 0.74 seconds
Started Jun 07 07:53:01 PM PDT 24
Finished Jun 07 07:53:03 PM PDT 24
Peak memory 206620 kb
Host smart-4debd7c9-c2c3-4d2c-9311-a1b2bbf602cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558833536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3558833536
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3732600432
Short name T353
Test name
Test status
Simulation time 134209074 ps
CPU time 2.69 seconds
Started Jun 07 07:52:59 PM PDT 24
Finished Jun 07 07:53:03 PM PDT 24
Peak memory 225368 kb
Host smart-a924d516-9341-49cb-ba3f-fc123225326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732600432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3732600432
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3817968597
Short name T761
Test name
Test status
Simulation time 55499814 ps
CPU time 0.81 seconds
Started Jun 07 07:52:57 PM PDT 24
Finished Jun 07 07:52:58 PM PDT 24
Peak memory 207712 kb
Host smart-3c4e86ff-ca0d-43e6-af68-4c87c3979b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817968597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3817968597
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3359897502
Short name T533
Test name
Test status
Simulation time 2228418283 ps
CPU time 21.4 seconds
Started Jun 07 07:52:59 PM PDT 24
Finished Jun 07 07:53:22 PM PDT 24
Peak memory 239656 kb
Host smart-ed63f739-fa2d-44da-8c59-42bada5d67d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359897502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3359897502
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1546031352
Short name T598
Test name
Test status
Simulation time 12969110303 ps
CPU time 69.15 seconds
Started Jun 07 07:53:01 PM PDT 24
Finished Jun 07 07:54:11 PM PDT 24
Peak memory 250340 kb
Host smart-4101762e-7908-4f71-8f1a-0ea1f8457678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546031352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1546031352
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4089705497
Short name T280
Test name
Test status
Simulation time 8776135902 ps
CPU time 74.16 seconds
Started Jun 07 07:52:58 PM PDT 24
Finished Jun 07 07:54:13 PM PDT 24
Peak memory 250388 kb
Host smart-656e80b6-b6e3-4601-bdca-1cc03b1fa8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089705497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4089705497
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.757023589
Short name T723
Test name
Test status
Simulation time 379970692 ps
CPU time 7.19 seconds
Started Jun 07 07:52:58 PM PDT 24
Finished Jun 07 07:53:06 PM PDT 24
Peak memory 234636 kb
Host smart-eeec40a7-d530-4d00-a0f7-8e3a0e99ff32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757023589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.757023589
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1982207056
Short name T586
Test name
Test status
Simulation time 18011817367 ps
CPU time 12.28 seconds
Started Jun 07 07:53:00 PM PDT 24
Finished Jun 07 07:53:13 PM PDT 24
Peak memory 233692 kb
Host smart-5403ecca-bd48-4dd9-8ca8-d38aa95f61bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982207056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1982207056
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3811800059
Short name T330
Test name
Test status
Simulation time 143007541 ps
CPU time 2.27 seconds
Started Jun 07 07:52:58 PM PDT 24
Finished Jun 07 07:53:01 PM PDT 24
Peak memory 224000 kb
Host smart-79c90752-f966-45ab-82c4-9c97a83e18a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811800059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3811800059
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1395033872
Short name T591
Test name
Test status
Simulation time 32283454892 ps
CPU time 25.32 seconds
Started Jun 07 07:53:00 PM PDT 24
Finished Jun 07 07:53:27 PM PDT 24
Peak memory 233724 kb
Host smart-d85be0a9-81a3-4dca-9eb1-eae83bb361ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395033872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1395033872
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3697844447
Short name T446
Test name
Test status
Simulation time 25082544470 ps
CPU time 5.65 seconds
Started Jun 07 07:53:00 PM PDT 24
Finished Jun 07 07:53:07 PM PDT 24
Peak memory 225404 kb
Host smart-0aedf8c7-d68d-4784-b2b2-8f176d9b3d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697844447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3697844447
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.242611839
Short name T818
Test name
Test status
Simulation time 3310575810 ps
CPU time 3.81 seconds
Started Jun 07 07:53:01 PM PDT 24
Finished Jun 07 07:53:06 PM PDT 24
Peak memory 223484 kb
Host smart-2fdd0c46-d9b7-4fce-a9aa-13071a59dfe0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=242611839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.242611839
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3973305788
Short name T153
Test name
Test status
Simulation time 7402046093 ps
CPU time 155.59 seconds
Started Jun 07 07:53:00 PM PDT 24
Finished Jun 07 07:55:37 PM PDT 24
Peak memory 258332 kb
Host smart-a7a87964-3826-45f9-a527-fac8be9abbe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973305788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3973305788
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3587495235
Short name T940
Test name
Test status
Simulation time 93222194 ps
CPU time 0.72 seconds
Started Jun 07 07:53:02 PM PDT 24
Finished Jun 07 07:53:04 PM PDT 24
Peak memory 206488 kb
Host smart-bcedcbac-4e68-441b-bdf6-e6b975e90bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587495235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3587495235
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.491013308
Short name T490
Test name
Test status
Simulation time 2252024836 ps
CPU time 7.86 seconds
Started Jun 07 07:53:00 PM PDT 24
Finished Jun 07 07:53:10 PM PDT 24
Peak memory 217252 kb
Host smart-9170d3b8-767f-4a7a-921a-b6ab6ebe5f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491013308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.491013308
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1931033870
Short name T516
Test name
Test status
Simulation time 124510944 ps
CPU time 1.62 seconds
Started Jun 07 07:52:59 PM PDT 24
Finished Jun 07 07:53:01 PM PDT 24
Peak memory 208960 kb
Host smart-fc566181-d924-4999-a5f4-05f9a3ff1728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931033870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1931033870
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2305866551
Short name T91
Test name
Test status
Simulation time 42605902 ps
CPU time 0.85 seconds
Started Jun 07 07:53:00 PM PDT 24
Finished Jun 07 07:53:02 PM PDT 24
Peak memory 206676 kb
Host smart-e50549ad-d3e4-47d9-9995-2e2b9e65c139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305866551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2305866551
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3911612400
Short name T739
Test name
Test status
Simulation time 12092405060 ps
CPU time 7.18 seconds
Started Jun 07 07:52:59 PM PDT 24
Finished Jun 07 07:53:07 PM PDT 24
Peak memory 225408 kb
Host smart-939c77ba-0ab1-4f0a-b1d9-1c75937dea61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911612400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3911612400
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1391596523
Short name T760
Test name
Test status
Simulation time 31650150 ps
CPU time 0.71 seconds
Started Jun 07 07:53:08 PM PDT 24
Finished Jun 07 07:53:09 PM PDT 24
Peak memory 206264 kb
Host smart-b81559b8-eb03-479d-a9be-e3ba8db63411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391596523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1391596523
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2976306284
Short name T920
Test name
Test status
Simulation time 1086216058 ps
CPU time 11.93 seconds
Started Jun 07 07:53:11 PM PDT 24
Finished Jun 07 07:53:24 PM PDT 24
Peak memory 225240 kb
Host smart-48eeb70e-31af-4a33-97dc-70ab8872b8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976306284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2976306284
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.160622960
Short name T438
Test name
Test status
Simulation time 21690244 ps
CPU time 0.83 seconds
Started Jun 07 07:53:02 PM PDT 24
Finished Jun 07 07:53:03 PM PDT 24
Peak memory 207448 kb
Host smart-5b80429a-54b5-4bf8-8ed1-4daf38c901d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160622960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.160622960
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2950534102
Short name T771
Test name
Test status
Simulation time 1188292281 ps
CPU time 21 seconds
Started Jun 07 07:53:09 PM PDT 24
Finished Jun 07 07:53:32 PM PDT 24
Peak memory 240428 kb
Host smart-e4455d51-3716-4877-b83b-fab137949c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950534102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2950534102
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.4148654183
Short name T551
Test name
Test status
Simulation time 4077311645 ps
CPU time 38.71 seconds
Started Jun 07 07:53:08 PM PDT 24
Finished Jun 07 07:53:48 PM PDT 24
Peak memory 240332 kb
Host smart-6732ccef-a080-4255-a66f-0623353c267f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148654183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.4148654183
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3655390214
Short name T521
Test name
Test status
Simulation time 1609225783 ps
CPU time 31.06 seconds
Started Jun 07 07:53:10 PM PDT 24
Finished Jun 07 07:53:42 PM PDT 24
Peak memory 233536 kb
Host smart-4bb6bcd1-cb9f-427b-9e8d-4c0e7bed6dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655390214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3655390214
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.4191563821
Short name T146
Test name
Test status
Simulation time 1188301391 ps
CPU time 5.68 seconds
Started Jun 07 07:53:10 PM PDT 24
Finished Jun 07 07:53:17 PM PDT 24
Peak memory 225260 kb
Host smart-4cda6d42-f4a4-49b6-9194-1c9d0f254fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191563821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4191563821
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.4284706459
Short name T95
Test name
Test status
Simulation time 53228836648 ps
CPU time 130.85 seconds
Started Jun 07 07:53:09 PM PDT 24
Finished Jun 07 07:55:21 PM PDT 24
Peak memory 241456 kb
Host smart-cae748a4-2037-4d56-8b25-62a13c4461dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284706459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.4284706459
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3966082500
Short name T868
Test name
Test status
Simulation time 1055280637 ps
CPU time 4.85 seconds
Started Jun 07 07:53:06 PM PDT 24
Finished Jun 07 07:53:12 PM PDT 24
Peak memory 233584 kb
Host smart-aa1ee9f4-f87f-4c38-985d-2446b271a0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966082500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3966082500
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2548217114
Short name T388
Test name
Test status
Simulation time 211381445 ps
CPU time 2.5 seconds
Started Jun 07 07:53:10 PM PDT 24
Finished Jun 07 07:53:14 PM PDT 24
Peak memory 225208 kb
Host smart-0ae5671f-3e6f-4981-a51c-04de3fbff620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548217114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2548217114
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.301735131
Short name T679
Test name
Test status
Simulation time 697969349 ps
CPU time 4.39 seconds
Started Jun 07 07:53:06 PM PDT 24
Finished Jun 07 07:53:11 PM PDT 24
Peak memory 220164 kb
Host smart-32d7c599-f511-4793-ba7e-e7d251e9bbe0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=301735131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.301735131
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3985931832
Short name T316
Test name
Test status
Simulation time 3599865571 ps
CPU time 19.12 seconds
Started Jun 07 07:52:59 PM PDT 24
Finished Jun 07 07:53:19 PM PDT 24
Peak memory 217328 kb
Host smart-55c3b184-7f31-4f64-b5aa-7b8ab718e60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985931832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3985931832
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1100907657
Short name T360
Test name
Test status
Simulation time 7887391163 ps
CPU time 22.06 seconds
Started Jun 07 07:52:57 PM PDT 24
Finished Jun 07 07:53:20 PM PDT 24
Peak memory 217252 kb
Host smart-74281c1c-8527-416e-ba68-d8597d5ee258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100907657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1100907657
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1656711986
Short name T534
Test name
Test status
Simulation time 245839728 ps
CPU time 1.96 seconds
Started Jun 07 07:53:08 PM PDT 24
Finished Jun 07 07:53:12 PM PDT 24
Peak memory 217124 kb
Host smart-4c9dda50-f172-4561-8317-967ee41644da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656711986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1656711986
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2356151115
Short name T402
Test name
Test status
Simulation time 28689468 ps
CPU time 0.83 seconds
Started Jun 07 07:52:59 PM PDT 24
Finished Jun 07 07:53:02 PM PDT 24
Peak memory 206696 kb
Host smart-bf5ce490-8f83-44fd-83f2-604cb3237af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356151115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2356151115
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4272000571
Short name T700
Test name
Test status
Simulation time 1570475765 ps
CPU time 11.15 seconds
Started Jun 07 07:53:09 PM PDT 24
Finished Jun 07 07:53:21 PM PDT 24
Peak memory 233588 kb
Host smart-10a8fc35-657f-4d21-960b-e7e7071731a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272000571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4272000571
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2290880283
Short name T792
Test name
Test status
Simulation time 19504167 ps
CPU time 0.74 seconds
Started Jun 07 07:53:23 PM PDT 24
Finished Jun 07 07:53:26 PM PDT 24
Peak memory 206624 kb
Host smart-5f6badd3-d2d1-4ec2-a478-676d90ebc35e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290880283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2290880283
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3847305499
Short name T344
Test name
Test status
Simulation time 18247264 ps
CPU time 0.8 seconds
Started Jun 07 07:53:09 PM PDT 24
Finished Jun 07 07:53:11 PM PDT 24
Peak memory 207276 kb
Host smart-58c01aab-d763-4a53-9f68-afda37622e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847305499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3847305499
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3158211217
Short name T371
Test name
Test status
Simulation time 29983422697 ps
CPU time 53.83 seconds
Started Jun 07 07:53:20 PM PDT 24
Finished Jun 07 07:54:16 PM PDT 24
Peak memory 250336 kb
Host smart-16de7c3e-8789-41af-ada1-5cb93c54196e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158211217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3158211217
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.4266172885
Short name T652
Test name
Test status
Simulation time 2247634828 ps
CPU time 37.16 seconds
Started Jun 07 07:53:20 PM PDT 24
Finished Jun 07 07:53:59 PM PDT 24
Peak memory 250124 kb
Host smart-a1bb5c77-4d30-4ac0-a895-e2e2e50f0464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266172885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.4266172885
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.710461624
Short name T860
Test name
Test status
Simulation time 85983642 ps
CPU time 5.54 seconds
Started Jun 07 07:53:21 PM PDT 24
Finished Jun 07 07:53:29 PM PDT 24
Peak memory 233540 kb
Host smart-81d60c96-12d5-4f58-acab-2a90bcd0de64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710461624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.710461624
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1461316068
Short name T158
Test name
Test status
Simulation time 753241459 ps
CPU time 9.13 seconds
Started Jun 07 07:53:08 PM PDT 24
Finished Jun 07 07:53:19 PM PDT 24
Peak memory 225332 kb
Host smart-5a4eb3f9-4d0a-43be-b0d2-f23465078d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461316068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1461316068
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.729153322
Short name T495
Test name
Test status
Simulation time 13708149930 ps
CPU time 112.51 seconds
Started Jun 07 07:53:07 PM PDT 24
Finished Jun 07 07:55:01 PM PDT 24
Peak memory 233640 kb
Host smart-39a7d9b1-848c-4ea1-b0b3-88207f047cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729153322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.729153322
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3402763492
Short name T510
Test name
Test status
Simulation time 1990517614 ps
CPU time 5.75 seconds
Started Jun 07 07:53:09 PM PDT 24
Finished Jun 07 07:53:17 PM PDT 24
Peak memory 233564 kb
Host smart-4530f60e-bb85-4f0a-95b1-a7652fb8d1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402763492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3402763492
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2075662703
Short name T201
Test name
Test status
Simulation time 23553261568 ps
CPU time 16.04 seconds
Started Jun 07 07:53:10 PM PDT 24
Finished Jun 07 07:53:27 PM PDT 24
Peak memory 225208 kb
Host smart-99a2b657-7ce5-4426-93ab-44063b83f58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075662703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2075662703
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3006365255
Short name T579
Test name
Test status
Simulation time 2526800108 ps
CPU time 8.67 seconds
Started Jun 07 07:53:20 PM PDT 24
Finished Jun 07 07:53:30 PM PDT 24
Peak memory 223884 kb
Host smart-78db8f95-ea3f-4b27-bbc1-16a9a4c45f88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3006365255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3006365255
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2685065037
Short name T24
Test name
Test status
Simulation time 43285853151 ps
CPU time 490.62 seconds
Started Jun 07 07:53:21 PM PDT 24
Finished Jun 07 08:01:34 PM PDT 24
Peak memory 274476 kb
Host smart-178fbd75-e447-4336-9f03-b845d0052378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685065037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2685065037
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.673030534
Short name T498
Test name
Test status
Simulation time 14770570 ps
CPU time 0.75 seconds
Started Jun 07 07:53:08 PM PDT 24
Finished Jun 07 07:53:09 PM PDT 24
Peak memory 206512 kb
Host smart-8c593cdf-30f2-4994-8df9-afd4a13df4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673030534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.673030534
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2099492202
Short name T379
Test name
Test status
Simulation time 395303984 ps
CPU time 1.38 seconds
Started Jun 07 07:53:07 PM PDT 24
Finished Jun 07 07:53:09 PM PDT 24
Peak memory 208600 kb
Host smart-1f6d55fd-4936-4dd5-9060-a15a907f0309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099492202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2099492202
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.203538451
Short name T762
Test name
Test status
Simulation time 41825019 ps
CPU time 1.3 seconds
Started Jun 07 07:53:09 PM PDT 24
Finished Jun 07 07:53:12 PM PDT 24
Peak memory 216940 kb
Host smart-7df2600f-7abe-4ec9-ac5e-8c4448ee4316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203538451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.203538451
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1274557099
Short name T386
Test name
Test status
Simulation time 109515050 ps
CPU time 0.9 seconds
Started Jun 07 07:53:07 PM PDT 24
Finished Jun 07 07:53:09 PM PDT 24
Peak memory 206680 kb
Host smart-4d19020f-fc9e-4c9f-8ed7-a427538a203a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274557099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1274557099
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2562497468
Short name T588
Test name
Test status
Simulation time 144503687 ps
CPU time 2.21 seconds
Started Jun 07 07:53:08 PM PDT 24
Finished Jun 07 07:53:11 PM PDT 24
Peak memory 225088 kb
Host smart-24c54444-c77e-48c2-8f59-25c3d33814eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562497468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2562497468
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1607236110
Short name T456
Test name
Test status
Simulation time 46067401 ps
CPU time 0.74 seconds
Started Jun 07 07:53:30 PM PDT 24
Finished Jun 07 07:53:35 PM PDT 24
Peak memory 205696 kb
Host smart-132e02ff-49c8-43d8-90e9-4f480a1be7fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607236110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1607236110
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1824976116
Short name T646
Test name
Test status
Simulation time 2216014096 ps
CPU time 4.67 seconds
Started Jun 07 07:53:20 PM PDT 24
Finished Jun 07 07:53:26 PM PDT 24
Peak memory 233712 kb
Host smart-7953fec1-cff0-422e-b80d-fd94282554fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824976116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1824976116
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1080803569
Short name T754
Test name
Test status
Simulation time 18090465 ps
CPU time 0.8 seconds
Started Jun 07 07:53:21 PM PDT 24
Finished Jun 07 07:53:24 PM PDT 24
Peak memory 207364 kb
Host smart-0f9c7b74-fbd2-4380-8be7-ef5761d4d0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080803569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1080803569
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.632623872
Short name T170
Test name
Test status
Simulation time 44731817701 ps
CPU time 116.48 seconds
Started Jun 07 07:53:33 PM PDT 24
Finished Jun 07 07:55:33 PM PDT 24
Peak memory 250172 kb
Host smart-fd8415fa-ab00-40a9-a8ba-6a36e6a040e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632623872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.632623872
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.225689751
Short name T869
Test name
Test status
Simulation time 5635315354 ps
CPU time 22.79 seconds
Started Jun 07 07:53:32 PM PDT 24
Finished Jun 07 07:53:58 PM PDT 24
Peak memory 218468 kb
Host smart-d273bf4b-b278-4dd9-b447-7814aa39d61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225689751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.225689751
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3195211548
Short name T130
Test name
Test status
Simulation time 2763887986 ps
CPU time 63.22 seconds
Started Jun 07 07:53:32 PM PDT 24
Finished Jun 07 07:54:39 PM PDT 24
Peak memory 250104 kb
Host smart-6a735589-221a-4c0a-a902-89cfce6de825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195211548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3195211548
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2990202723
Short name T142
Test name
Test status
Simulation time 760924528 ps
CPU time 10.87 seconds
Started Jun 07 07:53:30 PM PDT 24
Finished Jun 07 07:53:45 PM PDT 24
Peak memory 225352 kb
Host smart-e6299bc1-90cd-4831-b071-cb1b45c76855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990202723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2990202723
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.142808971
Short name T199
Test name
Test status
Simulation time 518131630 ps
CPU time 6.85 seconds
Started Jun 07 07:53:23 PM PDT 24
Finished Jun 07 07:53:33 PM PDT 24
Peak memory 225292 kb
Host smart-4f216eb8-f440-42c9-b668-3cddbb9dfa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142808971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.142808971
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3591660241
Short name T322
Test name
Test status
Simulation time 56207461 ps
CPU time 2.18 seconds
Started Jun 07 07:53:21 PM PDT 24
Finished Jun 07 07:53:26 PM PDT 24
Peak memory 223700 kb
Host smart-3234c66f-5f7f-4042-b7c7-0acfed30430d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591660241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3591660241
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.790747421
Short name T295
Test name
Test status
Simulation time 22267796092 ps
CPU time 17.96 seconds
Started Jun 07 07:53:21 PM PDT 24
Finished Jun 07 07:53:41 PM PDT 24
Peak memory 233696 kb
Host smart-8cb185a1-e138-4138-9298-4a921db30679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790747421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.790747421
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3733731745
Short name T706
Test name
Test status
Simulation time 306222229 ps
CPU time 3.63 seconds
Started Jun 07 07:53:20 PM PDT 24
Finished Jun 07 07:53:25 PM PDT 24
Peak memory 225416 kb
Host smart-7959dc03-d994-45a0-89c0-0789b9a4221d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733731745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3733731745
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.236601004
Short name T139
Test name
Test status
Simulation time 1337195323 ps
CPU time 10.69 seconds
Started Jun 07 07:53:33 PM PDT 24
Finished Jun 07 07:53:48 PM PDT 24
Peak memory 221348 kb
Host smart-3a4c4ee4-b52c-433d-afb7-10647017b8fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=236601004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.236601004
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.591856051
Short name T568
Test name
Test status
Simulation time 10000377759 ps
CPU time 134.36 seconds
Started Jun 07 07:53:31 PM PDT 24
Finished Jun 07 07:55:49 PM PDT 24
Peak memory 252148 kb
Host smart-5d3c7352-ac50-49be-b1a4-19b2491cc1d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591856051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.591856051
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1077969256
Short name T527
Test name
Test status
Simulation time 2526271337 ps
CPU time 22.38 seconds
Started Jun 07 07:53:22 PM PDT 24
Finished Jun 07 07:53:47 PM PDT 24
Peak memory 217696 kb
Host smart-0ecbcde4-5438-464e-a550-7937524d1aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077969256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1077969256
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3211153319
Short name T373
Test name
Test status
Simulation time 42351928 ps
CPU time 0.74 seconds
Started Jun 07 07:53:21 PM PDT 24
Finished Jun 07 07:53:24 PM PDT 24
Peak memory 206508 kb
Host smart-9ebbf4e9-e777-47ea-ad7a-5b52f4f9b8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211153319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3211153319
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1099943591
Short name T658
Test name
Test status
Simulation time 50204098 ps
CPU time 0.75 seconds
Started Jun 07 07:53:22 PM PDT 24
Finished Jun 07 07:53:26 PM PDT 24
Peak memory 206712 kb
Host smart-ed32d2a8-0343-4f80-ab45-003908f2976c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099943591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1099943591
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.27983912
Short name T92
Test name
Test status
Simulation time 41073988 ps
CPU time 0.82 seconds
Started Jun 07 07:53:20 PM PDT 24
Finished Jun 07 07:53:22 PM PDT 24
Peak memory 206692 kb
Host smart-f1f63944-92c1-4bae-b31e-cab566a9eef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27983912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.27983912
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1103308753
Short name T450
Test name
Test status
Simulation time 17062756882 ps
CPU time 12.54 seconds
Started Jun 07 07:53:19 PM PDT 24
Finished Jun 07 07:53:33 PM PDT 24
Peak memory 225436 kb
Host smart-ff2c92d8-8469-464f-8364-6ef25e701b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103308753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1103308753
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.572639159
Short name T777
Test name
Test status
Simulation time 17057206 ps
CPU time 0.72 seconds
Started Jun 07 07:53:40 PM PDT 24
Finished Jun 07 07:53:44 PM PDT 24
Peak memory 206600 kb
Host smart-16f52177-a0da-44eb-a35e-d80b6c461f82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572639159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.572639159
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3180002559
Short name T10
Test name
Test status
Simulation time 1472523360 ps
CPU time 6.2 seconds
Started Jun 07 07:53:31 PM PDT 24
Finished Jun 07 07:53:42 PM PDT 24
Peak memory 233496 kb
Host smart-7bb029dd-0ed9-4bfc-a82d-c7a5d807b256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180002559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3180002559
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2834838426
Short name T853
Test name
Test status
Simulation time 20776360 ps
CPU time 0.8 seconds
Started Jun 07 07:53:29 PM PDT 24
Finished Jun 07 07:53:34 PM PDT 24
Peak memory 207680 kb
Host smart-f4a6149d-de05-415e-adae-26c0294951ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834838426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2834838426
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3211558569
Short name T663
Test name
Test status
Simulation time 84003619065 ps
CPU time 289.18 seconds
Started Jun 07 07:53:31 PM PDT 24
Finished Jun 07 07:58:24 PM PDT 24
Peak memory 255184 kb
Host smart-1b4d89a7-3085-431a-b5ae-a977ca4c4e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211558569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3211558569
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2985475011
Short name T824
Test name
Test status
Simulation time 4244686117 ps
CPU time 33.3 seconds
Started Jun 07 07:53:32 PM PDT 24
Finished Jun 07 07:54:09 PM PDT 24
Peak memory 225484 kb
Host smart-ace24d03-522e-4c33-acf5-34921e6a1baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985475011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2985475011
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3782394509
Short name T162
Test name
Test status
Simulation time 1916344964 ps
CPU time 29.32 seconds
Started Jun 07 07:53:29 PM PDT 24
Finished Jun 07 07:54:01 PM PDT 24
Peak memory 241692 kb
Host smart-7a15053f-d254-4390-b343-a2bc72c5ef94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782394509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3782394509
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3152276754
Short name T878
Test name
Test status
Simulation time 631651362 ps
CPU time 5.04 seconds
Started Jun 07 07:53:32 PM PDT 24
Finished Jun 07 07:53:41 PM PDT 24
Peak memory 233488 kb
Host smart-77b69ea8-e5ef-485c-bb5d-9005fe1fc24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152276754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3152276754
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2882844264
Short name T349
Test name
Test status
Simulation time 182678673 ps
CPU time 2.15 seconds
Started Jun 07 07:53:30 PM PDT 24
Finished Jun 07 07:53:35 PM PDT 24
Peak memory 224088 kb
Host smart-b02b0789-0684-4c59-bae5-95e66c98d8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882844264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2882844264
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3776270868
Short name T29
Test name
Test status
Simulation time 4352353800 ps
CPU time 15.53 seconds
Started Jun 07 07:53:30 PM PDT 24
Finished Jun 07 07:53:50 PM PDT 24
Peak memory 241336 kb
Host smart-dd2e8e55-f653-4eea-ac7f-f1f67d7f2e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776270868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3776270868
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1578701293
Short name T239
Test name
Test status
Simulation time 3124887604 ps
CPU time 7.16 seconds
Started Jun 07 07:53:31 PM PDT 24
Finished Jun 07 07:53:43 PM PDT 24
Peak memory 241800 kb
Host smart-d8d9d14c-1835-483b-887f-5c9203469d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578701293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1578701293
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1392787317
Short name T555
Test name
Test status
Simulation time 3232688362 ps
CPU time 6.31 seconds
Started Jun 07 07:53:33 PM PDT 24
Finished Jun 07 07:53:43 PM PDT 24
Peak memory 223948 kb
Host smart-ac313ada-4d82-435e-b5d4-85148e6d94c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1392787317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1392787317
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.221810526
Short name T13
Test name
Test status
Simulation time 292775938 ps
CPU time 2.12 seconds
Started Jun 07 07:53:31 PM PDT 24
Finished Jun 07 07:53:37 PM PDT 24
Peak memory 216948 kb
Host smart-1ed0579d-2644-499f-9589-dcf6c008c8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221810526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.221810526
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.715601961
Short name T9
Test name
Test status
Simulation time 90788352 ps
CPU time 2.07 seconds
Started Jun 07 07:53:31 PM PDT 24
Finished Jun 07 07:53:38 PM PDT 24
Peak memory 217076 kb
Host smart-5c51a9a5-5b05-43ca-b235-a855bd7149dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715601961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.715601961
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.495624463
Short name T368
Test name
Test status
Simulation time 31524146 ps
CPU time 0.73 seconds
Started Jun 07 07:53:33 PM PDT 24
Finished Jun 07 07:53:37 PM PDT 24
Peak memory 206744 kb
Host smart-ca14995d-b28c-4cfc-9cb7-2a49ddc35290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495624463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.495624463
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3459049182
Short name T520
Test name
Test status
Simulation time 3706386289 ps
CPU time 5.89 seconds
Started Jun 07 07:53:32 PM PDT 24
Finished Jun 07 07:53:41 PM PDT 24
Peak memory 225512 kb
Host smart-acf47c15-b658-4ecd-8b54-aef01260624a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459049182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3459049182
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.263426607
Short name T339
Test name
Test status
Simulation time 21998953 ps
CPU time 0.74 seconds
Started Jun 07 07:53:40 PM PDT 24
Finished Jun 07 07:53:45 PM PDT 24
Peak memory 206624 kb
Host smart-1d077485-ef81-4a6a-bcc2-8c0a101ce09b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263426607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.263426607
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2486938721
Short name T876
Test name
Test status
Simulation time 538538018 ps
CPU time 4.86 seconds
Started Jun 07 07:53:40 PM PDT 24
Finished Jun 07 07:53:49 PM PDT 24
Peak memory 225404 kb
Host smart-73076681-8336-4edb-a05e-d71534670594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486938721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2486938721
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3108018724
Short name T324
Test name
Test status
Simulation time 20931435 ps
CPU time 0.81 seconds
Started Jun 07 07:53:43 PM PDT 24
Finished Jun 07 07:53:47 PM PDT 24
Peak memory 207428 kb
Host smart-849e57d8-d7ad-4284-984e-c8790d0d3ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108018724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3108018724
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1004688363
Short name T261
Test name
Test status
Simulation time 54626199401 ps
CPU time 382.96 seconds
Started Jun 07 07:53:44 PM PDT 24
Finished Jun 07 08:00:10 PM PDT 24
Peak memory 250116 kb
Host smart-da74642c-6668-41f0-92bc-5699835b8e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004688363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1004688363
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3843841006
Short name T601
Test name
Test status
Simulation time 21309832829 ps
CPU time 199.96 seconds
Started Jun 07 07:53:42 PM PDT 24
Finished Jun 07 07:57:06 PM PDT 24
Peak memory 250168 kb
Host smart-51397bc1-f5da-4f47-be0e-8a7212c6d54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843841006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3843841006
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2917791830
Short name T251
Test name
Test status
Simulation time 4548517640 ps
CPU time 12.73 seconds
Started Jun 07 07:53:41 PM PDT 24
Finished Jun 07 07:53:57 PM PDT 24
Peak memory 233704 kb
Host smart-971fd22c-ae19-4dfe-a384-7c526218e5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917791830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2917791830
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.721364027
Short name T730
Test name
Test status
Simulation time 1982667046 ps
CPU time 32.27 seconds
Started Jun 07 07:53:42 PM PDT 24
Finished Jun 07 07:54:18 PM PDT 24
Peak memory 225296 kb
Host smart-b9feecca-b3d0-4490-9a30-b5168d4859bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721364027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.721364027
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.4208218315
Short name T56
Test name
Test status
Simulation time 65801240 ps
CPU time 2.44 seconds
Started Jun 07 07:53:40 PM PDT 24
Finished Jun 07 07:53:46 PM PDT 24
Peak memory 233552 kb
Host smart-d9f3f4ec-fc2e-4548-b6ad-ac9250d74a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208218315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4208218315
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.247525711
Short name T235
Test name
Test status
Simulation time 7848170686 ps
CPU time 31.08 seconds
Started Jun 07 07:53:42 PM PDT 24
Finished Jun 07 07:54:17 PM PDT 24
Peak memory 225412 kb
Host smart-a3837546-ff00-466e-8922-7b2aa738f956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247525711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.247525711
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1866921879
Short name T269
Test name
Test status
Simulation time 55136466525 ps
CPU time 44.14 seconds
Started Jun 07 07:53:40 PM PDT 24
Finished Jun 07 07:54:28 PM PDT 24
Peak memory 249488 kb
Host smart-f2b6d50e-beb3-4ea3-97ba-0461b44cb93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866921879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1866921879
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1516999502
Short name T902
Test name
Test status
Simulation time 208191103 ps
CPU time 4.35 seconds
Started Jun 07 07:53:42 PM PDT 24
Finished Jun 07 07:53:50 PM PDT 24
Peak memory 225376 kb
Host smart-ac8b3951-a9b4-4434-b55e-803ff061382d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516999502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1516999502
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.220462693
Short name T782
Test name
Test status
Simulation time 4232299020 ps
CPU time 16.93 seconds
Started Jun 07 07:53:40 PM PDT 24
Finished Jun 07 07:54:01 PM PDT 24
Peak memory 220004 kb
Host smart-8750e7ba-4836-4883-8ae0-32d72a86c1af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=220462693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.220462693
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1947759774
Short name T503
Test name
Test status
Simulation time 2253401976 ps
CPU time 24.88 seconds
Started Jun 07 07:53:44 PM PDT 24
Finished Jun 07 07:54:12 PM PDT 24
Peak memory 217524 kb
Host smart-19bbcd7e-4229-4f10-97b8-7d743eb2bca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947759774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1947759774
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2278303402
Short name T489
Test name
Test status
Simulation time 1513687748 ps
CPU time 5.87 seconds
Started Jun 07 07:53:42 PM PDT 24
Finished Jun 07 07:53:51 PM PDT 24
Peak memory 217108 kb
Host smart-71f7aa19-01a4-4644-83bc-4c27fd0923ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278303402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2278303402
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3358643662
Short name T440
Test name
Test status
Simulation time 364727707 ps
CPU time 3.78 seconds
Started Jun 07 07:53:44 PM PDT 24
Finished Jun 07 07:53:51 PM PDT 24
Peak memory 217132 kb
Host smart-616142c6-9d51-4f1b-ac9a-628833a07bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358643662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3358643662
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1758624606
Short name T854
Test name
Test status
Simulation time 214377163 ps
CPU time 0.73 seconds
Started Jun 07 07:53:42 PM PDT 24
Finished Jun 07 07:53:46 PM PDT 24
Peak memory 206724 kb
Host smart-baed900c-8147-4a8e-b1f0-20768ed25411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758624606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1758624606
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1003145196
Short name T561
Test name
Test status
Simulation time 438767676 ps
CPU time 2.56 seconds
Started Jun 07 07:53:41 PM PDT 24
Finished Jun 07 07:53:48 PM PDT 24
Peak memory 225312 kb
Host smart-61b7423f-d2f5-443f-a874-5f3812121adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003145196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1003145196
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.947898967
Short name T337
Test name
Test status
Simulation time 59166312 ps
CPU time 0.72 seconds
Started Jun 07 07:50:20 PM PDT 24
Finished Jun 07 07:50:25 PM PDT 24
Peak memory 205672 kb
Host smart-9bb9a891-d4bb-4afa-a1ae-15998002abb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947898967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.947898967
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1080372306
Short name T458
Test name
Test status
Simulation time 560316456 ps
CPU time 4.23 seconds
Started Jun 07 07:50:12 PM PDT 24
Finished Jun 07 07:50:19 PM PDT 24
Peak memory 225276 kb
Host smart-bef14a95-dcf1-4070-b032-05e0a8e4420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080372306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1080372306
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2965948623
Short name T575
Test name
Test status
Simulation time 24651690 ps
CPU time 0.76 seconds
Started Jun 07 07:50:12 PM PDT 24
Finished Jun 07 07:50:16 PM PDT 24
Peak memory 206392 kb
Host smart-c740dfc0-3fe9-43b7-a062-480b7f342ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965948623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2965948623
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.649835050
Short name T834
Test name
Test status
Simulation time 57365041948 ps
CPU time 358.37 seconds
Started Jun 07 07:50:11 PM PDT 24
Finished Jun 07 07:56:11 PM PDT 24
Peak memory 239076 kb
Host smart-94b1f288-e9d3-4008-bb2c-54a6871df58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649835050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.649835050
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4135749661
Short name T217
Test name
Test status
Simulation time 16341971234 ps
CPU time 140.09 seconds
Started Jun 07 07:50:11 PM PDT 24
Finished Jun 07 07:52:34 PM PDT 24
Peak memory 274292 kb
Host smart-fed83cdf-145a-48a8-ad35-237f4bbba9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135749661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4135749661
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3925744838
Short name T230
Test name
Test status
Simulation time 1101027456 ps
CPU time 17.55 seconds
Started Jun 07 07:50:21 PM PDT 24
Finished Jun 07 07:50:43 PM PDT 24
Peak memory 241796 kb
Host smart-5b3a12a0-b93e-4505-9f0f-ebc1bbbf22ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925744838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3925744838
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3249537711
Short name T678
Test name
Test status
Simulation time 336725757 ps
CPU time 7.69 seconds
Started Jun 07 07:50:12 PM PDT 24
Finished Jun 07 07:50:23 PM PDT 24
Peak memory 225324 kb
Host smart-0415970d-57ee-45be-80e7-db465d914007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249537711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3249537711
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.943172298
Short name T553
Test name
Test status
Simulation time 2015556289 ps
CPU time 17.94 seconds
Started Jun 07 07:50:12 PM PDT 24
Finished Jun 07 07:50:32 PM PDT 24
Peak memory 225400 kb
Host smart-d00100c3-71bd-44c3-a11d-76bb1191359f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943172298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.943172298
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3652123074
Short name T215
Test name
Test status
Simulation time 20823122373 ps
CPU time 28.84 seconds
Started Jun 07 07:50:11 PM PDT 24
Finished Jun 07 07:50:43 PM PDT 24
Peak memory 238336 kb
Host smart-8cea07f6-6c53-43aa-88de-c26e561fcf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652123074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3652123074
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.743980618
Short name T194
Test name
Test status
Simulation time 8796582703 ps
CPU time 11.76 seconds
Started Jun 07 07:50:12 PM PDT 24
Finished Jun 07 07:50:27 PM PDT 24
Peak memory 225436 kb
Host smart-7f545a98-1348-455b-ab3c-0b935b31c871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743980618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
743980618
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1945150845
Short name T272
Test name
Test status
Simulation time 1578392613 ps
CPU time 7.54 seconds
Started Jun 07 07:50:10 PM PDT 24
Finished Jun 07 07:50:20 PM PDT 24
Peak memory 233516 kb
Host smart-88a3ae10-5b3d-4dc3-b07b-025c6c1beb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945150845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1945150845
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1962664828
Short name T583
Test name
Test status
Simulation time 2959967451 ps
CPU time 7.96 seconds
Started Jun 07 07:50:12 PM PDT 24
Finished Jun 07 07:50:22 PM PDT 24
Peak memory 219928 kb
Host smart-038c779f-af36-4027-ad83-85560931638e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1962664828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1962664828
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1736934533
Short name T76
Test name
Test status
Simulation time 67449545 ps
CPU time 1.04 seconds
Started Jun 07 07:50:20 PM PDT 24
Finished Jun 07 07:50:25 PM PDT 24
Peak memory 235792 kb
Host smart-bd0fc7aa-edb0-48b7-b5f4-350684be97af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736934533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1736934533
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1554662907
Short name T366
Test name
Test status
Simulation time 32858991747 ps
CPU time 45.57 seconds
Started Jun 07 07:50:12 PM PDT 24
Finished Jun 07 07:51:00 PM PDT 24
Peak memory 217300 kb
Host smart-8beb294e-4074-42e9-87f5-b2548a16abc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554662907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1554662907
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2775460587
Short name T674
Test name
Test status
Simulation time 11584946 ps
CPU time 0.69 seconds
Started Jun 07 07:50:12 PM PDT 24
Finished Jun 07 07:50:16 PM PDT 24
Peak memory 206476 kb
Host smart-e8c0190e-862e-4c5e-858c-98a1ecde3381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775460587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2775460587
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2661409058
Short name T743
Test name
Test status
Simulation time 496530777 ps
CPU time 2.1 seconds
Started Jun 07 07:50:10 PM PDT 24
Finished Jun 07 07:50:15 PM PDT 24
Peak memory 217128 kb
Host smart-bab06340-dd34-4954-8b8a-20d21af64f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661409058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2661409058
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1550950407
Short name T838
Test name
Test status
Simulation time 195345082 ps
CPU time 0.88 seconds
Started Jun 07 07:50:11 PM PDT 24
Finished Jun 07 07:50:15 PM PDT 24
Peak memory 206736 kb
Host smart-65d5fbf8-0f60-4f33-9606-12740abd4bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550950407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1550950407
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3848455024
Short name T532
Test name
Test status
Simulation time 777341556 ps
CPU time 3.79 seconds
Started Jun 07 07:50:11 PM PDT 24
Finished Jun 07 07:50:17 PM PDT 24
Peak memory 225276 kb
Host smart-b8e6e9cb-b6e2-4e2e-b8f1-4fcd0e937e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848455024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3848455024
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3748588472
Short name T812
Test name
Test status
Simulation time 14399775 ps
CPU time 0.69 seconds
Started Jun 07 07:53:52 PM PDT 24
Finished Jun 07 07:53:55 PM PDT 24
Peak memory 206236 kb
Host smart-75b4cebe-b621-477e-a199-60e134065921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748588472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3748588472
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3026220946
Short name T464
Test name
Test status
Simulation time 1678882517 ps
CPU time 4.61 seconds
Started Jun 07 07:53:38 PM PDT 24
Finished Jun 07 07:53:46 PM PDT 24
Peak memory 233560 kb
Host smart-f1fb0d55-be2e-4470-b6cb-2cd60a02b425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026220946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3026220946
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2818343353
Short name T336
Test name
Test status
Simulation time 35793957 ps
CPU time 0.83 seconds
Started Jun 07 07:53:40 PM PDT 24
Finished Jun 07 07:53:45 PM PDT 24
Peak memory 207384 kb
Host smart-e39c501d-ca3c-475d-af61-7e41835bf482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818343353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2818343353
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.640182638
Short name T21
Test name
Test status
Simulation time 5647066671 ps
CPU time 61.89 seconds
Started Jun 07 07:53:53 PM PDT 24
Finished Jun 07 07:54:57 PM PDT 24
Peak memory 253372 kb
Host smart-e2edbdaf-5bd4-4d3f-b903-5f9d09fa6492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640182638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.640182638
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3995858944
Short name T320
Test name
Test status
Simulation time 6206489793 ps
CPU time 55.59 seconds
Started Jun 07 07:53:52 PM PDT 24
Finished Jun 07 07:54:50 PM PDT 24
Peak memory 239480 kb
Host smart-fb565780-4a80-4ff9-b2d0-b32202c342eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995858944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3995858944
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3330952981
Short name T129
Test name
Test status
Simulation time 8719906159 ps
CPU time 146.78 seconds
Started Jun 07 07:53:52 PM PDT 24
Finished Jun 07 07:56:21 PM PDT 24
Peak memory 264740 kb
Host smart-fba48b77-1d15-444f-a759-2a2da913e1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330952981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3330952981
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.196456085
Short name T445
Test name
Test status
Simulation time 3512645957 ps
CPU time 11.54 seconds
Started Jun 07 07:53:41 PM PDT 24
Finished Jun 07 07:53:56 PM PDT 24
Peak memory 233712 kb
Host smart-efb5520c-b0d5-4203-a73a-6b42f90496f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196456085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.196456085
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1898538474
Short name T825
Test name
Test status
Simulation time 1131120210 ps
CPU time 6.37 seconds
Started Jun 07 07:53:41 PM PDT 24
Finished Jun 07 07:53:51 PM PDT 24
Peak memory 233540 kb
Host smart-9c03e2a2-c471-40f6-a079-8dda201496f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898538474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1898538474
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.467467036
Short name T93
Test name
Test status
Simulation time 5816211885 ps
CPU time 72.2 seconds
Started Jun 07 07:53:42 PM PDT 24
Finished Jun 07 07:54:58 PM PDT 24
Peak memory 241812 kb
Host smart-a171108b-0798-4cc2-85f6-ed4292a3dd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467467036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.467467036
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.428557332
Short name T262
Test name
Test status
Simulation time 2870299159 ps
CPU time 11.06 seconds
Started Jun 07 07:53:43 PM PDT 24
Finished Jun 07 07:53:58 PM PDT 24
Peak memory 225508 kb
Host smart-61fec1dc-c297-4055-afeb-dd5ff9be5635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428557332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.428557332
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4053452256
Short name T439
Test name
Test status
Simulation time 2550740873 ps
CPU time 4.75 seconds
Started Jun 07 07:53:41 PM PDT 24
Finished Jun 07 07:53:50 PM PDT 24
Peak memory 233640 kb
Host smart-fe39c6de-d93e-453a-9050-107cad5734ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053452256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4053452256
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.299946971
Short name T44
Test name
Test status
Simulation time 1272554920 ps
CPU time 7.87 seconds
Started Jun 07 07:53:52 PM PDT 24
Finished Jun 07 07:54:02 PM PDT 24
Peak memory 223632 kb
Host smart-bf777a3c-e2b2-4b3a-80b0-8bf65032ff10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=299946971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.299946971
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1664981868
Short name T356
Test name
Test status
Simulation time 106243733 ps
CPU time 1.03 seconds
Started Jun 07 07:53:50 PM PDT 24
Finished Jun 07 07:53:53 PM PDT 24
Peak memory 206668 kb
Host smart-45727cec-e7b7-4bd2-92fd-7b52a81de37c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664981868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1664981868
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1615664809
Short name T631
Test name
Test status
Simulation time 19413855977 ps
CPU time 35.23 seconds
Started Jun 07 07:53:44 PM PDT 24
Finished Jun 07 07:54:22 PM PDT 24
Peak memory 217292 kb
Host smart-19b6d5c1-e7cf-41df-85c3-4322aab62e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615664809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1615664809
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3373064773
Short name T390
Test name
Test status
Simulation time 1679199766 ps
CPU time 4.2 seconds
Started Jun 07 07:53:42 PM PDT 24
Finished Jun 07 07:53:50 PM PDT 24
Peak memory 217132 kb
Host smart-6aa04273-f9ee-4dd3-a49d-8c41e1f573ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373064773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3373064773
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3056998317
Short name T508
Test name
Test status
Simulation time 217194093 ps
CPU time 1 seconds
Started Jun 07 07:53:40 PM PDT 24
Finished Jun 07 07:53:44 PM PDT 24
Peak memory 207696 kb
Host smart-990de6d4-b4db-49e2-9ef7-69c8d868ed88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056998317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3056998317
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1769815424
Short name T823
Test name
Test status
Simulation time 62250019 ps
CPU time 0.9 seconds
Started Jun 07 07:53:40 PM PDT 24
Finished Jun 07 07:53:44 PM PDT 24
Peak memory 206752 kb
Host smart-b99103e2-2bd4-40f0-bdc1-4b8e964a998b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769815424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1769815424
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.250708248
Short name T270
Test name
Test status
Simulation time 18717639201 ps
CPU time 25.76 seconds
Started Jun 07 07:53:41 PM PDT 24
Finished Jun 07 07:54:10 PM PDT 24
Peak memory 239704 kb
Host smart-8f127f1b-9d67-4354-8f0b-5b99bcb9b659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250708248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.250708248
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2548227853
Short name T415
Test name
Test status
Simulation time 14549158 ps
CPU time 0.72 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:53:54 PM PDT 24
Peak memory 206620 kb
Host smart-eba9f68d-adf1-4ef0-89bd-0516d1696cad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548227853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2548227853
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.345951958
Short name T830
Test name
Test status
Simulation time 247733390 ps
CPU time 4.75 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:53:58 PM PDT 24
Peak memory 233576 kb
Host smart-a7bd29a2-b485-406d-a1a8-23d4518539a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345951958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.345951958
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.402592899
Short name T147
Test name
Test status
Simulation time 20318143 ps
CPU time 0.78 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:53:53 PM PDT 24
Peak memory 207416 kb
Host smart-2c5ee8c2-534d-473e-83c1-5912e2fc3b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402592899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.402592899
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3544113227
Short name T721
Test name
Test status
Simulation time 12298142690 ps
CPU time 44.79 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:54:38 PM PDT 24
Peak memory 233768 kb
Host smart-a30718c7-dcd2-477c-9c2d-8c96f52e2b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544113227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3544113227
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2258165024
Short name T238
Test name
Test status
Simulation time 4659067737 ps
CPU time 36.41 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:54:30 PM PDT 24
Peak memory 241792 kb
Host smart-1d0855f7-c0e1-4c61-85fa-d9a158ffd043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258165024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2258165024
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2571676453
Short name T699
Test name
Test status
Simulation time 4550034697 ps
CPU time 7.06 seconds
Started Jun 07 07:53:50 PM PDT 24
Finished Jun 07 07:53:59 PM PDT 24
Peak memory 218348 kb
Host smart-7951464f-3c8a-4153-93f2-874ead4ba621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571676453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2571676453
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1638164677
Short name T42
Test name
Test status
Simulation time 442219015 ps
CPU time 3.17 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:53:57 PM PDT 24
Peak memory 225324 kb
Host smart-57ec9b61-4af6-43e8-9268-2d43173e729f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638164677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1638164677
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.415298581
Short name T764
Test name
Test status
Simulation time 772799659 ps
CPU time 3.95 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:53:56 PM PDT 24
Peak memory 233536 kb
Host smart-e8d12d37-027b-4898-ac9c-f9376e5bc9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415298581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.415298581
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3758454803
Short name T459
Test name
Test status
Simulation time 42469513263 ps
CPU time 58.46 seconds
Started Jun 07 07:53:52 PM PDT 24
Finished Jun 07 07:54:53 PM PDT 24
Peak memory 225368 kb
Host smart-bd54b0cb-68e1-41e9-a531-29e6518a6a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758454803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3758454803
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3041626665
Short name T845
Test name
Test status
Simulation time 413180290 ps
CPU time 3.56 seconds
Started Jun 07 07:53:53 PM PDT 24
Finished Jun 07 07:53:58 PM PDT 24
Peak memory 233488 kb
Host smart-1debd72f-b4a8-43d1-b589-8dad634ed874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041626665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3041626665
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2137770413
Short name T894
Test name
Test status
Simulation time 31204740094 ps
CPU time 9.66 seconds
Started Jun 07 07:53:50 PM PDT 24
Finished Jun 07 07:54:01 PM PDT 24
Peak memory 240380 kb
Host smart-16167cee-402b-4028-8473-691c0709fc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137770413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2137770413
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.550669687
Short name T827
Test name
Test status
Simulation time 975502468 ps
CPU time 6.04 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:53:59 PM PDT 24
Peak memory 223840 kb
Host smart-36453cae-1e50-45bf-bee6-2b3a423b138b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=550669687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.550669687
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2037659263
Short name T294
Test name
Test status
Simulation time 3443229647 ps
CPU time 72.91 seconds
Started Jun 07 07:53:53 PM PDT 24
Finished Jun 07 07:55:08 PM PDT 24
Peak memory 256136 kb
Host smart-31e2006c-9b95-4fa8-acb7-cf29a2335373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037659263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2037659263
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.636337677
Short name T354
Test name
Test status
Simulation time 26613731 ps
CPU time 0.81 seconds
Started Jun 07 07:53:52 PM PDT 24
Finished Jun 07 07:53:55 PM PDT 24
Peak memory 206444 kb
Host smart-a85fe94b-de92-4b9c-a974-1e8c1742e954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636337677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.636337677
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2645455916
Short name T406
Test name
Test status
Simulation time 1334496541 ps
CPU time 5.39 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:53:58 PM PDT 24
Peak memory 217088 kb
Host smart-f7373b39-d11a-477e-bd1b-cbdcfc6a404c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645455916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2645455916
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.4261836233
Short name T829
Test name
Test status
Simulation time 80465036 ps
CPU time 1.12 seconds
Started Jun 07 07:53:52 PM PDT 24
Finished Jun 07 07:53:55 PM PDT 24
Peak memory 208460 kb
Host smart-ef516977-8b26-4331-94c8-8e4556fec429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261836233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4261836233
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1763656399
Short name T688
Test name
Test status
Simulation time 75013995 ps
CPU time 0.82 seconds
Started Jun 07 07:53:52 PM PDT 24
Finished Jun 07 07:53:56 PM PDT 24
Peak memory 206568 kb
Host smart-1f4674a8-a925-499b-9c0c-ffcc05110347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763656399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1763656399
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3058892349
Short name T181
Test name
Test status
Simulation time 9048606462 ps
CPU time 12.73 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:54:05 PM PDT 24
Peak memory 225428 kb
Host smart-b74b4ff7-58b7-4136-acde-d678e98b02b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058892349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3058892349
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3090726288
Short name T365
Test name
Test status
Simulation time 11834019 ps
CPU time 0.72 seconds
Started Jun 07 07:54:06 PM PDT 24
Finished Jun 07 07:54:07 PM PDT 24
Peak memory 206624 kb
Host smart-3140d020-20ca-42a6-9868-ac9e2c538529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090726288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3090726288
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1628390534
Short name T560
Test name
Test status
Simulation time 204900648 ps
CPU time 2.96 seconds
Started Jun 07 07:53:53 PM PDT 24
Finished Jun 07 07:53:58 PM PDT 24
Peak memory 233636 kb
Host smart-8cdca9f4-c051-43e5-b289-c9c900c05bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628390534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1628390534
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.337271455
Short name T78
Test name
Test status
Simulation time 119147796 ps
CPU time 0.81 seconds
Started Jun 07 07:53:52 PM PDT 24
Finished Jun 07 07:53:56 PM PDT 24
Peak memory 207448 kb
Host smart-cd6e4d04-72d3-4f4f-aa02-e430ee9a0adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337271455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.337271455
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.627126462
Short name T206
Test name
Test status
Simulation time 4932378220 ps
CPU time 96.56 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:55:29 PM PDT 24
Peak memory 258256 kb
Host smart-6efed8b5-c51b-4fc4-b015-7b86f812a405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627126462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.627126462
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2451172190
Short name T841
Test name
Test status
Simulation time 5569906265 ps
CPU time 56.62 seconds
Started Jun 07 07:54:00 PM PDT 24
Finished Jun 07 07:54:59 PM PDT 24
Peak memory 253316 kb
Host smart-23332d9b-34f7-4efa-a1bc-62ce07878d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451172190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2451172190
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2505529717
Short name T306
Test name
Test status
Simulation time 58650147 ps
CPU time 3.76 seconds
Started Jun 07 07:53:52 PM PDT 24
Finished Jun 07 07:53:59 PM PDT 24
Peak memory 225360 kb
Host smart-000a8815-b513-4e34-8dc8-f4a86e10efee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505529717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2505529717
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1187970453
Short name T773
Test name
Test status
Simulation time 2608170624 ps
CPU time 8.12 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:54:01 PM PDT 24
Peak memory 233656 kb
Host smart-a2750209-1a9c-46f9-8baf-26a751c17cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187970453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1187970453
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.622778458
Short name T660
Test name
Test status
Simulation time 269376564 ps
CPU time 6.64 seconds
Started Jun 07 07:53:54 PM PDT 24
Finished Jun 07 07:54:03 PM PDT 24
Peak memory 233540 kb
Host smart-35227a51-966a-40b8-ac51-35aa36fa1415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622778458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.622778458
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2311044441
Short name T573
Test name
Test status
Simulation time 1997436196 ps
CPU time 6.07 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:53:59 PM PDT 24
Peak memory 233580 kb
Host smart-20cc4ce1-173c-4fdd-a464-3f1cc649fdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311044441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2311044441
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.294468995
Short name T250
Test name
Test status
Simulation time 8494109272 ps
CPU time 16.06 seconds
Started Jun 07 07:53:50 PM PDT 24
Finished Jun 07 07:54:08 PM PDT 24
Peak memory 250720 kb
Host smart-e234ed8c-76ee-4255-b31f-f751818772fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294468995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.294468995
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2847654974
Short name T144
Test name
Test status
Simulation time 220881114 ps
CPU time 3.65 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:53:57 PM PDT 24
Peak memory 219648 kb
Host smart-5929aa86-984d-4366-86ea-ecc97fbfb29c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2847654974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2847654974
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2881836614
Short name T200
Test name
Test status
Simulation time 4776625600 ps
CPU time 117.31 seconds
Started Jun 07 07:54:15 PM PDT 24
Finished Jun 07 07:56:13 PM PDT 24
Peak memory 266532 kb
Host smart-47f844ab-48aa-4a4c-b7bd-9fcae77b45d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881836614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2881836614
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2457379856
Short name T577
Test name
Test status
Simulation time 9645449096 ps
CPU time 27.05 seconds
Started Jun 07 07:53:52 PM PDT 24
Finished Jun 07 07:54:22 PM PDT 24
Peak memory 217548 kb
Host smart-c1940a48-4a3f-4017-abb9-9acbfc6fd9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457379856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2457379856
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1723582567
Short name T933
Test name
Test status
Simulation time 1951313839 ps
CPU time 2.14 seconds
Started Jun 07 07:53:52 PM PDT 24
Finished Jun 07 07:53:57 PM PDT 24
Peak memory 208536 kb
Host smart-4403a49b-507a-41ce-8eb8-b2c54fb85750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723582567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1723582567
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1063085826
Short name T400
Test name
Test status
Simulation time 30303250 ps
CPU time 1.03 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:53:54 PM PDT 24
Peak memory 207924 kb
Host smart-e808aa74-bbfc-4f85-86f0-0e5e73ebf02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063085826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1063085826
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3149993778
Short name T892
Test name
Test status
Simulation time 592625945 ps
CPU time 0.92 seconds
Started Jun 07 07:53:50 PM PDT 24
Finished Jun 07 07:53:53 PM PDT 24
Peak memory 207740 kb
Host smart-de9286d0-fd00-4534-a230-a4c6eeb12902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149993778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3149993778
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1663554901
Short name T254
Test name
Test status
Simulation time 5522293884 ps
CPU time 6.81 seconds
Started Jun 07 07:53:51 PM PDT 24
Finished Jun 07 07:54:00 PM PDT 24
Peak memory 233648 kb
Host smart-f3e27efe-dbb0-4577-8332-d7dc950bd0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663554901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1663554901
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2779453823
Short name T711
Test name
Test status
Simulation time 12569115 ps
CPU time 0.74 seconds
Started Jun 07 07:54:06 PM PDT 24
Finished Jun 07 07:54:08 PM PDT 24
Peak memory 206300 kb
Host smart-4aa18885-2eb1-4eb8-b00e-e80a16420878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779453823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2779453823
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1123026558
Short name T843
Test name
Test status
Simulation time 206193031 ps
CPU time 2.54 seconds
Started Jun 07 07:53:58 PM PDT 24
Finished Jun 07 07:54:02 PM PDT 24
Peak memory 233428 kb
Host smart-67e46beb-9e90-4041-b97b-3506a8d001da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123026558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1123026558
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4159781968
Short name T372
Test name
Test status
Simulation time 16487234 ps
CPU time 0.79 seconds
Started Jun 07 07:53:59 PM PDT 24
Finished Jun 07 07:54:02 PM PDT 24
Peak memory 206352 kb
Host smart-7f847166-8050-4c4a-b990-0a769f81a014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159781968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4159781968
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.4269975502
Short name T434
Test name
Test status
Simulation time 6762758549 ps
CPU time 34.06 seconds
Started Jun 07 07:54:04 PM PDT 24
Finished Jun 07 07:54:39 PM PDT 24
Peak memory 257804 kb
Host smart-2289d94d-2be0-4195-9e1c-55b8d1ddc9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269975502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.4269975502
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.490981621
Short name T380
Test name
Test status
Simulation time 11054042036 ps
CPU time 96.13 seconds
Started Jun 07 07:54:15 PM PDT 24
Finished Jun 07 07:55:52 PM PDT 24
Peak memory 252552 kb
Host smart-0948b3fa-7297-47df-9242-8ec62f5af745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490981621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.490981621
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2584071552
Short name T138
Test name
Test status
Simulation time 14524289758 ps
CPU time 45.96 seconds
Started Jun 07 07:54:01 PM PDT 24
Finished Jun 07 07:54:49 PM PDT 24
Peak memory 233696 kb
Host smart-5529af84-a367-4aca-a6cf-d6e7e6033135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584071552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2584071552
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1957005376
Short name T457
Test name
Test status
Simulation time 675609277 ps
CPU time 7.09 seconds
Started Jun 07 07:54:01 PM PDT 24
Finished Jun 07 07:54:10 PM PDT 24
Peak memory 225324 kb
Host smart-f41e3e8a-f92a-4b7e-ab23-f5ed2312955c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957005376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1957005376
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1228496881
Short name T748
Test name
Test status
Simulation time 973120235 ps
CPU time 12.3 seconds
Started Jun 07 07:54:00 PM PDT 24
Finished Jun 07 07:54:14 PM PDT 24
Peak memory 233540 kb
Host smart-ba1a16fc-c52e-4791-841f-c2b9f2d2c810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228496881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1228496881
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2709532054
Short name T383
Test name
Test status
Simulation time 8002607929 ps
CPU time 9.93 seconds
Started Jun 07 07:53:59 PM PDT 24
Finished Jun 07 07:54:10 PM PDT 24
Peak memory 225444 kb
Host smart-73c6f19d-86b6-478c-b4e4-25a58d609485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709532054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2709532054
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3067520688
Short name T734
Test name
Test status
Simulation time 728029762 ps
CPU time 8.92 seconds
Started Jun 07 07:54:01 PM PDT 24
Finished Jun 07 07:54:12 PM PDT 24
Peak memory 239032 kb
Host smart-5f266208-30d2-478f-9112-4f2c23435444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067520688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3067520688
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1695578560
Short name T453
Test name
Test status
Simulation time 2582667611 ps
CPU time 12.92 seconds
Started Jun 07 07:54:08 PM PDT 24
Finished Jun 07 07:54:23 PM PDT 24
Peak memory 224024 kb
Host smart-896d4982-f5f5-4040-af1e-a7952c8e34cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1695578560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1695578560
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1040580874
Short name T493
Test name
Test status
Simulation time 38357131620 ps
CPU time 326.63 seconds
Started Jun 07 07:54:02 PM PDT 24
Finished Jun 07 07:59:30 PM PDT 24
Peak memory 250136 kb
Host smart-a8779179-3383-4ba2-ab9e-c7cf9ead29e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040580874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1040580874
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1007175504
Short name T17
Test name
Test status
Simulation time 12657885141 ps
CPU time 25.64 seconds
Started Jun 07 07:54:08 PM PDT 24
Finished Jun 07 07:54:34 PM PDT 24
Peak memory 217292 kb
Host smart-d8e7c9e8-4ce4-49c5-8ceb-a37b2f1eb097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007175504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1007175504
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2506043591
Short name T420
Test name
Test status
Simulation time 31440323 ps
CPU time 0.73 seconds
Started Jun 07 07:53:59 PM PDT 24
Finished Jun 07 07:54:02 PM PDT 24
Peak memory 206512 kb
Host smart-ae7d604b-5e6b-4f92-b156-14ec11c07c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506043591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2506043591
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1651804030
Short name T418
Test name
Test status
Simulation time 80125769 ps
CPU time 1.26 seconds
Started Jun 07 07:54:08 PM PDT 24
Finished Jun 07 07:54:11 PM PDT 24
Peak memory 208244 kb
Host smart-ed971117-b4d9-4e49-b9be-55c862abfc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651804030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1651804030
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1465512544
Short name T569
Test name
Test status
Simulation time 128366825 ps
CPU time 0.85 seconds
Started Jun 07 07:54:09 PM PDT 24
Finished Jun 07 07:54:11 PM PDT 24
Peak memory 206724 kb
Host smart-a222b305-1d5a-4295-8f50-d59b907465f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465512544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1465512544
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3596598422
Short name T432
Test name
Test status
Simulation time 514675479 ps
CPU time 6.29 seconds
Started Jun 07 07:54:01 PM PDT 24
Finished Jun 07 07:54:09 PM PDT 24
Peak memory 233532 kb
Host smart-34c333ec-1802-4158-93a2-69fdd9d4c50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596598422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3596598422
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4232029105
Short name T564
Test name
Test status
Simulation time 25603379 ps
CPU time 0.77 seconds
Started Jun 07 07:54:08 PM PDT 24
Finished Jun 07 07:54:10 PM PDT 24
Peak memory 205672 kb
Host smart-b24b60ea-1d10-4c9f-911c-36a6135fc0f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232029105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4232029105
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.650729418
Short name T574
Test name
Test status
Simulation time 1626735543 ps
CPU time 12.77 seconds
Started Jun 07 07:54:12 PM PDT 24
Finished Jun 07 07:54:26 PM PDT 24
Peak memory 233584 kb
Host smart-60f86428-d1de-4634-a842-5511eb39682f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650729418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.650729418
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1817017255
Short name T540
Test name
Test status
Simulation time 22083611 ps
CPU time 0.79 seconds
Started Jun 07 07:54:00 PM PDT 24
Finished Jun 07 07:54:03 PM PDT 24
Peak memory 207280 kb
Host smart-e205f37f-fe8e-4e21-a275-ff7959236359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817017255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1817017255
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.4196447847
Short name T546
Test name
Test status
Simulation time 61813146758 ps
CPU time 101.45 seconds
Started Jun 07 07:54:10 PM PDT 24
Finished Jun 07 07:55:53 PM PDT 24
Peak memory 254344 kb
Host smart-243d424c-9f5b-456c-abd1-945ebdf4fa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196447847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4196447847
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4137740448
Short name T887
Test name
Test status
Simulation time 7084144515 ps
CPU time 60.65 seconds
Started Jun 07 07:54:10 PM PDT 24
Finished Jun 07 07:55:12 PM PDT 24
Peak memory 237120 kb
Host smart-b1dab828-7c03-4e7b-9195-eb919ad4837c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137740448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4137740448
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2257802299
Short name T689
Test name
Test status
Simulation time 14949887983 ps
CPU time 119.32 seconds
Started Jun 07 07:54:11 PM PDT 24
Finished Jun 07 07:56:11 PM PDT 24
Peak memory 267616 kb
Host smart-0a46924c-2419-4a5c-accc-5ae3b395bb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257802299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2257802299
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3511044384
Short name T504
Test name
Test status
Simulation time 2608764958 ps
CPU time 7.71 seconds
Started Jun 07 07:54:10 PM PDT 24
Finished Jun 07 07:54:19 PM PDT 24
Peak memory 225496 kb
Host smart-ad486d08-4e4f-4a98-8b24-0448b140444e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511044384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3511044384
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2296853760
Short name T526
Test name
Test status
Simulation time 21255156338 ps
CPU time 21.83 seconds
Started Jun 07 07:54:09 PM PDT 24
Finished Jun 07 07:54:32 PM PDT 24
Peak memory 225472 kb
Host smart-7935ca9c-c703-457e-91ef-6cb9b9cc444e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296853760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2296853760
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2816107291
Short name T738
Test name
Test status
Simulation time 1069662373 ps
CPU time 10.51 seconds
Started Jun 07 07:54:09 PM PDT 24
Finished Jun 07 07:54:20 PM PDT 24
Peak memory 233460 kb
Host smart-a69d0704-6693-45d9-a12c-804b520b5276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816107291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2816107291
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.438097545
Short name T563
Test name
Test status
Simulation time 193464241 ps
CPU time 3.83 seconds
Started Jun 07 07:54:08 PM PDT 24
Finished Jun 07 07:54:13 PM PDT 24
Peak memory 233520 kb
Host smart-d4b9bed7-57b3-4122-8119-e926b2fdd579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438097545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.438097545
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2417669277
Short name T500
Test name
Test status
Simulation time 1677090327 ps
CPU time 3.08 seconds
Started Jun 07 07:54:11 PM PDT 24
Finished Jun 07 07:54:15 PM PDT 24
Peak memory 233644 kb
Host smart-944afa85-9368-4bee-958c-14f6089f4661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417669277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2417669277
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2208288071
Short name T45
Test name
Test status
Simulation time 200405127 ps
CPU time 4.2 seconds
Started Jun 07 07:54:08 PM PDT 24
Finished Jun 07 07:54:13 PM PDT 24
Peak memory 223960 kb
Host smart-a673f32a-33e3-420a-975c-9b23b0c72def
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2208288071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2208288071
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1978883100
Short name T196
Test name
Test status
Simulation time 6019659611 ps
CPU time 40.82 seconds
Started Jun 07 07:54:09 PM PDT 24
Finished Jun 07 07:54:51 PM PDT 24
Peak memory 255680 kb
Host smart-2f65bd95-7187-4562-9dec-a6e5602da8f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978883100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1978883100
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.687545806
Short name T538
Test name
Test status
Simulation time 29987102 ps
CPU time 0.75 seconds
Started Jun 07 07:54:07 PM PDT 24
Finished Jun 07 07:54:08 PM PDT 24
Peak memory 206524 kb
Host smart-c84f67ab-5af0-4dd5-a0be-b7daf8156783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687545806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.687545806
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.4115110354
Short name T319
Test name
Test status
Simulation time 2828428790 ps
CPU time 9.91 seconds
Started Jun 07 07:54:07 PM PDT 24
Finished Jun 07 07:54:18 PM PDT 24
Peak memory 217264 kb
Host smart-a19d82bf-fb19-4dea-a771-3f993b03a89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115110354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4115110354
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.4246580437
Short name T12
Test name
Test status
Simulation time 29192054 ps
CPU time 1.2 seconds
Started Jun 07 07:54:12 PM PDT 24
Finished Jun 07 07:54:15 PM PDT 24
Peak memory 208792 kb
Host smart-3e8f6418-4c62-41b9-be89-fe6054b400ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246580437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4246580437
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2023033601
Short name T519
Test name
Test status
Simulation time 12845881 ps
CPU time 0.71 seconds
Started Jun 07 07:54:13 PM PDT 24
Finished Jun 07 07:54:14 PM PDT 24
Peak memory 206432 kb
Host smart-3fad0f44-19fd-41da-a6ab-0aa0f74c8bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023033601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2023033601
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.213722602
Short name T640
Test name
Test status
Simulation time 441730328 ps
CPU time 5.23 seconds
Started Jun 07 07:54:09 PM PDT 24
Finished Jun 07 07:54:16 PM PDT 24
Peak memory 241368 kb
Host smart-4b322106-6080-4012-8b9a-6b008fa0d372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213722602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.213722602
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2278029153
Short name T462
Test name
Test status
Simulation time 14732040 ps
CPU time 0.76 seconds
Started Jun 07 07:54:21 PM PDT 24
Finished Jun 07 07:54:23 PM PDT 24
Peak memory 206328 kb
Host smart-5511d274-b6e3-48b0-8e28-0f7156b3b6f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278029153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2278029153
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2910995771
Short name T461
Test name
Test status
Simulation time 384403059 ps
CPU time 2.43 seconds
Started Jun 07 07:54:19 PM PDT 24
Finished Jun 07 07:54:22 PM PDT 24
Peak memory 224028 kb
Host smart-2dd83c2f-e502-40c6-9164-414d3aae6b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910995771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2910995771
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1324634632
Short name T600
Test name
Test status
Simulation time 92626282 ps
CPU time 0.77 seconds
Started Jun 07 07:54:15 PM PDT 24
Finished Jun 07 07:54:16 PM PDT 24
Peak memory 207376 kb
Host smart-d2962ad5-467c-4e43-b4b5-a58a2eafaadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324634632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1324634632
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.943563001
Short name T639
Test name
Test status
Simulation time 6189063010 ps
CPU time 78.72 seconds
Started Jun 07 07:54:24 PM PDT 24
Finished Jun 07 07:55:43 PM PDT 24
Peak memory 252744 kb
Host smart-f43ffa71-91db-4344-bb94-5966425a353f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943563001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.943563001
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2559797439
Short name T220
Test name
Test status
Simulation time 35006823910 ps
CPU time 76.58 seconds
Started Jun 07 07:54:19 PM PDT 24
Finished Jun 07 07:55:37 PM PDT 24
Peak memory 253024 kb
Host smart-4490fd63-52fb-473e-b010-12d69851a53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559797439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2559797439
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2067612408
Short name T657
Test name
Test status
Simulation time 1382602269 ps
CPU time 16.54 seconds
Started Jun 07 07:54:22 PM PDT 24
Finished Jun 07 07:54:40 PM PDT 24
Peak memory 225368 kb
Host smart-0b358f72-c81f-41f9-b10e-efef487d1cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067612408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2067612408
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.747104788
Short name T430
Test name
Test status
Simulation time 3373962481 ps
CPU time 6.83 seconds
Started Jun 07 07:54:18 PM PDT 24
Finished Jun 07 07:54:26 PM PDT 24
Peak memory 233700 kb
Host smart-4c171672-9305-4425-8d9d-408d14ab0e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747104788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.747104788
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.357578068
Short name T264
Test name
Test status
Simulation time 137098607 ps
CPU time 2.78 seconds
Started Jun 07 07:54:18 PM PDT 24
Finished Jun 07 07:54:22 PM PDT 24
Peak memory 225276 kb
Host smart-3ecd13c5-c15b-4a46-807b-603ae7d5e6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357578068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.357578068
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1826568040
Short name T791
Test name
Test status
Simulation time 473959790 ps
CPU time 8.17 seconds
Started Jun 07 07:54:19 PM PDT 24
Finished Jun 07 07:54:28 PM PDT 24
Peak memory 233544 kb
Host smart-ab04a565-e5ff-40a5-93ef-03e252e8f07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826568040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1826568040
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1152711858
Short name T202
Test name
Test status
Simulation time 11183371190 ps
CPU time 26.14 seconds
Started Jun 07 07:54:11 PM PDT 24
Finished Jun 07 07:54:38 PM PDT 24
Peak memory 233640 kb
Host smart-c5c0f296-86df-43d5-83f6-611fef5d0beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152711858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1152711858
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1543850593
Short name T381
Test name
Test status
Simulation time 342571852 ps
CPU time 4.46 seconds
Started Jun 07 07:54:19 PM PDT 24
Finished Jun 07 07:54:24 PM PDT 24
Peak memory 220916 kb
Host smart-b8649305-741d-4906-9efc-49bfdb30a3e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1543850593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1543850593
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2381162227
Short name T60
Test name
Test status
Simulation time 299077400214 ps
CPU time 357.75 seconds
Started Jun 07 07:54:19 PM PDT 24
Finished Jun 07 08:00:18 PM PDT 24
Peak memory 250904 kb
Host smart-4961beff-67d7-43ca-8f61-812fcc7a7dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381162227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2381162227
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2657894913
Short name T578
Test name
Test status
Simulation time 1630827697 ps
CPU time 11.31 seconds
Started Jun 07 07:54:07 PM PDT 24
Finished Jun 07 07:54:20 PM PDT 24
Peak memory 217212 kb
Host smart-3f1a4e7b-b0af-4641-b4f1-573dd2a8c5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657894913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2657894913
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4074539667
Short name T886
Test name
Test status
Simulation time 1197153949 ps
CPU time 4.93 seconds
Started Jun 07 07:54:10 PM PDT 24
Finished Jun 07 07:54:16 PM PDT 24
Peak memory 217120 kb
Host smart-cd352eb3-1ec4-407d-8d8e-4ef2359ffc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074539667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4074539667
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2429754848
Short name T752
Test name
Test status
Simulation time 155111129 ps
CPU time 2.46 seconds
Started Jun 07 07:54:10 PM PDT 24
Finished Jun 07 07:54:13 PM PDT 24
Peak memory 217216 kb
Host smart-c22f394a-4a99-4acd-9dff-3c0689de42f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429754848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2429754848
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.202464592
Short name T861
Test name
Test status
Simulation time 97509503 ps
CPU time 0.91 seconds
Started Jun 07 07:54:11 PM PDT 24
Finished Jun 07 07:54:13 PM PDT 24
Peak memory 206784 kb
Host smart-c58457e3-32ae-4527-a930-470bcc966c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202464592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.202464592
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2207461709
Short name T585
Test name
Test status
Simulation time 38560817 ps
CPU time 2.72 seconds
Started Jun 07 07:54:18 PM PDT 24
Finished Jun 07 07:54:21 PM PDT 24
Peak memory 233432 kb
Host smart-683714e1-a03b-45f6-8db9-507b56bafb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207461709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2207461709
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3149433880
Short name T65
Test name
Test status
Simulation time 14207708 ps
CPU time 0.78 seconds
Started Jun 07 07:54:28 PM PDT 24
Finished Jun 07 07:54:30 PM PDT 24
Peak memory 206576 kb
Host smart-80e31d10-4582-43ff-9134-bbf4e0c72368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149433880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3149433880
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1984036324
Short name T6
Test name
Test status
Simulation time 681317187 ps
CPU time 6.13 seconds
Started Jun 07 07:54:29 PM PDT 24
Finished Jun 07 07:54:37 PM PDT 24
Peak memory 233604 kb
Host smart-2ad650f1-cbc2-4435-b51f-907052516f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984036324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1984036324
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.104152025
Short name T950
Test name
Test status
Simulation time 48543341 ps
CPU time 0.79 seconds
Started Jun 07 07:54:17 PM PDT 24
Finished Jun 07 07:54:18 PM PDT 24
Peak memory 207436 kb
Host smart-08dd8946-b477-4c42-aa22-09277b975725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104152025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.104152025
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2442752607
Short name T779
Test name
Test status
Simulation time 1115815368 ps
CPU time 6.99 seconds
Started Jun 07 07:54:29 PM PDT 24
Finished Jun 07 07:54:37 PM PDT 24
Peak memory 220324 kb
Host smart-3e4bf824-8f67-4ac6-a506-af745db4f7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442752607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2442752607
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3308993561
Short name T25
Test name
Test status
Simulation time 22336209934 ps
CPU time 149.15 seconds
Started Jun 07 07:54:27 PM PDT 24
Finished Jun 07 07:56:58 PM PDT 24
Peak memory 253412 kb
Host smart-fff7ea8a-f656-43a6-a41c-7958fa7a90c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308993561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3308993561
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2196260396
Short name T620
Test name
Test status
Simulation time 1004899851 ps
CPU time 8.38 seconds
Started Jun 07 07:54:27 PM PDT 24
Finished Jun 07 07:54:37 PM PDT 24
Peak memory 233600 kb
Host smart-05c0ca2e-f85d-4204-aae4-3e1ecc259c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196260396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2196260396
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3055231248
Short name T46
Test name
Test status
Simulation time 403112283 ps
CPU time 5.17 seconds
Started Jun 07 07:54:29 PM PDT 24
Finished Jun 07 07:54:36 PM PDT 24
Peak memory 225320 kb
Host smart-ea2522cb-6682-4fea-a1d8-dc5c519ec433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055231248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3055231248
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1312247769
Short name T867
Test name
Test status
Simulation time 66161137006 ps
CPU time 128.44 seconds
Started Jun 07 07:54:27 PM PDT 24
Finished Jun 07 07:56:37 PM PDT 24
Peak memory 225476 kb
Host smart-ea887691-febd-48b6-8f8f-56e3b2b2bdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312247769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1312247769
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3502515983
Short name T271
Test name
Test status
Simulation time 1308023667 ps
CPU time 6.18 seconds
Started Jun 07 07:54:28 PM PDT 24
Finished Jun 07 07:54:36 PM PDT 24
Peak memory 233528 kb
Host smart-ef18976a-b6ee-4325-b2a1-572f7eccbc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502515983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3502515983
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.376424436
Short name T919
Test name
Test status
Simulation time 2586009179 ps
CPU time 10.84 seconds
Started Jun 07 07:54:27 PM PDT 24
Finished Jun 07 07:54:39 PM PDT 24
Peak memory 225360 kb
Host smart-466fe5da-9ee5-42ad-8c9b-432587d45f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376424436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.376424436
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.941306704
Short name T466
Test name
Test status
Simulation time 3305644448 ps
CPU time 7.32 seconds
Started Jun 07 07:54:27 PM PDT 24
Finished Jun 07 07:54:35 PM PDT 24
Peak memory 222312 kb
Host smart-3838c523-7d82-451e-af74-8a52870c09b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=941306704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.941306704
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1895115492
Short name T23
Test name
Test status
Simulation time 61055315483 ps
CPU time 288.91 seconds
Started Jun 07 07:54:26 PM PDT 24
Finished Jun 07 07:59:16 PM PDT 24
Peak memory 250068 kb
Host smart-30116450-0b1d-4cc6-aecb-ad3a31af4655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895115492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1895115492
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3727530545
Short name T314
Test name
Test status
Simulation time 10734008971 ps
CPU time 50.12 seconds
Started Jun 07 07:54:23 PM PDT 24
Finished Jun 07 07:55:14 PM PDT 24
Peak memory 217252 kb
Host smart-211f4d75-5340-4e25-8466-c943cb1fc32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727530545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3727530545
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2113084142
Short name T923
Test name
Test status
Simulation time 548865823 ps
CPU time 2.52 seconds
Started Jun 07 07:54:20 PM PDT 24
Finished Jun 07 07:54:23 PM PDT 24
Peak memory 208704 kb
Host smart-d81c40f3-259d-41ea-8928-caaf21b50676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113084142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2113084142
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2240089568
Short name T472
Test name
Test status
Simulation time 70926834 ps
CPU time 1.53 seconds
Started Jun 07 07:54:27 PM PDT 24
Finished Jun 07 07:54:30 PM PDT 24
Peak memory 217184 kb
Host smart-a89fde39-378c-4f51-a791-0cfd41da77d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240089568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2240089568
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2465882752
Short name T404
Test name
Test status
Simulation time 51538948 ps
CPU time 0.94 seconds
Started Jun 07 07:54:27 PM PDT 24
Finished Jun 07 07:54:29 PM PDT 24
Peak memory 206716 kb
Host smart-cdc03e41-cdbf-481c-b7f6-31649d1c4a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465882752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2465882752
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.20256308
Short name T786
Test name
Test status
Simulation time 466162909 ps
CPU time 3.47 seconds
Started Jun 07 07:54:27 PM PDT 24
Finished Jun 07 07:54:32 PM PDT 24
Peak memory 233560 kb
Host smart-2ac77721-0d01-49c0-af37-a4247463aaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20256308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.20256308
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2608414605
Short name T63
Test name
Test status
Simulation time 21042942 ps
CPU time 0.71 seconds
Started Jun 07 07:54:36 PM PDT 24
Finished Jun 07 07:54:39 PM PDT 24
Peak memory 206344 kb
Host smart-c71df2fd-270e-4393-92d5-8fef25dcad49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608414605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2608414605
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1669524325
Short name T835
Test name
Test status
Simulation time 118409921 ps
CPU time 2.51 seconds
Started Jun 07 07:54:36 PM PDT 24
Finished Jun 07 07:54:40 PM PDT 24
Peak memory 225276 kb
Host smart-a348f30c-8ee9-4ec3-97ee-1de2d0d767a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669524325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1669524325
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4001209482
Short name T382
Test name
Test status
Simulation time 97801834 ps
CPU time 0.83 seconds
Started Jun 07 07:54:25 PM PDT 24
Finished Jun 07 07:54:26 PM PDT 24
Peak memory 207436 kb
Host smart-e68d9326-e5dd-477c-b8f9-2aa79179278f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001209482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4001209482
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3830475560
Short name T802
Test name
Test status
Simulation time 37331346 ps
CPU time 0.78 seconds
Started Jun 07 07:54:36 PM PDT 24
Finished Jun 07 07:54:39 PM PDT 24
Peak memory 216688 kb
Host smart-31339fbd-3d8a-4045-9f1f-c289b569b2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830475560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3830475560
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2390871474
Short name T882
Test name
Test status
Simulation time 54529301835 ps
CPU time 102.9 seconds
Started Jun 07 07:54:36 PM PDT 24
Finished Jun 07 07:56:21 PM PDT 24
Peak memory 258044 kb
Host smart-7cdc5c2e-062d-498f-8aa0-458612695e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390871474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2390871474
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.4228621762
Short name T471
Test name
Test status
Simulation time 8299133413 ps
CPU time 47.39 seconds
Started Jun 07 07:54:36 PM PDT 24
Finished Jun 07 07:55:26 PM PDT 24
Peak memory 240968 kb
Host smart-7f2d704a-b0e0-45c2-a1f4-747d4640531e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228621762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.4228621762
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2760620256
Short name T576
Test name
Test status
Simulation time 394831681 ps
CPU time 4.72 seconds
Started Jun 07 07:54:33 PM PDT 24
Finished Jun 07 07:54:39 PM PDT 24
Peak memory 241260 kb
Host smart-5dca9d92-9c6f-4f5c-a872-168cb185f157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760620256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2760620256
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2855624430
Short name T236
Test name
Test status
Simulation time 762937499 ps
CPU time 5.41 seconds
Started Jun 07 07:54:26 PM PDT 24
Finished Jun 07 07:54:32 PM PDT 24
Peak memory 219500 kb
Host smart-93bbd218-7e1f-415d-a231-05598d6deb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855624430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2855624430
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2845912227
Short name T630
Test name
Test status
Simulation time 848853115 ps
CPU time 9.4 seconds
Started Jun 07 07:54:26 PM PDT 24
Finished Jun 07 07:54:36 PM PDT 24
Peak memory 225364 kb
Host smart-a2b16a75-818a-48e7-99d8-bf8ac91d1c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845912227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2845912227
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3487500835
Short name T695
Test name
Test status
Simulation time 3057858443 ps
CPU time 4.57 seconds
Started Jun 07 07:54:28 PM PDT 24
Finished Jun 07 07:54:34 PM PDT 24
Peak memory 225464 kb
Host smart-6dc9e2be-afbb-48de-ad94-25ef5c44c9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487500835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3487500835
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2873140205
Short name T241
Test name
Test status
Simulation time 25530589229 ps
CPU time 16.78 seconds
Started Jun 07 07:54:29 PM PDT 24
Finished Jun 07 07:54:48 PM PDT 24
Peak memory 233688 kb
Host smart-06a99cce-2eb6-458f-a840-461b0944d5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873140205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2873140205
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2759380669
Short name T910
Test name
Test status
Simulation time 248214875 ps
CPU time 4.78 seconds
Started Jun 07 07:54:35 PM PDT 24
Finished Jun 07 07:54:42 PM PDT 24
Peak memory 219584 kb
Host smart-020f91d2-f8d4-4f94-9dee-2148eb6716d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2759380669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2759380669
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2535309952
Short name T767
Test name
Test status
Simulation time 34236117 ps
CPU time 0.96 seconds
Started Jun 07 07:54:35 PM PDT 24
Finished Jun 07 07:54:38 PM PDT 24
Peak memory 207412 kb
Host smart-ecb9c3a8-00d1-4943-83a9-5e9e6b84de31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535309952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2535309952
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.4134380727
Short name T846
Test name
Test status
Simulation time 84817383649 ps
CPU time 41.06 seconds
Started Jun 07 07:54:26 PM PDT 24
Finished Jun 07 07:55:08 PM PDT 24
Peak memory 217308 kb
Host smart-6031cc48-7ba4-4503-bf00-ad6aa392691d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134380727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4134380727
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3499992460
Short name T904
Test name
Test status
Simulation time 468722160 ps
CPU time 3.25 seconds
Started Jun 07 07:54:27 PM PDT 24
Finished Jun 07 07:54:32 PM PDT 24
Peak memory 217200 kb
Host smart-100fdc8f-0561-4e4f-a7a0-800db59f6fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499992460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3499992460
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.652315381
Short name T552
Test name
Test status
Simulation time 243052829 ps
CPU time 1.78 seconds
Started Jun 07 07:54:28 PM PDT 24
Finished Jun 07 07:54:31 PM PDT 24
Peak memory 217120 kb
Host smart-393be91c-8c94-4dff-b43b-c395ac780e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652315381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.652315381
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3937070569
Short name T419
Test name
Test status
Simulation time 66195158 ps
CPU time 0.86 seconds
Started Jun 07 07:54:27 PM PDT 24
Finished Jun 07 07:54:29 PM PDT 24
Peak memory 206672 kb
Host smart-f4f3ba76-e156-4cea-a17c-56306f211b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937070569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3937070569
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1407128138
Short name T720
Test name
Test status
Simulation time 1061606055 ps
CPU time 9.41 seconds
Started Jun 07 07:54:27 PM PDT 24
Finished Jun 07 07:54:38 PM PDT 24
Peak memory 238660 kb
Host smart-45b238e0-f348-4bc9-9190-4d67cac889ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407128138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1407128138
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3013204034
Short name T392
Test name
Test status
Simulation time 12459267 ps
CPU time 0.72 seconds
Started Jun 07 07:54:43 PM PDT 24
Finished Jun 07 07:54:46 PM PDT 24
Peak memory 205704 kb
Host smart-d348e55a-766e-454b-9ad0-2e7dd55ea284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013204034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3013204034
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2017656527
Short name T580
Test name
Test status
Simulation time 884122861 ps
CPU time 9.2 seconds
Started Jun 07 07:54:35 PM PDT 24
Finished Jun 07 07:54:46 PM PDT 24
Peak memory 225396 kb
Host smart-2b1f517d-14ea-4eb8-87bf-6275de9b1501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017656527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2017656527
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3790536869
Short name T613
Test name
Test status
Simulation time 52875628 ps
CPU time 0.76 seconds
Started Jun 07 07:54:37 PM PDT 24
Finished Jun 07 07:54:40 PM PDT 24
Peak memory 207452 kb
Host smart-eb1213f9-97dc-4f54-aded-b993c331eec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790536869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3790536869
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3883418283
Short name T192
Test name
Test status
Simulation time 5669026450 ps
CPU time 51.7 seconds
Started Jun 07 07:54:35 PM PDT 24
Finished Jun 07 07:55:27 PM PDT 24
Peak memory 254620 kb
Host smart-ad22184b-7a0b-420f-a286-c890329cad0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883418283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3883418283
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.4154662412
Short name T931
Test name
Test status
Simulation time 2855611800 ps
CPU time 8.14 seconds
Started Jun 07 07:54:37 PM PDT 24
Finished Jun 07 07:54:47 PM PDT 24
Peak memory 220508 kb
Host smart-374ba70d-0b6d-4aab-8e64-068176af4e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154662412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.4154662412
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.544625506
Short name T27
Test name
Test status
Simulation time 13581820566 ps
CPU time 58.94 seconds
Started Jun 07 07:54:35 PM PDT 24
Finished Jun 07 07:55:35 PM PDT 24
Peak memory 251916 kb
Host smart-f924e5dc-05b9-4171-b3e6-0bd7a638e85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544625506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.544625506
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2465471220
Short name T899
Test name
Test status
Simulation time 495577978 ps
CPU time 14.34 seconds
Started Jun 07 07:54:34 PM PDT 24
Finished Jun 07 07:54:49 PM PDT 24
Peak memory 233588 kb
Host smart-a3680b29-dc41-47b0-9626-cb9904c08f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465471220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2465471220
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3597913386
Short name T442
Test name
Test status
Simulation time 30651125 ps
CPU time 2.05 seconds
Started Jun 07 07:54:35 PM PDT 24
Finished Jun 07 07:54:39 PM PDT 24
Peak memory 224140 kb
Host smart-e2a2e83f-b3e1-4778-81be-500f120f0dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597913386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3597913386
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.255811261
Short name T346
Test name
Test status
Simulation time 3032985056 ps
CPU time 22.88 seconds
Started Jun 07 07:54:36 PM PDT 24
Finished Jun 07 07:55:01 PM PDT 24
Peak memory 233556 kb
Host smart-d496b05a-4a53-4fe2-947f-6971e2246ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255811261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.255811261
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3552306428
Short name T297
Test name
Test status
Simulation time 20564659856 ps
CPU time 19.63 seconds
Started Jun 07 07:54:35 PM PDT 24
Finished Jun 07 07:54:56 PM PDT 24
Peak memory 233548 kb
Host smart-753bdf56-fef8-4a98-9b12-c0f0fd4a0bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552306428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3552306428
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.578203065
Short name T816
Test name
Test status
Simulation time 6267777841 ps
CPU time 11.37 seconds
Started Jun 07 07:54:35 PM PDT 24
Finished Jun 07 07:54:48 PM PDT 24
Peak memory 225476 kb
Host smart-637e2368-fab5-4341-a28a-b1529a010eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578203065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.578203065
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1133441372
Short name T747
Test name
Test status
Simulation time 89281244 ps
CPU time 4.24 seconds
Started Jun 07 07:54:36 PM PDT 24
Finished Jun 07 07:54:42 PM PDT 24
Peak memory 223920 kb
Host smart-2733b079-8b6d-4524-bcea-5647882d86b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1133441372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1133441372
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.917062917
Short name T152
Test name
Test status
Simulation time 121573424 ps
CPU time 1.2 seconds
Started Jun 07 07:54:34 PM PDT 24
Finished Jun 07 07:54:37 PM PDT 24
Peak memory 208736 kb
Host smart-5ca3dd9f-0ab1-41f1-a9da-1216608f99dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917062917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.917062917
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1812301416
Short name T826
Test name
Test status
Simulation time 18410101797 ps
CPU time 40.18 seconds
Started Jun 07 07:54:36 PM PDT 24
Finished Jun 07 07:55:19 PM PDT 24
Peak memory 217272 kb
Host smart-3d2e8d6f-1a54-4b88-929e-52916d057fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812301416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1812301416
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.217326878
Short name T828
Test name
Test status
Simulation time 3832495214 ps
CPU time 7.87 seconds
Started Jun 07 07:54:37 PM PDT 24
Finished Jun 07 07:54:47 PM PDT 24
Peak memory 217276 kb
Host smart-51faf347-af91-4fb3-9f4a-9fa3505b16c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217326878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.217326878
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3026590253
Short name T343
Test name
Test status
Simulation time 385727881 ps
CPU time 1.04 seconds
Started Jun 07 07:54:35 PM PDT 24
Finished Jun 07 07:54:37 PM PDT 24
Peak memory 207724 kb
Host smart-1659e0a6-5488-4343-8162-f3f2451e66d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026590253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3026590253
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3008928198
Short name T509
Test name
Test status
Simulation time 121978192 ps
CPU time 0.73 seconds
Started Jun 07 07:54:35 PM PDT 24
Finished Jun 07 07:54:38 PM PDT 24
Peak memory 206716 kb
Host smart-07af6ad1-2e36-47a1-9c68-75a1d9ce7eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008928198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3008928198
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1841957828
Short name T873
Test name
Test status
Simulation time 6611999551 ps
CPU time 9.4 seconds
Started Jun 07 07:54:37 PM PDT 24
Finished Jun 07 07:54:48 PM PDT 24
Peak memory 225496 kb
Host smart-d1a8a17f-773d-4979-99d9-4cabcfcf167c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841957828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1841957828
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4074752663
Short name T717
Test name
Test status
Simulation time 14341345 ps
CPU time 0.74 seconds
Started Jun 07 07:54:44 PM PDT 24
Finished Jun 07 07:54:46 PM PDT 24
Peak memory 205708 kb
Host smart-1e22e9a9-caed-44f8-9394-b3bb624dd41d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074752663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4074752663
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3136378967
Short name T7
Test name
Test status
Simulation time 630135875 ps
CPU time 4.64 seconds
Started Jun 07 07:54:43 PM PDT 24
Finished Jun 07 07:54:49 PM PDT 24
Peak memory 225184 kb
Host smart-0fb1af8a-a0a7-4e12-b3a5-975b54ecc4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136378967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3136378967
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2319058202
Short name T895
Test name
Test status
Simulation time 14100591 ps
CPU time 0.8 seconds
Started Jun 07 07:54:44 PM PDT 24
Finished Jun 07 07:54:47 PM PDT 24
Peak memory 206372 kb
Host smart-3894ac01-39a6-4f68-8a19-e9d3cfea5ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319058202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2319058202
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2093121972
Short name T171
Test name
Test status
Simulation time 2239636378 ps
CPU time 15.44 seconds
Started Jun 07 07:54:44 PM PDT 24
Finished Jun 07 07:55:01 PM PDT 24
Peak memory 236212 kb
Host smart-a62a71ab-e4f5-4647-a6ec-819d7e3241f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093121972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2093121972
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.144827608
Short name T401
Test name
Test status
Simulation time 6474490076 ps
CPU time 106.9 seconds
Started Jun 07 07:54:43 PM PDT 24
Finished Jun 07 07:56:32 PM PDT 24
Peak memory 251500 kb
Host smart-ddef8ad9-466b-4b0a-875f-6ddd7360ef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144827608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.144827608
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3211204183
Short name T323
Test name
Test status
Simulation time 2494529025 ps
CPU time 35.4 seconds
Started Jun 07 07:54:46 PM PDT 24
Finished Jun 07 07:55:23 PM PDT 24
Peak memory 241868 kb
Host smart-abc3182b-b2ff-45d6-b087-fa4e6ac443cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211204183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3211204183
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2583023971
Short name T226
Test name
Test status
Simulation time 1769220251 ps
CPU time 9.43 seconds
Started Jun 07 07:54:45 PM PDT 24
Finished Jun 07 07:54:56 PM PDT 24
Peak memory 233568 kb
Host smart-762c284b-1b2e-4c50-96c2-4797b2ded6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583023971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2583023971
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.958678146
Short name T275
Test name
Test status
Simulation time 2688928988 ps
CPU time 19.66 seconds
Started Jun 07 07:54:43 PM PDT 24
Finished Jun 07 07:55:04 PM PDT 24
Peak memory 233640 kb
Host smart-e19eec2c-c81b-4ca0-a7c2-37f3a637b43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958678146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.958678146
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1797056792
Short name T549
Test name
Test status
Simulation time 1167372432 ps
CPU time 5.45 seconds
Started Jun 07 07:54:44 PM PDT 24
Finished Jun 07 07:54:52 PM PDT 24
Peak memory 225336 kb
Host smart-82934f2f-c039-4a5c-99c2-7c189b3244df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797056792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1797056792
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2125634915
Short name T898
Test name
Test status
Simulation time 2275818503 ps
CPU time 9.65 seconds
Started Jun 07 07:54:45 PM PDT 24
Finished Jun 07 07:54:56 PM PDT 24
Peak memory 225420 kb
Host smart-e242f6a1-b4a3-4074-aa91-934207510824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125634915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2125634915
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1003651109
Short name T359
Test name
Test status
Simulation time 3271464830 ps
CPU time 6.53 seconds
Started Jun 07 07:54:44 PM PDT 24
Finished Jun 07 07:54:52 PM PDT 24
Peak memory 223536 kb
Host smart-124bb3d2-f8a5-446b-9a4a-63b26816c09c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1003651109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1003651109
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3789904095
Short name T713
Test name
Test status
Simulation time 62866504161 ps
CPU time 207.8 seconds
Started Jun 07 07:54:44 PM PDT 24
Finished Jun 07 07:58:13 PM PDT 24
Peak memory 250164 kb
Host smart-479106d3-e5d0-4b07-8088-0d11a46dd45b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789904095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3789904095
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.119339336
Short name T751
Test name
Test status
Simulation time 2195909731 ps
CPU time 28.13 seconds
Started Jun 07 07:54:45 PM PDT 24
Finished Jun 07 07:55:15 PM PDT 24
Peak memory 217536 kb
Host smart-a659d27e-fad3-4397-9518-0dd1c6e439b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119339336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.119339336
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2500973832
Short name T332
Test name
Test status
Simulation time 9841933869 ps
CPU time 12.7 seconds
Started Jun 07 07:54:45 PM PDT 24
Finished Jun 07 07:54:59 PM PDT 24
Peak memory 217288 kb
Host smart-5e101675-5e1d-46ac-b2f8-490ff7811c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500973832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2500973832
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2641815421
Short name T556
Test name
Test status
Simulation time 76500218 ps
CPU time 1.47 seconds
Started Jun 07 07:54:45 PM PDT 24
Finished Jun 07 07:54:48 PM PDT 24
Peak memory 217164 kb
Host smart-76f5a1e2-d18c-4ffd-afc6-adf452a952ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641815421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2641815421
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.731400822
Short name T820
Test name
Test status
Simulation time 33150052 ps
CPU time 0.79 seconds
Started Jun 07 07:54:43 PM PDT 24
Finished Jun 07 07:54:45 PM PDT 24
Peak memory 206680 kb
Host smart-31bcfa87-d9ff-407f-83af-1d5e1c03a87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731400822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.731400822
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.850678673
Short name T659
Test name
Test status
Simulation time 128218385 ps
CPU time 2.32 seconds
Started Jun 07 07:54:43 PM PDT 24
Finished Jun 07 07:54:47 PM PDT 24
Peak memory 225096 kb
Host smart-c20ff952-4ef5-4ac1-9f88-b8969c393cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850678673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.850678673
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3440202371
Short name T447
Test name
Test status
Simulation time 44145946 ps
CPU time 0.71 seconds
Started Jun 07 07:50:21 PM PDT 24
Finished Jun 07 07:50:26 PM PDT 24
Peak memory 206692 kb
Host smart-b0d74022-2a4e-4252-9827-f37f5d9e4f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440202371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
440202371
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.264097534
Short name T668
Test name
Test status
Simulation time 18078747 ps
CPU time 0.76 seconds
Started Jun 07 07:50:20 PM PDT 24
Finished Jun 07 07:50:26 PM PDT 24
Peak memory 206696 kb
Host smart-352732ea-2da6-4b79-aed4-32007706d49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264097534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.264097534
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2030177415
Short name T645
Test name
Test status
Simulation time 14390578464 ps
CPU time 67.93 seconds
Started Jun 07 07:50:22 PM PDT 24
Finished Jun 07 07:51:34 PM PDT 24
Peak memory 255836 kb
Host smart-b8ae0192-bbda-4429-a7bb-772ccd73b8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030177415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2030177415
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.4014011613
Short name T41
Test name
Test status
Simulation time 305937819419 ps
CPU time 767.38 seconds
Started Jun 07 07:50:20 PM PDT 24
Finished Jun 07 08:03:12 PM PDT 24
Peak memory 266236 kb
Host smart-31ee50fa-88cd-4f92-938f-ebf3de71b85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014011613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.4014011613
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.900585479
Short name T714
Test name
Test status
Simulation time 3791044109 ps
CPU time 31.34 seconds
Started Jun 07 07:50:21 PM PDT 24
Finished Jun 07 07:50:57 PM PDT 24
Peak memory 241868 kb
Host smart-3cfa0761-d883-427f-976f-74f1d0b7d94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900585479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
900585479
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1912806293
Short name T681
Test name
Test status
Simulation time 501663008 ps
CPU time 7.96 seconds
Started Jun 07 07:50:20 PM PDT 24
Finished Jun 07 07:50:32 PM PDT 24
Peak memory 233512 kb
Host smart-35fe76b6-7333-4b61-8224-fe181279c7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912806293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1912806293
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.755020625
Short name T776
Test name
Test status
Simulation time 243597120 ps
CPU time 4.06 seconds
Started Jun 07 07:50:19 PM PDT 24
Finished Jun 07 07:50:27 PM PDT 24
Peak memory 225412 kb
Host smart-82e583d5-42da-4097-b2c4-6f48c022c3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755020625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.755020625
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3832041640
Short name T103
Test name
Test status
Simulation time 5263487203 ps
CPU time 29.51 seconds
Started Jun 07 07:50:20 PM PDT 24
Finished Jun 07 07:50:53 PM PDT 24
Peak memory 241844 kb
Host smart-dd7746d7-e014-4b6d-a846-68a565e5a5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832041640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3832041640
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3370453744
Short name T225
Test name
Test status
Simulation time 409226111 ps
CPU time 3.59 seconds
Started Jun 07 07:50:23 PM PDT 24
Finished Jun 07 07:50:30 PM PDT 24
Peak memory 233548 kb
Host smart-5d833a8c-aa13-425c-9096-2e6ad4458d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370453744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3370453744
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2004443374
Short name T597
Test name
Test status
Simulation time 131820901 ps
CPU time 2.78 seconds
Started Jun 07 07:50:20 PM PDT 24
Finished Jun 07 07:50:27 PM PDT 24
Peak memory 224828 kb
Host smart-c78da705-dba8-486c-ae41-50fd7cf284b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004443374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2004443374
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3436777561
Short name T701
Test name
Test status
Simulation time 178732455 ps
CPU time 5.38 seconds
Started Jun 07 07:50:19 PM PDT 24
Finished Jun 07 07:50:29 PM PDT 24
Peak memory 219820 kb
Host smart-9bc19b08-c209-457b-ad5b-695d0b64ed35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3436777561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3436777561
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2066628693
Short name T75
Test name
Test status
Simulation time 98044172 ps
CPU time 1.19 seconds
Started Jun 07 07:50:19 PM PDT 24
Finished Jun 07 07:50:23 PM PDT 24
Peak memory 237404 kb
Host smart-2a073eed-5226-4b4b-8400-ed53fe97ffe0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066628693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2066628693
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1625795851
Short name T874
Test name
Test status
Simulation time 32341452243 ps
CPU time 196.45 seconds
Started Jun 07 07:50:22 PM PDT 24
Finished Jun 07 07:53:42 PM PDT 24
Peak memory 258328 kb
Host smart-4dbfd593-30de-44fe-a024-e18fecda9aed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625795851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1625795851
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.740598917
Short name T727
Test name
Test status
Simulation time 1089222210 ps
CPU time 6.41 seconds
Started Jun 07 07:50:20 PM PDT 24
Finished Jun 07 07:50:30 PM PDT 24
Peak memory 217220 kb
Host smart-c57d5d48-290b-4e95-a3fa-ec6b5d899c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740598917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.740598917
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1015814145
Short name T740
Test name
Test status
Simulation time 6029303073 ps
CPU time 17.56 seconds
Started Jun 07 07:50:19 PM PDT 24
Finished Jun 07 07:50:41 PM PDT 24
Peak memory 217196 kb
Host smart-ea4f989b-e4e2-4d15-b013-30e9e2b6af77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015814145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1015814145
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3286376585
Short name T684
Test name
Test status
Simulation time 151261626 ps
CPU time 5.15 seconds
Started Jun 07 07:50:20 PM PDT 24
Finished Jun 07 07:50:29 PM PDT 24
Peak memory 217128 kb
Host smart-9ad6904b-b6c3-4b5d-81ac-2ad07b644bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286376585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3286376585
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1451367032
Short name T463
Test name
Test status
Simulation time 130379353 ps
CPU time 0.81 seconds
Started Jun 07 07:50:20 PM PDT 24
Finished Jun 07 07:50:24 PM PDT 24
Peak memory 206660 kb
Host smart-58a246f3-3a01-423f-bdd2-1f34b713c26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451367032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1451367032
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2123300841
Short name T433
Test name
Test status
Simulation time 91862675 ps
CPU time 2.81 seconds
Started Jun 07 07:50:22 PM PDT 24
Finished Jun 07 07:50:29 PM PDT 24
Peak memory 225188 kb
Host smart-dd93927f-8347-4cc4-9d76-ae4520cc5e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123300841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2123300841
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1549752872
Short name T326
Test name
Test status
Simulation time 15497050 ps
CPU time 0.71 seconds
Started Jun 07 07:54:52 PM PDT 24
Finished Jun 07 07:54:54 PM PDT 24
Peak memory 205676 kb
Host smart-4b4499f8-a2f5-436c-a52e-a3e62b8787a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549752872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1549752872
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2292602315
Short name T184
Test name
Test status
Simulation time 785696616 ps
CPU time 3.31 seconds
Started Jun 07 07:54:49 PM PDT 24
Finished Jun 07 07:54:53 PM PDT 24
Peak memory 233508 kb
Host smart-ff2bdd0f-69ac-4e16-b1d6-3b16820fc896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292602315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2292602315
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.157938349
Short name T805
Test name
Test status
Simulation time 66454318 ps
CPU time 0.77 seconds
Started Jun 07 07:54:43 PM PDT 24
Finished Jun 07 07:54:46 PM PDT 24
Peak memory 207416 kb
Host smart-b74f5b10-3928-4fb0-add2-af1040dc812d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157938349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.157938349
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.21733569
Short name T806
Test name
Test status
Simulation time 91552733643 ps
CPU time 198.03 seconds
Started Jun 07 07:54:51 PM PDT 24
Finished Jun 07 07:58:10 PM PDT 24
Peak memory 250088 kb
Host smart-398a6b3a-b92e-4a97-af5e-e0903cd762e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21733569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.21733569
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3421061095
Short name T245
Test name
Test status
Simulation time 29518829105 ps
CPU time 141.18 seconds
Started Jun 07 07:54:51 PM PDT 24
Finished Jun 07 07:57:14 PM PDT 24
Peak memory 239536 kb
Host smart-6704fe6e-2a26-449b-99b5-59712aafdec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421061095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3421061095
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1688829510
Short name T303
Test name
Test status
Simulation time 3263609350 ps
CPU time 27.54 seconds
Started Jun 07 07:54:43 PM PDT 24
Finished Jun 07 07:55:12 PM PDT 24
Peak memory 225512 kb
Host smart-70959c5c-5ca0-4ef9-9a9a-d4af4e87e297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688829510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1688829510
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4158175166
Short name T850
Test name
Test status
Simulation time 5266153189 ps
CPU time 12.62 seconds
Started Jun 07 07:54:48 PM PDT 24
Finished Jun 07 07:55:02 PM PDT 24
Peak memory 233644 kb
Host smart-80fbb95f-b8ea-4016-8ce6-2a82bd49788a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158175166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4158175166
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.398258873
Short name T278
Test name
Test status
Simulation time 12485648445 ps
CPU time 23.06 seconds
Started Jun 07 07:54:45 PM PDT 24
Finished Jun 07 07:55:10 PM PDT 24
Peak memory 219556 kb
Host smart-2b70e438-b765-491d-825c-eb1000c08b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398258873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.398258873
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.429731120
Short name T165
Test name
Test status
Simulation time 3947972731 ps
CPU time 14.1 seconds
Started Jun 07 07:54:45 PM PDT 24
Finished Jun 07 07:55:01 PM PDT 24
Peak memory 241804 kb
Host smart-3d0dbae1-211d-4ee4-8b16-bdfdfbb61ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429731120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.429731120
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2358593101
Short name T929
Test name
Test status
Simulation time 197497512 ps
CPU time 4.21 seconds
Started Jun 07 07:54:51 PM PDT 24
Finished Jun 07 07:54:56 PM PDT 24
Peak memory 223904 kb
Host smart-69ee0510-3a2d-47d5-9ad8-722f018e162e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2358593101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2358593101
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3154774087
Short name T308
Test name
Test status
Simulation time 1008091050 ps
CPU time 13.72 seconds
Started Jun 07 07:54:43 PM PDT 24
Finished Jun 07 07:54:59 PM PDT 24
Peak memory 220232 kb
Host smart-ae795833-a939-40ea-af24-93f21a66e431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154774087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3154774087
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.437747706
Short name T736
Test name
Test status
Simulation time 85945157 ps
CPU time 1.09 seconds
Started Jun 07 07:54:43 PM PDT 24
Finished Jun 07 07:54:46 PM PDT 24
Peak memory 208740 kb
Host smart-bd77ca30-8d40-413c-a786-b4d655fc5a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437747706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.437747706
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1726340699
Short name T350
Test name
Test status
Simulation time 409530691 ps
CPU time 5.72 seconds
Started Jun 07 07:54:43 PM PDT 24
Finished Jun 07 07:54:51 PM PDT 24
Peak memory 217124 kb
Host smart-27d39a5c-81f9-44b0-9d82-42c00f2dce2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726340699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1726340699
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2450166063
Short name T502
Test name
Test status
Simulation time 194141113 ps
CPU time 0.87 seconds
Started Jun 07 07:54:46 PM PDT 24
Finished Jun 07 07:54:48 PM PDT 24
Peak memory 207108 kb
Host smart-891092fe-52da-4769-a39f-00a5b537ff92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450166063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2450166063
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1852050987
Short name T426
Test name
Test status
Simulation time 1777596891 ps
CPU time 5.11 seconds
Started Jun 07 07:54:46 PM PDT 24
Finished Jun 07 07:54:52 PM PDT 24
Peak memory 225348 kb
Host smart-f821d199-0e4d-4c7a-a3ff-aedb77f72288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852050987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1852050987
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3193948958
Short name T488
Test name
Test status
Simulation time 21939798 ps
CPU time 0.7 seconds
Started Jun 07 07:54:59 PM PDT 24
Finished Jun 07 07:55:01 PM PDT 24
Peak memory 205672 kb
Host smart-500dbf7e-25a5-451f-9517-67c82d2cb8f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193948958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3193948958
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3311538530
Short name T253
Test name
Test status
Simulation time 4737110940 ps
CPU time 11.39 seconds
Started Jun 07 07:54:53 PM PDT 24
Finished Jun 07 07:55:06 PM PDT 24
Peak memory 233672 kb
Host smart-adb5a20e-a08f-4e1a-8868-f6ab7b74658d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311538530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3311538530
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1013365318
Short name T809
Test name
Test status
Simulation time 24465022 ps
CPU time 0.75 seconds
Started Jun 07 07:54:50 PM PDT 24
Finished Jun 07 07:54:52 PM PDT 24
Peak memory 206704 kb
Host smart-994eb3a6-442d-42d8-97ba-1cafeacca21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013365318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1013365318
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.877093779
Short name T625
Test name
Test status
Simulation time 30810190 ps
CPU time 0.79 seconds
Started Jun 07 07:55:03 PM PDT 24
Finished Jun 07 07:55:05 PM PDT 24
Peak memory 216652 kb
Host smart-7b1fd71d-b31d-4648-a925-23784d7baee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877093779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.877093779
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.11011415
Short name T290
Test name
Test status
Simulation time 29881766645 ps
CPU time 107.72 seconds
Started Jun 07 07:55:00 PM PDT 24
Finished Jun 07 07:56:50 PM PDT 24
Peak memory 255016 kb
Host smart-07705d71-63a2-4844-92b2-b4c8f303dd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11011415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.11011415
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3969616722
Short name T664
Test name
Test status
Simulation time 31188812447 ps
CPU time 100.62 seconds
Started Jun 07 07:54:58 PM PDT 24
Finished Jun 07 07:56:40 PM PDT 24
Peak memory 249996 kb
Host smart-8620715f-f3ca-4a83-baf9-c4a06151cc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969616722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3969616722
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1306720725
Short name T914
Test name
Test status
Simulation time 2022812185 ps
CPU time 31.24 seconds
Started Jun 07 07:54:50 PM PDT 24
Finished Jun 07 07:55:22 PM PDT 24
Peak memory 234888 kb
Host smart-df592e26-4ee3-45c8-b3be-7f5b32eecf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306720725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1306720725
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.881128229
Short name T497
Test name
Test status
Simulation time 12208222943 ps
CPU time 31.58 seconds
Started Jun 07 07:54:55 PM PDT 24
Finished Jun 07 07:55:28 PM PDT 24
Peak memory 233652 kb
Host smart-f7afcd1d-93c5-46e2-acd8-11d0ccb24cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881128229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.881128229
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.402708390
Short name T716
Test name
Test status
Simulation time 7784077092 ps
CPU time 27.75 seconds
Started Jun 07 07:54:51 PM PDT 24
Finished Jun 07 07:55:20 PM PDT 24
Peak memory 234600 kb
Host smart-619ddcbf-e94b-4c9b-a940-3bacb92cbd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402708390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.402708390
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.695804577
Short name T455
Test name
Test status
Simulation time 13755489344 ps
CPU time 12.88 seconds
Started Jun 07 07:54:55 PM PDT 24
Finished Jun 07 07:55:09 PM PDT 24
Peak memory 225460 kb
Host smart-60867d70-5b1e-44d4-a551-efb2755d6174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695804577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.695804577
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.185738642
Short name T233
Test name
Test status
Simulation time 5831137242 ps
CPU time 17.07 seconds
Started Jun 07 07:54:51 PM PDT 24
Finished Jun 07 07:55:09 PM PDT 24
Peak memory 233708 kb
Host smart-de7aaa7c-ae8d-4ff2-aa82-37e02d0c4307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185738642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.185738642
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.556245015
Short name T626
Test name
Test status
Simulation time 570594574 ps
CPU time 4.35 seconds
Started Jun 07 07:54:51 PM PDT 24
Finished Jun 07 07:54:56 PM PDT 24
Peak memory 224048 kb
Host smart-732bb1d0-b30e-4d65-a707-dd0d5543a8fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=556245015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.556245015
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4151679329
Short name T289
Test name
Test status
Simulation time 57363349417 ps
CPU time 315.63 seconds
Started Jun 07 07:54:58 PM PDT 24
Finished Jun 07 08:00:15 PM PDT 24
Peak memory 274716 kb
Host smart-33ed1390-d433-4d9a-ae36-ca043514531f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151679329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4151679329
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.204051739
Short name T469
Test name
Test status
Simulation time 5505519029 ps
CPU time 31.84 seconds
Started Jun 07 07:54:52 PM PDT 24
Finished Jun 07 07:55:25 PM PDT 24
Peak memory 217368 kb
Host smart-0929ea72-b377-4334-882a-b9db408bc5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204051739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.204051739
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1692518768
Short name T338
Test name
Test status
Simulation time 33532433389 ps
CPU time 8.21 seconds
Started Jun 07 07:54:50 PM PDT 24
Finished Jun 07 07:55:00 PM PDT 24
Peak memory 218308 kb
Host smart-ccc8b1fa-1e15-4c50-92b1-1c342c3f2915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692518768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1692518768
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1529040157
Short name T413
Test name
Test status
Simulation time 124706846 ps
CPU time 1.68 seconds
Started Jun 07 07:54:50 PM PDT 24
Finished Jun 07 07:54:53 PM PDT 24
Peak memory 217104 kb
Host smart-3fa905a8-da03-4a57-ab48-346bd4d79b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529040157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1529040157
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.512727714
Short name T705
Test name
Test status
Simulation time 31090528 ps
CPU time 0.77 seconds
Started Jun 07 07:54:54 PM PDT 24
Finished Jun 07 07:54:55 PM PDT 24
Peak memory 206676 kb
Host smart-6c4eb558-cefe-4dbb-be37-3fb0486829f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512727714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.512727714
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3353270343
Short name T702
Test name
Test status
Simulation time 1570908082 ps
CPU time 6.51 seconds
Started Jun 07 07:54:51 PM PDT 24
Finished Jun 07 07:54:59 PM PDT 24
Peak memory 225384 kb
Host smart-75052e9d-259c-4039-8e54-4b859bcbc8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353270343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3353270343
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.950721716
Short name T62
Test name
Test status
Simulation time 11727119 ps
CPU time 0.75 seconds
Started Jun 07 07:54:59 PM PDT 24
Finished Jun 07 07:55:01 PM PDT 24
Peak memory 206232 kb
Host smart-06c9a9aa-0b96-4c57-81ee-bb00c87f3529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950721716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.950721716
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4293459400
Short name T726
Test name
Test status
Simulation time 322047795 ps
CPU time 2.85 seconds
Started Jun 07 07:55:03 PM PDT 24
Finished Jun 07 07:55:08 PM PDT 24
Peak memory 225288 kb
Host smart-4977a8b0-1b64-4b08-a50b-17ed1bcfc61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293459400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4293459400
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1316616359
Short name T422
Test name
Test status
Simulation time 18159311 ps
CPU time 0.81 seconds
Started Jun 07 07:55:00 PM PDT 24
Finished Jun 07 07:55:03 PM PDT 24
Peak memory 207412 kb
Host smart-d28d8854-8d89-4c33-b3cc-676833c382ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316616359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1316616359
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2222988353
Short name T605
Test name
Test status
Simulation time 9211642028 ps
CPU time 55.55 seconds
Started Jun 07 07:55:00 PM PDT 24
Finished Jun 07 07:55:58 PM PDT 24
Peak memory 252560 kb
Host smart-45ca73c3-e388-4fcb-8f1e-3301e2eb93e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222988353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2222988353
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.329017132
Short name T655
Test name
Test status
Simulation time 1310884935 ps
CPU time 11.16 seconds
Started Jun 07 07:55:03 PM PDT 24
Finished Jun 07 07:55:15 PM PDT 24
Peak memory 233564 kb
Host smart-5401ca7c-e347-4c61-9b8b-5abf4a5b96ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329017132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.329017132
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2927218448
Short name T33
Test name
Test status
Simulation time 1024138811 ps
CPU time 13.51 seconds
Started Jun 07 07:54:57 PM PDT 24
Finished Jun 07 07:55:12 PM PDT 24
Peak memory 233576 kb
Host smart-df38ccba-b0ae-43db-8095-d5208322cb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927218448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2927218448
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2576759785
Short name T476
Test name
Test status
Simulation time 6248747251 ps
CPU time 36.69 seconds
Started Jun 07 07:55:01 PM PDT 24
Finished Jun 07 07:55:39 PM PDT 24
Peak memory 241632 kb
Host smart-ae8989b6-6a56-4ad4-b825-9f1fa0f0b4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576759785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2576759785
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.993355992
Short name T896
Test name
Test status
Simulation time 124328603 ps
CPU time 3.04 seconds
Started Jun 07 07:55:01 PM PDT 24
Finished Jun 07 07:55:06 PM PDT 24
Peak memory 233584 kb
Host smart-f8080ecc-f763-4bb3-becd-d121c11ec0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993355992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.993355992
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.466873431
Short name T80
Test name
Test status
Simulation time 16303640067 ps
CPU time 12.21 seconds
Started Jun 07 07:55:00 PM PDT 24
Finished Jun 07 07:55:14 PM PDT 24
Peak memory 233672 kb
Host smart-3534f27b-1d6a-414d-9529-10d1c3f5a5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466873431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.466873431
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1547064242
Short name T581
Test name
Test status
Simulation time 1861732740 ps
CPU time 10.05 seconds
Started Jun 07 07:55:03 PM PDT 24
Finished Jun 07 07:55:15 PM PDT 24
Peak memory 222768 kb
Host smart-125466fb-50ec-4141-b8fc-d331ce4c746c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1547064242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1547064242
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1521027683
Short name T157
Test name
Test status
Simulation time 235867812 ps
CPU time 1.25 seconds
Started Jun 07 07:55:02 PM PDT 24
Finished Jun 07 07:55:04 PM PDT 24
Peak memory 208032 kb
Host smart-034896b1-8aae-4a0c-b44e-4439ca121216
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521027683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1521027683
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2954533554
Short name T798
Test name
Test status
Simulation time 983383929 ps
CPU time 9.68 seconds
Started Jun 07 07:55:02 PM PDT 24
Finished Jun 07 07:55:13 PM PDT 24
Peak memory 217116 kb
Host smart-4ab69873-5ed3-4c5b-9a9c-3581a964d4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954533554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2954533554
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3410696392
Short name T819
Test name
Test status
Simulation time 8373000469 ps
CPU time 26.69 seconds
Started Jun 07 07:54:57 PM PDT 24
Finished Jun 07 07:55:25 PM PDT 24
Peak memory 217236 kb
Host smart-c81efb5b-635f-47f3-8588-9fdc7d61c27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410696392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3410696392
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.518474538
Short name T928
Test name
Test status
Simulation time 557840299 ps
CPU time 1.92 seconds
Started Jun 07 07:55:00 PM PDT 24
Finished Jun 07 07:55:04 PM PDT 24
Peak memory 217084 kb
Host smart-bbb4e885-cb9f-4e69-9244-089dcb9f5432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518474538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.518474538
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2642532554
Short name T436
Test name
Test status
Simulation time 14749262 ps
CPU time 0.7 seconds
Started Jun 07 07:55:02 PM PDT 24
Finished Jun 07 07:55:04 PM PDT 24
Peak memory 206344 kb
Host smart-1d93a5f3-acdf-40ef-a388-0c68a8b0ffd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642532554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2642532554
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1703117143
Short name T638
Test name
Test status
Simulation time 4901231002 ps
CPU time 10.92 seconds
Started Jun 07 07:54:58 PM PDT 24
Finished Jun 07 07:55:11 PM PDT 24
Peak memory 233640 kb
Host smart-a90118fd-ba45-4a77-80a7-fdf4a3d00082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703117143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1703117143
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2080514200
Short name T347
Test name
Test status
Simulation time 42464442 ps
CPU time 0.73 seconds
Started Jun 07 07:55:10 PM PDT 24
Finished Jun 07 07:55:12 PM PDT 24
Peak memory 205676 kb
Host smart-1feb2535-ad17-4421-82cb-40aaee81580e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080514200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2080514200
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2009199620
Short name T817
Test name
Test status
Simulation time 686685529 ps
CPU time 5.02 seconds
Started Jun 07 07:55:09 PM PDT 24
Finished Jun 07 07:55:15 PM PDT 24
Peak memory 225344 kb
Host smart-3fdddf3b-7f15-4c24-96fc-60eb23aad325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009199620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2009199620
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2459967827
Short name T694
Test name
Test status
Simulation time 24317276 ps
CPU time 0.83 seconds
Started Jun 07 07:55:00 PM PDT 24
Finished Jun 07 07:55:03 PM PDT 24
Peak memory 207412 kb
Host smart-304150ae-04df-4051-869d-13ee0e702cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459967827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2459967827
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2160595124
Short name T610
Test name
Test status
Simulation time 4336062522 ps
CPU time 31.72 seconds
Started Jun 07 07:55:09 PM PDT 24
Finished Jun 07 07:55:42 PM PDT 24
Peak memory 241836 kb
Host smart-245be112-d8b0-4568-95ab-bbf2e3f323f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160595124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2160595124
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3681545029
Short name T745
Test name
Test status
Simulation time 41785664218 ps
CPU time 234.3 seconds
Started Jun 07 07:55:07 PM PDT 24
Finished Jun 07 07:59:03 PM PDT 24
Peak memory 252024 kb
Host smart-80a0b909-648d-4d1d-b8a1-4a37d87b8f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681545029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3681545029
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.546967594
Short name T483
Test name
Test status
Simulation time 6898820532 ps
CPU time 38.92 seconds
Started Jun 07 07:55:06 PM PDT 24
Finished Jun 07 07:55:47 PM PDT 24
Peak memory 218480 kb
Host smart-4968674e-5cdc-4dae-b359-419ccd77fe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546967594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.546967594
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3700915883
Short name T19
Test name
Test status
Simulation time 575407509 ps
CPU time 15.73 seconds
Started Jun 07 07:55:08 PM PDT 24
Finished Jun 07 07:55:25 PM PDT 24
Peak memory 249920 kb
Host smart-19e2fe97-f9c3-4b44-b7cc-59e42ca23091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700915883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3700915883
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.78811893
Short name T634
Test name
Test status
Simulation time 77182489 ps
CPU time 3.5 seconds
Started Jun 07 07:55:09 PM PDT 24
Finished Jun 07 07:55:14 PM PDT 24
Peak memory 229200 kb
Host smart-d9b4eac3-200a-4645-9700-86bd1e085a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78811893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.78811893
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1737271365
Short name T160
Test name
Test status
Simulation time 1124929417 ps
CPU time 7.92 seconds
Started Jun 07 07:55:09 PM PDT 24
Finished Jun 07 07:55:18 PM PDT 24
Peak memory 233588 kb
Host smart-ff6d77c3-700a-466e-8345-47ff95f9b8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737271365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1737271365
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2438157208
Short name T5
Test name
Test status
Simulation time 105036791 ps
CPU time 2.71 seconds
Started Jun 07 07:55:08 PM PDT 24
Finished Jun 07 07:55:12 PM PDT 24
Peak memory 233548 kb
Host smart-5ddcdada-526d-46e7-8593-56fc0c700f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438157208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2438157208
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1630971337
Short name T629
Test name
Test status
Simulation time 797981246 ps
CPU time 9.66 seconds
Started Jun 07 07:55:10 PM PDT 24
Finished Jun 07 07:55:21 PM PDT 24
Peak memory 233544 kb
Host smart-63204233-bb86-4654-9a8a-dbfec319ab86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630971337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1630971337
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1613663810
Short name T852
Test name
Test status
Simulation time 142339794 ps
CPU time 3.78 seconds
Started Jun 07 07:55:08 PM PDT 24
Finished Jun 07 07:55:14 PM PDT 24
Peak memory 221260 kb
Host smart-8aaeb1bf-fc6d-4518-9add-267b03beb57d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1613663810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1613663810
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2662281704
Short name T897
Test name
Test status
Simulation time 20603916755 ps
CPU time 242.43 seconds
Started Jun 07 07:55:10 PM PDT 24
Finished Jun 07 07:59:14 PM PDT 24
Peak memory 265396 kb
Host smart-5be1b816-dfd1-4fcc-a297-86500a2edd41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662281704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2662281704
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1773942050
Short name T79
Test name
Test status
Simulation time 2634416172 ps
CPU time 30.52 seconds
Started Jun 07 07:55:08 PM PDT 24
Finished Jun 07 07:55:40 PM PDT 24
Peak memory 217300 kb
Host smart-76288378-3f14-43ad-9153-a2e71098fb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773942050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1773942050
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1522237559
Short name T593
Test name
Test status
Simulation time 40564077631 ps
CPU time 27.6 seconds
Started Jun 07 07:55:09 PM PDT 24
Finished Jun 07 07:55:38 PM PDT 24
Peak memory 217272 kb
Host smart-49a666bd-ae28-4cf0-9c08-dacea6eb60ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522237559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1522237559
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3425385577
Short name T901
Test name
Test status
Simulation time 122167742 ps
CPU time 2.76 seconds
Started Jun 07 07:55:06 PM PDT 24
Finished Jun 07 07:55:10 PM PDT 24
Peak memory 217156 kb
Host smart-9ca22870-fab8-4bc4-bf75-55cc828782bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425385577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3425385577
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.587154945
Short name T484
Test name
Test status
Simulation time 58340703 ps
CPU time 0.83 seconds
Started Jun 07 07:55:07 PM PDT 24
Finished Jun 07 07:55:09 PM PDT 24
Peak memory 206732 kb
Host smart-d213b198-487f-4759-a864-9a30b6a2c6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587154945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.587154945
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1282442352
Short name T746
Test name
Test status
Simulation time 136412038 ps
CPU time 4.01 seconds
Started Jun 07 07:55:08 PM PDT 24
Finished Jun 07 07:55:14 PM PDT 24
Peak memory 233536 kb
Host smart-b7cde5e0-94c4-488a-859b-c6fe62c2e57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282442352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1282442352
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.843371846
Short name T599
Test name
Test status
Simulation time 26238248 ps
CPU time 0.73 seconds
Started Jun 07 07:55:20 PM PDT 24
Finished Jun 07 07:55:22 PM PDT 24
Peak memory 206272 kb
Host smart-8fa4d36a-534b-4185-a25f-f16f34438742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843371846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.843371846
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1532008037
Short name T449
Test name
Test status
Simulation time 542251075 ps
CPU time 6.61 seconds
Started Jun 07 07:55:23 PM PDT 24
Finished Jun 07 07:55:30 PM PDT 24
Peak memory 225296 kb
Host smart-571bce45-904e-4a92-94a2-f06e3fbbbdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532008037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1532008037
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2747625917
Short name T429
Test name
Test status
Simulation time 30951866 ps
CPU time 0.78 seconds
Started Jun 07 07:55:08 PM PDT 24
Finished Jun 07 07:55:10 PM PDT 24
Peak memory 206696 kb
Host smart-d8ac37cb-cbf4-48af-9344-f2cec5ba63a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747625917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2747625917
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2665824223
Short name T857
Test name
Test status
Simulation time 2835660053 ps
CPU time 48.49 seconds
Started Jun 07 07:55:18 PM PDT 24
Finished Jun 07 07:56:08 PM PDT 24
Peak memory 257928 kb
Host smart-0115936a-24c6-489e-b35f-3a344dfaf32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665824223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2665824223
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1763022344
Short name T35
Test name
Test status
Simulation time 132410504639 ps
CPU time 315.27 seconds
Started Jun 07 07:55:19 PM PDT 24
Finished Jun 07 08:00:35 PM PDT 24
Peak memory 250104 kb
Host smart-a489e05c-b5a0-4074-86a0-cca51a14b6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763022344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1763022344
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2175475910
Short name T301
Test name
Test status
Simulation time 32495202797 ps
CPU time 48.4 seconds
Started Jun 07 07:55:18 PM PDT 24
Finished Jun 07 07:56:08 PM PDT 24
Peak memory 241848 kb
Host smart-d97c1c80-6288-4368-9a3c-f1f748645093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175475910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2175475910
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2769728498
Short name T96
Test name
Test status
Simulation time 78082937 ps
CPU time 3.03 seconds
Started Jun 07 07:55:18 PM PDT 24
Finished Jun 07 07:55:23 PM PDT 24
Peak memory 225404 kb
Host smart-1ae40f5a-5821-47c2-a7e3-364aa20293e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769728498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2769728498
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.544645318
Short name T249
Test name
Test status
Simulation time 2346398436 ps
CPU time 8.22 seconds
Started Jun 07 07:55:18 PM PDT 24
Finished Jun 07 07:55:28 PM PDT 24
Peak memory 225404 kb
Host smart-b9bf609f-7f60-4f52-bebd-cf550b068be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544645318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.544645318
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2258441195
Short name T11
Test name
Test status
Simulation time 8517935943 ps
CPU time 43.22 seconds
Started Jun 07 07:55:17 PM PDT 24
Finished Jun 07 07:56:02 PM PDT 24
Peak memory 233592 kb
Host smart-65f9c7d6-e028-4ff8-a14f-0620c5c3ee9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258441195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2258441195
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.669783197
Short name T478
Test name
Test status
Simulation time 132882516 ps
CPU time 2.67 seconds
Started Jun 07 07:55:17 PM PDT 24
Finished Jun 07 07:55:21 PM PDT 24
Peak memory 233516 kb
Host smart-78affe12-34b3-4df5-9c62-af4bfb2c2b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669783197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.669783197
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.813881015
Short name T765
Test name
Test status
Simulation time 2408882158 ps
CPU time 7.83 seconds
Started Jun 07 07:55:18 PM PDT 24
Finished Jun 07 07:55:27 PM PDT 24
Peak memory 249584 kb
Host smart-fb3ea7fe-b3a0-4dc5-9cf7-3bd0e77b1d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813881015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.813881015
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2135201062
Short name T849
Test name
Test status
Simulation time 2177045221 ps
CPU time 8.22 seconds
Started Jun 07 07:55:17 PM PDT 24
Finished Jun 07 07:55:27 PM PDT 24
Peak memory 223812 kb
Host smart-3d3516d8-26aa-4c7b-b916-e17d8e523db3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2135201062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2135201062
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3581416596
Short name T941
Test name
Test status
Simulation time 32432564990 ps
CPU time 169.83 seconds
Started Jun 07 07:55:16 PM PDT 24
Finished Jun 07 07:58:07 PM PDT 24
Peak memory 255440 kb
Host smart-a8d81dcb-6a7a-4177-be9f-a017592add6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581416596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3581416596
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3893639615
Short name T565
Test name
Test status
Simulation time 1758418803 ps
CPU time 18.49 seconds
Started Jun 07 07:55:16 PM PDT 24
Finished Jun 07 07:55:36 PM PDT 24
Peak memory 217208 kb
Host smart-aa874a08-03a0-43b9-b5ad-d00a691a3c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893639615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3893639615
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4277079484
Short name T477
Test name
Test status
Simulation time 14176919559 ps
CPU time 21.68 seconds
Started Jun 07 07:55:09 PM PDT 24
Finished Jun 07 07:55:32 PM PDT 24
Peak memory 217260 kb
Host smart-bc071020-405d-4b99-88e4-bc61f93d6c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277079484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4277079484
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1202338380
Short name T946
Test name
Test status
Simulation time 60941784 ps
CPU time 0.85 seconds
Started Jun 07 07:55:18 PM PDT 24
Finished Jun 07 07:55:20 PM PDT 24
Peak memory 207240 kb
Host smart-2f2ca132-e40e-4bce-9206-6807565928e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202338380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1202338380
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4210148896
Short name T403
Test name
Test status
Simulation time 35495801 ps
CPU time 0.75 seconds
Started Jun 07 07:55:18 PM PDT 24
Finished Jun 07 07:55:20 PM PDT 24
Peak memory 206728 kb
Host smart-3515d9ff-e83a-42b4-a384-1829208c872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210148896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4210148896
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2871347277
Short name T179
Test name
Test status
Simulation time 258328801 ps
CPU time 2.33 seconds
Started Jun 07 07:55:18 PM PDT 24
Finished Jun 07 07:55:22 PM PDT 24
Peak memory 225232 kb
Host smart-b91b5571-a7f5-4b02-8a65-db54e6f9bc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871347277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2871347277
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2961756081
Short name T398
Test name
Test status
Simulation time 23247444 ps
CPU time 0.76 seconds
Started Jun 07 07:55:27 PM PDT 24
Finished Jun 07 07:55:30 PM PDT 24
Peak memory 206620 kb
Host smart-1ff1c2f0-d58e-4afc-8395-d28c65e89444
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961756081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2961756081
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3744382864
Short name T180
Test name
Test status
Simulation time 166959968 ps
CPU time 4.84 seconds
Started Jun 07 07:55:28 PM PDT 24
Finished Jun 07 07:55:34 PM PDT 24
Peak memory 233560 kb
Host smart-d4389a8e-b8dc-43ce-aed8-b7e597a91685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744382864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3744382864
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1743304867
Short name T370
Test name
Test status
Simulation time 68450432 ps
CPU time 0.75 seconds
Started Jun 07 07:55:20 PM PDT 24
Finished Jun 07 07:55:22 PM PDT 24
Peak memory 206396 kb
Host smart-830c5c61-65ff-43bc-96c1-b5f71da969ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743304867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1743304867
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2272285925
Short name T284
Test name
Test status
Simulation time 125524685151 ps
CPU time 126.68 seconds
Started Jun 07 07:55:34 PM PDT 24
Finished Jun 07 07:57:42 PM PDT 24
Peak memory 255772 kb
Host smart-9063814a-a031-4efa-804f-8319c18dc643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272285925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2272285925
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3669974304
Short name T603
Test name
Test status
Simulation time 47995700444 ps
CPU time 111.48 seconds
Started Jun 07 07:55:27 PM PDT 24
Finished Jun 07 07:57:21 PM PDT 24
Peak memory 252120 kb
Host smart-727e249c-edba-4614-b58f-cea40da288cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669974304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3669974304
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3207255215
Short name T451
Test name
Test status
Simulation time 1994538166 ps
CPU time 11.87 seconds
Started Jun 07 07:55:26 PM PDT 24
Finished Jun 07 07:55:39 PM PDT 24
Peak memory 225324 kb
Host smart-58830af4-017e-4a35-8338-621d8996d551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207255215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3207255215
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.156869493
Short name T804
Test name
Test status
Simulation time 97478888 ps
CPU time 3.87 seconds
Started Jun 07 07:55:26 PM PDT 24
Finished Jun 07 07:55:31 PM PDT 24
Peak memory 233544 kb
Host smart-f7f75961-2e46-48d4-9852-36f737ccdc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156869493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.156869493
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.730842087
Short name T163
Test name
Test status
Simulation time 95270503 ps
CPU time 2.44 seconds
Started Jun 07 07:55:27 PM PDT 24
Finished Jun 07 07:55:32 PM PDT 24
Peak memory 225336 kb
Host smart-b50ed64f-0ca4-4395-ac10-d8fc998aed3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730842087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.730842087
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3949815190
Short name T465
Test name
Test status
Simulation time 2675752174 ps
CPU time 10.61 seconds
Started Jun 07 07:55:34 PM PDT 24
Finished Jun 07 07:55:47 PM PDT 24
Peak memory 225424 kb
Host smart-b05e8660-2aa3-4242-8123-2bc9e052a98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949815190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3949815190
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1240433264
Short name T649
Test name
Test status
Simulation time 7477706710 ps
CPU time 12.22 seconds
Started Jun 07 07:55:18 PM PDT 24
Finished Jun 07 07:55:32 PM PDT 24
Peak memory 219552 kb
Host smart-98ccecb3-e56d-4b90-b650-771b84928958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240433264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1240433264
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.240243916
Short name T572
Test name
Test status
Simulation time 17536290627 ps
CPU time 13.11 seconds
Started Jun 07 07:55:18 PM PDT 24
Finished Jun 07 07:55:32 PM PDT 24
Peak memory 233676 kb
Host smart-64b042fa-bff8-4398-bc1e-774b515b638f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240243916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.240243916
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1500462065
Short name T758
Test name
Test status
Simulation time 636246986 ps
CPU time 7.72 seconds
Started Jun 07 07:55:27 PM PDT 24
Finished Jun 07 07:55:37 PM PDT 24
Peak memory 223816 kb
Host smart-1088f8fb-f529-4687-8eec-6946bf2dfec1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1500462065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1500462065
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.355312013
Short name T938
Test name
Test status
Simulation time 79132591745 ps
CPU time 198.85 seconds
Started Jun 07 07:55:28 PM PDT 24
Finished Jun 07 07:58:48 PM PDT 24
Peak memory 258292 kb
Host smart-3db33df5-80ce-4046-89cf-00e06109cb1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355312013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.355312013
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3920877579
Short name T542
Test name
Test status
Simulation time 17716636825 ps
CPU time 17.83 seconds
Started Jun 07 07:55:18 PM PDT 24
Finished Jun 07 07:55:37 PM PDT 24
Peak memory 217120 kb
Host smart-50d5b385-8b21-47d5-823e-916ee9b55c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920877579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3920877579
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3139796763
Short name T811
Test name
Test status
Simulation time 554548010 ps
CPU time 1.98 seconds
Started Jun 07 07:55:16 PM PDT 24
Finished Jun 07 07:55:19 PM PDT 24
Peak memory 216944 kb
Host smart-9ef69ff8-d3a7-49a0-985e-cabab4987032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139796763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3139796763
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.452904072
Short name T675
Test name
Test status
Simulation time 112879738 ps
CPU time 1.28 seconds
Started Jun 07 07:55:23 PM PDT 24
Finished Jun 07 07:55:25 PM PDT 24
Peak memory 217088 kb
Host smart-fcde6880-1a3c-460a-bcb4-00f95632828a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452904072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.452904072
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1654782078
Short name T492
Test name
Test status
Simulation time 24757827 ps
CPU time 0.7 seconds
Started Jun 07 07:55:20 PM PDT 24
Finished Jun 07 07:55:21 PM PDT 24
Peak memory 206716 kb
Host smart-99a23ff2-11fe-4174-b4c0-ebcd8074adbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654782078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1654782078
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.464057483
Short name T548
Test name
Test status
Simulation time 1961868310 ps
CPU time 4.21 seconds
Started Jun 07 07:55:34 PM PDT 24
Finished Jun 07 07:55:40 PM PDT 24
Peak memory 233492 kb
Host smart-3b64b406-3ec7-46a6-8a9e-b7bab5773940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464057483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.464057483
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.4127958567
Short name T428
Test name
Test status
Simulation time 11464797 ps
CPU time 0.74 seconds
Started Jun 07 07:55:28 PM PDT 24
Finished Jun 07 07:55:31 PM PDT 24
Peak memory 206584 kb
Host smart-b404fce3-e872-4ab4-ae1c-13af1f5ec512
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127958567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
4127958567
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3776332992
Short name T943
Test name
Test status
Simulation time 601007745 ps
CPU time 4.43 seconds
Started Jun 07 07:55:25 PM PDT 24
Finished Jun 07 07:55:31 PM PDT 24
Peak memory 233552 kb
Host smart-9d87abc3-eb6a-4358-bbfe-9c4af47b8009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776332992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3776332992
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2357779378
Short name T367
Test name
Test status
Simulation time 16488661 ps
CPU time 0.74 seconds
Started Jun 07 07:55:27 PM PDT 24
Finished Jun 07 07:55:29 PM PDT 24
Peak memory 207696 kb
Host smart-c9c4f7e2-03cf-4c9f-9b6b-f3d6fdd0259d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357779378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2357779378
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.4135980142
Short name T300
Test name
Test status
Simulation time 30378403346 ps
CPU time 172.29 seconds
Started Jun 07 07:55:29 PM PDT 24
Finished Jun 07 07:58:23 PM PDT 24
Peak memory 256464 kb
Host smart-b52bdb53-ded9-4e16-a604-66a3aeac18d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135980142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4135980142
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3827878072
Short name T193
Test name
Test status
Simulation time 12724572190 ps
CPU time 73.89 seconds
Started Jun 07 07:55:27 PM PDT 24
Finished Jun 07 07:56:43 PM PDT 24
Peak memory 255584 kb
Host smart-eb5d2118-4d6a-407a-b429-a5ca5076b0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827878072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3827878072
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2276937239
Short name T299
Test name
Test status
Simulation time 25691621918 ps
CPU time 296.41 seconds
Started Jun 07 07:55:26 PM PDT 24
Finished Jun 07 08:00:23 PM PDT 24
Peak memory 262848 kb
Host smart-4dffafef-7ef4-428d-92a0-dea3e7d10e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276937239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2276937239
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3840197523
Short name T143
Test name
Test status
Simulation time 4359931455 ps
CPU time 57.53 seconds
Started Jun 07 07:55:27 PM PDT 24
Finished Jun 07 07:56:27 PM PDT 24
Peak memory 234100 kb
Host smart-cd480720-4236-48d8-8bdd-d8a84cb110ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840197523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3840197523
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.4165350979
Short name T709
Test name
Test status
Simulation time 367780617 ps
CPU time 4.81 seconds
Started Jun 07 07:55:26 PM PDT 24
Finished Jun 07 07:55:32 PM PDT 24
Peak memory 225300 kb
Host smart-6f68d173-1942-441e-b2b6-ace0c7c9428e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165350979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.4165350979
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3957922020
Short name T257
Test name
Test status
Simulation time 2811497326 ps
CPU time 8.34 seconds
Started Jun 07 07:55:25 PM PDT 24
Finished Jun 07 07:55:34 PM PDT 24
Peak memory 219664 kb
Host smart-3425c48e-bc05-485a-bc2a-13e82f61ecf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957922020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3957922020
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.573817587
Short name T536
Test name
Test status
Simulation time 1330215740 ps
CPU time 3 seconds
Started Jun 07 07:55:34 PM PDT 24
Finished Jun 07 07:55:39 PM PDT 24
Peak memory 225308 kb
Host smart-0713e9ae-139d-477d-95ed-21706d6ffe5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573817587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.573817587
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1795753648
Short name T728
Test name
Test status
Simulation time 179435209 ps
CPU time 4.74 seconds
Started Jun 07 07:55:27 PM PDT 24
Finished Jun 07 07:55:33 PM PDT 24
Peak memory 240896 kb
Host smart-c15a0a17-7bde-4bf6-8e84-6f3d6d13dddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795753648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1795753648
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.145856331
Short name T636
Test name
Test status
Simulation time 1928243682 ps
CPU time 12.66 seconds
Started Jun 07 07:55:27 PM PDT 24
Finished Jun 07 07:55:42 PM PDT 24
Peak memory 219612 kb
Host smart-69241055-ec72-4b0c-90e7-addeee9d77ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=145856331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.145856331
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1181179366
Short name T228
Test name
Test status
Simulation time 255992526156 ps
CPU time 288.27 seconds
Started Jun 07 07:55:27 PM PDT 24
Finished Jun 07 08:00:17 PM PDT 24
Peak memory 250012 kb
Host smart-631989d7-a1a0-4cca-8904-859b835d5fe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181179366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1181179366
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.11881471
Short name T669
Test name
Test status
Simulation time 3377746867 ps
CPU time 12.7 seconds
Started Jun 07 07:55:26 PM PDT 24
Finished Jun 07 07:55:40 PM PDT 24
Peak memory 217248 kb
Host smart-5db18b78-d658-4f6d-83d1-fbf296d74a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11881471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.11881471
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3424844277
Short name T485
Test name
Test status
Simulation time 21224499168 ps
CPU time 11.01 seconds
Started Jun 07 07:55:34 PM PDT 24
Finished Jun 07 07:55:47 PM PDT 24
Peak memory 218416 kb
Host smart-d9ba11fb-73ce-4bd5-9205-19ae63c8589e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424844277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3424844277
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2002912821
Short name T318
Test name
Test status
Simulation time 26396971 ps
CPU time 0.92 seconds
Started Jun 07 07:55:29 PM PDT 24
Finished Jun 07 07:55:32 PM PDT 24
Peak memory 207692 kb
Host smart-5c75040b-abaa-4613-8e47-6c98e30e0a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002912821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2002912821
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2054644711
Short name T329
Test name
Test status
Simulation time 55770868 ps
CPU time 0.86 seconds
Started Jun 07 07:55:27 PM PDT 24
Finished Jun 07 07:55:30 PM PDT 24
Peak memory 206708 kb
Host smart-b127f725-144f-438a-9493-b13643fbe087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054644711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2054644711
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.896013364
Short name T922
Test name
Test status
Simulation time 3582705638 ps
CPU time 16.6 seconds
Started Jun 07 07:55:26 PM PDT 24
Finished Jun 07 07:55:44 PM PDT 24
Peak memory 233628 kb
Host smart-84a52dd9-b383-485c-aaee-5fcd549ca2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896013364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.896013364
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.514820406
Short name T624
Test name
Test status
Simulation time 15586030 ps
CPU time 0.69 seconds
Started Jun 07 07:55:36 PM PDT 24
Finished Jun 07 07:55:39 PM PDT 24
Peak memory 205672 kb
Host smart-d9fe75c0-21f3-4d85-8cd9-10bd38332ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514820406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.514820406
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3029706034
Short name T255
Test name
Test status
Simulation time 194939846 ps
CPU time 2.2 seconds
Started Jun 07 07:55:34 PM PDT 24
Finished Jun 07 07:55:37 PM PDT 24
Peak memory 233420 kb
Host smart-314fc643-147f-4457-aabc-d008a350f6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029706034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3029706034
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1533952902
Short name T781
Test name
Test status
Simulation time 61813084 ps
CPU time 0.81 seconds
Started Jun 07 07:55:28 PM PDT 24
Finished Jun 07 07:55:31 PM PDT 24
Peak memory 207412 kb
Host smart-9f9f62e4-93ee-4fcc-92b6-76a24a310898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533952902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1533952902
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1500200585
Short name T291
Test name
Test status
Simulation time 13878901343 ps
CPU time 44.9 seconds
Started Jun 07 07:55:36 PM PDT 24
Finished Jun 07 07:56:23 PM PDT 24
Peak memory 252504 kb
Host smart-35ed90f4-1b67-47cb-a4a2-7e21a74cda5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500200585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1500200585
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1213413846
Short name T953
Test name
Test status
Simulation time 4246504163 ps
CPU time 106.4 seconds
Started Jun 07 07:55:35 PM PDT 24
Finished Jun 07 07:57:24 PM PDT 24
Peak memory 264912 kb
Host smart-8013862e-6a2f-418a-ac96-6db68d1dbfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213413846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1213413846
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1442242721
Short name T570
Test name
Test status
Simulation time 21069563849 ps
CPU time 37.4 seconds
Started Jun 07 07:55:34 PM PDT 24
Finished Jun 07 07:56:14 PM PDT 24
Peak memory 233668 kb
Host smart-35ec0773-2ba5-418b-b8ac-a067c9cdc136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442242721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1442242721
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.740240216
Short name T140
Test name
Test status
Simulation time 140043362 ps
CPU time 4.56 seconds
Started Jun 07 07:55:35 PM PDT 24
Finished Jun 07 07:55:42 PM PDT 24
Peak memory 225460 kb
Host smart-2480ab72-3319-4c38-af53-2d824940b098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740240216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.740240216
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3079672668
Short name T784
Test name
Test status
Simulation time 298170098 ps
CPU time 4.79 seconds
Started Jun 07 07:55:35 PM PDT 24
Finished Jun 07 07:55:42 PM PDT 24
Peak memory 233552 kb
Host smart-ee5ab7f8-f2ab-46b8-9354-c1a2d10c6783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079672668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3079672668
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1660810456
Short name T276
Test name
Test status
Simulation time 13029448264 ps
CPU time 40.98 seconds
Started Jun 07 07:55:36 PM PDT 24
Finished Jun 07 07:56:19 PM PDT 24
Peak memory 233656 kb
Host smart-9fc432c2-e859-4173-b429-e216acd7c438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660810456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1660810456
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1621204759
Short name T36
Test name
Test status
Simulation time 144429865 ps
CPU time 3.76 seconds
Started Jun 07 07:55:35 PM PDT 24
Finished Jun 07 07:55:41 PM PDT 24
Peak memory 228928 kb
Host smart-3403e7e4-34cf-443a-adc4-2fa755b70638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621204759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1621204759
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2995583494
Short name T501
Test name
Test status
Simulation time 17392952004 ps
CPU time 8.4 seconds
Started Jun 07 07:55:35 PM PDT 24
Finished Jun 07 07:55:45 PM PDT 24
Peak memory 241456 kb
Host smart-57a3b8df-1595-4f54-97e0-59e80a2a683d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995583494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2995583494
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3784262857
Short name T870
Test name
Test status
Simulation time 736355366 ps
CPU time 4.65 seconds
Started Jun 07 07:55:36 PM PDT 24
Finished Jun 07 07:55:43 PM PDT 24
Peak memory 220992 kb
Host smart-68667ecc-2b5a-46f8-8096-74ad77efd331
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3784262857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3784262857
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.759362666
Short name T594
Test name
Test status
Simulation time 7870060500 ps
CPU time 40.72 seconds
Started Jun 07 07:55:34 PM PDT 24
Finished Jun 07 07:56:16 PM PDT 24
Peak memory 217156 kb
Host smart-e74395a2-c2f0-4507-9460-43b548038fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759362666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.759362666
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.406394058
Short name T522
Test name
Test status
Simulation time 9694232916 ps
CPU time 9.56 seconds
Started Jun 07 07:55:29 PM PDT 24
Finished Jun 07 07:55:40 PM PDT 24
Peak memory 217308 kb
Host smart-37b93f10-8b99-4df8-8569-f517f5067815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406394058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.406394058
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3995559672
Short name T317
Test name
Test status
Simulation time 77606500 ps
CPU time 1.57 seconds
Started Jun 07 07:55:35 PM PDT 24
Finished Jun 07 07:55:39 PM PDT 24
Peak memory 217104 kb
Host smart-656f1982-a54d-4df9-9b81-ee65b4a646d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995559672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3995559672
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2290121351
Short name T4
Test name
Test status
Simulation time 128445745 ps
CPU time 0.84 seconds
Started Jun 07 07:55:33 PM PDT 24
Finished Jun 07 07:55:35 PM PDT 24
Peak memory 206628 kb
Host smart-0d9b5ebd-02b4-4b9d-b7b2-9001faaabd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290121351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2290121351
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1288097168
Short name T405
Test name
Test status
Simulation time 216674259 ps
CPU time 2.42 seconds
Started Jun 07 07:55:34 PM PDT 24
Finished Jun 07 07:55:38 PM PDT 24
Peak memory 224080 kb
Host smart-c64029d0-46a1-4c26-845b-33a607491aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288097168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1288097168
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.56806416
Short name T637
Test name
Test status
Simulation time 41130143 ps
CPU time 0.69 seconds
Started Jun 07 07:55:41 PM PDT 24
Finished Jun 07 07:55:44 PM PDT 24
Peak memory 206288 kb
Host smart-acba2643-6099-4e59-abc3-7eef42825895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56806416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.56806416
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1211928215
Short name T58
Test name
Test status
Simulation time 137083182 ps
CPU time 4.01 seconds
Started Jun 07 07:55:36 PM PDT 24
Finished Jun 07 07:55:42 PM PDT 24
Peak memory 233532 kb
Host smart-15fbea44-c409-4dc3-93f9-f037be779946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211928215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1211928215
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1884171003
Short name T376
Test name
Test status
Simulation time 40839288 ps
CPU time 0.8 seconds
Started Jun 07 07:55:34 PM PDT 24
Finished Jun 07 07:55:37 PM PDT 24
Peak memory 207396 kb
Host smart-0b9cdca9-bbe6-4ea8-97f1-a43f179297ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884171003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1884171003
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.774047488
Short name T187
Test name
Test status
Simulation time 20230616251 ps
CPU time 149.4 seconds
Started Jun 07 07:55:43 PM PDT 24
Finished Jun 07 07:58:15 PM PDT 24
Peak memory 250060 kb
Host smart-742fbc07-3fbf-4c8e-bad9-f5f5d30e16bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774047488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.774047488
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1945156833
Short name T431
Test name
Test status
Simulation time 115370580558 ps
CPU time 215.04 seconds
Started Jun 07 07:55:43 PM PDT 24
Finished Jun 07 07:59:20 PM PDT 24
Peak memory 256700 kb
Host smart-12724da7-2e86-4ec9-ac01-69035c77f29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945156833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1945156833
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3023759316
Short name T218
Test name
Test status
Simulation time 57983602390 ps
CPU time 166.7 seconds
Started Jun 07 07:55:41 PM PDT 24
Finished Jun 07 07:58:30 PM PDT 24
Peak memory 256112 kb
Host smart-baa830b0-36b4-4802-956a-33dcdb1766c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023759316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3023759316
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2420578188
Short name T302
Test name
Test status
Simulation time 2976083347 ps
CPU time 12.45 seconds
Started Jun 07 07:55:41 PM PDT 24
Finished Jun 07 07:55:55 PM PDT 24
Peak memory 233604 kb
Host smart-05a56c2d-1538-4fd2-8139-1b1916017aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420578188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2420578188
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3691925742
Short name T387
Test name
Test status
Simulation time 5883817563 ps
CPU time 8.15 seconds
Started Jun 07 07:55:34 PM PDT 24
Finished Jun 07 07:55:44 PM PDT 24
Peak memory 225488 kb
Host smart-7c2854a2-6fae-4cea-9f43-dac1fda60316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691925742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3691925742
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4268222658
Short name T273
Test name
Test status
Simulation time 8909183332 ps
CPU time 79.99 seconds
Started Jun 07 07:55:33 PM PDT 24
Finished Jun 07 07:56:55 PM PDT 24
Peak memory 241920 kb
Host smart-a0ce6341-a67c-4dfa-a6d3-c317a8e166d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268222658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4268222658
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1812148321
Short name T259
Test name
Test status
Simulation time 4060369586 ps
CPU time 14.42 seconds
Started Jun 07 07:55:34 PM PDT 24
Finished Jun 07 07:55:51 PM PDT 24
Peak memory 241608 kb
Host smart-740fb921-a545-42cc-bde9-121bbfcfd8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812148321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1812148321
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1759040720
Short name T788
Test name
Test status
Simulation time 12510703191 ps
CPU time 5.56 seconds
Started Jun 07 07:55:36 PM PDT 24
Finished Jun 07 07:55:43 PM PDT 24
Peak memory 225408 kb
Host smart-84a4bde9-2a73-4232-ab8c-0d6036c51994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759040720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1759040720
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3221101677
Short name T364
Test name
Test status
Simulation time 590873991 ps
CPU time 7.74 seconds
Started Jun 07 07:55:44 PM PDT 24
Finished Jun 07 07:55:54 PM PDT 24
Peak memory 224060 kb
Host smart-fbb13307-6b97-4995-b3e4-469cb09d967f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3221101677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3221101677
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2056987992
Short name T69
Test name
Test status
Simulation time 49578618233 ps
CPU time 253.05 seconds
Started Jun 07 07:55:43 PM PDT 24
Finished Jun 07 07:59:58 PM PDT 24
Peak memory 254320 kb
Host smart-5307bc6a-e5be-4155-9bb4-6843c2bacc97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056987992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2056987992
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2950272844
Short name T315
Test name
Test status
Simulation time 9495683719 ps
CPU time 15.76 seconds
Started Jun 07 07:55:34 PM PDT 24
Finished Jun 07 07:55:52 PM PDT 24
Peak memory 217300 kb
Host smart-5b93dbb5-2612-4fa9-9b5b-0adfc9c6994d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950272844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2950272844
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1025823382
Short name T719
Test name
Test status
Simulation time 2725433364 ps
CPU time 6.56 seconds
Started Jun 07 07:55:35 PM PDT 24
Finished Jun 07 07:55:43 PM PDT 24
Peak memory 217220 kb
Host smart-db61fa95-86a9-4b7d-bfd4-842d1375bb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025823382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1025823382
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2880900566
Short name T614
Test name
Test status
Simulation time 69849943 ps
CPU time 1.07 seconds
Started Jun 07 07:55:34 PM PDT 24
Finished Jun 07 07:55:38 PM PDT 24
Peak memory 208708 kb
Host smart-e0925359-c506-4cb4-9278-26abb59aeb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880900566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2880900566
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1337084698
Short name T530
Test name
Test status
Simulation time 92543593 ps
CPU time 0.76 seconds
Started Jun 07 07:55:33 PM PDT 24
Finished Jun 07 07:55:35 PM PDT 24
Peak memory 206668 kb
Host smart-bbe9bca9-b2a7-463c-bf89-9e5236aed426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337084698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1337084698
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2244119582
Short name T821
Test name
Test status
Simulation time 32343198677 ps
CPU time 12.37 seconds
Started Jun 07 07:55:35 PM PDT 24
Finished Jun 07 07:55:49 PM PDT 24
Peak memory 233568 kb
Host smart-f5003571-4d97-4e0e-b023-e50cd8478ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244119582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2244119582
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3020950768
Short name T448
Test name
Test status
Simulation time 41759695 ps
CPU time 0.79 seconds
Started Jun 07 07:55:44 PM PDT 24
Finished Jun 07 07:55:47 PM PDT 24
Peak memory 205696 kb
Host smart-ab3b22c4-1c23-4985-8eb6-350597047021
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020950768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3020950768
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.4182657135
Short name T690
Test name
Test status
Simulation time 474613562 ps
CPU time 3.86 seconds
Started Jun 07 07:55:42 PM PDT 24
Finished Jun 07 07:55:48 PM PDT 24
Peak memory 233524 kb
Host smart-fa9d3eaa-4784-48f3-bfe3-894d13a70285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182657135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.4182657135
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3986727922
Short name T907
Test name
Test status
Simulation time 20347379 ps
CPU time 0.84 seconds
Started Jun 07 07:55:42 PM PDT 24
Finished Jun 07 07:55:45 PM PDT 24
Peak memory 207384 kb
Host smart-ac172ef6-bf75-45e5-8314-ad92564ef16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986727922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3986727922
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.543397757
Short name T204
Test name
Test status
Simulation time 262638252599 ps
CPU time 197.7 seconds
Started Jun 07 07:55:42 PM PDT 24
Finished Jun 07 07:59:03 PM PDT 24
Peak memory 250040 kb
Host smart-3c9bf039-fe3c-4174-8a61-55a7cada5994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543397757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.543397757
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3992944505
Short name T223
Test name
Test status
Simulation time 199957585148 ps
CPU time 252.58 seconds
Started Jun 07 07:55:43 PM PDT 24
Finished Jun 07 07:59:58 PM PDT 24
Peak memory 241948 kb
Host smart-216c9bbe-7915-43da-82b6-da507677274e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992944505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3992944505
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3748435432
Short name T487
Test name
Test status
Simulation time 542317638 ps
CPU time 6.14 seconds
Started Jun 07 07:55:43 PM PDT 24
Finished Jun 07 07:55:51 PM PDT 24
Peak memory 233576 kb
Host smart-48bf0569-0144-434d-bc97-8d46f31179a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748435432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3748435432
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1749168896
Short name T750
Test name
Test status
Simulation time 2128574779 ps
CPU time 19.59 seconds
Started Jun 07 07:55:45 PM PDT 24
Finished Jun 07 07:56:07 PM PDT 24
Peak memory 233596 kb
Host smart-8c2f6ba8-6001-469c-bee5-2fd4e5a58fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749168896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1749168896
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.695312724
Short name T844
Test name
Test status
Simulation time 8730004782 ps
CPU time 28.38 seconds
Started Jun 07 07:55:44 PM PDT 24
Finished Jun 07 07:56:15 PM PDT 24
Peak memory 249708 kb
Host smart-599c2e49-9ad9-43f6-8376-1df30c80e6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695312724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.695312724
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3293341342
Short name T737
Test name
Test status
Simulation time 4721262404 ps
CPU time 6.15 seconds
Started Jun 07 07:55:42 PM PDT 24
Finished Jun 07 07:55:50 PM PDT 24
Peak memory 233664 kb
Host smart-d84cbaca-0814-444a-a43f-2624278ff957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293341342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3293341342
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1191096370
Short name T856
Test name
Test status
Simulation time 6691724422 ps
CPU time 6.12 seconds
Started Jun 07 07:55:44 PM PDT 24
Finished Jun 07 07:55:53 PM PDT 24
Peak memory 225508 kb
Host smart-dc614dce-616e-4f6c-ab82-9a4e1478800b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191096370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1191096370
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3007589546
Short name T881
Test name
Test status
Simulation time 17701224257 ps
CPU time 9.23 seconds
Started Jun 07 07:55:44 PM PDT 24
Finished Jun 07 07:55:55 PM PDT 24
Peak memory 221352 kb
Host smart-65d612c7-5d34-42cd-ba8d-8f4bdbf0889b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3007589546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3007589546
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2970405735
Short name T871
Test name
Test status
Simulation time 28182492316 ps
CPU time 163.91 seconds
Started Jun 07 07:55:43 PM PDT 24
Finished Jun 07 07:58:29 PM PDT 24
Peak memory 258324 kb
Host smart-470578f8-3f5e-48e4-bb49-01db9b620f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970405735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2970405735
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.629872535
Short name T759
Test name
Test status
Simulation time 33786224 ps
CPU time 0.69 seconds
Started Jun 07 07:55:46 PM PDT 24
Finished Jun 07 07:55:49 PM PDT 24
Peak memory 206532 kb
Host smart-176bf8d9-55ce-4a28-b64e-62c0d3ba7ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629872535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.629872535
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3992961003
Short name T408
Test name
Test status
Simulation time 565718153 ps
CPU time 2.23 seconds
Started Jun 07 07:55:46 PM PDT 24
Finished Jun 07 07:55:50 PM PDT 24
Peak memory 217184 kb
Host smart-1886552c-b851-46b1-be03-36855ec76133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992961003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3992961003
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.667450741
Short name T528
Test name
Test status
Simulation time 229867165 ps
CPU time 1.14 seconds
Started Jun 07 07:55:42 PM PDT 24
Finished Jun 07 07:55:45 PM PDT 24
Peak memory 208696 kb
Host smart-2329463d-f33d-4ca1-ba07-c61825a4bf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667450741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.667450741
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3096237268
Short name T479
Test name
Test status
Simulation time 80007689 ps
CPU time 0.93 seconds
Started Jun 07 07:55:46 PM PDT 24
Finished Jun 07 07:55:49 PM PDT 24
Peak memory 206724 kb
Host smart-f2c12025-dc12-4076-9ed0-a910e745c211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096237268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3096237268
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.4029487336
Short name T389
Test name
Test status
Simulation time 54004000 ps
CPU time 1.97 seconds
Started Jun 07 07:55:42 PM PDT 24
Finished Jun 07 07:55:46 PM PDT 24
Peak memory 223844 kb
Host smart-c3fa7429-572e-4f6b-8475-7a7fca2f24d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029487336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4029487336
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2842624057
Short name T900
Test name
Test status
Simulation time 54898695 ps
CPU time 0.72 seconds
Started Jun 07 07:50:29 PM PDT 24
Finished Jun 07 07:50:32 PM PDT 24
Peak memory 206272 kb
Host smart-875833c4-851e-406f-a329-f89df9edb803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842624057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
842624057
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1866200686
Short name T651
Test name
Test status
Simulation time 929034694 ps
CPU time 7.01 seconds
Started Jun 07 07:50:27 PM PDT 24
Finished Jun 07 07:50:37 PM PDT 24
Peak memory 225232 kb
Host smart-d6ed9693-d1bf-4f6b-9d0b-9c464f08e1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866200686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1866200686
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3117278823
Short name T352
Test name
Test status
Simulation time 15591687 ps
CPU time 0.77 seconds
Started Jun 07 07:50:21 PM PDT 24
Finished Jun 07 07:50:26 PM PDT 24
Peak memory 206368 kb
Host smart-f758c0a8-1b28-470d-bcdc-931bf329163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117278823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3117278823
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1066260650
Short name T169
Test name
Test status
Simulation time 1466348797 ps
CPU time 26.11 seconds
Started Jun 07 07:50:29 PM PDT 24
Finished Jun 07 07:50:57 PM PDT 24
Peak memory 249900 kb
Host smart-047cce9a-96cf-43bb-93df-fcd155fc905e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066260650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1066260650
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2188272755
Short name T482
Test name
Test status
Simulation time 13300298660 ps
CPU time 26.5 seconds
Started Jun 07 07:50:27 PM PDT 24
Finished Jun 07 07:50:56 PM PDT 24
Peak memory 234776 kb
Host smart-24b8429b-7b5c-456f-a465-172155a973e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188272755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2188272755
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.760991806
Short name T77
Test name
Test status
Simulation time 18142151658 ps
CPU time 172.76 seconds
Started Jun 07 07:50:30 PM PDT 24
Finished Jun 07 07:53:25 PM PDT 24
Peak memory 255956 kb
Host smart-cb3de927-7c10-41c2-8435-5c6f2c13da0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760991806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
760991806
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.824114762
Short name T83
Test name
Test status
Simulation time 7295022398 ps
CPU time 13.13 seconds
Started Jun 07 07:50:27 PM PDT 24
Finished Jun 07 07:50:42 PM PDT 24
Peak memory 233692 kb
Host smart-cf8a2901-8896-44a6-95c3-1d8575704a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824114762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.824114762
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3292668898
Short name T589
Test name
Test status
Simulation time 1361695374 ps
CPU time 7.66 seconds
Started Jun 07 07:50:26 PM PDT 24
Finished Jun 07 07:50:36 PM PDT 24
Peak memory 225320 kb
Host smart-16cfd732-4b9c-4a73-9e64-fcab92a62c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292668898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3292668898
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.77364234
Short name T908
Test name
Test status
Simulation time 1007003940 ps
CPU time 4.9 seconds
Started Jun 07 07:50:30 PM PDT 24
Finished Jun 07 07:50:37 PM PDT 24
Peak memory 241620 kb
Host smart-e0998209-b1d4-40e3-974d-4bf96da55915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77364234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.77364234
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2575361222
Short name T263
Test name
Test status
Simulation time 378709108 ps
CPU time 3.36 seconds
Started Jun 07 07:50:19 PM PDT 24
Finished Jun 07 07:50:27 PM PDT 24
Peak memory 224880 kb
Host smart-03d8a723-d8d3-4954-9e84-8274f1348d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575361222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2575361222
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1035615225
Short name T205
Test name
Test status
Simulation time 742949077 ps
CPU time 4.95 seconds
Started Jun 07 07:50:20 PM PDT 24
Finished Jun 07 07:50:29 PM PDT 24
Peak memory 225348 kb
Host smart-19e1db84-0a3a-43b5-b32e-f0f2b26d7c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035615225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1035615225
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3466911961
Short name T865
Test name
Test status
Simulation time 163035763 ps
CPU time 4.64 seconds
Started Jun 07 07:50:27 PM PDT 24
Finished Jun 07 07:50:34 PM PDT 24
Peak memory 223784 kb
Host smart-aac62bef-0316-4adb-bc31-64fd7bbc7f21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3466911961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3466911961
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2579566762
Short name T164
Test name
Test status
Simulation time 49472982266 ps
CPU time 252.57 seconds
Started Jun 07 07:50:27 PM PDT 24
Finished Jun 07 07:54:42 PM PDT 24
Peak memory 250516 kb
Host smart-42ca2e24-7f02-43b0-81c8-b3b8490609e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579566762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2579566762
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1902678517
Short name T622
Test name
Test status
Simulation time 2299122369 ps
CPU time 26.67 seconds
Started Jun 07 07:50:20 PM PDT 24
Finished Jun 07 07:50:51 PM PDT 24
Peak memory 217580 kb
Host smart-3acacfff-c827-445b-baa0-41f91c1fe476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902678517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1902678517
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2263196518
Short name T414
Test name
Test status
Simulation time 810212131 ps
CPU time 2.95 seconds
Started Jun 07 07:50:21 PM PDT 24
Finished Jun 07 07:50:28 PM PDT 24
Peak memory 208532 kb
Host smart-02bb9b4b-bcd7-418d-826d-267bfd4314c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263196518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2263196518
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1195449486
Short name T342
Test name
Test status
Simulation time 11650042 ps
CPU time 0.79 seconds
Started Jun 07 07:50:21 PM PDT 24
Finished Jun 07 07:50:26 PM PDT 24
Peak memory 206680 kb
Host smart-42890803-8dcc-478a-8bda-3092a93b8381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195449486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1195449486
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3660467311
Short name T769
Test name
Test status
Simulation time 177028265 ps
CPU time 1.12 seconds
Started Jun 07 07:50:21 PM PDT 24
Finished Jun 07 07:50:26 PM PDT 24
Peak memory 207732 kb
Host smart-c2ed9402-73ea-47f8-a560-7c2835c56541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660467311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3660467311
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1765346567
Short name T558
Test name
Test status
Simulation time 21649509491 ps
CPU time 19.24 seconds
Started Jun 07 07:50:26 PM PDT 24
Finished Jun 07 07:50:48 PM PDT 24
Peak memory 233712 kb
Host smart-12f39945-99ef-4303-a867-72e683532048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765346567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1765346567
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1823606401
Short name T696
Test name
Test status
Simulation time 14912618 ps
CPU time 0.74 seconds
Started Jun 07 07:51:05 PM PDT 24
Finished Jun 07 07:51:08 PM PDT 24
Peak memory 206600 kb
Host smart-fde3d3dc-c3e7-4b3f-ae62-163513b999a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823606401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
823606401
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.277091621
Short name T258
Test name
Test status
Simulation time 980537172 ps
CPU time 8 seconds
Started Jun 07 07:50:35 PM PDT 24
Finished Jun 07 07:50:44 PM PDT 24
Peak memory 225264 kb
Host smart-61067da0-e506-4876-ae92-9ade9d6928bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277091621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.277091621
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1246321018
Short name T16
Test name
Test status
Simulation time 66396507 ps
CPU time 0.8 seconds
Started Jun 07 07:50:30 PM PDT 24
Finished Jun 07 07:50:32 PM PDT 24
Peak memory 207436 kb
Host smart-41eb5428-7cab-4327-a616-bb26a43246e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246321018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1246321018
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1918226360
Short name T742
Test name
Test status
Simulation time 8429920073 ps
CPU time 90.22 seconds
Started Jun 07 07:51:07 PM PDT 24
Finished Jun 07 07:52:39 PM PDT 24
Peak memory 258304 kb
Host smart-9ecc81eb-dec7-4aec-bbf2-851b8edc5762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918226360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1918226360
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1239060358
Short name T128
Test name
Test status
Simulation time 131482108425 ps
CPU time 230.61 seconds
Started Jun 07 07:51:05 PM PDT 24
Finished Jun 07 07:54:57 PM PDT 24
Peak memory 263028 kb
Host smart-2ca8f0b4-0e6f-43a6-9c6d-766eca74d5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239060358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1239060358
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2173644307
Short name T195
Test name
Test status
Simulation time 26055168194 ps
CPU time 107.54 seconds
Started Jun 07 07:51:05 PM PDT 24
Finished Jun 07 07:52:54 PM PDT 24
Peak memory 241764 kb
Host smart-fa1ebdf4-4df6-43bd-9c0e-4cf465b42777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173644307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2173644307
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2716072047
Short name T707
Test name
Test status
Simulation time 747851756 ps
CPU time 14.11 seconds
Started Jun 07 07:50:37 PM PDT 24
Finished Jun 07 07:50:52 PM PDT 24
Peak memory 234612 kb
Host smart-9b51bb8b-bb92-4ccd-be93-3f23cbf44d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716072047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2716072047
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2989310284
Short name T937
Test name
Test status
Simulation time 510532325 ps
CPU time 8.1 seconds
Started Jun 07 07:50:37 PM PDT 24
Finished Jun 07 07:50:46 PM PDT 24
Peak memory 233552 kb
Host smart-a454cf2f-a221-4735-8e41-fd013fb9cee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989310284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2989310284
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2870340896
Short name T539
Test name
Test status
Simulation time 39168607732 ps
CPU time 97.19 seconds
Started Jun 07 07:50:36 PM PDT 24
Finished Jun 07 07:52:15 PM PDT 24
Peak memory 238048 kb
Host smart-06217ea3-bdc2-4146-b0c1-d36858009990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870340896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2870340896
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3606040519
Short name T587
Test name
Test status
Simulation time 3687632394 ps
CPU time 4.05 seconds
Started Jun 07 07:50:36 PM PDT 24
Finished Jun 07 07:50:42 PM PDT 24
Peak memory 233620 kb
Host smart-38c13209-8f2e-4aba-a74e-7a8028aed591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606040519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3606040519
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1078068396
Short name T831
Test name
Test status
Simulation time 665043660 ps
CPU time 5.12 seconds
Started Jun 07 07:50:35 PM PDT 24
Finished Jun 07 07:50:41 PM PDT 24
Peak memory 225380 kb
Host smart-36c6d693-e81a-4bf8-bce3-a37d0e550b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078068396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1078068396
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.13178659
Short name T708
Test name
Test status
Simulation time 84004295 ps
CPU time 3.69 seconds
Started Jun 07 07:51:06 PM PDT 24
Finished Jun 07 07:51:11 PM PDT 24
Peak memory 223284 kb
Host smart-3d907b39-deb0-4fa0-9091-74c9b4db2f6e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=13178659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct
.13178659
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.566578447
Short name T155
Test name
Test status
Simulation time 23120319563 ps
CPU time 107.53 seconds
Started Jun 07 07:51:04 PM PDT 24
Finished Jun 07 07:52:52 PM PDT 24
Peak memory 250152 kb
Host smart-e2b759f9-e029-4a5c-9e9e-02b87bc1b17e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566578447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.566578447
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1482589347
Short name T312
Test name
Test status
Simulation time 5301784829 ps
CPU time 28.73 seconds
Started Jun 07 07:50:26 PM PDT 24
Finished Jun 07 07:50:57 PM PDT 24
Peak memory 217292 kb
Host smart-f3fb1029-f6ec-468e-b4cf-0ef3d20d91e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482589347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1482589347
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1486978318
Short name T680
Test name
Test status
Simulation time 981180514 ps
CPU time 3.35 seconds
Started Jun 07 07:50:26 PM PDT 24
Finished Jun 07 07:50:32 PM PDT 24
Peak memory 217100 kb
Host smart-1be84a06-95fb-4144-9b5a-3e4b29b792bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486978318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1486978318
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.920292254
Short name T672
Test name
Test status
Simulation time 110760951 ps
CPU time 1.09 seconds
Started Jun 07 07:50:36 PM PDT 24
Finished Jun 07 07:50:38 PM PDT 24
Peak memory 208948 kb
Host smart-7a379711-de34-4ea6-b828-76762f61e18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920292254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.920292254
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.260249352
Short name T932
Test name
Test status
Simulation time 87824931 ps
CPU time 0.81 seconds
Started Jun 07 07:50:27 PM PDT 24
Finished Jun 07 07:50:30 PM PDT 24
Peak memory 206716 kb
Host smart-6946312e-def9-48ba-9c96-499d31ff2ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260249352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.260249352
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3548968860
Short name T677
Test name
Test status
Simulation time 115897715 ps
CPU time 2.3 seconds
Started Jun 07 07:50:37 PM PDT 24
Finished Jun 07 07:50:41 PM PDT 24
Peak memory 233536 kb
Host smart-0122b24b-ac7c-4a51-bb87-cde491996dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548968860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3548968860
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3775134826
Short name T2
Test name
Test status
Simulation time 14628892 ps
CPU time 0.75 seconds
Started Jun 07 07:51:07 PM PDT 24
Finished Jun 07 07:51:10 PM PDT 24
Peak memory 206292 kb
Host smart-59b3ad6f-9e0f-4bbc-b415-2078d9247dc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775134826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
775134826
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1356385077
Short name T596
Test name
Test status
Simulation time 104929324 ps
CPU time 2.26 seconds
Started Jun 07 07:51:09 PM PDT 24
Finished Jun 07 07:51:13 PM PDT 24
Peak memory 225312 kb
Host smart-f625d84f-5b9a-465e-86c8-d72b30abf9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356385077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1356385077
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.707276267
Short name T547
Test name
Test status
Simulation time 17448747 ps
CPU time 0.82 seconds
Started Jun 07 07:51:04 PM PDT 24
Finished Jun 07 07:51:06 PM PDT 24
Peak memory 207712 kb
Host smart-361480d9-ed3c-45d5-803e-19ab4a99f29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707276267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.707276267
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3383019520
Short name T84
Test name
Test status
Simulation time 350368447473 ps
CPU time 636.43 seconds
Started Jun 07 07:51:08 PM PDT 24
Finished Jun 07 08:01:47 PM PDT 24
Peak memory 269048 kb
Host smart-83e04958-ec67-407b-b9e9-7609db8e8154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383019520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3383019520
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2682347737
Short name T875
Test name
Test status
Simulation time 8325296435 ps
CPU time 44.65 seconds
Started Jun 07 07:51:08 PM PDT 24
Finished Jun 07 07:51:55 PM PDT 24
Peak memory 239404 kb
Host smart-16cb83d9-a807-4c0e-94bd-9ee2fd388268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682347737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2682347737
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2106462904
Short name T930
Test name
Test status
Simulation time 2082457326 ps
CPU time 45.34 seconds
Started Jun 07 07:51:08 PM PDT 24
Finished Jun 07 07:51:55 PM PDT 24
Peak memory 256172 kb
Host smart-12bde331-2ffe-4f96-8ea3-3c02d3f897a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106462904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2106462904
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2099326409
Short name T866
Test name
Test status
Simulation time 9569232621 ps
CPU time 16.21 seconds
Started Jun 07 07:51:09 PM PDT 24
Finished Jun 07 07:51:27 PM PDT 24
Peak memory 241808 kb
Host smart-a560e371-3dd8-4658-b13c-704b88237088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099326409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2099326409
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3355312319
Short name T604
Test name
Test status
Simulation time 2669447624 ps
CPU time 9.45 seconds
Started Jun 07 07:51:09 PM PDT 24
Finished Jun 07 07:51:20 PM PDT 24
Peak memory 225500 kb
Host smart-92da349c-d1dc-44b7-af93-f0fce6f51c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355312319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3355312319
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2196990925
Short name T855
Test name
Test status
Simulation time 5155549042 ps
CPU time 50.36 seconds
Started Jun 07 07:51:08 PM PDT 24
Finished Jun 07 07:52:01 PM PDT 24
Peak memory 240096 kb
Host smart-2d408be8-8f25-4c4d-9f0b-37dccf165b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196990925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2196990925
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1201079101
Short name T697
Test name
Test status
Simulation time 156872104 ps
CPU time 3.05 seconds
Started Jun 07 07:51:09 PM PDT 24
Finished Jun 07 07:51:14 PM PDT 24
Peak memory 225320 kb
Host smart-d67bb18d-90c8-4c81-a07f-b8fc405b3772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201079101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1201079101
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.957287700
Short name T423
Test name
Test status
Simulation time 1596256816 ps
CPU time 3.77 seconds
Started Jun 07 07:51:04 PM PDT 24
Finished Jun 07 07:51:09 PM PDT 24
Peak memory 233644 kb
Host smart-c6220895-1f5e-42f0-9096-5f3fe03da4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957287700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.957287700
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.948517074
Short name T550
Test name
Test status
Simulation time 596684782 ps
CPU time 5.3 seconds
Started Jun 07 07:51:09 PM PDT 24
Finished Jun 07 07:51:17 PM PDT 24
Peak memory 220120 kb
Host smart-fe14316c-8f97-41a0-8c76-9ab8847aa18f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=948517074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.948517074
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.544986834
Short name T666
Test name
Test status
Simulation time 2957713507 ps
CPU time 18.14 seconds
Started Jun 07 07:51:08 PM PDT 24
Finished Jun 07 07:51:28 PM PDT 24
Peak memory 241968 kb
Host smart-843b827e-6756-4a3b-81dd-32446ea17bd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544986834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.544986834
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1468811142
Short name T307
Test name
Test status
Simulation time 9340966135 ps
CPU time 14.5 seconds
Started Jun 07 07:51:04 PM PDT 24
Finished Jun 07 07:51:20 PM PDT 24
Peak memory 218220 kb
Host smart-841328c3-8fa5-4892-94b2-e750a4a78ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468811142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1468811142
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.349649372
Short name T554
Test name
Test status
Simulation time 11906469857 ps
CPU time 12.86 seconds
Started Jun 07 07:51:04 PM PDT 24
Finished Jun 07 07:51:19 PM PDT 24
Peak memory 217176 kb
Host smart-36eef314-f9bd-47dc-bac6-fe2acbf68915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349649372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.349649372
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3789995478
Short name T328
Test name
Test status
Simulation time 129743115 ps
CPU time 1.25 seconds
Started Jun 07 07:51:04 PM PDT 24
Finished Jun 07 07:51:06 PM PDT 24
Peak memory 216928 kb
Host smart-200ae493-2f4f-49a2-97cd-5a38eea1f037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789995478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3789995478
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2843051526
Short name T340
Test name
Test status
Simulation time 105053347 ps
CPU time 0.75 seconds
Started Jun 07 07:51:05 PM PDT 24
Finished Jun 07 07:51:08 PM PDT 24
Peak memory 206724 kb
Host smart-5c800726-0476-47af-b260-ff432cb25111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843051526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2843051526
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2372932117
Short name T544
Test name
Test status
Simulation time 145846667 ps
CPU time 2.37 seconds
Started Jun 07 07:51:09 PM PDT 24
Finished Jun 07 07:51:14 PM PDT 24
Peak memory 225108 kb
Host smart-e960505e-5123-4405-a3df-0e48b39c4b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372932117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2372932117
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.575993275
Short name T377
Test name
Test status
Simulation time 12154071 ps
CPU time 0.72 seconds
Started Jun 07 07:51:13 PM PDT 24
Finished Jun 07 07:51:17 PM PDT 24
Peak memory 206240 kb
Host smart-bf38739d-9687-48c7-b572-632a9523fead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575993275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.575993275
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.479862173
Short name T15
Test name
Test status
Simulation time 442894679 ps
CPU time 8.32 seconds
Started Jun 07 07:51:10 PM PDT 24
Finished Jun 07 07:51:20 PM PDT 24
Peak memory 225336 kb
Host smart-3445188b-88f4-4750-ab7f-dd71e6bbf304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479862173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.479862173
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.594598330
Short name T724
Test name
Test status
Simulation time 139885640 ps
CPU time 0.78 seconds
Started Jun 07 07:51:09 PM PDT 24
Finished Jun 07 07:51:12 PM PDT 24
Peak memory 206412 kb
Host smart-7173a8d0-e3d6-4fc5-928e-320ce1d83b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594598330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.594598330
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1108048082
Short name T212
Test name
Test status
Simulation time 53970908863 ps
CPU time 106.14 seconds
Started Jun 07 07:51:09 PM PDT 24
Finished Jun 07 07:52:58 PM PDT 24
Peak memory 252504 kb
Host smart-ebd2d97a-9ff9-4ec9-8f74-d3934835b4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108048082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1108048082
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.235741336
Short name T286
Test name
Test status
Simulation time 8512975433 ps
CPU time 126.67 seconds
Started Jun 07 07:51:13 PM PDT 24
Finished Jun 07 07:53:22 PM PDT 24
Peak memory 258284 kb
Host smart-af3ec8ba-0813-4269-93e9-1aba576d835c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235741336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.235741336
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2811931356
Short name T656
Test name
Test status
Simulation time 9423549772 ps
CPU time 50.9 seconds
Started Jun 07 07:51:12 PM PDT 24
Finished Jun 07 07:52:05 PM PDT 24
Peak memory 218540 kb
Host smart-5ec89607-433e-4882-b2bc-30e424aad509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811931356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2811931356
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3775621939
Short name T55
Test name
Test status
Simulation time 2027009410 ps
CPU time 11.17 seconds
Started Jun 07 07:51:10 PM PDT 24
Finished Jun 07 07:51:23 PM PDT 24
Peak memory 225384 kb
Host smart-90096f24-64c8-4f56-9eb4-c3d847cc4389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775621939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3775621939
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2255319323
Short name T266
Test name
Test status
Simulation time 79796462 ps
CPU time 3.39 seconds
Started Jun 07 07:51:09 PM PDT 24
Finished Jun 07 07:51:14 PM PDT 24
Peak memory 230312 kb
Host smart-b99be0fb-2008-48c8-9a6a-7d5a14ad2201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255319323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2255319323
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.542329931
Short name T541
Test name
Test status
Simulation time 14191191522 ps
CPU time 34.26 seconds
Started Jun 07 07:51:10 PM PDT 24
Finished Jun 07 07:51:46 PM PDT 24
Peak memory 250032 kb
Host smart-718ae82e-c0fc-4c39-9580-8599a0ed5274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542329931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.542329931
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1468904206
Short name T515
Test name
Test status
Simulation time 247210432 ps
CPU time 3.24 seconds
Started Jun 07 07:51:10 PM PDT 24
Finished Jun 07 07:51:15 PM PDT 24
Peak memory 233520 kb
Host smart-6854b75b-3030-4f93-aeb3-402db0decbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468904206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1468904206
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.621685767
Short name T934
Test name
Test status
Simulation time 101208232 ps
CPU time 2.54 seconds
Started Jun 07 07:51:09 PM PDT 24
Finished Jun 07 07:51:14 PM PDT 24
Peak memory 233292 kb
Host smart-a20d27f7-5ad5-4811-a07f-8fa3284593ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621685767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.621685767
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3879521175
Short name T507
Test name
Test status
Simulation time 496632581 ps
CPU time 5.99 seconds
Started Jun 07 07:51:10 PM PDT 24
Finished Jun 07 07:51:18 PM PDT 24
Peak memory 224004 kb
Host smart-8b5bb2fb-dbb4-4de9-9c23-103e30599d05
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3879521175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3879521175
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3640620912
Short name T840
Test name
Test status
Simulation time 44679802 ps
CPU time 0.99 seconds
Started Jun 07 07:51:09 PM PDT 24
Finished Jun 07 07:51:12 PM PDT 24
Peak memory 207484 kb
Host smart-b572a599-a93e-4ca1-80b1-7359afcf388c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640620912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3640620912
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1729598076
Short name T473
Test name
Test status
Simulation time 9763642444 ps
CPU time 50.7 seconds
Started Jun 07 07:51:09 PM PDT 24
Finished Jun 07 07:52:01 PM PDT 24
Peak memory 217252 kb
Host smart-7f24ebe8-2506-4c0d-af00-abcbe8428ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729598076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1729598076
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.727608588
Short name T608
Test name
Test status
Simulation time 1914044175 ps
CPU time 8.54 seconds
Started Jun 07 07:51:09 PM PDT 24
Finished Jun 07 07:51:20 PM PDT 24
Peak memory 217036 kb
Host smart-8cc6fbf9-e3fd-45a8-b3f5-82dd38fceae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727608588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.727608588
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.982428057
Short name T355
Test name
Test status
Simulation time 83476011 ps
CPU time 1.14 seconds
Started Jun 07 07:51:10 PM PDT 24
Finished Jun 07 07:51:14 PM PDT 24
Peak memory 208732 kb
Host smart-3f35fda7-019c-433c-b184-52460c642348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982428057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.982428057
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2188971819
Short name T789
Test name
Test status
Simulation time 37176421 ps
CPU time 0.8 seconds
Started Jun 07 07:51:10 PM PDT 24
Finished Jun 07 07:51:13 PM PDT 24
Peak memory 206716 kb
Host smart-d1c2f413-a058-4211-a3b7-60022709e40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188971819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2188971819
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4130362549
Short name T673
Test name
Test status
Simulation time 5992638413 ps
CPU time 6.68 seconds
Started Jun 07 07:51:12 PM PDT 24
Finished Jun 07 07:51:21 PM PDT 24
Peak memory 233656 kb
Host smart-63267195-51f3-4889-9ff3-7244c8a0e442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130362549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4130362549
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.532885103
Short name T590
Test name
Test status
Simulation time 15224669 ps
CPU time 0.74 seconds
Started Jun 07 07:51:14 PM PDT 24
Finished Jun 07 07:51:17 PM PDT 24
Peak memory 206584 kb
Host smart-db563ed4-72bc-4e97-a4f6-78dc3dbf2ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532885103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.532885103
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1217897197
Short name T653
Test name
Test status
Simulation time 896905059 ps
CPU time 9.96 seconds
Started Jun 07 07:51:14 PM PDT 24
Finished Jun 07 07:51:27 PM PDT 24
Peak memory 225292 kb
Host smart-b5fe9a8c-0aa6-4cda-b453-15c21417328f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217897197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1217897197
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1666759600
Short name T796
Test name
Test status
Simulation time 21471676 ps
CPU time 0.78 seconds
Started Jun 07 07:51:13 PM PDT 24
Finished Jun 07 07:51:16 PM PDT 24
Peak memory 206396 kb
Host smart-e1bd89ab-0f21-4ffb-bc05-1330cf58d98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666759600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1666759600
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3386899200
Short name T48
Test name
Test status
Simulation time 2876554702 ps
CPU time 30.66 seconds
Started Jun 07 07:51:13 PM PDT 24
Finished Jun 07 07:51:46 PM PDT 24
Peak memory 225492 kb
Host smart-f5dcc8da-ba3f-4d9f-8dec-0c3d7af5397e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386899200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3386899200
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.4085542190
Short name T945
Test name
Test status
Simulation time 34570010862 ps
CPU time 66.87 seconds
Started Jun 07 07:51:13 PM PDT 24
Finished Jun 07 07:52:23 PM PDT 24
Peak memory 238252 kb
Host smart-a75fc568-7803-4b23-baae-31258793528e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085542190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.4085542190
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2851045486
Short name T240
Test name
Test status
Simulation time 170065864231 ps
CPU time 448.36 seconds
Started Jun 07 07:51:11 PM PDT 24
Finished Jun 07 07:58:42 PM PDT 24
Peak memory 257156 kb
Host smart-474f38f6-4924-4d5c-a6d5-dfb56b4c156f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851045486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2851045486
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3360224184
Short name T884
Test name
Test status
Simulation time 1865799745 ps
CPU time 19.53 seconds
Started Jun 07 07:51:15 PM PDT 24
Finished Jun 07 07:51:37 PM PDT 24
Peak memory 240260 kb
Host smart-82c948f2-64f6-46e0-b66b-26364d6124ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360224184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3360224184
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2571059404
Short name T947
Test name
Test status
Simulation time 4719366121 ps
CPU time 10.11 seconds
Started Jun 07 07:51:12 PM PDT 24
Finished Jun 07 07:51:25 PM PDT 24
Peak memory 225380 kb
Host smart-8dfb354d-83ea-4f2a-a713-4623cd957694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571059404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2571059404
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1711326285
Short name T246
Test name
Test status
Simulation time 4844417547 ps
CPU time 8.27 seconds
Started Jun 07 07:51:13 PM PDT 24
Finished Jun 07 07:51:24 PM PDT 24
Peak memory 233596 kb
Host smart-d8c2eaf2-9cc0-4b7b-ad0d-f731d55f5711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711326285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1711326285
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3816309663
Short name T296
Test name
Test status
Simulation time 4427425501 ps
CPU time 14.63 seconds
Started Jun 07 07:51:14 PM PDT 24
Finished Jun 07 07:51:31 PM PDT 24
Peak memory 233576 kb
Host smart-a76cf7e1-f7b8-40e6-83ca-867822e86155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816309663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3816309663
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3322878530
Short name T505
Test name
Test status
Simulation time 1067759595 ps
CPU time 4.33 seconds
Started Jun 07 07:51:12 PM PDT 24
Finished Jun 07 07:51:19 PM PDT 24
Peak memory 233508 kb
Host smart-2c0a8746-d1f4-4472-982a-786fba2681a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322878530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3322878530
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2922640085
Short name T768
Test name
Test status
Simulation time 166141098 ps
CPU time 4.23 seconds
Started Jun 07 07:51:12 PM PDT 24
Finished Jun 07 07:51:19 PM PDT 24
Peak memory 222092 kb
Host smart-69294c02-eaf8-4655-88a7-72f3a33aedc4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2922640085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2922640085
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3601353140
Short name T935
Test name
Test status
Simulation time 3104561439 ps
CPU time 4.13 seconds
Started Jun 07 07:51:12 PM PDT 24
Finished Jun 07 07:51:19 PM PDT 24
Peak memory 217280 kb
Host smart-82615997-377e-4035-b4cd-fe0d4d0ca34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601353140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3601353140
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.4211473913
Short name T481
Test name
Test status
Simulation time 91135086 ps
CPU time 0.92 seconds
Started Jun 07 07:51:13 PM PDT 24
Finished Jun 07 07:51:17 PM PDT 24
Peak memory 206732 kb
Host smart-76f66a80-62a9-4b16-afa6-65de662389bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211473913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.4211473913
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2850378341
Short name T393
Test name
Test status
Simulation time 48540440 ps
CPU time 1.24 seconds
Started Jun 07 07:51:16 PM PDT 24
Finished Jun 07 07:51:19 PM PDT 24
Peak memory 208728 kb
Host smart-075826e5-f182-438f-938b-7e68d872ba41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850378341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2850378341
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1523800530
Short name T357
Test name
Test status
Simulation time 55563371 ps
CPU time 0.78 seconds
Started Jun 07 07:51:13 PM PDT 24
Finished Jun 07 07:51:17 PM PDT 24
Peak memory 206692 kb
Host smart-fa401d53-0b4f-4d63-97b5-9e122d66c083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523800530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1523800530
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.909743941
Short name T537
Test name
Test status
Simulation time 1467670835 ps
CPU time 7.86 seconds
Started Jun 07 07:51:12 PM PDT 24
Finished Jun 07 07:51:22 PM PDT 24
Peak memory 241224 kb
Host smart-f92b2d1a-28df-4bd3-92ea-a8b2bcf9e557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909743941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.909743941
Directory /workspace/9.spi_device_upload/latest
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