Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3018685	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3493780

1

T1

4

T2

43

T3

1024

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3624567	1			T1	1		T2	219		T3	2905
values[0x0]	1442941	1			T1	2		T2	24		T3	517
values[0x1]	1444957	1			T1	2		T2	16		T3	494

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2145095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4367370

1

T1

4

T2

122

T3

1947

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28229	1			T3	14		T5	4		T6	2
valid_sources[0x01]	28808	1			T3	8		T5	5		T7	16
valid_sources[0x02]	25294	1			T3	5		T5	6		T6	7
valid_sources[0x03]	22313	1			T3	3		T5	4		T6	6
valid_sources[0x04]	22594	1			T3	12		T5	3		T6	1
valid_sources[0x05]	24861	1			T3	15		T5	7		T6	4
valid_sources[0x06]	31974	1			T3	20		T5	6		T6	1
valid_sources[0x07]	25429	1			T3	29		T5	1		T6	8
valid_sources[0x08]	26953	1			T3	13		T5	4		T6	1
valid_sources[0x09]	32142	1			T3	14		T5	2		T7	26
valid_sources[0x0a]	22372	1			T3	12		T5	3		T6	5
valid_sources[0x0b]	24910	1			T3	3		T5	3		T6	7
valid_sources[0x0c]	21814	1			T3	20		T5	1		T6	4
valid_sources[0x0d]	23629	1			T3	9		T4	63		T5	3
valid_sources[0x0e]	35038	1			T3	10		T5	1		T6	3
valid_sources[0x0f]	28354	1			T3	8		T5	3		T6	4
valid_sources[0x10]	26328	1			T3	22		T5	3		T6	1
valid_sources[0x11]	24100	1			T3	13		T5	1		T7	26
valid_sources[0x12]	23735	1			T3	18		T5	1		T7	20
valid_sources[0x13]	24919	1			T3	17		T5	6		T6	8
valid_sources[0x14]	25216	1			T3	37		T5	4		T6	2
valid_sources[0x15]	23769	1			T3	10		T5	4		T6	1
valid_sources[0x16]	23497	1			T3	17		T5	4		T6	8
valid_sources[0x17]	25188	1			T3	27		T5	3		T6	6
valid_sources[0x18]	24053	1			T3	24		T5	4		T6	1
valid_sources[0x19]	24905	1			T3	10		T5	3		T6	5
valid_sources[0x1a]	23148	1			T3	13		T5	3		T6	5
valid_sources[0x1b]	34971	1			T3	11		T5	6		T7	21
valid_sources[0x1c]	27052	1			T3	11		T5	2		T6	2
valid_sources[0x1d]	25117	1			T5	2		T6	3		T7	29
valid_sources[0x1e]	25111	1			T3	9		T5	5		T6	4
valid_sources[0x1f]	28876	1			T3	14		T5	2		T6	3
valid_sources[0x20]	25604	1			T3	16		T5	4		T6	6
valid_sources[0x21]	23437	1			T3	21		T5	2		T7	30
valid_sources[0x22]	22922	1			T3	21		T5	4		T6	3
valid_sources[0x23]	25845	1			T3	10		T5	2		T6	7
valid_sources[0x24]	24986	1			T3	16		T5	1		T6	1
valid_sources[0x25]	22494	1			T3	19		T5	3		T6	4
valid_sources[0x26]	24309	1			T3	16		T5	5		T6	5
valid_sources[0x27]	21375	1			T3	20		T5	6		T6	4
valid_sources[0x28]	27495	1			T3	8		T5	4		T6	5
valid_sources[0x29]	22820	1			T3	23		T5	5		T7	25
valid_sources[0x2a]	25335	1			T3	27		T5	8		T6	5
valid_sources[0x2b]	23139	1			T3	7		T5	1		T6	8
valid_sources[0x2c]	25621	1			T3	17		T5	4		T6	3
valid_sources[0x2d]	24696	1			T3	9		T5	4		T7	20
valid_sources[0x2e]	22497	1			T3	16		T5	2		T6	3
valid_sources[0x2f]	28902	1			T2	259		T3	10		T5	6
valid_sources[0x30]	25554	1			T3	22		T5	6		T6	3
valid_sources[0x31]	27613	1			T3	8		T5	4		T6	2
valid_sources[0x32]	24421	1			T3	20		T5	4		T6	5
valid_sources[0x33]	21453	1			T3	16		T5	3		T6	3
valid_sources[0x34]	25417	1			T3	12		T5	7		T6	2
valid_sources[0x35]	24384	1			T3	20		T5	5		T6	7
valid_sources[0x36]	23914	1			T3	14		T5	2		T6	4
valid_sources[0x37]	23227	1			T3	10		T5	1		T7	25
valid_sources[0x38]	22641	1			T3	13		T5	4		T6	3
valid_sources[0x39]	26713	1			T3	21		T5	6		T6	3
valid_sources[0x3a]	40986	1			T3	9		T5	5		T6	4
valid_sources[0x3b]	27214	1			T3	7		T5	2		T6	3
valid_sources[0x3c]	22963	1			T3	19		T5	4		T6	3
valid_sources[0x3d]	24451	1			T3	15		T5	5		T6	1
valid_sources[0x3e]	24199	1			T3	15		T5	2		T6	1
valid_sources[0x3f]	22538	1			T3	20		T5	8		T6	4
valid_sources[0x40]	24182	1			T3	20		T5	8		T6	2
valid_sources[0x41]	24798	1			T3	16		T5	5		T7	24
valid_sources[0x42]	23058	1			T3	20		T5	3		T6	1
valid_sources[0x43]	26140	1			T3	17		T5	1		T6	1
valid_sources[0x44]	24378	1			T3	19		T5	2		T6	2
valid_sources[0x45]	25649	1			T3	11		T5	5		T7	24
valid_sources[0x46]	25354	1			T3	12		T5	6		T6	7
valid_sources[0x47]	22823	1			T3	15		T5	7		T7	18
valid_sources[0x48]	25327	1			T3	8		T5	6		T6	6
valid_sources[0x49]	28410	1			T3	11		T5	4		T7	30
valid_sources[0x4a]	23972	1			T3	25		T5	8		T6	3
valid_sources[0x4b]	26052	1			T3	13		T6	1		T7	33
valid_sources[0x4c]	23376	1			T3	20		T5	5		T7	27
valid_sources[0x4d]	22663	1			T3	15		T5	5		T6	1
valid_sources[0x4e]	22522	1			T3	4		T5	6		T7	27
valid_sources[0x4f]	23989	1			T3	26		T5	6		T6	1
valid_sources[0x50]	25618	1			T3	25		T5	5		T6	2
valid_sources[0x51]	25724	1			T3	23		T5	1		T6	1
valid_sources[0x52]	24854	1			T3	54		T5	1		T6	8
valid_sources[0x53]	24065	1			T3	34		T5	7		T6	5
valid_sources[0x54]	31614	1			T3	21		T5	8		T6	2
valid_sources[0x55]	23746	1			T3	17		T5	6		T6	2
valid_sources[0x56]	24348	1			T3	6		T5	3		T6	4
valid_sources[0x57]	23110	1			T3	11		T5	7		T6	2
valid_sources[0x58]	23990	1			T3	12		T5	4		T6	7
valid_sources[0x59]	22790	1			T3	12		T5	1		T6	1
valid_sources[0x5a]	23966	1			T3	7		T5	4		T6	14
valid_sources[0x5b]	25749	1			T3	19		T5	2		T6	1
valid_sources[0x5c]	25917	1			T3	32		T5	4		T6	1
valid_sources[0x5d]	26422	1			T3	7		T5	1		T6	1
valid_sources[0x5e]	26549	1			T3	7		T5	5		T6	7
valid_sources[0x5f]	23651	1			T3	8		T5	2		T6	7
valid_sources[0x60]	27395	1			T3	10		T5	6		T6	1
valid_sources[0x61]	25807	1			T3	13		T5	5		T6	4
valid_sources[0x62]	31671	1			T3	16		T5	2		T6	9
valid_sources[0x63]	25420	1			T3	8		T5	8		T6	2
valid_sources[0x64]	25868	1			T3	16		T5	2		T6	3
valid_sources[0x65]	22150	1			T3	13		T5	5		T6	4
valid_sources[0x66]	24927	1			T3	15		T5	8		T6	2
valid_sources[0x67]	24084	1			T3	12		T5	5		T7	24
valid_sources[0x68]	24078	1			T3	15		T5	8		T7	27
valid_sources[0x69]	24692	1			T3	11		T5	3		T6	6
valid_sources[0x6a]	24281	1			T3	18		T5	3		T7	31
valid_sources[0x6b]	25287	1			T3	13		T5	2		T6	10
valid_sources[0x6c]	24610	1			T3	14		T5	2		T7	23
valid_sources[0x6d]	23592	1			T3	15		T5	2		T6	8
valid_sources[0x6e]	21733	1			T3	27		T5	6		T7	26
valid_sources[0x6f]	22520	1			T3	9		T5	3		T6	3
valid_sources[0x70]	33016	1			T3	12		T5	5		T7	30
valid_sources[0x71]	26641	1			T3	18		T5	4		T6	2
valid_sources[0x72]	24056	1			T3	10		T5	2		T6	3
valid_sources[0x73]	30850	1			T3	9		T6	5		T7	32
valid_sources[0x74]	23820	1			T3	13		T5	1		T6	1
valid_sources[0x75]	25395	1			T3	9		T5	7		T6	1
valid_sources[0x76]	34296	1			T3	13		T5	3		T6	3
valid_sources[0x77]	25950	1			T3	11		T5	3		T6	8
valid_sources[0x78]	23377	1			T3	12		T5	4		T6	2
valid_sources[0x79]	23985	1			T3	20		T5	3		T6	4
valid_sources[0x7a]	23479	1			T3	19		T5	2		T6	3
valid_sources[0x7b]	24669	1			T3	6		T5	1		T6	6
valid_sources[0x7c]	22311	1			T3	13		T5	3		T6	2
valid_sources[0x7d]	24380	1			T3	11		T6	5		T7	33
valid_sources[0x7e]	23331	1			T3	11		T5	2		T6	7
valid_sources[0x7f]	23611	1			T3	12		T5	7		T7	23
valid_sources[0x80]	22902	1			T3	30		T5	2		T6	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

885368

1

T1

1

T2

8

T3

245

values[0x0]

all_enables

biggest_size

1313680

1

T1

2

T2

21

T3

403

values[0x1]

all_enables

biggest_size

1294732

1

T1

1

T2

14

T3

376