Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3037978

1

T1

1

T2

216

T3

2892

full_word

3494878

1

T1

4

T2

43

T3

1024

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6532396	1			T1	5		T2	259		T3	3916
auto[TlIntgErrCmd]	149	1			T92	14		T93	3		T94	5
auto[TlIntgErrData]	142	1			T92	10		T93	3		T94	3
auto[TlIntgErrBoth]	169	1			T92	6		T93	4		T94	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3627756

1

T1

1

T2

219

T3

2905

auto[1]

2905100

1

T1

4

T2

40

T3

1011

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2741969	1			T2	211		T3	2660		T4	62
auto[TlIntgErrNone]	partial	auto[1]	295590	1			T1	1		T2	5		T3	232
auto[TlIntgErrNone]	full_word	auto[0]	885593	1			T1	1		T2	8		T3	245
auto[TlIntgErrNone]	full_word	auto[1]	2609244	1			T1	3		T2	35		T3	779
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T92	3		T93	2		T94	3
auto[TlIntgErrCmd]	partial	auto[1]	83	1			T92	10		T93	1		T94	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T94	1		T177	1		T179	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T92	1		T180	1		T181	2
auto[TlIntgErrData]	partial	auto[0]	58	1			T92	5		T94	3		T145	4
auto[TlIntgErrData]	partial	auto[1]	68	1			T92	5		T93	3		T145	3
auto[TlIntgErrData]	full_word	auto[0]	9	1			T145	1		T181	1		T182	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T176	1		T180	1		T181	1
auto[TlIntgErrBoth]	partial	auto[0]	60	1			T93	1		T94	4		T144	5
auto[TlIntgErrBoth]	partial	auto[1]	95	1			T92	3		T93	3		T94	8
auto[TlIntgErrBoth]	full_word	auto[0]	9	1			T92	3		T181	1		T183	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T178	2		T184	2		T185	1