Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	461635938	2537964	0	0
gen_wmask[1].MaskCheckPortA_A	461635938	2537964	0	0
gen_wmask[2].MaskCheckPortA_A	461635938	2537964	0	0
gen_wmask[3].MaskCheckPortA_A	461635938	2537964	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461635938	2537964	0	0
T2	4048	35	0	0
T3	267774	1164	0	0
T4	2180	0	0	0
T5	163600	832	0	0
T6	342941	832	0	0
T7	183046	832	0	0
T8	411590	4617	0	0
T9	1064	0	0	0
T10	1045681	832	0	0
T11	218049	832	0	0
T12	78622	832	0	0
T13	79690	832	0	0
T15	0	1852	0	0
T16	0	8	0	0
T17	0	1149	0	0
T18	0	9272	0	0
T19	0	2770	0	0
T25	0	2457	0	0
T26	0	1721	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461635938	2537964	0	0
T2	4048	35	0	0
T3	267774	1164	0	0
T4	2180	0	0	0
T5	163600	832	0	0
T6	342941	832	0	0
T7	183046	832	0	0
T8	411590	4617	0	0
T9	1064	0	0	0
T10	1045681	832	0	0
T11	218049	832	0	0
T12	78622	832	0	0
T13	79690	832	0	0
T15	0	1852	0	0
T16	0	8	0	0
T17	0	1149	0	0
T18	0	9272	0	0
T19	0	2770	0	0
T25	0	2457	0	0
T26	0	1721	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461635938	2537964	0	0
T2	4048	35	0	0
T3	267774	1164	0	0
T4	2180	0	0	0
T5	163600	832	0	0
T6	342941	832	0	0
T7	183046	832	0	0
T8	411590	4617	0	0
T9	1064	0	0	0
T10	1045681	832	0	0
T11	218049	832	0	0
T12	78622	832	0	0
T13	79690	832	0	0
T15	0	1852	0	0
T16	0	8	0	0
T17	0	1149	0	0
T18	0	9272	0	0
T19	0	2770	0	0
T25	0	2457	0	0
T26	0	1721	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461635938	2537964	0	0
T2	4048	35	0	0
T3	267774	1164	0	0
T4	2180	0	0	0
T5	163600	832	0	0
T6	342941	832	0	0
T7	183046	832	0	0
T8	411590	4617	0	0
T9	1064	0	0	0
T10	1045681	832	0	0
T11	218049	832	0	0
T12	78622	832	0	0
T13	79690	832	0	0
T15	0	1852	0	0
T16	0	8	0	0
T17	0	1149	0	0
T18	0	9272	0	0
T19	0	2770	0	0
T25	0	2457	0	0
T26	0	1721	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	341249657	1696089	0	0
gen_wmask[1].MaskCheckPortA_A	341249657	1696089	0	0
gen_wmask[2].MaskCheckPortA_A	341249657	1696089	0	0
gen_wmask[3].MaskCheckPortA_A	341249657	1696089	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	1696089	0	0
T2	2412	27	0	0
T3	234058	454	0	0
T4	2180	0	0	0
T5	36423	832	0	0
T6	232158	832	0	0
T7	153080	832	0	0
T8	183747	1664	0	0
T9	1064	0	0	0
T10	930418	832	0	0
T11	112593	832	0	0
T12	0	832	0	0
T13	0	832	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	1696089	0	0
T2	2412	27	0	0
T3	234058	454	0	0
T4	2180	0	0	0
T5	36423	832	0	0
T6	232158	832	0	0
T7	153080	832	0	0
T8	183747	1664	0	0
T9	1064	0	0	0
T10	930418	832	0	0
T11	112593	832	0	0
T12	0	832	0	0
T13	0	832	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	1696089	0	0
T2	2412	27	0	0
T3	234058	454	0	0
T4	2180	0	0	0
T5	36423	832	0	0
T6	232158	832	0	0
T7	153080	832	0	0
T8	183747	1664	0	0
T9	1064	0	0	0
T10	930418	832	0	0
T11	112593	832	0	0
T12	0	832	0	0
T13	0	832	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	1696089	0	0
T2	2412	27	0	0
T3	234058	454	0	0
T4	2180	0	0	0
T5	36423	832	0	0
T6	232158	832	0	0
T7	153080	832	0	0
T8	183747	1664	0	0
T9	1064	0	0	0
T10	930418	832	0	0
T11	112593	832	0	0
T12	0	832	0	0
T13	0	832	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	120386281	841875	0	0
gen_wmask[1].MaskCheckPortA_A	120386281	841875	0	0
gen_wmask[2].MaskCheckPortA_A	120386281	841875	0	0
gen_wmask[3].MaskCheckPortA_A	120386281	841875	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	841875	0	0
T2	1636	8	0	0
T3	33716	710	0	0
T5	127177	0	0	0
T6	110783	0	0	0
T7	29966	0	0	0
T8	227843	2953	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T15	0	1852	0	0
T16	0	8	0	0
T17	0	1149	0	0
T18	0	9272	0	0
T19	0	2770	0	0
T25	0	2457	0	0
T26	0	1721	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	841875	0	0
T2	1636	8	0	0
T3	33716	710	0	0
T5	127177	0	0	0
T6	110783	0	0	0
T7	29966	0	0	0
T8	227843	2953	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T15	0	1852	0	0
T16	0	8	0	0
T17	0	1149	0	0
T18	0	9272	0	0
T19	0	2770	0	0
T25	0	2457	0	0
T26	0	1721	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	841875	0	0
T2	1636	8	0	0
T3	33716	710	0	0
T5	127177	0	0	0
T6	110783	0	0	0
T7	29966	0	0	0
T8	227843	2953	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T15	0	1852	0	0
T16	0	8	0	0
T17	0	1149	0	0
T18	0	9272	0	0
T19	0	2770	0	0
T25	0	2457	0	0
T26	0	1721	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	841875	0	0
T2	1636	8	0	0
T3	33716	710	0	0
T5	127177	0	0	0
T6	110783	0	0	0
T7	29966	0	0	0
T8	227843	2953	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T15	0	1852	0	0
T16	0	8	0	0
T17	0	1149	0	0
T18	0	9272	0	0
T19	0	2770	0	0
T25	0	2457	0	0
T26	0	1721	0	0