Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	344058805	2321118	0	0
DepthKnown_A	344058805	343924901	0	0
RvalidKnown_A	344058805	343924901	0	0
WreadyKnown_A	344058805	343924901	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	2321118	0	0
T5	36423	1663	0	0
T6	232158	1666	0	0
T7	153080	1663	0	0
T8	183747	1664	0	0
T9	1064	0	0	0
T10	930418	832	0	0
T11	112593	1663	0	0
T12	81849	1669	0	0
T13	322473	1664	0	0
T14	10672	832	0	0
T15	0	17487	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	344058805	2446993	0	0
DepthKnown_A	344058805	343924901	0	0
RvalidKnown_A	344058805	343924901	0	0
WreadyKnown_A	344058805	343924901	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	2446993	0	0
T5	36423	832	0	0
T6	232158	836	0	0
T7	153080	832	0	0
T8	183747	1664	0	0
T9	1064	0	0	0
T10	930418	2482	0	0
T11	112593	832	0	0
T12	81849	838	0	0
T13	322473	833	0	0
T14	10672	832	0	0
T15	0	18591	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	344058805	146774	0	0
DepthKnown_A	344058805	343924901	0	0
RvalidKnown_A	344058805	343924901	0	0
WreadyKnown_A	344058805	343924901	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	146774	0	0
T2	2412	2	0	0
T3	234058	185	0	0
T4	2180	0	0	0
T5	36423	0	0	0
T6	232158	0	0	0
T7	153080	0	0	0
T8	183747	128	0	0
T9	1064	0	0	0
T10	930418	0	0	0
T11	112593	0	0	0
T15	0	471	0	0
T16	0	2	0	0
T17	0	296	0	0
T18	0	1521	0	0
T19	0	500	0	0
T25	0	606	0	0
T26	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	344058805	329495	0	0
DepthKnown_A	344058805	343924901	0	0
RvalidKnown_A	344058805	343924901	0	0
WreadyKnown_A	344058805	343924901	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	329495	0	0
T2	2412	2	0	0
T3	234058	185	0	0
T4	2180	0	0	0
T5	36423	0	0	0
T6	232158	0	0	0
T7	153080	0	0	0
T8	183747	128	0	0
T9	1064	0	0	0
T10	930418	0	0	0
T11	112593	0	0	0
T15	0	2019	0	0
T16	0	2	0	0
T17	0	1505	0	0
T18	0	1521	0	0
T19	0	2377	0	0
T25	0	2806	0	0
T26	0	279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	344058805	5247978	0	0
DepthKnown_A	344058805	343924901	0	0
RvalidKnown_A	344058805	343924901	0	0
WreadyKnown_A	344058805	343924901	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	5247978	0	0
T1	996	5	0	0
T2	2412	257	0	0
T3	234058	3737	0	0
T4	2180	63	0	0
T5	36423	139	0	0
T6	232158	69	0	0
T7	153080	6304	0	0
T8	183747	2839	0	0
T9	1064	12	0	0
T10	930418	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	344058805	11100972	0	0
DepthKnown_A	344058805	343924901	0	0
RvalidKnown_A	344058805	343924901	0	0
WreadyKnown_A	344058805	343924901	0	0
gen_passthru_fifo.paramCheckPass	1081	1081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	11100972	0	0
T1	996	5	0	0
T2	2412	257	0	0
T3	234058	3731	0	0
T4	2180	303	0	0
T5	36423	135	0	0
T6	232158	288	0	0
T7	153080	27240	0	0
T8	183747	2836	0	0
T9	1064	12	0	0
T10	930418	182	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	344058805	343924901	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081	1081	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0