Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T15
1	0	Covered	T2,T3,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T15,T17

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T15,T17
1	0	Covered	T8,T15,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T8,T15,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	582022219	460386097	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	582022219	2871849	0	0
GntImpliesValid_A	582022219	2871849	0	0
GrantKnown_A	582022219	460386097	0	0
IdxKnown_A	582022219	460386097	0	0
IndexIsCorrect_A	582022219	2871849	0	0
LockArbDecision_A	582022219	0	0	0
NoReadyValidNoGrant_A	582022219	0	0	0
ReadyAndValidImplyGrant_A	582022219	2871849	0	0
ReqAndReadyImplyGrant_A	582022219	2871849	0	0
ReqImpliesValid_A	582022219	2871849	0	0
ReqStaysHighUntilGranted0_M	582022219	0	0	0
RoundRobin_A	582022219	1	0	906
ValidKnown_A	582022219	460386097	0	0
gen_data_port_assertion.DataFlow_A	582022219	2871849	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582022219	460386097	0	0
T1	1068	1004	0	0
T2	4048	3731	0	0
T3	267774	266199	0	0
T4	2180	2082	0	0
T5	290777	163394	0	0
T6	453724	342025	0	0
T7	213012	182959	0	0
T8	639433	411404	0	0
T9	1064	966	0	0
T10	1160944	1045229	0	0
T11	210912	105038	0	0
T12	157244	78622	0	0
T13	79690	79690	0	0
T14	12744	12744	0	0
T15	522525	517887	0	0
T16	0	600	0	0
T17	0	40192	0	0
T18	0	101824	0	0
T19	0	168355	0	0
T25	0	72368	0	0
T36	0	720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582022219	2871849	0	0
T2	4048	67	0	0
T3	267774	1841	0	0
T4	2180	0	0	0
T5	163600	832	0	0
T6	342941	832	0	0
T7	183046	832	0	0
T8	639433	4750	0	0
T9	1064	0	0	0
T10	1160944	832	0	0
T11	323505	832	0	0
T12	157244	832	0	0
T13	159380	832	0	0
T14	12744	0	0	0
T15	522525	2392	0	0
T16	600	20	0	0
T17	148217	1539	0	0
T18	0	10688	0	0
T19	0	3591	0	0
T25	0	3450	0	0
T26	0	1721	0	0
T27	16	0	0	0
T28	0	1833	0	0
T38	0	4988	0	0
T43	0	6014	0	0
T44	0	136	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582022219	2871849	0	0
T2	4048	67	0	0
T3	267774	1841	0	0
T4	2180	0	0	0
T5	163600	832	0	0
T6	342941	832	0	0
T7	183046	832	0	0
T8	639433	4750	0	0
T9	1064	0	0	0
T10	1160944	832	0	0
T11	323505	832	0	0
T12	157244	832	0	0
T13	159380	832	0	0
T14	12744	0	0	0
T15	522525	2392	0	0
T16	600	20	0	0
T17	148217	1539	0	0
T18	0	10688	0	0
T19	0	3591	0	0
T25	0	3450	0	0
T26	0	1721	0	0
T27	16	0	0	0
T28	0	1833	0	0
T38	0	4988	0	0
T43	0	6014	0	0
T44	0	136	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582022219	460386097	0	0
T1	1068	1004	0	0
T2	4048	3731	0	0
T3	267774	266199	0	0
T4	2180	2082	0	0
T5	290777	163394	0	0
T6	453724	342025	0	0
T7	213012	182959	0	0
T8	639433	411404	0	0
T9	1064	966	0	0
T10	1160944	1045229	0	0
T11	210912	105038	0	0
T12	157244	78622	0	0
T13	79690	79690	0	0
T14	12744	12744	0	0
T15	522525	517887	0	0
T16	0	600	0	0
T17	0	40192	0	0
T18	0	101824	0	0
T19	0	168355	0	0
T25	0	72368	0	0
T36	0	720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582022219	460386097	0	0
T1	1068	1004	0	0
T2	4048	3731	0	0
T3	267774	266199	0	0
T4	2180	2082	0	0
T5	290777	163394	0	0
T6	453724	342025	0	0
T7	213012	182959	0	0
T8	639433	411404	0	0
T9	1064	966	0	0
T10	1160944	1045229	0	0
T11	210912	105038	0	0
T12	157244	78622	0	0
T13	79690	79690	0	0
T14	12744	12744	0	0
T15	522525	517887	0	0
T16	0	600	0	0
T17	0	40192	0	0
T18	0	101824	0	0
T19	0	168355	0	0
T25	0	72368	0	0
T36	0	720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582022219	2871849	0	0
T2	4048	67	0	0
T3	267774	1841	0	0
T4	2180	0	0	0
T5	163600	832	0	0
T6	342941	832	0	0
T7	183046	832	0	0
T8	639433	4750	0	0
T9	1064	0	0	0
T10	1160944	832	0	0
T11	323505	832	0	0
T12	157244	832	0	0
T13	159380	832	0	0
T14	12744	0	0	0
T15	522525	2392	0	0
T16	600	20	0	0
T17	148217	1539	0	0
T18	0	10688	0	0
T19	0	3591	0	0
T25	0	3450	0	0
T26	0	1721	0	0
T27	16	0	0	0
T28	0	1833	0	0
T38	0	4988	0	0
T43	0	6014	0	0
T44	0	136	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582022219	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582022219	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582022219	2871849	0	0
T2	4048	67	0	0
T3	267774	1841	0	0
T4	2180	0	0	0
T5	163600	832	0	0
T6	342941	832	0	0
T7	183046	832	0	0
T8	639433	4750	0	0
T9	1064	0	0	0
T10	1160944	832	0	0
T11	323505	832	0	0
T12	157244	832	0	0
T13	159380	832	0	0
T14	12744	0	0	0
T15	522525	2392	0	0
T16	600	20	0	0
T17	148217	1539	0	0
T18	0	10688	0	0
T19	0	3591	0	0
T25	0	3450	0	0
T26	0	1721	0	0
T27	16	0	0	0
T28	0	1833	0	0
T38	0	4988	0	0
T43	0	6014	0	0
T44	0	136	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582022219	2871849	0	0
T2	4048	67	0	0
T3	267774	1841	0	0
T4	2180	0	0	0
T5	163600	832	0	0
T6	342941	832	0	0
T7	183046	832	0	0
T8	639433	4750	0	0
T9	1064	0	0	0
T10	1160944	832	0	0
T11	323505	832	0	0
T12	157244	832	0	0
T13	159380	832	0	0
T14	12744	0	0	0
T15	522525	2392	0	0
T16	600	20	0	0
T17	148217	1539	0	0
T18	0	10688	0	0
T19	0	3591	0	0
T25	0	3450	0	0
T26	0	1721	0	0
T27	16	0	0	0
T28	0	1833	0	0
T38	0	4988	0	0
T43	0	6014	0	0
T44	0	136	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582022219	2871849	0	0
T2	4048	67	0	0
T3	267774	1841	0	0
T4	2180	0	0	0
T5	163600	832	0	0
T6	342941	832	0	0
T7	183046	832	0	0
T8	639433	4750	0	0
T9	1064	0	0	0
T10	1160944	832	0	0
T11	323505	832	0	0
T12	157244	832	0	0
T13	159380	832	0	0
T14	12744	0	0	0
T15	522525	2392	0	0
T16	600	20	0	0
T17	148217	1539	0	0
T18	0	10688	0	0
T19	0	3591	0	0
T25	0	3450	0	0
T26	0	1721	0	0
T27	16	0	0	0
T28	0	1833	0	0
T38	0	4988	0	0
T43	0	6014	0	0
T44	0	136	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	582022219	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582022219	1	0	906
T45	586717	1	0	1
T46	312581	0	0	1
T47	1337	0	0	1
T48	1226	0	0	1
T49	6541	0	0	1
T50	42399	0	0	1
T51	21200	0	0	1
T52	69232	0	0	1
T53	55597	0	0	1
T54	38489	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582022219	460386097	0	0
T1	1068	1004	0	0
T2	4048	3731	0	0
T3	267774	266199	0	0
T4	2180	2082	0	0
T5	290777	163394	0	0
T6	453724	342025	0	0
T7	213012	182959	0	0
T8	639433	411404	0	0
T9	1064	966	0	0
T10	1160944	1045229	0	0
T11	210912	105038	0	0
T12	157244	78622	0	0
T13	79690	79690	0	0
T14	12744	12744	0	0
T15	522525	517887	0	0
T16	0	600	0	0
T17	0	40192	0	0
T18	0	101824	0	0
T19	0	168355	0	0
T25	0	72368	0	0
T36	0	720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	582022219	2871849	0	0
T2	4048	67	0	0
T3	267774	1841	0	0
T4	2180	0	0	0
T5	163600	832	0	0
T6	342941	832	0	0
T7	183046	832	0	0
T8	639433	4750	0	0
T9	1064	0	0	0
T10	1160944	832	0	0
T11	323505	832	0	0
T12	157244	832	0	0
T13	159380	832	0	0
T14	12744	0	0	0
T15	522525	2392	0	0
T16	600	20	0	0
T17	148217	1539	0	0
T18	0	10688	0	0
T19	0	3591	0	0
T25	0	3450	0	0
T26	0	1721	0	0
T27	16	0	0	0
T28	0	1833	0	0
T38	0	4988	0	0
T43	0	6014	0	0
T44	0	136	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T15
1	0	Covered	T2,T3,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T15
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	120386281	27665148	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	120386281	589325	0	0
GntImpliesValid_A	120386281	589325	0	0
GrantKnown_A	120386281	27665148	0	0
IdxKnown_A	120386281	27665148	0	0
IndexIsCorrect_A	120386281	589325	0	0
LockArbDecision_A	120386281	0	0	0
NoReadyValidNoGrant_A	120386281	0	0	0
ReadyAndValidImplyGrant_A	120386281	589325	0	0
ReqAndReadyImplyGrant_A	120386281	589325	0	0
ReqImpliesValid_A	120386281	589325	0	0
ReqStaysHighUntilGranted0_M	120386281	0	0	0
RoundRobin_A	120386281	0	0	0
ValidKnown_A	120386281	27665148	0	0
gen_data_port_assertion.DataFlow_A	120386281	589325	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	27665148	0	0
T1	72	72	0	0
T2	1636	1376	0	0
T3	33716	32224	0	0
T5	127177	0	0	0
T6	110783	0	0	0
T7	29966	0	0	0
T8	227843	0	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T15	0	36576	0	0
T16	0	600	0	0
T17	0	40192	0	0
T18	0	101824	0	0
T19	0	168355	0	0
T25	0	72368	0	0
T36	0	720	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	589325	0	0
T2	1636	38	0	0
T3	33716	1202	0	0
T5	127177	0	0	0
T6	110783	0	0	0
T7	29966	0	0	0
T8	227843	0	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T15	0	1868	0	0
T16	0	20	0	0
T17	0	1537	0	0
T18	0	4842	0	0
T19	0	2238	0	0
T25	0	2962	0	0
T38	0	4988	0	0
T43	0	6014	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	589325	0	0
T2	1636	38	0	0
T3	33716	1202	0	0
T5	127177	0	0	0
T6	110783	0	0	0
T7	29966	0	0	0
T8	227843	0	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T15	0	1868	0	0
T16	0	20	0	0
T17	0	1537	0	0
T18	0	4842	0	0
T19	0	2238	0	0
T25	0	2962	0	0
T38	0	4988	0	0
T43	0	6014	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	27665148	0	0
T1	72	72	0	0
T2	1636	1376	0	0
T3	33716	32224	0	0
T5	127177	0	0	0
T6	110783	0	0	0
T7	29966	0	0	0
T8	227843	0	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T15	0	36576	0	0
T16	0	600	0	0
T17	0	40192	0	0
T18	0	101824	0	0
T19	0	168355	0	0
T25	0	72368	0	0
T36	0	720	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	27665148	0	0
T1	72	72	0	0
T2	1636	1376	0	0
T3	33716	32224	0	0
T5	127177	0	0	0
T6	110783	0	0	0
T7	29966	0	0	0
T8	227843	0	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T15	0	36576	0	0
T16	0	600	0	0
T17	0	40192	0	0
T18	0	101824	0	0
T19	0	168355	0	0
T25	0	72368	0	0
T36	0	720	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	589325	0	0
T2	1636	38	0	0
T3	33716	1202	0	0
T5	127177	0	0	0
T6	110783	0	0	0
T7	29966	0	0	0
T8	227843	0	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T15	0	1868	0	0
T16	0	20	0	0
T17	0	1537	0	0
T18	0	4842	0	0
T19	0	2238	0	0
T25	0	2962	0	0
T38	0	4988	0	0
T43	0	6014	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	589325	0	0
T2	1636	38	0	0
T3	33716	1202	0	0
T5	127177	0	0	0
T6	110783	0	0	0
T7	29966	0	0	0
T8	227843	0	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T15	0	1868	0	0
T16	0	20	0	0
T17	0	1537	0	0
T18	0	4842	0	0
T19	0	2238	0	0
T25	0	2962	0	0
T38	0	4988	0	0
T43	0	6014	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	589325	0	0
T2	1636	38	0	0
T3	33716	1202	0	0
T5	127177	0	0	0
T6	110783	0	0	0
T7	29966	0	0	0
T8	227843	0	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T15	0	1868	0	0
T16	0	20	0	0
T17	0	1537	0	0
T18	0	4842	0	0
T19	0	2238	0	0
T25	0	2962	0	0
T38	0	4988	0	0
T43	0	6014	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	589325	0	0
T2	1636	38	0	0
T3	33716	1202	0	0
T5	127177	0	0	0
T6	110783	0	0	0
T7	29966	0	0	0
T8	227843	0	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T15	0	1868	0	0
T16	0	20	0	0
T17	0	1537	0	0
T18	0	4842	0	0
T19	0	2238	0	0
T25	0	2962	0	0
T38	0	4988	0	0
T43	0	6014	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	27665148	0	0
T1	72	72	0	0
T2	1636	1376	0	0
T3	33716	32224	0	0
T5	127177	0	0	0
T6	110783	0	0	0
T7	29966	0	0	0
T8	227843	0	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T15	0	36576	0	0
T16	0	600	0	0
T17	0	40192	0	0
T18	0	101824	0	0
T19	0	168355	0	0
T25	0	72368	0	0
T36	0	720	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	589325	0	0
T2	1636	38	0	0
T3	33716	1202	0	0
T5	127177	0	0	0
T6	110783	0	0	0
T7	29966	0	0	0
T8	227843	0	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T15	0	1868	0	0
T16	0	20	0	0
T17	0	1537	0	0
T18	0	4842	0	0
T19	0	2238	0	0
T25	0	2962	0	0
T38	0	4988	0	0
T43	0	6014	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T15,T17

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T15,T17
1	0	Covered	T8,T15,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T8,T15,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T15,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T15,T17
0	0	1	Unreachable
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T15,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T15,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	120386281	91555676	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	120386281	447003	0	0
GntImpliesValid_A	120386281	447003	0	0
GrantKnown_A	120386281	91555676	0	0
IdxKnown_A	120386281	91555676	0	0
IndexIsCorrect_A	120386281	447003	0	0
LockArbDecision_A	120386281	0	0	0
NoReadyValidNoGrant_A	120386281	0	0	0
ReadyAndValidImplyGrant_A	120386281	447003	0	0
ReqAndReadyImplyGrant_A	120386281	447003	0	0
ReqImpliesValid_A	120386281	447003	0	0
ReqStaysHighUntilGranted0_M	120386281	0	0	0
RoundRobin_A	120386281	0	0	0
ValidKnown_A	120386281	91555676	0	0
gen_data_port_assertion.DataFlow_A	120386281	447003	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	91555676	0	0
T5	127177	127064	0	0
T6	110783	109956	0	0
T7	29966	29930	0	0
T8	227843	227663	0	0
T10	115263	114888	0	0
T11	105456	105038	0	0
T12	78622	78622	0	0
T13	79690	79690	0	0
T14	12744	12744	0	0
T15	522525	481311	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	447003	0	0
T8	227843	2953	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T14	12744	0	0	0
T15	522525	524	0	0
T16	600	0	0	0
T17	148217	2	0	0
T18	0	5846	0	0
T19	0	1353	0	0
T25	0	488	0	0
T26	0	1721	0	0
T27	16	0	0	0
T28	0	1833	0	0
T29	0	10	0	0
T44	0	136	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	447003	0	0
T8	227843	2953	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T14	12744	0	0	0
T15	522525	524	0	0
T16	600	0	0	0
T17	148217	2	0	0
T18	0	5846	0	0
T19	0	1353	0	0
T25	0	488	0	0
T26	0	1721	0	0
T27	16	0	0	0
T28	0	1833	0	0
T29	0	10	0	0
T44	0	136	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	91555676	0	0
T5	127177	127064	0	0
T6	110783	109956	0	0
T7	29966	29930	0	0
T8	227843	227663	0	0
T10	115263	114888	0	0
T11	105456	105038	0	0
T12	78622	78622	0	0
T13	79690	79690	0	0
T14	12744	12744	0	0
T15	522525	481311	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	91555676	0	0
T5	127177	127064	0	0
T6	110783	109956	0	0
T7	29966	29930	0	0
T8	227843	227663	0	0
T10	115263	114888	0	0
T11	105456	105038	0	0
T12	78622	78622	0	0
T13	79690	79690	0	0
T14	12744	12744	0	0
T15	522525	481311	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	447003	0	0
T8	227843	2953	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T14	12744	0	0	0
T15	522525	524	0	0
T16	600	0	0	0
T17	148217	2	0	0
T18	0	5846	0	0
T19	0	1353	0	0
T25	0	488	0	0
T26	0	1721	0	0
T27	16	0	0	0
T28	0	1833	0	0
T29	0	10	0	0
T44	0	136	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	447003	0	0
T8	227843	2953	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T14	12744	0	0	0
T15	522525	524	0	0
T16	600	0	0	0
T17	148217	2	0	0
T18	0	5846	0	0
T19	0	1353	0	0
T25	0	488	0	0
T26	0	1721	0	0
T27	16	0	0	0
T28	0	1833	0	0
T29	0	10	0	0
T44	0	136	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	447003	0	0
T8	227843	2953	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T14	12744	0	0	0
T15	522525	524	0	0
T16	600	0	0	0
T17	148217	2	0	0
T18	0	5846	0	0
T19	0	1353	0	0
T25	0	488	0	0
T26	0	1721	0	0
T27	16	0	0	0
T28	0	1833	0	0
T29	0	10	0	0
T44	0	136	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	447003	0	0
T8	227843	2953	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T14	12744	0	0	0
T15	522525	524	0	0
T16	600	0	0	0
T17	148217	2	0	0
T18	0	5846	0	0
T19	0	1353	0	0
T25	0	488	0	0
T26	0	1721	0	0
T27	16	0	0	0
T28	0	1833	0	0
T29	0	10	0	0
T44	0	136	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	91555676	0	0
T5	127177	127064	0	0
T6	110783	109956	0	0
T7	29966	29930	0	0
T8	227843	227663	0	0
T10	115263	114888	0	0
T11	105456	105038	0	0
T12	78622	78622	0	0
T13	79690	79690	0	0
T14	12744	12744	0	0
T15	522525	481311	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120386281	447003	0	0
T8	227843	2953	0	0
T10	115263	0	0	0
T11	105456	0	0	0
T12	78622	0	0	0
T13	79690	0	0	0
T14	12744	0	0	0
T15	522525	524	0	0
T16	600	0	0	0
T17	148217	2	0	0
T18	0	5846	0	0
T19	0	1353	0	0
T25	0	488	0	0
T26	0	1721	0	0
T27	16	0	0	0
T28	0	1833	0	0
T29	0	10	0	0
T44	0	136	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	341249657	341165273	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	341249657	1835521	0	0
GntImpliesValid_A	341249657	1835521	0	0
GrantKnown_A	341249657	341165273	0	0
IdxKnown_A	341249657	341165273	0	0
IndexIsCorrect_A	341249657	1835521	0	0
LockArbDecision_A	341249657	0	0	0
NoReadyValidNoGrant_A	341249657	0	0	0
ReadyAndValidImplyGrant_A	341249657	1835521	0	0
ReqAndReadyImplyGrant_A	341249657	1835521	0	0
ReqImpliesValid_A	341249657	1835521	0	0
ReqStaysHighUntilGranted0_M	341249657	0	0	0
RoundRobin_A	341249657	1	0	906
ValidKnown_A	341249657	341165273	0	0
gen_data_port_assertion.DataFlow_A	341249657	1835521	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	1835521	0	0
T2	2412	29	0	0
T3	234058	639	0	0
T4	2180	0	0	0
T5	36423	832	0	0
T6	232158	832	0	0
T7	153080	832	0	0
T8	183747	1797	0	0
T9	1064	0	0	0
T10	930418	832	0	0
T11	112593	832	0	0
T12	0	832	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	1835521	0	0
T2	2412	29	0	0
T3	234058	639	0	0
T4	2180	0	0	0
T5	36423	832	0	0
T6	232158	832	0	0
T7	153080	832	0	0
T8	183747	1797	0	0
T9	1064	0	0	0
T10	930418	832	0	0
T11	112593	832	0	0
T12	0	832	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	1835521	0	0
T2	2412	29	0	0
T3	234058	639	0	0
T4	2180	0	0	0
T5	36423	832	0	0
T6	232158	832	0	0
T7	153080	832	0	0
T8	183747	1797	0	0
T9	1064	0	0	0
T10	930418	832	0	0
T11	112593	832	0	0
T12	0	832	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	1835521	0	0
T2	2412	29	0	0
T3	234058	639	0	0
T4	2180	0	0	0
T5	36423	832	0	0
T6	232158	832	0	0
T7	153080	832	0	0
T8	183747	1797	0	0
T9	1064	0	0	0
T10	930418	832	0	0
T11	112593	832	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	1835521	0	0
T2	2412	29	0	0
T3	234058	639	0	0
T4	2180	0	0	0
T5	36423	832	0	0
T6	232158	832	0	0
T7	153080	832	0	0
T8	183747	1797	0	0
T9	1064	0	0	0
T10	930418	832	0	0
T11	112593	832	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	1835521	0	0
T2	2412	29	0	0
T3	234058	639	0	0
T4	2180	0	0	0
T5	36423	832	0	0
T6	232158	832	0	0
T7	153080	832	0	0
T8	183747	1797	0	0
T9	1064	0	0	0
T10	930418	832	0	0
T11	112593	832	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	1	0	906
T45	586717	1	0	1
T46	312581	0	0	1
T47	1337	0	0	1
T48	1226	0	0	1
T49	6541	0	0	1
T50	42399	0	0	1
T51	21200	0	0	1
T52	69232	0	0	1
T53	55597	0	0	1
T54	38489	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	341165273	0	0
T1	996	932	0	0
T2	2412	2355	0	0
T3	234058	233975	0	0
T4	2180	2082	0	0
T5	36423	36330	0	0
T6	232158	232069	0	0
T7	153080	153029	0	0
T8	183747	183741	0	0
T9	1064	966	0	0
T10	930418	930341	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	341249657	1835521	0	0
T2	2412	29	0	0
T3	234058	639	0	0
T4	2180	0	0	0
T5	36423	832	0	0
T6	232158	832	0	0
T7	153080	832	0	0
T8	183747	1797	0	0
T9	1064	0	0	0
T10	930418	832	0	0
T11	112593	832	0	0
T12	0	832	0	0
T13	0	832	0	0